From nobody Sat May 30 08:44:25 2026 Received: from SN4PR2101CU001.outbound.protection.outlook.com (mail-southcentralusazon11012040.outbound.protection.outlook.com [40.93.195.40]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 178B334DCC7; Sun, 10 May 2026 05:35:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.195.40 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778391346; cv=fail; b=SKotiLUiyMbjrVTQMNiNEvLI1e7G4RqJqGYgrcESwXhRPGIEwvZHT6ft4j25ER0s58jvBov+Jt2bGs0/+iRw/5S6rzkdU+NeUP5O2H30R/mCsg8GwmBGkFzyy8z4k49YvGFjwaXIYCIVOgEG1Atw4pH+dLOcg+GXEHrEMjFvXdg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778391346; c=relaxed/simple; bh=Imiyc4JkQ9507L/3L3ICNB6mDfkWJi5/Foqhwtwqt3Y=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=acbYKXBuWujZHpv2PPX8cLoc7aKzS2R+P9MWiTDrDQVjVM7eDZlcmMOZF/fPGfaqNPywkOr2aD8Kh8b92VUw4LsXjL0Cz2MoOECsPiFV4wqzr14IE5597T8t0UXMykW9seozyyd07PcneslWOhIdxnnvtUnm7NIaZQFJ9ewM+Ok= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=jxGE2n9z; arc=fail smtp.client-ip=40.93.195.40 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="jxGE2n9z" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=hompxr9JASmZekyfF/UFY2Xzlgby+yFeRU7w5Pefdc4GE1xDKsOPyiVNeZPDVPOTgf2KwfgA9jCNzlqnFfBEfv5JApzjG/i9UlVmAaynV0j/AlVptXOuB3jiOEbJrnSKcvFj8NJSiuOL/jIZmStsAFAmyv8kuGSxN2Tl2YqrvTa/w0y354I2i/Yqb5H/a+4/3MhnJhP+s7eEoFsmPAnk+EAYBT5yizgysPNRp49BfCsE992I8KgBbW+oegKQ6Ol0Alh9/WxJj1BpSx0yaLU/qloO2STM7PXZK8Wypw5qF/QU5ODVfMDKmIlCRiEV8dyfKGsotz5wYJ7Y6oIRJ+M+Aw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=9T2tcPdLK52zItliQ5yhu/ldUvY90XwPGct/NrkxDTY=; b=LUQdf93oU9geth16gdqPPLzqWJX3HaegmJJI3t33obUoAZ3YKFotgLSgsSMv9n962Yx5RZ5lTa6zTbdQRrXNMh2yoOb0ajlIQX7S9if0xJBAF7echl1MCnRWJtzWVcxTKEPqoRlyu/hy7N0awDqPj4dJjUqwdsQ8ojxr7eTk0Pd/LgcrSvjfpAeZlyW4zvcirTws44aTYoqbOu5JoPxyj+9PZwkOPolW3PQ96YnTn8VgsQh+znkzheddAGQeXg5duKK6I7fIcXOnL7dMPAoaf7x/BqDIOgpUMJC+6SbGvezAOLblGiXdWN6C5oTHLQAISv5L2ocv7k7SVzfnY/dt0g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9T2tcPdLK52zItliQ5yhu/ldUvY90XwPGct/NrkxDTY=; b=jxGE2n9z14viZiIzO6NYiJ33pFCgkDwUvi8ayp0438Q0s5M+w4cVcCQkFFF28B/tqlo1Yf/HQIipbIg9/td3xDnzyMos3ohSvd38jBrNaVWP5rXBpsgX954MYtXD6O1VxO8EfP/NG0yzPb/fqok/jsOzKeqNrTLEMlmBj+9Ps91bqsMXt/rUkdvgupOv4NcbTwpHjHNX3++W0cFEwLhsYLd7slUHdWsxkCCYwuJha8yUsbUqKr1vywiOfH6Py/htCWFCL95JKV1Ow2k9Vh8I6N12lxPssUIzZBFDKydRg7NbLOc2s3lnBRZucWrIhHfMNs2C2tJB00pT5N/GIdkflw== Received: from PH8P222CA0022.NAMP222.PROD.OUTLOOK.COM (2603:10b6:510:2d7::33) by SJ2PR12MB9243.namprd12.prod.outlook.com (2603:10b6:a03:578::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9891.20; Sun, 10 May 2026 05:35:37 +0000 Received: from CY4PEPF0000EE35.namprd05.prod.outlook.com (2603:10b6:510:2d7:cafe::dc) by PH8P222CA0022.outlook.office365.com (2603:10b6:510:2d7::33) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9891.22 via Frontend Transport; Sun, 10 May 2026 05:35:36 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CY4PEPF0000EE35.mail.protection.outlook.com (10.167.242.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.13 via Frontend Transport; Sun, 10 May 2026 05:35:36 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 9 May 2026 22:35:18 -0700 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 9 May 2026 22:35:18 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Sat, 9 May 2026 22:35:14 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Moshe Shemesh" , Akiva Goldberger , , , , Gal Pressman , Dragos Tatulea Subject: [PATCH net-next 1/8] net/mlx5: Use helper to parse host PF info Date: Sun, 10 May 2026 08:34:41 +0300 Message-ID: <20260510053448.326823-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260510053448.326823-1-tariqt@nvidia.com> References: <20260510053448.326823-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE35:EE_|SJ2PR12MB9243:EE_ X-MS-Office365-Filtering-Correlation-Id: 4483ca2a-4a8f-46ae-69fb-08deae55f6ae X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|82310400026|1800799024|3023799003|56012099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: 44+Qvg36oQhAiPgS2dztzC65mjLYEfFTOGz+ZrLSHNjNMcMLOo1BXLYooLvUp3LHvzEfrSOclfrBEbYWtNBAdrWQsoyuoG+4tvLk/v45l0Su7lEbu5LnsKYCYthnNJ6l/SZpLSbxDQwBNgz+7KO4gkYd6StYg4w17Rk99MeT5mlQaYJkHfxCYQQl15OrvzHW5Y+k7Zr1/jibIXG6xA3j+bi4fDJ72qmDmTAYksAgrANDs6dgSN2uhrWNifvpGj0ksKMXLGmaGTPyqxYdPKsN4SyiRb/gQa58thsP4Qhw3SVFHkt+agm4q7NP5k6qHJ6GDk+erD2L/HQTO2P0wNxAYsZ7bYU/U5TBdANCEWODLoJef9PcspWVKmQY6VLazSdOpHvJverQfaLLDK0BrXa/V4p1bnL1QM2c8FXr/RL3Rza4lleFddPOalBaYE96xt3V8z/j5xDYfYTI44TUayN58M5RW+TL45tdhFMiNEahibPJwNvXnhCf8Mxxk7kVN7RlMY+auJcJcIhpC3r7lKL1+ow21rPXwA723AY1IpfDrlbx5kTMeA8Zto2DJjryp08IK+kjCxSWh+tMKa1xw/dRopMcWugiOCF2zUfKulNqjHleo8qPTMNoIHXnrCwJkzWAR9vImJ4av1jBt+SLp7gUDWfnXzGITp04z3hMkQGXtFlPWLAXsAdNbgil7NDOjbz/DIFcnF2ERw/LOnsW+IZGupX5h3GIewtAw8jwQjG8Az4= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700016)(82310400026)(1800799024)(3023799003)(56012099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: giKfDYw7J2O/Kmwos5bDPBuom4dBJQnLKHcraOiDPtRGx+RSKXWNo1t0AyX+Sx2MJC7Bsv3w1hMvCvvLM/Dpbf2CAgIpFZZlOuQzzP2Z2mOrF8uzWeE4Ppnv/Ure+fPspLBrIHR2PuQDCYHLvd5rTtoG2M7584g3qmB5NdMJXm2deYoFtWCb1KegvhrrfGdeQ34meiGLUNRZB5SQBBLuP62S5WghH+ogXV4jflPoeL2V1XziHhcjZgpdk/AMBqWaGU2SPsWTFaH+3kVLcmRUb1fTgrc2EcZjrqUbw3oidLdF5tTcI8kyqd+Nm4dDwvsWTMNqQ9dXypenE7G0DTj11PuRJkJibCmKxtRyVBZuDAoXNxZIyMT4suxxfuMlMDDRwADY0DzaQdhiv2pHSqxywyuQ6hx7MjCo/EO9kuBvwsuxWXNgsDGwjh/x+J3g+Ymf X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2026 05:35:36.6186 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4483ca2a-4a8f-46ae-69fb-08deae55f6ae X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE35.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9243 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh Add a helper mlx5_esw_get_host_pf_info() to retrieve host PF data from the query_esw_functions command output, so callers no longer need to parse the layout to obtain the required information. Convert all callers of mlx5_esw_query_functions() to use the new helper, preparing for upcoming support of the new op_mod that returns data in the network_function_params layout. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan Reviewed-by: Simon Horman --- .../net/ethernet/mellanox/mlx5/core/eswitch.c | 43 ++++++++++++++----- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 15 +++++++ .../mellanox/mlx5/core/eswitch_offloads.c | 34 ++++++--------- .../net/ethernet/mellanox/mlx5/core/sriov.c | 8 ++-- 4 files changed, 62 insertions(+), 38 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.c index 43c40353b2d8..861e79ddb489 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -1083,10 +1083,36 @@ const u32 *mlx5_esw_query_functions(struct mlx5_cor= e_dev *dev) return ERR_PTR(err); } =20 +static struct mlx5_esw_pf_info +mlx5_esw_host_pf_from_host_params(const void *entry) +{ + return (struct mlx5_esw_pf_info) { + .pf_not_exist =3D MLX5_GET(host_params_context, entry, + host_pf_not_exist), + .pf_disabled =3D MLX5_GET(host_params_context, entry, + host_pf_disabled), + .num_of_vfs =3D MLX5_GET(host_params_context, entry, + host_num_of_vfs), + .total_vfs =3D MLX5_GET(host_params_context, entry, + host_total_vfs), + .host_number =3D MLX5_GET(host_params_context, entry, + host_number), + }; +} + +struct mlx5_esw_pf_info mlx5_esw_get_host_pf_info(const u32 *out) +{ + const void *entry; + + entry =3D MLX5_ADDR_OF(query_esw_functions_out, out, net_function_params); + + return mlx5_esw_host_pf_from_host_params(entry); +} + static int mlx5_esw_host_functions_enabled_query(struct mlx5_eswitch *esw) { + struct mlx5_esw_pf_info host_pf_info; const u32 *query_host_out; - void *host_params; =20 if (!mlx5_core_is_ecpf_esw_manager(esw->dev)) return 0; @@ -1095,11 +1121,8 @@ static int mlx5_esw_host_functions_enabled_query(str= uct mlx5_eswitch *esw) if (IS_ERR(query_host_out)) return PTR_ERR(query_host_out); =20 - host_params =3D MLX5_ADDR_OF(query_esw_functions_out, - query_host_out, net_function_params); - esw->esw_funcs.host_funcs_disabled =3D - MLX5_GET(host_params_context, host_params, - host_pf_not_exist); + host_pf_info =3D mlx5_esw_get_host_pf_info(query_host_out); + esw->esw_funcs.host_funcs_disabled =3D host_pf_info.pf_not_exist; =20 kvfree(query_host_out); return 0; @@ -1523,7 +1546,7 @@ static void mlx5_eswitch_get_devlink_param(struct mlx= 5_eswitch *esw) static void mlx5_eswitch_update_num_of_vfs(struct mlx5_eswitch *esw, int num_vfs) { - void *host_params; + struct mlx5_esw_pf_info host_pf_info; const u32 *out; =20 if (num_vfs < 0) @@ -1538,10 +1561,8 @@ mlx5_eswitch_update_num_of_vfs(struct mlx5_eswitch *= esw, int num_vfs) if (IS_ERR(out)) return; =20 - host_params =3D MLX5_ADDR_OF(query_esw_functions_out, out, - net_function_params); - esw->esw_funcs.num_vfs =3D MLX5_GET(host_params_context, host_params, - host_num_of_vfs); + host_pf_info =3D mlx5_esw_get_host_pf_info(out); + esw->esw_funcs.num_vfs =3D host_pf_info.num_of_vfs; if (mlx5_core_ec_sriov_enabled(esw->dev)) esw->esw_funcs.num_ec_vfs =3D num_vfs; =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.h index 291271afa96c..cfaae59a6e7c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -71,6 +71,14 @@ struct mlx5_mapped_obj { }; }; =20 +struct mlx5_esw_pf_info { + bool pf_not_exist; + bool pf_disabled; + u16 num_of_vfs; + u16 total_vfs; + u16 host_number; +}; + #ifdef CONFIG_MLX5_ESWITCH =20 #define ESW_OFFLOADS_DEFAULT_NUM_GROUPS 15 @@ -649,6 +657,7 @@ bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *de= v0, struct mlx5_core_dev *dev1); =20 const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev); +struct mlx5_esw_pf_info mlx5_esw_get_host_pf_info(const u32 *out); int mlx5_esw_host_pf_enable_hca(struct mlx5_core_dev *dev); int mlx5_esw_host_pf_disable_hca(struct mlx5_core_dev *dev); =20 @@ -976,6 +985,12 @@ static inline const u32 *mlx5_esw_query_functions(stru= ct mlx5_core_dev *dev) return ERR_PTR(-EOPNOTSUPP); } =20 +static inline struct mlx5_esw_pf_info +mlx5_esw_get_host_pf_info(const u32 *out) +{ + return (struct mlx5_esw_pf_info) {}; +} + static inline struct mlx5_flow_handle * esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index d95af87a4f5f..217c2fe6b690 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -3708,8 +3708,7 @@ static void esw_offloads_steering_cleanup(struct mlx5= _eswitch *esw) =20 static void esw_vfs_changed_event_handler(struct mlx5_eswitch *esw) { - bool host_pf_disabled; - void *host_params; + struct mlx5_esw_pf_info host_pf_info; u16 new_num_vfs; const u32 *out; =20 @@ -3717,14 +3716,10 @@ static void esw_vfs_changed_event_handler(struct ml= x5_eswitch *esw) if (IS_ERR(out)) return; =20 - host_params =3D MLX5_ADDR_OF(query_esw_functions_out, out, - net_function_params); - new_num_vfs =3D MLX5_GET(host_params_context, host_params, - host_num_of_vfs); - host_pf_disabled =3D MLX5_GET(host_params_context, host_params, - host_pf_disabled); + host_pf_info =3D mlx5_esw_get_host_pf_info(out); + new_num_vfs =3D host_pf_info.num_of_vfs; =20 - if (new_num_vfs =3D=3D esw->esw_funcs.num_vfs || host_pf_disabled) + if (new_num_vfs =3D=3D esw->esw_funcs.num_vfs || host_pf_info.pf_disabled) goto free; =20 mlx5_esw_reps_block(esw); @@ -3826,8 +3821,8 @@ int mlx5_esw_funcs_changed_handler(struct notifier_bl= ock *nb, =20 static int mlx5_esw_host_number_init(struct mlx5_eswitch *esw) { + struct mlx5_esw_pf_info host_pf_info; const u32 *query_host_out; - void *host_params; =20 if (!mlx5_core_is_ecpf_esw_manager(esw->dev)) return 0; @@ -3837,10 +3832,8 @@ static int mlx5_esw_host_number_init(struct mlx5_esw= itch *esw) return PTR_ERR(query_host_out); =20 /* Mark non local controller with non zero controller number. */ - host_params =3D MLX5_ADDR_OF(query_esw_functions_out, - query_host_out, net_function_params); - esw->offloads.host_number =3D MLX5_GET(host_params_context, - host_params, host_number); + host_pf_info =3D mlx5_esw_get_host_pf_info(query_host_out); + esw->offloads.host_number =3D host_pf_info.host_number; kvfree(query_host_out); return 0; } @@ -4980,9 +4973,8 @@ int mlx5_devlink_pf_port_fn_state_get(struct devlink_= port *port, struct netlink_ext_ack *extack) { struct mlx5_vport *vport =3D mlx5_devlink_port_vport_get(port); + struct mlx5_esw_pf_info host_pf_info; const u32 *query_out; - void *host_params; - bool pf_disabled; =20 if (vport->vport !=3D MLX5_VPORT_HOST_PF) { NL_SET_ERR_MSG_MOD(extack, "State get is not supported for VF"); @@ -4996,13 +4988,11 @@ int mlx5_devlink_pf_port_fn_state_get(struct devlin= k_port *port, if (IS_ERR(query_out)) return PTR_ERR(query_out); =20 - host_params =3D MLX5_ADDR_OF(query_esw_functions_out, query_out, - net_function_params); - pf_disabled =3D MLX5_GET(host_params_context, host_params, - host_pf_disabled); + host_pf_info =3D mlx5_esw_get_host_pf_info(query_out); =20 - *opstate =3D pf_disabled ? DEVLINK_PORT_FN_OPSTATE_DETACHED : - DEVLINK_PORT_FN_OPSTATE_ATTACHED; + *opstate =3D host_pf_info.pf_disabled ? + DEVLINK_PORT_FN_OPSTATE_DETACHED : + DEVLINK_PORT_FN_OPSTATE_ATTACHED; =20 kvfree(query_out); return 0; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sriov.c b/drivers/net/= ethernet/mellanox/mlx5/core/sriov.c index 6eb6026eadd6..79f76c456d72 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/sriov.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/sriov.c @@ -273,8 +273,8 @@ void mlx5_sriov_detach(struct mlx5_core_dev *dev) =20 static u16 mlx5_get_max_vfs(struct mlx5_core_dev *dev) { + struct mlx5_esw_pf_info host_pf_info; u16 host_total_vfs; - void *host_params; const u32 *out; =20 if (mlx5_core_is_ecpf_esw_manager(dev)) { @@ -285,10 +285,8 @@ static u16 mlx5_get_max_vfs(struct mlx5_core_dev *dev) */ if (IS_ERR(out)) goto done; - host_params =3D MLX5_ADDR_OF(query_esw_functions_out, out, - net_function_params); - host_total_vfs =3D MLX5_GET(host_params_context, host_params, - host_total_vfs); + host_pf_info =3D mlx5_esw_get_host_pf_info(out); + host_total_vfs =3D host_pf_info.total_vfs; kvfree(out); return host_total_vfs; } --=20 2.44.0 From nobody Sat May 30 08:44:25 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012014.outbound.protection.outlook.com [52.101.43.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1CF0221FD4; Sun, 10 May 2026 05:35:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.14 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778391352; cv=fail; b=n/vS1rJOMsWxi8JjADgYh2wmuWfEzP3DniglWKN3e94qgelp7siuH4E43VRTOOvJ3VS9FSgdcEYTVP7Enuufx01f4TTh+mqIdp9DDQQxDriOhYSHRMBkO5xTqUUbuNFqq+YVmKm3l20u8wYt4IKbLyaS5dXxUdhvNiy0XzVouW4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778391352; c=relaxed/simple; bh=r2jatyJSARMcRxyW7hHy/YeXLWv/QSl8CVCIByUQGuU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=drLU1xSH5w1pYXpIRRLmeK0LOUqQ8W6dY+c1axAl1PpyZVPPk/vM6hTmJKPGiwPEg7ZWhC5/RtvYoz0S5pHz+tQ8H+WjSZ3+Ux5BfSQFVJ3v/571TRGD4q16/Rby/gsTWgsF0/JvrsOF7YA9gdXUkOfk3X8uFTzFguMO6C+K1OA= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=ougVtVab; arc=fail smtp.client-ip=52.101.43.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="ougVtVab" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ktb1xqi3LNiAHSODO3z0PNq9QVCaESftuyxjc6FCIhP5TlzgSXGthOrtXWdUueNMhL3DqE1gL7vf4IRDn3RlOtT6XTV3Pqnw8u8grCckxDPSrKNvh6Q3VG7f6CVJHJC7XeYmKMuhYsWysu723cjC2GeaMkI0xWBGnbS4jk+1kA36zSLYPo1iRrwb8qfGodnYPnDg7HoZ2m+KI8nIwr2vViqCfgiNK17HrscrMj54jZHv9y9iIKLxVapdu7pqdjexcbtOahEo1ShV47u/ds9khJZ5kFGQFEJCfYKUj4VkgM2FEbsJU+exgqvt1v0x5FSoexYAhkIgKG0l+t72PYPsvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=DKXCdreMC2e2wwIUTwS8qFyb3bC6jQvi7mIHk4qMTLw=; b=Ur0zjKXgH/iBGLtdyIIzRbWvMI39NdQ0dp4FAEavGEbz0KCg5navtD1UGF4eLLVs2Hf/nVmyBhOinTB3i84mK5Knz+J/8PiP4T1h/csBm9tkGmr62HiAmt5FHV0N/NEAVKDzSympe6NThcTbwxaKlAh1Zoqe+d5xzYOZQo6smvbpzQU9WbBO9NflB6xYud4HD/N8S3JZ7weI09m4kyhNPgufujP2+xmhQpY+N/v/xmo3unXZtkxoKcRI6VS2plSdolDt6smakCcxUOA1hkamiuwXSLe9aexTnOLEhAKrpW0tfUxM2mmR4dL3FOZ783QQRdWi21EyWd0kiuVv6sFiRw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=DKXCdreMC2e2wwIUTwS8qFyb3bC6jQvi7mIHk4qMTLw=; b=ougVtVabk5cgESIkBogycZMHXCcYAewwdzOGLPGohmfJZqb2nfrBmdVI1t6DZsqAga7KJvvFyAZcuqp+y7uhAkkoqjWdRAcjoi/gyjz/bJFDCb64srjABLqjXPSk26Ngue/7xRSixwApS62OY9TWdxS/2IcR6rzR7hRp5ybOcldkDTEbIdRbtLi+gvaUZIj8bfERLI2NGjnUKS2M9csGBrLyAN30ri2bJ+lHvLhssxeQ7LBkPMY02UAe5Vmr3d7RwntTwDJMteIG60yRgXCmUvrDZF3QeVI3UlELDCKR3tOANpK2lnXx6AqDningiDzjYBW7yPa+Ezm73AU1tpikYw== Received: from PH8PR20CA0019.namprd20.prod.outlook.com (2603:10b6:510:23c::25) by IA0PR12MB8647.namprd12.prod.outlook.com (2603:10b6:208:480::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9891.15; Sun, 10 May 2026 05:35:43 +0000 Received: from CY4PEPF0000EE30.namprd05.prod.outlook.com (2603:10b6:510:23c:cafe::34) by PH8PR20CA0019.outlook.office365.com (2603:10b6:510:23c::25) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9891.21 via Frontend Transport; Sun, 10 May 2026 05:35:43 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CY4PEPF0000EE30.mail.protection.outlook.com (10.167.242.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.13 via Frontend Transport; Sun, 10 May 2026 05:35:42 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 9 May 2026 22:35:24 -0700 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 9 May 2026 22:35:23 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Sat, 9 May 2026 22:35:19 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Moshe Shemesh" , Akiva Goldberger , , , , Gal Pressman , Dragos Tatulea Subject: [PATCH net-next 2/8] net/mlx5: Use v1 response layout for query_esw_functions Date: Sun, 10 May 2026 08:34:42 +0300 Message-ID: <20260510053448.326823-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260510053448.326823-1-tariqt@nvidia.com> References: <20260510053448.326823-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE30:EE_|IA0PR12MB8647:EE_ X-MS-Office365-Filtering-Correlation-Id: 8be03f7a-1ddc-4930-8c74-08deae55fa62 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|376014|18002099003|22082099003|56012099003|3023799003; X-Microsoft-Antispam-Message-Info: pIyPfu6AZqmJZ/JKbOrhA9wt5TP8qLQTPI1C2okpfqMmpyuDUCLrDBQG5eQcwQ4PPT9DGPra79o8rzIr8UboUWdNh6SZrB5SYiM41Cqa28zrfpuq+aYyN80mTClREtE9n+hAGKipQTMyBqYysr9AsmgC29dBfOs13M1IUDf2yBnIlpuMbMuBT22KIMeeoThaUmIBo4+UOI/1OzI7/Ovsdr+MW9Wzo1YQ7LJcyHF0t2pBNZAQZMusmivo6grIT+Vi27iXVl5wW636hniTGj+AbYbimWC5zSmLL8MYzUJLx7Ns1SyZDYOLCeEVXmXKfCgPNRy+92GClfwY/v2/udnd3m+ubZDofjq5n1PptdxxtEhclAgADY3V43qTjyCzCTsuPAhyEEawkOvVzQHhvDc+eXFqGxD6tER3mC6+QtpmVXyAgsU1JK8KbSrSXbNXRrwc+FhD3EhDd8OCxAjj/SfHMjNSf0QPGCUIiTsLw2j8HYI8mvpWMaVK4PeX+Me983QfuaPwOesSsecsHsqP5RKTCjr9BIGpb4/JYIH8rCcSqJTM6M/RlZoOREVKD2RFZeKnsQm1xtUZSsypjmXcG6xRiefsS/ksyNM1q5aN26H7bMmvSQOAto/BfzJ1R9LwBTW6nzx07/jaA5aoI3X9TLRHDndB1U8UBRcxLsxoSSISCiNtx5CVJ+vS0e3DcRjolEvAcCJDdxabwg3kWSUjThtgL0I5cnq9/a1Yn0r0acpBDTA= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700016)(376014)(18002099003)(22082099003)(56012099003)(3023799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: QaBdsQvqKda443ucdhnSLtNiIvXtHPAiSkVcc5zYjZz1NmNV+TyWBcHxaJU8jTk7Ia5RRWftjYYHXPxrP6sqZw0ND2LdrXPD0OG/fZj7SSOG+6iOhl9lksiyB/VTSJHxA02AGGS3RW0zZ1Qj/5YfSeoJgDVppOIu0v+YVqA73uXLtAcPeTlA2uzfyn13Stxnbt+HUU4dexOZuGRzb9gi9k+LeplFg5SDF1ngeSnmWJE7104W3i7nocb9BcwytnPGFJ0zmkxlGMjDcktnf7uqOqzwvgKdLlHYV+PTURuEGIKAEBofhehJGZC6jjESMyxZdPjCX3i5Xa5XNBCB6POeKZTbgAnRjsKXLF6QgwrFCxSguwIYhhOUVu/rjSi9Nc9M3+GcTBYr+sqBJXHNPRGdaTtZnC8ERZjBsyxxRSednphcAMtin/XjPQJAM9UZE5r2 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2026 05:35:42.8280 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8be03f7a-1ddc-4930-8c74-08deae55fa62 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE30.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8647 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh Use the v1 response layout for the query_esw_functions command when supported by the device. When query_host_net_function_v1 capability is set, use MLX5_QUERY_ESW_FUNC_OP_MOD_LAYOUT_V1 to retrieve parameters for multiple network functions, allocating the output buffer according to query_host_net_function_num_max. Validate that firmware does not return more entries than the allocated buffer. This change does not introduce new functionality, but enables the existing mlx5_esw_query_functions() callers to retrieve host PF information with the new layout as well. The mlx5_esw_get_host_pf_info() helper abstracts parsing the command output in both legacy and new formats, so callers do not need to handle the different layouts. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/eswitch.c | 88 +++++++++++++++++-- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 5 +- .../mellanox/mlx5/core/eswitch_offloads.c | 6 +- .../net/ethernet/mellanox/mlx5/core/sriov.c | 2 +- 4 files changed, 89 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.c index 861e79ddb489..8b62dde7eb70 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -1063,11 +1063,28 @@ static int eswitch_vport_event(struct notifier_bloc= k *nb, */ const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev) { - int outlen =3D MLX5_ST_SZ_BYTES(query_esw_functions_out); + bool net_func_v1 =3D MLX5_CAP_GEN(dev, query_host_net_function_v1); u32 in[MLX5_ST_SZ_DW(query_esw_functions_in)] =3D {}; + int alloc_entries; + int outlen; u32 *out; int err; =20 + if (net_func_v1) { + alloc_entries =3D MLX5_CAP_GEN(dev, + query_host_net_function_num_max); + alloc_entries =3D max(alloc_entries, 1); + MLX5_SET(query_esw_functions_in, in, op_mod, + MLX5_QUERY_ESW_FUNC_OP_MOD_LAYOUT_V1); + outlen =3D MLX5_BYTE_OFF(query_esw_functions_out, + net_function_params) + + alloc_entries * MLX5_UN_SZ_BYTES(net_function_params); + outlen =3D max_t(int, outlen, + MLX5_ST_SZ_BYTES(query_esw_functions_out)); + } else { + outlen =3D MLX5_ST_SZ_BYTES(query_esw_functions_out); + } + out =3D kvzalloc(outlen, GFP_KERNEL); if (!out) return ERR_PTR(-ENOMEM); @@ -1076,9 +1093,25 @@ const u32 *mlx5_esw_query_functions(struct mlx5_core= _dev *dev) MLX5_CMD_OP_QUERY_ESW_FUNCTIONS); =20 err =3D mlx5_cmd_exec(dev, in, sizeof(in), out, outlen); - if (!err) - return out; + if (err) + goto free; + + if (net_func_v1) { + int num_entries; + + num_entries =3D MLX5_GET(query_esw_functions_out, out, + net_function_num); + if (num_entries > alloc_entries) { + mlx5_core_warn(dev, "Got %d entries, max expected %d\n", + num_entries, alloc_entries); + err =3D -EINVAL; + goto free; + } + } + + return out; =20 +free: kvfree(out); return ERR_PTR(err); } @@ -1100,12 +1133,55 @@ mlx5_esw_host_pf_from_host_params(const void *entry) }; } =20 -struct mlx5_esw_pf_info mlx5_esw_get_host_pf_info(const u32 *out) +static struct mlx5_esw_pf_info +mlx5_esw_host_pf_from_net_func_params(const u8 *entry, int num_entries) +{ + int i; + + for (i =3D 0; i < num_entries; i++) { + int pf_type, state; + + pf_type =3D MLX5_GET(network_function_params, entry, pci_pf_type); + if (pf_type !=3D MLX5_PCI_PF_TYPE_EXTERNAL_HOST_PF) { + entry +=3D MLX5_UN_SZ_BYTES(net_function_params); + continue; + } + + state =3D MLX5_GET(network_function_params, entry, vhca_state); + + return (struct mlx5_esw_pf_info) { + .pf_disabled =3D state !=3D MLX5_VHCA_STATE_IN_USE, + .num_of_vfs =3D MLX5_GET(network_function_params, + entry, pci_num_vfs), + .total_vfs =3D MLX5_GET(network_function_params, + entry, pci_total_vfs), + .host_number =3D MLX5_GET(network_function_params, + entry, host_number), + }; + } + + /* No external host PF entry found */ + return (struct mlx5_esw_pf_info) { + .pf_not_exist =3D true, + .pf_disabled =3D true, + }; +} + +struct mlx5_esw_pf_info +mlx5_esw_get_host_pf_info(struct mlx5_core_dev *dev, const u32 *out) { const void *entry; =20 entry =3D MLX5_ADDR_OF(query_esw_functions_out, out, net_function_params); =20 + if (MLX5_CAP_GEN(dev, query_host_net_function_v1)) { + int num_entries =3D MLX5_GET(query_esw_functions_out, out, + net_function_num); + + return mlx5_esw_host_pf_from_net_func_params(entry, + num_entries); + } + return mlx5_esw_host_pf_from_host_params(entry); } =20 @@ -1121,7 +1197,7 @@ static int mlx5_esw_host_functions_enabled_query(stru= ct mlx5_eswitch *esw) if (IS_ERR(query_host_out)) return PTR_ERR(query_host_out); =20 - host_pf_info =3D mlx5_esw_get_host_pf_info(query_host_out); + host_pf_info =3D mlx5_esw_get_host_pf_info(esw->dev, query_host_out); esw->esw_funcs.host_funcs_disabled =3D host_pf_info.pf_not_exist; =20 kvfree(query_host_out); @@ -1561,7 +1637,7 @@ mlx5_eswitch_update_num_of_vfs(struct mlx5_eswitch *e= sw, int num_vfs) if (IS_ERR(out)) return; =20 - host_pf_info =3D mlx5_esw_get_host_pf_info(out); + host_pf_info =3D mlx5_esw_get_host_pf_info(esw->dev, out); esw->esw_funcs.num_vfs =3D host_pf_info.num_of_vfs; if (mlx5_core_ec_sriov_enabled(esw->dev)) esw->esw_funcs.num_ec_vfs =3D num_vfs; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.h index cfaae59a6e7c..a5f832ed2251 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -657,7 +657,8 @@ bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *de= v0, struct mlx5_core_dev *dev1); =20 const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev); -struct mlx5_esw_pf_info mlx5_esw_get_host_pf_info(const u32 *out); +struct mlx5_esw_pf_info mlx5_esw_get_host_pf_info(struct mlx5_core_dev *de= v, + const u32 *out); int mlx5_esw_host_pf_enable_hca(struct mlx5_core_dev *dev); int mlx5_esw_host_pf_disable_hca(struct mlx5_core_dev *dev); =20 @@ -986,7 +987,7 @@ static inline const u32 *mlx5_esw_query_functions(struc= t mlx5_core_dev *dev) } =20 static inline struct mlx5_esw_pf_info -mlx5_esw_get_host_pf_info(const u32 *out) +mlx5_esw_get_host_pf_info(struct mlx5_core_dev *dev, const u32 *out) { return (struct mlx5_esw_pf_info) {}; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index 217c2fe6b690..acbc37b05308 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -3716,7 +3716,7 @@ static void esw_vfs_changed_event_handler(struct mlx5= _eswitch *esw) if (IS_ERR(out)) return; =20 - host_pf_info =3D mlx5_esw_get_host_pf_info(out); + host_pf_info =3D mlx5_esw_get_host_pf_info(esw->dev, out); new_num_vfs =3D host_pf_info.num_of_vfs; =20 if (new_num_vfs =3D=3D esw->esw_funcs.num_vfs || host_pf_info.pf_disabled) @@ -3832,7 +3832,7 @@ static int mlx5_esw_host_number_init(struct mlx5_eswi= tch *esw) return PTR_ERR(query_host_out); =20 /* Mark non local controller with non zero controller number. */ - host_pf_info =3D mlx5_esw_get_host_pf_info(query_host_out); + host_pf_info =3D mlx5_esw_get_host_pf_info(esw->dev, query_host_out); esw->offloads.host_number =3D host_pf_info.host_number; kvfree(query_host_out); return 0; @@ -4988,7 +4988,7 @@ int mlx5_devlink_pf_port_fn_state_get(struct devlink_= port *port, if (IS_ERR(query_out)) return PTR_ERR(query_out); =20 - host_pf_info =3D mlx5_esw_get_host_pf_info(query_out); + host_pf_info =3D mlx5_esw_get_host_pf_info(vport->dev, query_out); =20 *opstate =3D host_pf_info.pf_disabled ? DEVLINK_PORT_FN_OPSTATE_DETACHED : diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sriov.c b/drivers/net/= ethernet/mellanox/mlx5/core/sriov.c index 79f76c456d72..0770b5d99c5d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/sriov.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/sriov.c @@ -285,7 +285,7 @@ static u16 mlx5_get_max_vfs(struct mlx5_core_dev *dev) */ if (IS_ERR(out)) goto done; - host_pf_info =3D mlx5_esw_get_host_pf_info(out); + host_pf_info =3D mlx5_esw_get_host_pf_info(dev, out); host_total_vfs =3D host_pf_info.total_vfs; kvfree(out); return host_total_vfs; --=20 2.44.0 From nobody Sat May 30 08:44:25 2026 Received: from CY7PR03CU001.outbound.protection.outlook.com (mail-westcentralusazon11010009.outbound.protection.outlook.com [40.93.198.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C5E3D351C14; Sun, 10 May 2026 05:35:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.198.9 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778391351; cv=fail; b=BeRI3WR/Bz0kD8PX1Ar7rKjGLCWwEiPM2OtD/LgrZW6bPy17hZ6pqMaQ/42dxnEHz0k6650Q9nCCaO/YZbeHxYxv+XxceM9FGIIUFxRgyEikcjfkr8rDOiXEnctUsjNzYg1NJK0Ltk1cbG7fZYrC6gCpTQsd7qmH76u4ySKIhGw= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778391351; c=relaxed/simple; bh=H4hXwnLJFJpfzzGXbiQbvTVznHVhQ8weOqWn+iJaQAk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DcB3RUCPx5i0iNPzkh/oGHMWCBNIeHjlDf6yytWWJeqnUwsh6EvTGr8Ejs3vpFuH9lbYE0rvOTYwEGZ24o16OEp//evaVx6oVGXh26eTuK9ClYAXQg7D7RimL2a/bLiI5Z7G8NWZinXwpmq5haWCBB7K0BgL+/V2FirINK+Y/7k= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=S6D14luy; arc=fail smtp.client-ip=40.93.198.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="S6D14luy" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=aFYetvr4k/JKYWhz/kxfLvoKHD/fUSBsE26/JHxx75VAtgCeV7J1tszI07+Q3dkIcuIRBjqj7DQtWjUVr8vkQKCTL6ixYrNQNJsqzkIAwf3mJg/IgE8YrM3foF0tU+1knkN4wj66DBNBKJ/TeqxnqJQFp83EHZy2d4SB97sx9SynE4CbwLH5bGUf0k8ADpGPOvlb2TK2WPSi0NdW5Saa44fZlXEMx/RGadziF1WrcIR2SaMljx0yQmSCi7dzeBAClesPMBePx3w6StPKu3ksGvSSdbR9hlMKpbt+HHTutYyEMn1/blAVXT7jrUC2tk2aH1m9jKFGQV9LkICIwA218g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=rqNRFrbQML1SBZp9yspiz/OB9A4G0PM5gmJVxRpoUjQ=; b=IBF7JbF4EhupJCT4RBpb3PiLef41PqVghv4ByyBvAptR/3rcbnHJA/X2fVRpZXKeMeRAn6N8bz0UvuOYE7Go5HkGbW58ju2QOiHxZ9z851k8qdl/TkzHoQYKpjKGknPiYw8OBuFOKt3qn4xphnZ8mxpJZlKaUarOK67dxuvoUlFmQOm1a4jXVXjhqtDODc3F/7uWWueHXfGEt4w4wRipWIIOofUKl9eimYAlGHDtMkwNW8Strzc3ULzV1KXYJP9yzT6xn7hmhWLND1LddJGfwH38lSxvry+Y1xuGPcVu14vRa0Z/0TNSoepaZ22kTLVu8wYYYeEIX2fpXsgSLdh98A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=rqNRFrbQML1SBZp9yspiz/OB9A4G0PM5gmJVxRpoUjQ=; b=S6D14luyFPts9zCNtGmdWnlkwsFtQQr5ldCSdxX14zifgJo8FyN+VbzTpRJLVDju+x2aOcb8oyXFIYHdzVolV14BRAYAUubzhZSGNXBNrfTj6z8wT6uCJF8JdmV174EsrvdgHrBJ6lgzfkTlj+T7o+vWz3fU01AjsjR1WoMv97YYtiX5CQe+IvX/4tM63299P6TvqixJm9W0RL/eDZBnoRPQvD04Q3+Y5W9N5x7K8i9DAfkZUAu/aqAl5MY0RANQSzAjFKHIjUdBTrIQ3MsH4GlXZnDdwQQgV7myVJPkT4LRnQhtajqRIGsbjog1ReoOb9jiwfQjgYvSXgTdhL4l0A== Received: from CH0PR03CA0412.namprd03.prod.outlook.com (2603:10b6:610:11b::24) by DS7PR12MB8083.namprd12.prod.outlook.com (2603:10b6:8:e4::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9891.22; Sun, 10 May 2026 05:35:43 +0000 Received: from CH2PEPF0000009C.namprd02.prod.outlook.com (2603:10b6:610:11b:cafe::4c) by CH0PR03CA0412.outlook.office365.com (2603:10b6:610:11b::24) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9891.21 via Frontend Transport; Sun, 10 May 2026 05:35:43 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CH2PEPF0000009C.mail.protection.outlook.com (10.167.244.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.13 via Frontend Transport; Sun, 10 May 2026 05:35:43 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 9 May 2026 22:35:29 -0700 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 9 May 2026 22:35:28 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Sat, 9 May 2026 22:35:24 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Moshe Shemesh" , Akiva Goldberger , , , , Gal Pressman , Dragos Tatulea Subject: [PATCH net-next 3/8] net/mlx5: Use mlx5_eswitch_is_vf_vport() for IPsec VF checks Date: Sun, 10 May 2026 08:34:43 +0300 Message-ID: <20260510053448.326823-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260510053448.326823-1-tariqt@nvidia.com> References: <20260510053448.326823-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009C:EE_|DS7PR12MB8083:EE_ X-MS-Office365-Filtering-Correlation-Id: 0e11fb62-9f3e-4250-b9d5-08deae55faeb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700016|1800799024|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: 6OH/KFANxm2HAzp1IwSZC+hyWenfm+g4VweUY2L/T6IKCboFqYczL9BR7QFeBNkCFiYIykbhyTJNq+1UJZhjM81jFI/3Lo79r+LO9p5OhLnfEyY9c4pQuvrFgIktkrY8YdJcZFjCrPBs8REUjfotgeW57NEWsAvGMtqJmGmTJw/yWyxwH8ujuk313r1TmysC2OhlPY7PI24pC7wmV+z8iUhdZl46EkrmuiwRqguK0NfC0KCelsed2l6vRxy81vKmuy0mfetEO6gQqWMASmIW+A4EZiVPQl6TDrmmtXFqP05+wlGRdLjne1nEMRQ3aBF8narZjuUyeQQQfSBzs7nvLgVCtDQNL/UrskiJGtTqCU4OHDbsm3ok0YzMCwcuzXIF+0nFIK7r19uYrV5DxWYxNsEz/MD3I1qKVoFfccnDAIPHR0HWsB2lkls7mN5evmiTMNXXXQUnPJrRmi5c3XjXKqIoho4Eh8WJmbPKQnKuphQSnf/UonhZ5nFNc1CqRml0+TE0cPiDzuNB+C1LY4LK6DEEdjJ3wbm35HXeiez+uGRUixDLjCj6UTYB581ku5O96FkZNyqPkjq1aJ6gZCo3g3b6NZOn1C3r+WU7kpf+KTLT5SDRErs5sDvcbhXBQn0/lnyf8gCeL2SxGQYisCmeLEdU4Yj6KzTxMpcnx+vN79IauSx/t0PXcSCRD20WvDq8SWFhvmrIzumuTb74lPyu2Kk20zsSol6r8JZy+uqULGo= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700016)(1800799024)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Wrvw32c5tVA3JRnNT9nGbgaO5Mv45J5bgwhtcC6W3+cFo1SoJs87hvSIpnizB+53QFcscweK+a4i1oWHHX1KC8d+9jblmXZgja8I3aWLAKjJUibswG6QC9N+sX2IrT3PY3znQWCbzczUmY5yPauy/5JjE6sNvn7EhhA+nyX8MLNLq6SpDZENcKsI8zXreM4yWT3z3hNq/vD1xgQBKO4vevuotLDYwPKHh8RmkMDltoOenJqt5/ElCQPzePVTHNZf0+x4qHGThT0EvH461BXEIRANJMDmBv5wxzIlkdqFterXqQ9slO6W6FMUUtZiSufTceb34iIfSCPoXMfUhQFPAtgJqhkKNTwj6APD9kyDp16ZXGJFQ8Kl8e+9WABJ3w++RmPrem2I4jTj4V+Mq5Io2FD24xVdDd/KWEm0g9t6zT3rEWeylE9RmEAfViNeaFYw X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2026 05:35:43.6725 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0e11fb62-9f3e-4250-b9d5-08deae55faeb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8083 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh IPsec eswitch offload operations and the enabled_ipsec_vf_count counter are intended for VF vports only. Replace the MLX5_VPORT_HOST_PF checks with mlx5_eswitch_is_vf_vport() to properly identify VF vports, as preparation for adding another type of PF vports. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec.c | 2 +- drivers/net/ethernet/mellanox/mlx5/core/eswitch.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec.c b/drivers/= net/ethernet/mellanox/mlx5/core/esw/ipsec.c index 4811b60ea430..b830ccd91e62 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec.c @@ -209,7 +209,7 @@ static int esw_ipsec_vf_offload_set_bytype(struct mlx5_= eswitch *esw, struct mlx5 struct mlx5_core_dev *dev =3D esw->dev; int err; =20 - if (vport->vport =3D=3D MLX5_VPORT_HOST_PF) + if (!mlx5_eswitch_is_vf_vport(esw, vport->vport)) return -EOPNOTSUPP; =20 if (type =3D=3D MLX5_ESW_VPORT_IPSEC_CRYPTO_OFFLOAD) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.c index 8b62dde7eb70..9a7de7c9a667 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -958,7 +958,7 @@ int mlx5_esw_vport_enable(struct mlx5_eswitch *esw, str= uct mlx5_vport *vport, /* Sync with current vport context */ vport->enabled_events =3D enabled_events; vport->enabled =3D true; - if (vport->vport !=3D MLX5_VPORT_HOST_PF && + if (mlx5_eswitch_is_vf_vport(esw, vport_num) && (vport->info.ipsec_crypto_enabled || vport->info.ipsec_packet_enabled= )) esw->enabled_ipsec_vf_count++; =20 @@ -1020,7 +1020,7 @@ void mlx5_esw_vport_disable(struct mlx5_eswitch *esw,= struct mlx5_vport *vport) mlx5_esw_vport_vhca_id_unmap(esw, vport); } =20 - if (vport->vport !=3D MLX5_VPORT_HOST_PF && + if (mlx5_eswitch_is_vf_vport(esw, vport_num) && (vport->info.ipsec_crypto_enabled || vport->info.ipsec_packet_enabled= )) esw->enabled_ipsec_vf_count--; =20 --=20 2.44.0 From nobody Sat May 30 08:44:25 2026 Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013006.outbound.protection.outlook.com [40.107.201.6]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3ED335504D; Sun, 10 May 2026 05:35:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.201.6 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778391353; cv=fail; b=M3m40SGZBNprtvVcIf9l4BxcJoUEwIMe1g9PJwzPJzQi4cjX72ekxv998tS9BCDmBzu+bry/vHiYjSJy2BTHhLhv9BuYpMm1Teh/DHNhaRPBvG5d/YSM5sPVkQkFI4G0YwyEjSscL3P2tu+6bDe1M8fF1RqjaWO00lTvNKbP8v4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778391353; c=relaxed/simple; bh=KsIjP4CqM/+gQ6LfrqdvKL7QuauvxqQSXB37hJqm0d0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QTBPHJ4ZgrbW3WfN3o9GNFEI0tGszCzrFrMKZe5Lzbs2f25IuPAsfUvQSv353j0BxQCVVoYXlsVRcNpl1sNOWkoTkfabL2ehdov2Re8lghNWe5HtT16dL3P9XhUzH7cr1k+21UnC/78XHRfKQPRBc/6SZCnfRrg1Q+uym5A7CGM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=NWya7THn; arc=fail smtp.client-ip=40.107.201.6 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="NWya7THn" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=BO0S3X0Yt0O/fxGXq49eLXiva+pPKrGG33kpP8aN+f4j3clRLYS/qHLhH1IzpJf0sUsVY4mAyoBl6ulOwOi5pmW0vP/XXogVL5AeyQbwXvEO+V6PTNMmDk5DxYHlwqLlByyFQa5bePc7Gub3sSwWbXsxxvdo3cz5b55b3PP4SXXn6T+jHTDpOgh4WmeUNkNdb4mT9dqy9GbZXuk+nN6BwLGtF0twqImAiKE5SckT7E3KRZ13RBjhVsDBunIN/JIRTIwuCZdANbyf0U4r8AtHBgDCuT/+Mnv2AZi3U0JgEJxSFIrVnTHKjFpoakk6JHc/B0Z+VgmvJbiBrnxzlyOwYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Nxl7uYW8EnJ02wSrfhdGlj6juwCERjMWyIAXJP34RDU=; b=ubzPRh6MRrwy3x+n3kJPdBvl+pdQmjiTdlqIf65bEWvjjJqfKJvtuP7YO2QXxZ89FHxulIxlfmWME4WX5mFzX+Rvqyd35Hj5FBUq01GRfCQE3RN7K4o3hUHRA/xtlcN1L5INTCfrqQzybIiNpauk7c0Xv4pb8NINDiVEMZHejl+012AprbQNxyG3kIOXaKw6brxkxp0i6takiK+mmc2r9j0tJg7zYNB++fB0EN6YZBjyA12nvLJF2ypcwfwdfWel0Y2gQaH0IYfayp8lyrmol7cmOcRdQxep39hyFKhPQGZRl8wvFdDHpO/+9aQwQohJ1oPsQDumef/Xx/zTvfAEew== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Nxl7uYW8EnJ02wSrfhdGlj6juwCERjMWyIAXJP34RDU=; b=NWya7THnzC317T3enhukMOc3GTiAtIqSVHR04J2H4L75S8FfqXY9NHpe69P4ienhqhjWBVo+ABJJ+zb7IP4KQh8aZOjSTGyB3Un7973yGI2oF0AcIfh0YHaahq+jiHh3PhJNHwINMhyM3hKptNQjlWilyoDQOE/HkgVmWCqFpKeuzNLl+CRhyIUqmEPd8pQMs7x+qOdKR0uqZ3jiLX2dPNPQy3xQ3ZGVnRNRvzmjs0aKLHP6JrJTL4Owb4iTUNAokrDUyKKXOB2IvfFJ1Uwk/gsqkfkB21KqyoF2e/U3u+uuvy45Eli5BiinXwtnQPHXL1DDdoYkTwdFAdX/M/H7hg== Received: from CY5PR19CA0047.namprd19.prod.outlook.com (2603:10b6:930:1a::6) by CHXPR12MB999222.namprd12.prod.outlook.com (2603:10b6:610:2f9::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9891.19; Sun, 10 May 2026 05:35:47 +0000 Received: from CH2PEPF0000009B.namprd02.prod.outlook.com (2603:10b6:930:1a:cafe::b8) by CY5PR19CA0047.outlook.office365.com (2603:10b6:930:1a::6) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9891.21 via Frontend Transport; Sun, 10 May 2026 05:35:47 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CH2PEPF0000009B.mail.protection.outlook.com (10.167.244.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.13 via Frontend Transport; Sun, 10 May 2026 05:35:47 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 9 May 2026 22:35:34 -0700 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 9 May 2026 22:35:33 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Sat, 9 May 2026 22:35:29 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Moshe Shemesh" , Akiva Goldberger , , , , Gal Pressman , Dragos Tatulea Subject: [PATCH net-next 4/8] net/mlx5: Switch vport HCA cap helpers to kvzalloc Date: Sun, 10 May 2026 08:34:44 +0300 Message-ID: <20260510053448.326823-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260510053448.326823-1-tariqt@nvidia.com> References: <20260510053448.326823-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009B:EE_|CHXPR12MB999222:EE_ X-MS-Office365-Filtering-Correlation-Id: e5ca4433-0f31-4090-a845-08deae55fcf5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|1800799024|376014|56012099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: Tb2lH8wV3vUeg2Ms3xIcO1g5o4B0VzkONhfwdehfaHDC2KTDHuOenwjDAohwB296xjZHp4+Ni09hDY95tr2b59p6PLpPIdYLq2WGeeywYIEHe4jGnOwKLn+CAtVrXDXS7whOfVUQp/qR9GfRDpjy5ZIEJRHntaTufdSkpOlgcy49Cyki17zrR8K3VIoU0DxgFwVGcn+fjxDQRYQqB/I0hKteQ90MMSKQfSvxFXdcoVLAWtUqmnoguTSEW26Ux+26tXJ3LYCJldqh7T4R1icIjbnJIxS1+HP5SMS7aJdKCStGAMjJFj6ZzcKV64v/tN2zgrhRUAaLEaGCsXozQhhYG0AR/+MnPNcXJm9BKxQERgqtvZ0MA4Iukjh1dTMAM3wldembHolpI5sN+9uhSrXKQjDmTpQhPNcNQwUzNhVjA6R8PE264uPRmXBuNNW/4yyK1CxUzpDCcIK2z4qj2t1+5VFrs5N+f4OgSMsV59K6n1uftk6gL9+lhqwelIlIoXLDSTiCVr2S/X6zgnrh54iqkBMjO5c/fzmYQ74qIELKgBoqiBXYOnzuhjwnIGMobjdWgO+UitFaWE6RCbQiju40k9/9WsD5DElEruiNFEYqeXzQL9pDyzXjsWQCbGQ7+2GKzofkPc04Sq0mEvwdxKVRfdJLU6iGotBeyJJOdlaA4kRal/lIVQRC93eEkBSrc7QpP5NGqlY3cfn5JY99OK/4QXK18ntsb471B6ajuYWuV+g= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(1800799024)(376014)(56012099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: JXYLqI61ahXm+lJ2Hl0cHFgmhKRHzS78Gk/WeHrKhXW12DOCNfcwYI2vSw8raCgzQrHM8EuoTJx7gm4a32Ob8ZPNFIq9Z8B/MgyAEHJc/0QFdKIppcSf0h9vcdKFWqb3/PhJJWgySaTQH9NBjYpAHJH+mmoLXebA0YXVSbsc3xkLP0een6yPY6ny7QjdwfuZcPcY0Zos63DfHSnCnMsCNwafUTHkh9zvnHbsN5efB86i6Ce+PTgw74cJYlsZPulERZ4zMYHiBxdfrb+BSLNUKiy865AjIYiZFXa5PcfGfxw4jyc3bnbpakVMWI7fKg3hjoqHJSkuRpAYfZvLNCuX+Yzxw1F63DYnDZMYuOd5AgOnu2ePLosYdeIuAp4QZiWgIqUDYmEOinuCo6uZFOFEdXRb2JGL0r7Q8P6NvxL6aP9K0BENn7uGB157YGkpUuJR X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2026 05:35:47.1044 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e5ca4433-0f31-4090-a845-08deae55fcf5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CHXPR12MB999222 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh mlx5_vport_set_other_func_cap() and mlx5_vport_get_vhca_id() allocate command buffers that embed the HCA capability union, exceeding 4KiB. Use kvzalloc/kvfree so the allocation can fall back to vmalloc when contiguous memory is scarce. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/vport.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/vport.c b/drivers/net/= ethernet/mellanox/mlx5/core/vport.c index 4effe37fd455..f8e6b1ab7c5c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/vport.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/vport.c @@ -1336,7 +1336,7 @@ int mlx5_vport_get_vhca_id(struct mlx5_core_dev *dev,= u16 vport, u16 *vhca_id) if (mlx5_esw_vport_vhca_id(dev->priv.eswitch, vport, vhca_id)) return 0; =20 - query_ctx =3D kzalloc(query_out_sz, GFP_KERNEL); + query_ctx =3D kvzalloc(query_out_sz, GFP_KERNEL); if (!query_ctx) return -ENOMEM; =20 @@ -1348,7 +1348,7 @@ int mlx5_vport_get_vhca_id(struct mlx5_core_dev *dev,= u16 vport, u16 *vhca_id) *vhca_id =3D MLX5_GET(cmd_hca_cap, hca_caps, vhca_id); =20 out_free: - kfree(query_ctx); + kvfree(query_ctx); return err; } EXPORT_SYMBOL_GPL(mlx5_vport_get_vhca_id); @@ -1363,7 +1363,7 @@ int mlx5_vport_set_other_func_cap(struct mlx5_core_de= v *dev, const void *hca_cap void *set_ctx; int ret; =20 - set_ctx =3D kzalloc(set_sz, GFP_KERNEL); + set_ctx =3D kvzalloc(set_sz, GFP_KERNEL); if (!set_ctx) return -ENOMEM; =20 @@ -1392,6 +1392,6 @@ int mlx5_vport_set_other_func_cap(struct mlx5_core_de= v *dev, const void *hca_cap MLX5_SET(set_hca_cap_in, set_ctx, function_id, function_id); ret =3D mlx5_cmd_exec_in(dev, set_hca_cap, set_ctx); =20 - kfree(set_ctx); + kvfree(set_ctx); return ret; } --=20 2.44.0 From nobody Sat May 30 08:44:25 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012068.outbound.protection.outlook.com [52.101.43.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07A292E6CB8; Sun, 10 May 2026 05:36:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.68 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778391365; cv=fail; b=k7VUuzbdNBi6Gt0YfATdca0Zg+Qihc+lTqn6YHqI7Zwr2JaWcaWiT9q+No0U+BeoaH3ztx2mbXaky/mJVc55yBA+zY5t/zUPM8OS3J5lTDd3hfG+sJFxL8ODt4tLAcEEWLDeIJvf1SVT+vfTM5R+BXfEgPWZJHMhZdr8OujhWo0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778391365; c=relaxed/simple; bh=7cRR3dROHYOZW3uiR7MbvYW6XohxB2YMs3qlyQJfxoo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JcTp6bH1IzxEongoUNtvaXijbu5U2geEqACtHYHAhqzu9qFbUy5PB7x/rnbsnZYrH5BE08Wb2sgkSZtWMNoSk8LfTJNIilRIJYvH2wOMlU1+xqPw4mIOmlXwccHqfW629tOBnd4F+l/hEYinclqAQ1dNvCZrZNoC9IRFJXdCLyg= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=EPiLn2A2; arc=fail smtp.client-ip=52.101.43.68 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="EPiLn2A2" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=pSj8sO738WRlDadG5ED1TsRq4iw2GPRGpjvFbI9ZMh6VDEvDV3r+xOG8VXdw/6MUGSIYYINTyQC05qX0v8U/6h7rrvV6dUHv+RWEkPBCNzMgGo7QVwtcshBOHHp2Iwp4YiiBTPO4hSjaM80yC+IqYA+kEsKQvJigim85QGed3xEjs0DCEPX1/FpOzg8mqxe+ZnHyoBiuloe/dYWZLlBNmOXSV1jFGsayBzCo296f0sI+0ICL0CHZWKiMqS+Wbo6yASYAmMgrybfTMHnBwalizh00vMdCl2TW3IJqo30AjGug5gMAEwp9lIG1sAZZbkNy3IRq/d59bZXdPsx0DLXMSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0eY/nYDpFIEhYnyC1EfCso5ub1d7CkBWH5ne33vU02Y=; b=Qo+MsX4e1nqNaPSMGUmdPHEStgkKXsQ+bGC/pc57ShmYs/pi4pasIKyf9sgw3ELzDBJz581Dp3HllqpU0CoWpq06f8PeUfvNWwZhmmIcWxD6wp7wmOl0F+1Rxd/xFMrZcQDitbbdz3/Ohr3Yx0BF0gpXLxO5miAkStzO3SiLfcFEGRQIcX2UbaySeNQ9tKLEKJ2gV/Ce82eX/dsXaORazkZNe+F1GNHr5xr/tTTEpqmzHu+2WnOX0EjM+MjfbSTYNy8tTXK7YG9++x5oIJXAQQ/j2CnFnz41Q89YamLjj7NRpjO+YNx+O6aHyx3On4t/X/RTfpo14ogjrWumkYSRnw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0eY/nYDpFIEhYnyC1EfCso5ub1d7CkBWH5ne33vU02Y=; b=EPiLn2A26qk5XUP8cZDJpodRJnYQ7OJJratyzAcxFiNFI2uTURpb2VQ3m00TR9UaIOCkSt2zHLMzqxhWq7m3oDH16ZP+NxSaQxS53jtWGxyRMmYPylBaUdd4zUumgWaItJpRRmTy/IFB6ZMjnHO1cCsJtNjuGNXdnHgI5535BMRTaRYSlP1jr+KypbDcBwx1/yAnT1EeE9VnDHEfAKgOOOvOHM8JWaFnWgC/dAj3IQsOl6osuOKMS81h0nbeIJWB7RQ5700WIL4InRP4w9hf/BHpzKXE95o6pwnQ0Pw6D5VbRXB1T7IVg8Olc89r91Vws9g3iMYJ1DqWCS3zOqKuCw== Received: from PH8PR20CA0023.namprd20.prod.outlook.com (2603:10b6:510:23c::29) by DS1PR12MB999188.namprd12.prod.outlook.com (2603:10b6:8:495::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9870.25; Sun, 10 May 2026 05:35:56 +0000 Received: from CY4PEPF0000EE30.namprd05.prod.outlook.com (2603:10b6:510:23c:cafe::c1) by PH8PR20CA0023.outlook.office365.com (2603:10b6:510:23c::29) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9891.22 via Frontend Transport; Sun, 10 May 2026 05:35:55 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CY4PEPF0000EE30.mail.protection.outlook.com (10.167.242.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.13 via Frontend Transport; Sun, 10 May 2026 05:35:55 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 9 May 2026 22:35:39 -0700 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 9 May 2026 22:35:38 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Sat, 9 May 2026 22:35:34 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Moshe Shemesh" , Akiva Goldberger , , , , Gal Pressman , Dragos Tatulea Subject: [PATCH net-next 5/8] net/mlx5: Add mlx5_vport_set_other_func_general_cap macro Date: Sun, 10 May 2026 08:34:45 +0300 Message-ID: <20260510053448.326823-6-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260510053448.326823-1-tariqt@nvidia.com> References: <20260510053448.326823-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE30:EE_|DS1PR12MB999188:EE_ X-MS-Office365-Filtering-Correlation-Id: 7d0cb460-e218-40ef-d202-08deae5601fb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|376014|1800799024|56012099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: UnKJ1D10u8/bAePqg7soFyaPgBZ2ZzG9Zw8UW5Rm8TgLFS81Ivm226oDO0K9G+5BE+C8jnBkzV9jrFiY0yJ89YkvQ8NUsVzYQ5OBrwqxfTgojomVbg1iwhCMVNQwupwuPC8Vk0Wkneik0saO9jcEf26TlC28XeEpluHYntEpwnMdycmvwQeSWAp6OlXVNTXyUC/trZZnqRVwMAsr4lgsPqIScPqQ97FNAnqSNhcZItRq/N48G5x8zoqFPuu8twT+ck4KolzMWz+U8s2/ETE9G6LncVtuFE4NEvhzUKlB/RM0Bq+XCMOLuTOw0SiaBCM+NDKQwPd3zPtEjJg27ciFh+OUAOZkoqdwp8UbNfeCzWxkKbkkzXYSRs1/WAspZrdcscdIm4cclgOLBEEsqZPiqvZVRgL5WYtWrZqmyQ/fHa27On8HZ81zMUB6K4XgtWPJFLo2OGDEdVWayFSIankwaUm2P1UAdDS6iwFRUA6X21HQEqO8tVx2erhNytx6hllMGK5KIqA1QhbASgIvB7uDT3C0gMIuLFRCesL/nXixhYz7ptwsJszY6Dca1y3DMUMxkDBbWsRgJqUSRrAQTPDK8OjFgh9T6IA5GLvEy/oKNZCNoXZAXpqMqEjqXlzQ4KK1G7ko6Ut+GufTAVSaulyWvv7MLXjdlaPbX0NLheX9sKWMJYtrJggX7XqIU89dzQQNzdH/FN8yNEWdUHmyf0mzDLPXVKGhcRXZciE5FanuL5E= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(376014)(1800799024)(56012099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 2HF+yIKl/CUdOhRQfsLDkzkY/f3FzwzMUMhcSmavsDwteMCVFsAzqUPOFRKaOO32+U0Dv9VHwGYwe3BJZnFF8jNIgaKkp3viUGMFgsH84G8bHYmvJ09NIDNJXuCy4cnpY51M820lzD2QDdm/wkmhzTkrqADuBpgmvicf3PDy4lKrJYV+toCvCBWuIN74eUEFOUgw2xo8EH3TgzH1E35wPW58b5mYd4WpEXwWA6dK0vZ4eoGQqMLyh7NfujPyBq51ElfVjB9516zd+skHritXYgePghPfs6uYmipDtqW1R9aahpGkog2NsF5J2+TfU8ae/6PUKV89fwm9ROV4nhOs7YzAmRHe0q2kQjtHRfq+4v4tpPw/MeEoXRcdgPgmAQW9+3Gp+8ag0tMyf9I65lr7JINTkqyO0VKSh637zkKFUSJ/FkXSFWbO1p4Smu3ezZsp X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2026 05:35:55.5816 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7d0cb460-e218-40ef-d202-08deae5601fb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE30.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS1PR12MB999188 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh Add mlx5_vport_set_other_func_general_cap() convenience macro, symmetric to the existing mlx5_vport_get_other_func_general_cap(), and use it in mlx5_devlink_port_fn_roce_set(). No functional change in this patch. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c | 4 ++-- drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h | 4 ++++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index acbc37b05308..b06b10d443bd 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -4951,8 +4951,8 @@ int mlx5_devlink_port_fn_roce_set(struct devlink_port= *port, bool enable, hca_caps =3D MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability); MLX5_SET(cmd_hca_cap, hca_caps, roce, enable); =20 - err =3D mlx5_vport_set_other_func_cap(esw->dev, hca_caps, vport_num, - MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); + err =3D mlx5_vport_set_other_func_general_cap(esw->dev, hca_caps, + vport_num); if (err) { NL_SET_ERR_MSG_MOD(extack, "Failed setting HCA roce cap"); goto out_free; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h b/drivers/= net/ethernet/mellanox/mlx5/core/mlx5_core.h index d70907f499a9..2eba141bd521 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h @@ -457,6 +457,10 @@ int mlx5_vport_set_other_func_cap(struct mlx5_core_dev= *dev, const void *hca_cap #define mlx5_vport_get_other_func_general_cap(dev, vport, out) \ mlx5_vport_get_other_func_cap(dev, vport, out, MLX5_CAP_GENERAL) =20 +#define mlx5_vport_set_other_func_general_cap(dev, hca_cap, vport) \ + mlx5_vport_set_other_func_cap(dev, hca_cap, vport, \ + MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE) + static inline u32 mlx5_sriov_get_vf_total_msix(struct pci_dev *pdev) { struct mlx5_core_dev *dev =3D pci_get_drvdata(pdev); --=20 2.44.0 From nobody Sat May 30 08:44:25 2026 Received: from BN8PR05CU002.outbound.protection.outlook.com (mail-eastus2azon11011050.outbound.protection.outlook.com [52.101.57.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D948934DCC7; Sun, 10 May 2026 05:36:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.57.50 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778391368; cv=fail; b=Q8c2c3Rvu0wbIxnf9xFL6IsxzUw/Asoami/MbEU66pANWfw7VZv5Wvpb0agr1iGhZdLqTp3gO77I07zuzCq2go/wy8OoMUv2/Z/a9nSdKiyo1p2sd7pEq7JKkecD/IpGfo+n0XyYGvj8mBRwBq0S1ZZDYSBr0Zf6Idf0xWegZuc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778391368; c=relaxed/simple; bh=tQGfnkH9F4I81N/g/P3ZmdfBdICToAbIKUkaztMRL/M=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TOE5RDUkwdsaEyVX4jEHtDuT9S3badvS+k3HXE9fxBUA6AvLrxNEkfQL0sgbVUHdS4WH2rfzMraWb6d2TcxGiaL7Jp7+rvVR4mRfuErL9DyFmpWdMzI7RNXO4nJXgulCv4H48tQAJT6v1m6OzrUKLQ1TSbiE7HywmaoOiRMUFU0= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=FsmxJSed; arc=fail smtp.client-ip=52.101.57.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="FsmxJSed" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=yct9fsiaBAU5rE7y8u1KmK5RnXHfIOTQ16tgZd7bZb1IqSFkkxTM28VWMplUl4KG++XEuqLB1SfX9bA14crElmARqxGoH6HoMxP6gP8PGLV3kRFM+IcnPXA1HRJhvBb00cpfhQ2gl72rrC7z32PVHyQmx5C+4v09YlH9SMv8eRKLWgganJXOcgvScPZn9xC8TacR1/W29VB+AEodczEUhr+Ga08kXRnfDX/JYE7kW0cghQjHmytnQsM5vKM/5ywJTojlRjYmPXA6RH+6Vjfm6xKNCvAY/U7JOVfBP/YWDrIyjXtoCAQDcCicyXIafCpINmycGv7BlgcRZ/H9Z0DPtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=y+MCUb8TmhXN5OyMFxVX6ZGv5Yl8Zo6tIBlnxEBQmPU=; b=RugCd+hRTY8BgTOagEys+qC4zysi/hX/A2hT5ZclY//wZcpWdPs9XxVWXLzvwF4hVIXnUUAriCZkHn1In2bCZw1UGhakUy6hSF7bbXUx2/33rgveB5RgpsnXY+pe5v4RKG9jHV0BMHxrFThqkqhyBbxIGuXCMp5IndIy/XE/6phvfaaxy23MBfVXzf6tkTWtMIYyOV7zbLPw4e5MablrlgXB1AabA5DEgZr6Ekp/p+LkEkrtAmdNbYjf4Uu9ZY9oT7cjJllEeB5h+5wzONolaFBOrZDjCdgsW0IlaAdkaGsqaSnWY+1o9LAOL5Ofb6jgbo7YkBSOSd39co5qSQoFtQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=y+MCUb8TmhXN5OyMFxVX6ZGv5Yl8Zo6tIBlnxEBQmPU=; b=FsmxJSedvLLZ4/y+BjBy8gGViFD/BP/PEIXmONkzwGiZo0BtgkQL4W8LZ485ElrPa/98JV+R4ysUEpc/OjZ05u+wLqmiylW19LqmpHZPfOo3gvtJ+ZxgKVxIBi7g0RTwU+Jc7Sh16TMVBT/UUaI7IrWy0yLM1JUB+kqdd52W4ZSbu2gqmMwJL02u98ymMfulHX9nuGhzH79fiE9O92JpkLB8cmR/dGBYQhBB3i5HHHmmCzAthwER21KIb/n8a7N0rLgNWT/2XX7JLMPlQWJYQGX0l2VTKhkVlAmxUpfb5EqtgIDesSXMWoSN6Rr5IcN5YXpd3KJFLK/eCksWBwu0aA== Received: from CY8P222CA0024.NAMP222.PROD.OUTLOOK.COM (2603:10b6:930:6b::9) by IA1PR12MB8466.namprd12.prod.outlook.com (2603:10b6:208:44b::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9891.21; Sun, 10 May 2026 05:36:00 +0000 Received: from CH2PEPF0000009A.namprd02.prod.outlook.com (2603:10b6:930:6b:cafe::4c) by CY8P222CA0024.outlook.office365.com (2603:10b6:930:6b::9) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9891.22 via Frontend Transport; Sun, 10 May 2026 05:36:00 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CH2PEPF0000009A.mail.protection.outlook.com (10.167.244.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.13 via Frontend Transport; Sun, 10 May 2026 05:35:59 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 9 May 2026 22:35:44 -0700 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 9 May 2026 22:35:43 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Sat, 9 May 2026 22:35:39 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Moshe Shemesh" , Akiva Goldberger , , , , Gal Pressman , Dragos Tatulea Subject: [PATCH net-next 6/8] net/mlx5: Refactor mlx5_set_msix_vec_count() SET_HCA_CAP Date: Sun, 10 May 2026 08:34:46 +0300 Message-ID: <20260510053448.326823-7-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260510053448.326823-1-tariqt@nvidia.com> References: <20260510053448.326823-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009A:EE_|IA1PR12MB8466:EE_ X-MS-Office365-Filtering-Correlation-Id: 826df3ef-f497-4338-e127-08deae560492 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|376014|1800799024|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: Y6kXtaZ2boidPy1NoljGNJzBPupHYE7wuUBBX0VQmmIRNpdRUHBEKlTSGXMN3NqIji7zkMOAjrc0iWSzEk7ddX8ewmnhyJynmouXvFfuxNnsmA6D1lNM+ARAeXGc79YoSJ76rrGc/j9rv7G6F4BQjLacI3zmmEjrx+j3GLXKiXTQpG6TgF4Rb1p3GL59m0AnKKlNR1A+Y0C6chBp9VLv7Qjit/dp1SJA61xdaMcCSDZ5YuYsszMczyPUKNorLXPuvImA/Thpzd3n+AQRmEgcD9qLgYsNxi6F/JLjBeAg9bLEzpSzntMQnBYzlsRokM3a4vKHMDKExW+en5j9XuXhMtY1LejaK6wop7s1KcX4IpBJ+uQwNk+O9ZsJIEaYkK5F/ZaP4i3s+Uo+SNoam/NBzCJmkQgb5B84ZThg5uFbfQ1IO922SGhBQUKCJyzeFItxJW41frU3MdNLKQUkH56emxwOspafGepfzeuvXhfD4CMMxPq8XeFYoDzUWnh45N5+D6KQ8cjSjT7F3t9cXU/SY43NVKNgPXVB26mNs54F8UoKo9ec7UGFff5i/VLmoXovCStyCtAywtCIPnaKPPZfqk57M5hflZTyo/j89Lb7qcx6VgDYDmzxnYh7775UMjlYnxVR7uCVjftTXi4L+mFtae00ECX7FKVF5TB8hc+0Ey6Zak9L5m4oLPLm/qXF89mxy1ZO0itpnEkalB6R1S99Z9vkfQ0gnjRBJ6bd4fkvp8U= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(376014)(1800799024)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: sgiwLIkW1MK0CclGEzRV2rf0M6Py59jerF0bYNKoGzxrgRilMbADfOOFoblQ9EzYzvao4eC6iFn8FRgB8rvLh7Fuf3INW17l17pQyC1uxwVXkKhL+RZZqL55hJ2mL97Ghpnhv+OjoMlyPoYGSyRtj2mUmPHd7KYzvJoDW2DvmoLcjBF5eUI44UJzboQl3vgZVPe8+sokX9pwDsh/koeAFD65t2kPOfoRS9+nb6HdAoc9JUDS/XI4m90sq9m6JmuRUGbDz6Zw3O7djAEfl1TS/3EQoPuZSGDPdn2fBbwuv4KYogGijxPyoDlqgFjeI6X6bsPm6AvFP9hoavdR59i/2PDajL3RMgNz3vWtX5k27sIvJxPVqu8vm8YDEP1EWFRs68ZEhKFcywfOb+8tqODEdr6t0/2854D2eDpF0QSpjp4n4rTpKU7N043nVzIMaFns X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2026 05:35:59.8791 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 826df3ef-f497-4338-e127-08deae560492 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8466 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh Use mlx5_vport_set_other_func_general_cap() instead of open-coding the SET_HCA_CAP command. This removes redundant buffer allocation and ensures consistent use of vport-based function addressing. mlx5_vport_set_other_func_general_cap() supports both function_id and vhca_id based addressing, so this also enables SET_HCA_CAP for vhca_id indexed functions which was not supported before. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/pci_irq.c | 27 +++++-------------- 1 file changed, 7 insertions(+), 20 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/pci_irq.c index e051b9a939ee..0f5b8bc7861e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c @@ -87,9 +87,8 @@ int mlx5_set_msix_vec_count(struct mlx5_core_dev *dev, in= t function_id, int msix_vec_count) { int query_sz =3D MLX5_ST_SZ_BYTES(query_hca_cap_out); - int set_sz =3D MLX5_ST_SZ_BYTES(set_hca_cap_in); - void *hca_cap =3D NULL, *query_cap =3D NULL, *cap; int num_vf_msix, min_msix, max_msix; + void *query_cap, *hca_caps; bool ec_vf_function; int vport; int ret; @@ -111,11 +110,8 @@ int mlx5_set_msix_vec_count(struct mlx5_core_dev *dev,= int function_id, return -EOVERFLOW; =20 query_cap =3D kvzalloc(query_sz, GFP_KERNEL); - hca_cap =3D kvzalloc(set_sz, GFP_KERNEL); - if (!hca_cap || !query_cap) { - ret =3D -ENOMEM; - goto out; - } + if (!query_cap) + return -ENOMEM; =20 ec_vf_function =3D mlx5_core_ec_sriov_enabled(dev); vport =3D mlx5_core_func_to_vport(dev, function_id, ec_vf_function); @@ -123,21 +119,12 @@ int mlx5_set_msix_vec_count(struct mlx5_core_dev *dev= , int function_id, if (ret) goto out; =20 - cap =3D MLX5_ADDR_OF(set_hca_cap_in, hca_cap, capability); - memcpy(cap, MLX5_ADDR_OF(query_hca_cap_out, query_cap, capability), - MLX5_UN_SZ_BYTES(hca_cap_union)); - MLX5_SET(cmd_hca_cap, cap, dynamic_msix_table_size, msix_vec_count); - - MLX5_SET(set_hca_cap_in, hca_cap, opcode, MLX5_CMD_OP_SET_HCA_CAP); - MLX5_SET(set_hca_cap_in, hca_cap, other_function, 1); - MLX5_SET(set_hca_cap_in, hca_cap, ec_vf_function, ec_vf_function); - MLX5_SET(set_hca_cap_in, hca_cap, function_id, function_id); + hca_caps =3D MLX5_ADDR_OF(query_hca_cap_out, query_cap, capability); + MLX5_SET(cmd_hca_cap, hca_caps, dynamic_msix_table_size, + msix_vec_count); =20 - MLX5_SET(set_hca_cap_in, hca_cap, op_mod, - MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE << 1); - ret =3D mlx5_cmd_exec_in(dev, set_hca_cap, hca_cap); + ret =3D mlx5_vport_set_other_func_general_cap(dev, hca_caps, vport); out: - kvfree(hca_cap); kvfree(query_cap); return ret; } --=20 2.44.0 From nobody Sat May 30 08:44:25 2026 Received: from CY7PR03CU001.outbound.protection.outlook.com (mail-westcentralusazon11010041.outbound.protection.outlook.com [40.93.198.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F299351C25; Sun, 10 May 2026 05:36:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.198.41 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778391377; cv=fail; b=VxR2oHhI2we5SUyJC16Z3jjVj7hlw7MM17CrfF+/j2jrU3CCChu2VfylFhX9XZ09XvZHtBf1v6zkIO0Zyt6gKCfXY+sKWeDDeH7K8fDORQBYGGRCnNdVdDILfouWA8fXkchPEpAT6nbd9bfSLNqqZvBgwsMGSQ4ljXjHVyo/7Bk= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778391377; c=relaxed/simple; bh=dmlHeHL3Vzwqv3Pn5dynHIgWA43cpXX22f9yw+PrbfE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=t2Ax/vu3chMA5khG03M22N1iQIHAJEqkjFLGkK9zVBNkSykrWBTDXJ69n4Sy/NYLon0fZ1rExQ42/8Pt7xkL/OOcGBwFoMqF1S6GUiz+r/+/Pa6y8gR1ofGO2706D+byaQgqXCx4uu+6+W/cNE8l4aMzN6PpoEMJR9iGGhgZJsQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=VhySzxE8; arc=fail smtp.client-ip=40.93.198.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="VhySzxE8" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=GRm7qdd2gM748NcKLvA90n4ry5TCKRsm1TR5ximAUXOJ5HFHyW4ib9d0duWW9nNgkM8rE/ub5gznL0napSS/6/nBLH3miLZMsEH9J/1X1VyfLE9mYHWoMlKrINHwl2w5UrB/OXwx1jwU37CILcwVQUPfmtjOzqF3mViTg13aT9kKyo+ojQQJyuD6jAhLlR1uWp4rg/+qLogIk7/c19tIfAsInd/i+nfdPF76VHmzNmDn6jercy0E5jry6iAvjNj9UCvTsLO/qzgU6cw5KU+OlYZQfs32dRG98JO3lkCzQqX9znAZWX/xw3d9Ic7NhrMJLiH4gIeU3GLazU4w05sE6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=k//5NYtzwYj9LoHrlzJhqgt85UtgcgQD4sdpBuoEwRQ=; b=qH0o/dsFypylApzKwMLLU3vVosaguSPmR7G/dSDJRm+eCSyRJ7uDBaF8KlzvJ9AKSefnpfhETuWdr0QJhFZ59pGi2wNB3gJW58MR86MveSyY08OyH+2TN4RusbKDRtE+9KYjWyZ0Q2P7CvJiOa6Anvv7iLZ/QL0UtX6jGXN1N491+uGKaa2rbDgYA/2+ZoaR0JDhXjkTuZJt7MODmgDX7gixWR3bfblnBBsFJBlIF6ajqTKNEUS4ksV5YO6fw6E+gWXuFmtv6c1mBPCPbI2w2iCc7DDdGKcwelBSp024nq1/hg5okr6vtOMB75DdkqYsFXKfoB9i+Owx0l2IkW6Qcw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=k//5NYtzwYj9LoHrlzJhqgt85UtgcgQD4sdpBuoEwRQ=; b=VhySzxE8c+TVD6FV6n7Y0Zxh1ELa6QVW1gk5v8FnHOesXRYOBVtTKVTjV3yKuIBhTdLUZvobhcvLFFoZbhPFy+5PQveJq1WaRv4I0dOG1B8cN2KTPKyAwPV8tneDd+hIeOM0RixVaEM2fRIS4D/LWrIRHq5Pc4VgOLil0nnYTKn8lGDVjFMRpQrJStJrxlU/j08zS6EHVjQLNwzeQeFQs5/Do87R/FpS119gzOJbuhnD1d+zzMniM8PvwKHrzHsyoT/k0XEDht8VL+p+KQSjMASXCr+1rD1EzZo9jLPfJR1IETGWvQSEeVo8MzPbNZRRJxq/Ev4Tqq5JgUUzLIP3qw== Received: from PH8PR20CA0022.namprd20.prod.outlook.com (2603:10b6:510:23c::22) by SA0PR12MB4365.namprd12.prod.outlook.com (2603:10b6:806:96::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9891.19; Sun, 10 May 2026 05:36:11 +0000 Received: from CY4PEPF0000EE30.namprd05.prod.outlook.com (2603:10b6:510:23c:cafe::24) by PH8PR20CA0022.outlook.office365.com (2603:10b6:510:23c::22) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9891.22 via Frontend Transport; Sun, 10 May 2026 05:36:11 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CY4PEPF0000EE30.mail.protection.outlook.com (10.167.242.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.13 via Frontend Transport; Sun, 10 May 2026 05:36:11 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 9 May 2026 22:35:49 -0700 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 9 May 2026 22:35:48 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Sat, 9 May 2026 22:35:44 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Moshe Shemesh" , Akiva Goldberger , , , , Gal Pressman , Dragos Tatulea Subject: [PATCH net-next 7/8] net/mlx5: Use vport helper for IPsec eswitch set caps Date: Sun, 10 May 2026 08:34:47 +0300 Message-ID: <20260510053448.326823-8-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260510053448.326823-1-tariqt@nvidia.com> References: <20260510053448.326823-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE30:EE_|SA0PR12MB4365:EE_ X-MS-Office365-Filtering-Correlation-Id: 525a058c-8816-4c85-3d43-08deae560b76 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|82310400026|1800799024|56012099003|18002099003|22082099003|3023799003; X-Microsoft-Antispam-Message-Info: 8yK1zJhxe/hxkeXZzA2z7Kgo3tCZK6tJ16BKhgY96qcFjz3uDxp5ZjsdSjYjaPhdaY0LZMpfaQw4KrXVBX2nxITtJpGaxPHxIXY34ccW5j3d3lRsnK9Ef8NRhrv/t+u3+h2bhtsM8tMuYidQ3seMnBewBlAJ9bfCA4Wumz4PWSPjKrL67vIzHSr0vx+k1PXYqPjruW+saFXxw1gtQqoO5Ks45NXJVS2p3OJ7WlFkS3KThk2gB+s1I0odq0O5Q0ImmPFnEvQh8OVyr+3hHEJjxEUPkiTBY9YXJRZQCVzbsO5uXeHXQZ/9KY1Nk6gSGEej11pawYegkkn/TR8BnXa0GVgRlqG+fqZ6raqlxKV/UlMN/4U6EypaVueKcfsZ7eVCKbQ744ZU0fJwWET2bWc/fIyBQ+TIhSzvC4jYz6cx7LCsqsZHS4/rIwVTZIo+FsGsrBFRP6mHCF5nVo8UbWjcFTx/803L7Mqw47qFID1IGNTFkxZatRwS9HwhEbxr6WIDuk53bTNlLPnPaQnl0lykNqwv4iFpQce0QUuuVzmHkEWjMMHMemDz5PbmWjPXI80Atah72fSWmebn/tSKdySN79AxZYyfJqHi810MPoTn+2HK0BAKtkVYG66TEV5uZYi1aJZwZUqtqmDHhcyo/po5XDWwcytRn1xFgCgKybhoTjj6UxJfYBVOd9a6yOPwuF5yYsEaj0Bs7CeO4jcm+bHHznVUgqwAFOiwOkBbKS3zQcg= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(376014)(82310400026)(1800799024)(56012099003)(18002099003)(22082099003)(3023799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: BPL3zN6IavYaNtdyOt/jrswmjVpHuKKC94zQGzIIo2zvT+jf3VlmzesvkvduKahKre99WhhhTQeEaxE2T+39BcU3UTO4Heh2nUPxpIxb1sH+yXFhjQii9xR6u9BA1D6IyOmAe2BAJQxmrcSRZP8F/NRneU3gg7aVHALD1KZFrwUqViq7AFJDfocRQs4FtEP3/e7oZNLI7DePT7759W1ogh58SMBJss/Em60513v2z2qVAWB1kORGg/6TKV/1Y+JL5f8fhSjNp9nVG3coDA1TT+9Dg25y1w69rKVtYHy1VlR4ZskU4nTPJungskd8rCYUxDA3/VvyQKKqeDJVse3vO7jsjtuC831Bgzzc43y3LvrwoJqysc4TMA6hfo8dtJA5fTGBUghkm37BNgYaxw7324/GAwmDkX+ULvrQ2sNhTUQ1V+6j28aSFS26BnR8bYpJ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2026 05:36:11.4881 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 525a058c-8816-4c85-3d43-08deae560b76 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE30.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4365 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh Use mlx5_vport_set_other_func_cap() and mlx5_vport_set_other_func_general_cap() in the IPsec eswitch functions instead of open-coding the SET_HCA_CAP command. This removes redundant buffer allocation and boilerplate, and also enables vhca_id based addressing when supported. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/esw/ipsec.c | 81 ++++++------------- 1 file changed, 23 insertions(+), 58 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec.c b/drivers/= net/ethernet/mellanox/mlx5/core/esw/ipsec.c index b830ccd91e62..2b5765ab60d1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec.c @@ -81,38 +81,25 @@ int mlx5_esw_ipsec_vf_offload_get(struct mlx5_core_dev = *dev, struct mlx5_vport * static int esw_ipsec_vf_set_generic(struct mlx5_core_dev *dev, u16 vport_n= um, bool ipsec_ofld) { int query_sz =3D MLX5_ST_SZ_BYTES(query_hca_cap_out); - int set_sz =3D MLX5_ST_SZ_BYTES(set_hca_cap_in); - void *hca_cap, *query_cap, *cap; + void *query_cap, *hca_caps; int ret; =20 if (!MLX5_CAP_GEN(dev, vhca_resource_manager)) return -EOPNOTSUPP; =20 query_cap =3D kvzalloc(query_sz, GFP_KERNEL); - hca_cap =3D kvzalloc(set_sz, GFP_KERNEL); - if (!hca_cap || !query_cap) { - ret =3D -ENOMEM; - goto free; - } + if (!query_cap) + return -ENOMEM; =20 ret =3D mlx5_vport_get_other_func_general_cap(dev, vport_num, query_cap); if (ret) goto free; =20 - cap =3D MLX5_ADDR_OF(set_hca_cap_in, hca_cap, capability); - memcpy(cap, MLX5_ADDR_OF(query_hca_cap_out, query_cap, capability), - MLX5_UN_SZ_BYTES(hca_cap_union)); - MLX5_SET(cmd_hca_cap, cap, ipsec_offload, ipsec_ofld); + hca_caps =3D MLX5_ADDR_OF(query_hca_cap_out, query_cap, capability); + MLX5_SET(cmd_hca_cap, hca_caps, ipsec_offload, ipsec_ofld); =20 - MLX5_SET(set_hca_cap_in, hca_cap, opcode, MLX5_CMD_OP_SET_HCA_CAP); - MLX5_SET(set_hca_cap_in, hca_cap, other_function, 1); - MLX5_SET(set_hca_cap_in, hca_cap, function_id, vport_num); - - MLX5_SET(set_hca_cap_in, hca_cap, op_mod, - MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE << 1); - ret =3D mlx5_cmd_exec_in(dev, set_hca_cap, hca_cap); + ret =3D mlx5_vport_set_other_func_general_cap(dev, hca_caps, vport_num); free: - kvfree(hca_cap); kvfree(query_cap); return ret; } @@ -121,49 +108,37 @@ static int esw_ipsec_vf_set_bytype(struct mlx5_core_d= ev *dev, struct mlx5_vport bool enable, enum esw_vport_ipsec_offload type) { int query_sz =3D MLX5_ST_SZ_BYTES(query_hca_cap_out); - int set_sz =3D MLX5_ST_SZ_BYTES(set_hca_cap_in); - void *hca_cap, *query_cap, *cap; + void *query_cap, *hca_caps; int ret; =20 if (!MLX5_CAP_GEN(dev, vhca_resource_manager)) return -EOPNOTSUPP; =20 query_cap =3D kvzalloc(query_sz, GFP_KERNEL); - hca_cap =3D kvzalloc(set_sz, GFP_KERNEL); - if (!hca_cap || !query_cap) { - ret =3D -ENOMEM; - goto free; - } + if (!query_cap) + return -ENOMEM; =20 ret =3D mlx5_vport_get_other_func_cap(dev, vport->vport, query_cap, MLX5_= CAP_IPSEC); if (ret) goto free; =20 - cap =3D MLX5_ADDR_OF(set_hca_cap_in, hca_cap, capability); - memcpy(cap, MLX5_ADDR_OF(query_hca_cap_out, query_cap, capability), - MLX5_UN_SZ_BYTES(hca_cap_union)); + hca_caps =3D MLX5_ADDR_OF(query_hca_cap_out, query_cap, capability); =20 switch (type) { case MLX5_ESW_VPORT_IPSEC_CRYPTO_OFFLOAD: - MLX5_SET(ipsec_cap, cap, ipsec_crypto_offload, enable); + MLX5_SET(ipsec_cap, hca_caps, ipsec_crypto_offload, enable); break; case MLX5_ESW_VPORT_IPSEC_PACKET_OFFLOAD: - MLX5_SET(ipsec_cap, cap, ipsec_full_offload, enable); + MLX5_SET(ipsec_cap, hca_caps, ipsec_full_offload, enable); break; default: ret =3D -EOPNOTSUPP; goto free; } =20 - MLX5_SET(set_hca_cap_in, hca_cap, opcode, MLX5_CMD_OP_SET_HCA_CAP); - MLX5_SET(set_hca_cap_in, hca_cap, other_function, 1); - MLX5_SET(set_hca_cap_in, hca_cap, function_id, vport->vport); - - MLX5_SET(set_hca_cap_in, hca_cap, op_mod, - MLX5_SET_HCA_CAP_OP_MOD_IPSEC << 1); - ret =3D mlx5_cmd_exec_in(dev, set_hca_cap, hca_cap); + ret =3D mlx5_vport_set_other_func_cap(dev, hca_caps, vport->vport, + MLX5_SET_HCA_CAP_OP_MOD_IPSEC); free: - kvfree(hca_cap); kvfree(query_cap); return ret; } @@ -171,34 +146,24 @@ static int esw_ipsec_vf_set_bytype(struct mlx5_core_d= ev *dev, struct mlx5_vport static int esw_ipsec_vf_crypto_aux_caps_set(struct mlx5_core_dev *dev, u16= vport_num, bool enable) { int query_sz =3D MLX5_ST_SZ_BYTES(query_hca_cap_out); - int set_sz =3D MLX5_ST_SZ_BYTES(set_hca_cap_in); - struct mlx5_eswitch *esw =3D dev->priv.eswitch; - void *hca_cap, *query_cap, *cap; + void *query_cap, *hca_caps; int ret; =20 query_cap =3D kvzalloc(query_sz, GFP_KERNEL); - hca_cap =3D kvzalloc(set_sz, GFP_KERNEL); - if (!hca_cap || !query_cap) { - ret =3D -ENOMEM; - goto free; - } + if (!query_cap) + return -ENOMEM; =20 ret =3D mlx5_vport_get_other_func_cap(dev, vport_num, query_cap, MLX5_CAP= _ETHERNET_OFFLOADS); if (ret) goto free; =20 - cap =3D MLX5_ADDR_OF(set_hca_cap_in, hca_cap, capability); - memcpy(cap, MLX5_ADDR_OF(query_hca_cap_out, query_cap, capability), - MLX5_UN_SZ_BYTES(hca_cap_union)); - MLX5_SET(per_protocol_networking_offload_caps, cap, insert_trailer, enabl= e); - MLX5_SET(set_hca_cap_in, hca_cap, opcode, MLX5_CMD_OP_SET_HCA_CAP); - MLX5_SET(set_hca_cap_in, hca_cap, other_function, 1); - MLX5_SET(set_hca_cap_in, hca_cap, function_id, vport_num); - MLX5_SET(set_hca_cap_in, hca_cap, op_mod, - MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS << 1); - ret =3D mlx5_cmd_exec_in(esw->dev, set_hca_cap, hca_cap); + hca_caps =3D MLX5_ADDR_OF(query_hca_cap_out, query_cap, capability); + MLX5_SET(per_protocol_networking_offload_caps, hca_caps, + insert_trailer, enable); + + ret =3D mlx5_vport_set_other_func_cap(dev, hca_caps, vport_num, + MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS); free: - kvfree(hca_cap); kvfree(query_cap); return ret; } --=20 2.44.0 From nobody Sat May 30 08:44:25 2026 Received: from DM1PR04CU001.outbound.protection.outlook.com (mail-centralusazon11010055.outbound.protection.outlook.com [52.101.61.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D59CB351C1F; Sun, 10 May 2026 05:36:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.61.55 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778391377; cv=fail; b=pCnyLZj67iC4rRiP1C+ZS0CJ6KAlu//6qwQx+BPUluh+ZGYHPiPkZ/gtpfU/FnTHdCQEJw1tSDXvlgCrle019Y55UrLaPiR0V4Up7k1TLd2RoRkyqaZnh1HK+/MbJnHDGY8gWSCb4EROZwDEn3z4TNStCqy8ToLaGx+WxpBZphI= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778391377; c=relaxed/simple; bh=FJ6bNCM82zoO7lIe7vpOQAMzjmUIXErxyMPLeIIyudg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Qut/1w8rGzmqmy508gTv/LO1a/FvOy12pDStUER/euq5GZf62Mux55wurHOrkzr1Vjo/xeBABtwHVWNBzo7P99lBQW2z0fr0RdJPfcTguYHWxI90Z29Xpw14ZgxwZ6B1ACBSkjm0paJ/+NIu/5idJblWHAc7/1ZgdYd2RFYsv58= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=qbyvBs96; arc=fail smtp.client-ip=52.101.61.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="qbyvBs96" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=So1BN2/u30iJ7+W93J2hR9fGpADO+TUY3OwzewWDfcID/S5JFF1g1gRUGdcfdX8/VG/uzUZnc2f79/kb4dwzr8eM3RR+tAH3P295zu1dYfEuVZZaRrhzIoC/sFND55Lwn9ah2yEzGNiwIiEQCr17C/ZST5ggqZVHCtL1i8rZa+UNfmUSTB+b9h6y/1leUw5fIPZ2IT4j1bqnRrrZ90A4mO0BxQB8fQYfV20I/kZNelVR22DFAZujb2QVXmTLxu7Uy47xMsptmImgRVjI+xQLVoclZGssbFlHAvOuvweHZHqMQcf6C96ulwQExy8hUxiyqbvwDvj0AKk3ja7EzAO8wA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=WquzEuT3uild5hfbMR7BosqzCK7/3Xcu7d7smLcN4/w=; b=v2jRiAU23yGIh4uYMwXFKsxuA6F3mwyEkggaA1OWPu25i5pxlnj8q5PDv60F17iD2iHURLCFQ/Hq/SQyeuu4uYAV2ApmoFd6lgDJY109QIpbq0IvX9kdrd6xtVuqT6YznjiNJ9QZu233iBMjTNPRAByMV+epW0Ip276qwlgckPTAlbA+VpQWrC5PwMI31hgryUM0GLG6kfaTpBXGqYTLk8vZE8cZZmEkikvAeu9mMoezTHV3DkFmpCluSrJ/72IRsMbq0/MMQyAVKcPa4epqeDmVgA0y1YHF+FGevHbJXJXEvPgGHSKpj6PKtQDdWqxazUw1SYVlzPXk/loyb9oPJw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=WquzEuT3uild5hfbMR7BosqzCK7/3Xcu7d7smLcN4/w=; b=qbyvBs96hTQHAM63gXXW6+kRAanDVvLZK98bxzsa/aODrn+eWKQVOSQ0VLLl1ZrHUmt3K5ToehImgUsUyKwstnXDr4qgK/LbUr+kuL5DK3f4dlWMwOpbTV8VL3qybP+1s0z8AtssjUaXBa1DBmguqagzoP7LvaRM3fMSO7HJl4KLkX6tTxypFZNAUx4073M0wXd0hmpxP2vfVUCShg4ZAWNNzleI1LmqQ1DFtDv1W5HWm9qbdyLsr6Ak3U+G18fEREtohjBvQNjmxe+XqT5r4nz2VR0KUCCbYkq6e6ojwY+4t5+3vzstPzvlDNTUpgVsjHVauve0TeyYdOTLYnVrwA== Received: from CH2PR17CA0030.namprd17.prod.outlook.com (2603:10b6:610:53::40) by MW6PR12MB8897.namprd12.prod.outlook.com (2603:10b6:303:24a::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9891.22; Sun, 10 May 2026 05:36:09 +0000 Received: from CH2PEPF0000009F.namprd02.prod.outlook.com (2603:10b6:610:53:cafe::2b) by CH2PR17CA0030.outlook.office365.com (2603:10b6:610:53::40) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9891.21 via Frontend Transport; Sun, 10 May 2026 05:36:09 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CH2PEPF0000009F.mail.protection.outlook.com (10.167.244.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.13 via Frontend Transport; Sun, 10 May 2026 05:36:08 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 9 May 2026 22:35:54 -0700 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 9 May 2026 22:35:53 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Sat, 9 May 2026 22:35:49 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Moshe Shemesh" , Akiva Goldberger , , , , Gal Pressman , Dragos Tatulea Subject: [PATCH net-next 8/8] net/mlx5: Generalize enable/disable HCA for any PF vport Date: Sun, 10 May 2026 08:34:48 +0300 Message-ID: <20260510053448.326823-9-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260510053448.326823-1-tariqt@nvidia.com> References: <20260510053448.326823-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009F:EE_|MW6PR12MB8897:EE_ X-MS-Office365-Filtering-Correlation-Id: c9e8a02a-106b-4d9b-43f9-08deae5609fc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|1800799024|82310400026|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: ViwZJzY6SZILvH0KUaNt+Eu54jXzXKNbCEwx77jmNDxSex22Me0CaigIhXNkudfpX1S6ICKwnkJer5lC1IRTd0hvlbMLSpDDn2HP5inBSMinBHquYEGA+jqv2cJ0nFOHVf7g0EHCF9vcyyp36PAHt/Zov0o5HPn7PwCE6EiyvkeC4LkouyQXHLTmQjIyrCkJQEEzjaBF0R2L7LGH1vJ+n3QtgvxiwqmmSrHfgfdaSaH2EJAieCKgRdrrj1sQZxCtDOBCRN/CLbXod6cx23srWyHncyfTq2QUDq5ii5tQLVsT+hWoUHzwjNg7tKdtv9uyGRDHyTpX1bVXc3lWxC59vQOb5Gjo+rUNFnwGfNou1OjmnjRLOvk1GZ6iycd7Rl49JzZiH7AKfIfbeNqpbkomLsnjK25IfalW8SdqhxXv8yUz3qAusiO4fI2yBmSOyU1Q06JX+KADrN7cQz5HOWbsAky4YciPsY2QZ4FW+WErzCwcCGSGVj0tXbr3qnD2drW1MrrWhQ5noGHYzS4hrFhrAR7OM+HdOgr/9k7ZDRaiD/i3azr+nOlACJbRl7bQWQeZnKH+tTFN1vBH+kW3T+UX4jZWjdMdqJsfqmf/1kBU9TcvLkXcfQbHRis7SfAc0vJAMhkaZrJVo2cXimOCTWahAbQ/NqGSlm1aT4vPexinU/a5LEsmUk7cXy1lq1cz8yvQaWUnHIghCCeT524uvW9TZYqthTURu1h0GPue4Wwx+0Y= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700016)(1800799024)(82310400026)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +Au3ua7W+tr9UqrP0sy/X8OsIzp2Y7d39hcO6g+gLK7BxxkSPnSsJNwY2k4xMS4e1xdF0LVpnB2pM39lP8ZoJoTBGNr8zFjlFBTjR49qynZaw+NAE7i7sOwYOVU/9bLSoS1yXKDKHzf3E58+M30nxy+S/jtUn7CXNvg/7MMbk0lZu3s0O+C5BpraRvuJdLZEmYiZN+4tg9WF5tz6nswPDduqLOCgyz4h/rxSc77kEx+fd5Ho8ORF0uA075TSdcF071gbHFVaPx27BbSJ9MMH+Dum3mJPlSZZlhzuZ8dUK85S64Y7BT2S6cEnfM+/YCHll2G1jh2mwCVruGGk7ZfS/bk0shBWjJCMFzqcbyrxK39gapcqFl9Ox1zH6gjvZTnCfVnoN5mupe5lvA7FDus+RfUG1CxkXEoCOeNVMA/X/MX3d+xX7FFK6hyqk7Vo+4tt X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2026 05:36:08.9541 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c9e8a02a-106b-4d9b-43f9-08deae5609fc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8897 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh Refactor the host-PF-specific mlx5_cmd_host_pf_enable/disable_hca() into generic mlx5_cmd_pf_enable/disable_hca() that accept a vport number. The new functions use vhca_id as function_id when supported. Similarly, refactor the eswitch layer into generic static helpers mlx5_esw_pf_enable/disable_hca() with thin wrappers for the host PF case, in preparation for enable_hca on satellite PF vports. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/ecpf.c | 24 +++++++++++----- .../net/ethernet/mellanox/mlx5/core/ecpf.h | 4 +-- .../net/ethernet/mellanox/mlx5/core/eswitch.c | 28 +++++++++++++------ .../ethernet/mellanox/mlx5/core/mlx5_core.h | 2 ++ .../net/ethernet/mellanox/mlx5/core/vport.c | 4 +-- 5 files changed, 42 insertions(+), 20 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/ecpf.c b/drivers/net/e= thernet/mellanox/mlx5/core/ecpf.c index 15cb27aea2c9..350c47d3643b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/ecpf.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/ecpf.c @@ -18,25 +18,35 @@ static bool mlx5_ecpf_esw_admins_host_pf(const struct m= lx5_core_dev *dev) return mlx5_core_is_ecpf_esw_manager(dev); } =20 -int mlx5_cmd_host_pf_enable_hca(struct mlx5_core_dev *dev) +int mlx5_cmd_pf_enable_hca(struct mlx5_core_dev *dev, u16 vport_num) { u32 out[MLX5_ST_SZ_DW(enable_hca_out)] =3D {}; u32 in[MLX5_ST_SZ_DW(enable_hca_in)] =3D {}; + u16 vhca_id; =20 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); - MLX5_SET(enable_hca_in, in, function_id, 0); - MLX5_SET(enable_hca_in, in, embedded_cpu_function, 0); - return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); + if (mlx5_vport_use_vhca_id_as_func_id(dev, vport_num, &vhca_id)) { + MLX5_SET(enable_hca_in, in, function_id, vhca_id); + MLX5_SET(enable_hca_in, in, function_id_type, 1); + } else { + MLX5_SET(enable_hca_in, in, function_id, vport_num); + } + return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); } =20 -int mlx5_cmd_host_pf_disable_hca(struct mlx5_core_dev *dev) +int mlx5_cmd_pf_disable_hca(struct mlx5_core_dev *dev, u16 vport_num) { u32 out[MLX5_ST_SZ_DW(disable_hca_out)] =3D {}; u32 in[MLX5_ST_SZ_DW(disable_hca_in)] =3D {}; + u16 vhca_id; =20 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); - MLX5_SET(disable_hca_in, in, function_id, 0); - MLX5_SET(disable_hca_in, in, embedded_cpu_function, 0); + if (mlx5_vport_use_vhca_id_as_func_id(dev, vport_num, &vhca_id)) { + MLX5_SET(disable_hca_in, in, function_id, vhca_id); + MLX5_SET(disable_hca_in, in, function_id_type, 1); + } else { + MLX5_SET(disable_hca_in, in, function_id, vport_num); + } return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); } =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/ecpf.h b/drivers/net/e= thernet/mellanox/mlx5/core/ecpf.h index 40b6ad76dca6..d9f9a53b019b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/ecpf.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/ecpf.h @@ -17,8 +17,8 @@ bool mlx5_read_embedded_cpu(struct mlx5_core_dev *dev); int mlx5_ec_init(struct mlx5_core_dev *dev); void mlx5_ec_cleanup(struct mlx5_core_dev *dev); =20 -int mlx5_cmd_host_pf_enable_hca(struct mlx5_core_dev *dev); -int mlx5_cmd_host_pf_disable_hca(struct mlx5_core_dev *dev); +int mlx5_cmd_pf_enable_hca(struct mlx5_core_dev *dev, u16 vport_num); +int mlx5_cmd_pf_disable_hca(struct mlx5_core_dev *dev, u16 vport_num); =20 #else /* CONFIG_MLX5_ESWITCH */ =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.c index 9a7de7c9a667..206911817a04 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -1452,7 +1452,7 @@ static int mlx5_eswitch_load_ec_vf_vports(struct mlx5= _eswitch *esw, u16 num_ec_v return err; } =20 -int mlx5_esw_host_pf_enable_hca(struct mlx5_core_dev *dev) +static int mlx5_esw_pf_enable_hca(struct mlx5_core_dev *dev, u16 vport_num) { struct mlx5_eswitch *esw =3D dev->priv.eswitch; struct mlx5_vport *vport; @@ -1461,15 +1461,15 @@ int mlx5_esw_host_pf_enable_hca(struct mlx5_core_de= v *dev) if (!mlx5_core_is_ecpf(dev) || !mlx5_esw_allowed(esw)) return 0; =20 - vport =3D mlx5_eswitch_get_vport(esw, MLX5_VPORT_HOST_PF); + vport =3D mlx5_eswitch_get_vport(esw, vport_num); if (IS_ERR(vport)) return PTR_ERR(vport); =20 - /* Once vport and representor are ready, take out the external host PF - * out of initializing state. Enabling HCA clears the iser->initializing - * bit and host PF driver loading can progress. + /* Once vport and representor are ready, take the PF out of + * initializing state. Enabling HCA clears the iser->initializing + * bit and PF driver loading can progress. */ - err =3D mlx5_cmd_host_pf_enable_hca(dev); + err =3D mlx5_cmd_pf_enable_hca(dev, vport_num); if (err) return err; =20 @@ -1478,7 +1478,7 @@ int mlx5_esw_host_pf_enable_hca(struct mlx5_core_dev = *dev) return 0; } =20 -int mlx5_esw_host_pf_disable_hca(struct mlx5_core_dev *dev) +static int mlx5_esw_pf_disable_hca(struct mlx5_core_dev *dev, u16 vport_nu= m) { struct mlx5_eswitch *esw =3D dev->priv.eswitch; struct mlx5_vport *vport; @@ -1487,11 +1487,11 @@ int mlx5_esw_host_pf_disable_hca(struct mlx5_core_d= ev *dev) if (!mlx5_core_is_ecpf(dev) || !mlx5_esw_allowed(esw)) return 0; =20 - vport =3D mlx5_eswitch_get_vport(esw, MLX5_VPORT_HOST_PF); + vport =3D mlx5_eswitch_get_vport(esw, vport_num); if (IS_ERR(vport)) return PTR_ERR(vport); =20 - err =3D mlx5_cmd_host_pf_disable_hca(dev); + err =3D mlx5_cmd_pf_disable_hca(dev, vport_num); if (err) return err; =20 @@ -1500,6 +1500,16 @@ int mlx5_esw_host_pf_disable_hca(struct mlx5_core_de= v *dev) return 0; } =20 +int mlx5_esw_host_pf_enable_hca(struct mlx5_core_dev *dev) +{ + return mlx5_esw_pf_enable_hca(dev, MLX5_VPORT_HOST_PF); +} + +int mlx5_esw_host_pf_disable_hca(struct mlx5_core_dev *dev) +{ + return mlx5_esw_pf_disable_hca(dev, MLX5_VPORT_HOST_PF); +} + /* mlx5_eswitch_enable_pf_vf_vports() enables vports of PF, ECPF and VFs * whichever are present on the eswitch. */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h b/drivers/= net/ethernet/mellanox/mlx5/core/mlx5_core.h index 2eba141bd521..51637e58a48b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h @@ -452,6 +452,8 @@ void mlx5_unload_one_light(struct mlx5_core_dev *dev); =20 void mlx5_query_nic_sw_system_image_guid(struct mlx5_core_dev *mdev, u8 *b= uf, u8 *len); +bool mlx5_vport_use_vhca_id_as_func_id(struct mlx5_core_dev *dev, + u16 vport_num, u16 *vhca_id); int mlx5_vport_set_other_func_cap(struct mlx5_core_dev *dev, const void *h= ca_cap, u16 vport, u16 opmod); #define mlx5_vport_get_other_func_general_cap(dev, vport, out) \ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/vport.c b/drivers/net/= ethernet/mellanox/mlx5/core/vport.c index f8e6b1ab7c5c..e0848f4e88dd 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/vport.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/vport.c @@ -1283,8 +1283,8 @@ void mlx5_query_nic_sw_system_image_guid(struct mlx5_= core_dev *mdev, u8 *buf, buf[(*len)++] =3D MLX5_CAP_GEN_2(mdev, load_balance_id); } =20 -static bool mlx5_vport_use_vhca_id_as_func_id(struct mlx5_core_dev *dev, - u16 vport_num, u16 *vhca_id) +bool mlx5_vport_use_vhca_id_as_func_id(struct mlx5_core_dev *dev, + u16 vport_num, u16 *vhca_id) { if (!MLX5_CAP_GEN_2(dev, function_id_type_vhca_id)) return false; --=20 2.44.0