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Sat, 09 May 2026 22:26:00 -0700 (PDT) Received: from [172.17.0.2] ([134.128.219.200]) by smtp.gmail.com with ESMTPSA id af79cd13be357-907b9286f22sm689689085a.13.2026.05.09.22.25.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 May 2026 22:26:00 -0700 (PDT) From: Yuanshen Cao Date: Sun, 10 May 2026 05:25:35 +0000 Subject: [PATCH] pmdomain: sunxi: support power domain flags for pck600 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260510-pck600-a733-gpu-v1-1-d6393646d714@gmail.com> X-B4-Tracking: v=1; b=H4sIAAAAAAAC/x3MMQqAMAxA0auUzAZiRaVeRRw0Rg2ClhZFKN7d4 viG/xNECSoROpMgyK1RzyOjLAzwNh6roM7ZYMk2VJeEnveGCMe2qnD1F848LUzcsjgHufJBFn3 +Yz+87wdJjmRzYQAAAA== X-Change-ID: 20260510-pck600-a733-gpu-dcbfc0c7ce99 To: Ulf Hansson , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Icenowy Zheng , Mikhail Kalashnikov , Yuanshen Cao X-Mailer: b4 0.14.3 Hi everyone, This patch refactors the sunxi pck600 power domain implementation to support individual power domain flags. While bringing up the PowerVR GPU on the A733 (Radxa Cubie A7Z), we found that one of the GPU power domains must be configured as "always on." While the Radxa BSP device tree leaves the GPU power domain nodes commented out, the GPU driver code contains traces indicating an "always on" requirement [1]. Currently, sunxi_pck600_desc only supports specifying pd_names. This patch introduces sunxi_pck600_pd_desc, which stores both the name and its associated flags. This also (more or less) aligns the implementation with the existing sun50i PPU handling of always-on domains. With this change, individual power domains can now be configured more granularly. In particular, the GPU_CORE domain in sun60i_a733_pck600_pds can now be explicitly marked with GENPD_FLAG_ALWAYS_ON. The patch was tested on the Radxa Cubie A7Z, where the GPU now functions as expected. Thanks to Icenowy for her support and expertise on sunxi and PowerVR, and thanks to Mikhail for identifying this exact cause of the GPU bring-up issue. [1] https://github.com/radxa/allwinner-bsp/blob/cubie-aiot-v1.4.6/modules/g= pu/img-bxm/linux/rogue_km/services/system/rogue/rgx_sunxi/sunxi_platform.c#= L62 Signed-off-by: Yuanshen Cao --- drivers/pmdomain/sunxi/sun55i-pck600.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/drivers/pmdomain/sunxi/sun55i-pck600.c b/drivers/pmdomain/sunx= i/sun55i-pck600.c index 1d47bbd35ced..8a37d11b65a2 100644 --- a/drivers/pmdomain/sunxi/sun55i-pck600.c +++ b/drivers/pmdomain/sunxi/sun55i-pck600.c @@ -41,8 +41,13 @@ =20 #define PPU_REG_SIZE 0x1000 =20 +struct sunxi_pck600_pd_desc { + const char *name; + unsigned int flags; +}; + struct sunxi_pck600_desc { - const char * const *pd_names; + const struct sunxi_pck600_pd_desc *pd_descs; unsigned int num_domains; u32 logic_power_switch0_delay_offset; u32 logic_power_switch1_delay_offset; @@ -164,10 +169,12 @@ static int sunxi_pck600_probe(struct platform_device = *pdev) =20 for (i =3D 0; i < desc->num_domains; i++) { struct sunxi_pck600_pd *pd =3D &pck->pds[i]; + const struct sunxi_pck600_pd_desc *pd_desc =3D &desc->pd_descs[i]; =20 - pd->genpd.name =3D desc->pd_names[i]; + pd->genpd.name =3D pd_desc->name; pd->genpd.power_off =3D sunxi_pck600_power_off; pd->genpd.power_on =3D sunxi_pck600_power_on; + pd->genpd.flags =3D pd_desc->flags; pd->base =3D base + PPU_REG_SIZE * i; =20 sunxi_pck600_pd_setup(pd, desc); @@ -195,13 +202,14 @@ static int sunxi_pck600_probe(struct platform_device = *pdev) return ret; } =20 -static const char * const sun55i_a523_pck600_pd_names[] =3D { - "VE", "GPU", "VI", "VO0", "VO1", "DE", "NAND", "PCIE" +static const struct sunxi_pck600_pd_desc sun55i_a523_pck600_pds[] =3D { + { "VE", }, { "GPU", }, { "VI", }, { "VO0", }, { "VO1", }, + { "DE", }, { "NAND", }, { "PCIE", }, }; =20 static const struct sunxi_pck600_desc sun55i_a523_pck600_desc =3D { - .pd_names =3D sun55i_a523_pck600_pd_names, - .num_domains =3D ARRAY_SIZE(sun55i_a523_pck600_pd_names), + .pd_descs =3D sun55i_a523_pck600_pds, + .num_domains =3D ARRAY_SIZE(sun55i_a523_pck600_pds), .logic_power_switch0_delay_offset =3D 0xc00, .logic_power_switch1_delay_offset =3D 0xc04, .off2on_delay_offset =3D 0xc10, @@ -213,14 +221,15 @@ static const struct sunxi_pck600_desc sun55i_a523_pck= 600_desc =3D { .has_rst_clk =3D true, }; =20 -static const char * const sun60i_a733_pck600_pd_names[] =3D { - "VI", "DE_SYS", "VE_DEC", "VE_ENC", "NPU", - "GPU_TOP", "GPU_CORE", "PCIE", "USB2", "VO", "VO1" +static const struct sunxi_pck600_pd_desc sun60i_a733_pck600_pds[] =3D { + { "VI", }, { "DE_SYS", }, { "VE_DEC", }, { "VE_ENC", }, { "NPU", }, + { "GPU_TOP", }, { "GPU_CORE", GENPD_FLAG_ALWAYS_ON }, + { "PCIE", }, { "USB2", }, { "VO", }, { "VO1", }, }; =20 static const struct sunxi_pck600_desc sun60i_a733_pck600_desc =3D { - .pd_names =3D sun60i_a733_pck600_pd_names, - .num_domains =3D ARRAY_SIZE(sun60i_a733_pck600_pd_names), + .pd_descs =3D sun60i_a733_pck600_pds, + .num_domains =3D ARRAY_SIZE(sun60i_a733_pck600_pds), .logic_power_switch0_delay_offset =3D 0xc00, .logic_power_switch1_delay_offset =3D 0xc04, .off2on_delay_offset =3D 0xc10, --- base-commit: 1bfaee9d3351b9b32a99766bbfb1f5baed60ddef change-id: 20260510-pck600-a733-gpu-dcbfc0c7ce99 Best regards, --=20 Yuanshen Cao