From nobody Sat Jun 13 07:29:29 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 00A4230CD81 for ; Fri, 8 May 2026 16:24:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778257442; cv=none; b=aaW6f6nOcl++PAZCFcBHFpL0NKdBAzTC6vvJBAsIaqyVWo3oB5Sec0xzz38tOGmzsBJcZZoXwKdb89iqJI0Gh5qxhs2fATNJZR7vhSnjbsZaxvYADwDJHdFT0JOQoB64DQhj5epEcnjZRafKXjtrw0Jpkhzw1dhrOsPJjULhUaE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778257442; c=relaxed/simple; bh=/UBLQNQv/jESKVCey7P8WZJaGnOhYl64JzXcUuHLQyc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fVcc5ji2P8r/MaOTojyTZv8AUNfI6N3D2OFDV2lE4unEcV8yDPLON31pQSGuIh4aq0TPXgYQ1qtQqfeMJEciIX+GSvwANvsoGawyuPzyW2sGsp/2K0+Vn1Gde5fuG2PqR0Xrbeo4XxKWDIVev7BeMobOXUeTqgPkCg9LK1mZlEU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=U9In9eVz; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="U9In9eVz" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 23B2C1E5E; Fri, 8 May 2026 09:23:55 -0700 (PDT) Received: from eglon.cambridge.arm.com (eglon.cambridge.arm.com [10.1.196.96]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7ECBF3F763; Fri, 8 May 2026 09:23:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778257440; bh=/UBLQNQv/jESKVCey7P8WZJaGnOhYl64JzXcUuHLQyc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=U9In9eVzRoyWBnl/EdZ/eBCvm3lpoZfcWCHQN4ev0L4+Ug8VqM8tpEGUUDon/UnV0 p8eCYtPD6rbrxpkpEMCeRAcGAikvWdWEAPN3sDbqvB+MMjBnmuiYWzORDhQfllSEUZ 9KivCJVDol8B3ZdxF27DQflk1uTSS1Dn4WHkMMmM= From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, zengheng4@huawei.com Cc: wangkefeng.wang@huawei.com, xry111@xry111.site, catalin.marinas@arm.com, yang@os.amperecomputing.com, reinette.chatre@intel.com, will@kernel.org, thuth@redhat.com, ben.horgan@arm.com, mrigendra.chaubey@gmail.com, fenghuay@nvidia.com, ahmed.genidi@arm.com Subject: [PATCH v3 1/4] arm_mpam: Fix false positive assert failure during mpam_disable() Date: Fri, 8 May 2026 17:23:38 +0100 Message-ID: <20260508162341.3762549-2-james.morse@arm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260508162341.3762549-1-james.morse@arm.com> References: <20260508162341.3762549-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" mpam_assert_partid_sizes_fixed() is used to document that the caller doesn't expect the discovered PARTID size to change while it is walking a list sized by PARTID. Typically the MSC state is not written to until all the MSC have been discovered and this value is set. However, if discovering the MSC fails and schedules mpam_disable(), then the MSC state is written to reset it. In this case the discovered PARTID size may be become smaller - but only PARTID 0 will be used once resctrl_exit() has been called. Skip the WARN_ON_ONCE() if mpam_disable_reason has been set. Fixes: 3bd04fe7d807bb ("arm_mpam: Extend reset logic to allow devices to be= reset at any time") Signed-off-by: James Morse Reviewed-by: Ben Horgan --- drivers/resctrl/mpam_devices.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index 41b14344b16f..bef5e9e9e844 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -164,11 +164,17 @@ static void mpam_free_garbage(void) /* * Once mpam is enabled, new requestors cannot further reduce the available * partid. Assert that the size is fixed, and new requestors will be turned - * away. + * away. This is needed when walking over structures sized by PARTID. + * + * During mpam_disable() these structures are not fixed, but the MSC state + * is still reset using whatever sizes have been discovered so far. As only + * PARTID 0 will be used after mpam_disable(), any race would be benign. + * Skip the check if a mpam_disable_reason has been set. */ static void mpam_assert_partid_sizes_fixed(void) { - WARN_ON_ONCE(!partid_max_published); + if (!mpam_disable_reason) + WARN_ON_ONCE(!partid_max_published); } =20 static u32 __mpam_read_reg(struct mpam_msc *msc, u16 reg) --=20 2.53.0 From nobody Sat Jun 13 07:29:29 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6534137F8DF for ; Fri, 8 May 2026 16:24:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778257444; cv=none; b=hD1YcsaI4FFb//GzBma52RJR+z7vk6Un407qZqaTquiIalMtmQw/9FDR6gxFMDsotQxadY4q8azo1lOvwgd+g5Y7ATSVtJDh95FLHsrQ0AaixEWpTVvTq5YVzV0iF2PSEreNcC3rrYCHyP1yBTwOVsijD08XrV7QkCCB7gI/8uQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778257444; c=relaxed/simple; bh=YO55I0yn0I6BsYQRV+sPGwF7VaB+Agwv5B9KA1bPS18=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DdIxzMGr5dVlwRXlKpx+K3DDPUtWdp5TPWKnNJzrIZ3xPxI2c98pzNzOM8a+7xdAv9Xj93VFO7cSye6qQnK9yNSq4pMMpgbbd7Oo5ha0lNZESevloO1aRAYI3QNV8RXIND0bsrvNUmpITyQS73srU98xLiKZyQ5JjHveLbEVwbk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=dz92HdUJ; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="dz92HdUJ" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 71C5F1E7D; Fri, 8 May 2026 09:23:57 -0700 (PDT) Received: from eglon.cambridge.arm.com (eglon.cambridge.arm.com [10.1.196.96]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CED403F763; Fri, 8 May 2026 09:24:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778257442; bh=YO55I0yn0I6BsYQRV+sPGwF7VaB+Agwv5B9KA1bPS18=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dz92HdUJB0VlYOScG1Db+9H2H5xCh2I93kuH+gGn1hvKaOjIdkR1iEyWUw0ne5zOK 24JuBA9xceihx0hc9ANKtj3tOIOrXgA7qJp0DCT12eVogzlTqJqJP/ovoSyAHlEAFF rxY0vSlDj0NQzbMWY2V3THeS7AizCcwhDiX2rZ9E= From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, zengheng4@huawei.com Cc: wangkefeng.wang@huawei.com, xry111@xry111.site, catalin.marinas@arm.com, yang@os.amperecomputing.com, reinette.chatre@intel.com, will@kernel.org, thuth@redhat.com, ben.horgan@arm.com, mrigendra.chaubey@gmail.com, fenghuay@nvidia.com, ahmed.genidi@arm.com Subject: [PATCH v3 2/4] arm_mpam: Check whether the config array is allocated before destroying it Date: Fri, 8 May 2026 17:23:39 +0100 Message-ID: <20260508162341.3762549-3-james.morse@arm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260508162341.3762549-1-james.morse@arm.com> References: <20260508162341.3762549-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" __destroy_component_cfg() is called to free the configuration array. It uses the embedded 'garbage' structure, which means the array has to be allocated. If __destroy_component_cfg() is called from mpam_disable() before the configuration was ever allocated, then a NULL pointer is dereferenced. Check for this case and return early if the configuration is not allocated. __destroy_component_cfg() also frees the mbwu_state as this is allocated by __allocate_component_cfg(). As the mbwu_state is allocated after comp->cfg is set, and is also under mpam_list_lock, only the first pointer needs checking. Fixes: 3bd04fe7d807bb ("arm_mpam: Extend reset logic to allow devices to be= reset any time") Signed-off-by: James Morse Reviewed-by: Ben Horgan --- drivers/resctrl/mpam_devices.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index bef5e9e9e844..916d8fd45ed5 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -2591,6 +2591,9 @@ static void __destroy_component_cfg(struct mpam_compo= nent *comp) =20 lockdep_assert_held(&mpam_list_lock); =20 + if (!comp->cfg) + return; + add_to_garbage(comp->cfg); list_for_each_entry(vmsc, &comp->vmsc, comp_list) { msc =3D vmsc->msc; --=20 2.53.0 From nobody Sat Jun 13 07:29:29 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9CEE93DD53C for ; Fri, 8 May 2026 16:24:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778257447; cv=none; b=W/D0oEczL/VlC9io/9jw4bkOa+FAB/2nzRvsc+Hrl4KZsh35jkwusX5vvWGW4TqgKXVJ6xO4CqvpbbjdsrRj9UBRy7nnrrKLgTVvYNKrKnHJHvLK/YlgEwX4BYhZugUcVAs3uKNYzr7rRPsUpwKXEIH7fYws8OFCR2pFXplN9zY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778257447; c=relaxed/simple; bh=Taw+EgStIHXUnOnJUtTgeinZazPcPCvcQemD1Fo9qfk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uSFRimJTiiDLNFcjrqRB9NcXW/OcfR0itgyIug9hlcS8ubHxc0ngVBrHqhrQVWQ58ZtL9d/pfSaRYjUCDD21nuyaWVyi0qEp9uHS6J3itSp9pzkdgMOjeos/m1U7qK1TGZGJ3QPUceAULHcXp1kyeU9DinSk9uV0j2V8C7OrvWM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=vGImD2as; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="vGImD2as" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C76091E5E; Fri, 8 May 2026 09:23:59 -0700 (PDT) Received: from eglon.cambridge.arm.com (eglon.cambridge.arm.com [10.1.196.96]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 29C303F763; Fri, 8 May 2026 09:24:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778257445; bh=Taw+EgStIHXUnOnJUtTgeinZazPcPCvcQemD1Fo9qfk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vGImD2asj5EL5DUbxiUjNtrjpi7P7VSINO5fFd/zEzC9W3fSOgDJRnDMSvndfu0Fn r33oc8zGFNGw+Nr7RKc1yRRMY/6Q7sdQWApMs2/LOt90bHeViAO4m1tuAZVbVlENY/ Z5gWeHS5VTvizS1AOJihLmwARD5Hsg+SM3z1qeik= From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, zengheng4@huawei.com Cc: wangkefeng.wang@huawei.com, xry111@xry111.site, catalin.marinas@arm.com, yang@os.amperecomputing.com, reinette.chatre@intel.com, will@kernel.org, thuth@redhat.com, ben.horgan@arm.com, mrigendra.chaubey@gmail.com, fenghuay@nvidia.com, ahmed.genidi@arm.com Subject: [PATCH v3 3/4] arm64: cpufeature: Add support for the MPAM v0.1 architecture version Date: Fri, 8 May 2026 17:23:40 +0100 Message-ID: <20260508162341.3762549-4-james.morse@arm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260508162341.3762549-1-james.morse@arm.com> References: <20260508162341.3762549-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Zeng Heng According to the MPAM spec [1], the supported architecture versions are v1.0, v1.1 and v0.1. MPAM versions v0.1 and v1.1 are functionally identical, but v0.1 additionally supports the FORCE_NS feature. ID_AA64PR | ID_AA64PR | MPAM Extension | Notes F0_EL1. | F1_EL1. | Architecture | MPAM | MPAM_frac | version | Acked-by: Catalin Marinas Reviewed-by: James Morse --------------------------------------------------------------------------- 0b0000 | 0b0001 | v0.1 | MPAM v0.1 is implemented. | | | MPAM v0.1 is the same as MPAM v1.1 | | | with FORCE_NS which is | | | incompatible with MPAM v1.0. --------------------------------------------------------------------------- 0b0001 | 0b0000 | v1.0 | MPAM v1.0 is implemented. --------------------------------------------------------------------------- 0b0001 | 0b0001 | v1.1 | MPAM v1.1 is implemented. | | | MPAM v1.1 includes all features of | | | MPAM v1.0. | | | It must not include FORCE_NS. FORCE_NS is a feature that operates in EL3 mode. Consequently, the current Linux MPAM driver is also compatible with MPAM v0.1. To support v0.1, the existing driver which only checks ID_AA64PFR0_EL1.MPAM for the major version needs to examine ID_AA64PFR1_EL1.MPAM_frac for the minor version as well. [1] https://developer.arm.com/documentation/ddi0598/db/?lang=3Den Signed-off-by: Zeng Heng Reviewed-by: James Morse Signed-off-by: James Morse --- arch/arm64/include/asm/cpufeature.h | 7 +++++++ arch/arm64/include/asm/el2_setup.h | 4 +++- arch/arm64/kernel/cpufeature.c | 15 +++++++++++---- 3 files changed, 21 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/c= pufeature.h index 4de51f8d92cb..a57870fa96db 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -620,6 +620,13 @@ static inline bool id_aa64pfr0_mpam(u64 pfr0) return val > 0; } =20 +static inline bool id_aa64pfr1_mpamfrac(u64 pfr1) +{ + u32 val =3D cpuid_feature_extract_unsigned_field(pfr1, ID_AA64PFR1_EL1_MP= AM_frac_SHIFT); + + return val > 0; +} + static inline bool id_aa64pfr1_mte(u64 pfr1) { u32 val =3D cpuid_feature_extract_unsigned_field(pfr1, ID_AA64PFR1_EL1_MT= E_SHIFT); diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el= 2_setup.h index 587507a9980e..aa8ec9df8024 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -510,7 +510,9 @@ #endif =20 .macro finalise_el2_state - check_override id_aa64pfr0, ID_AA64PFR0_EL1_MPAM_SHIFT, .Linit_mpam_\@, .= Lskip_mpam_\@, x1, x2 + check_override id_aa64pfr0, ID_AA64PFR0_EL1_MPAM_SHIFT, .Linit_mpam_\@, .= Lmpam_minor_\@, x1, x2 +.Lmpam_minor_\@: + check_override id_aa64pfr1, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, .Linit_mpam_= \@, .Lskip_mpam_\@, x1, x2 =20 .Linit_mpam_\@: mov x0, #MPAM2_EL2_EnMPAMSM_MASK diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 6d53bb15cf7b..0a1d198b3995 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1164,6 +1164,14 @@ static __init void detect_system_supports_pseudo_nmi= (void) static inline void detect_system_supports_pseudo_nmi(void) { } #endif =20 +static bool detect_ftr_has_mpam(void) +{ + u64 pfr0 =3D read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); + u64 pfr1 =3D read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1); + + return id_aa64pfr0_mpam(pfr0) || id_aa64pfr1_mpamfrac(pfr1); +} + void __init init_cpu_features(struct cpuinfo_arm64 *info) { /* Before we start using the tables, make sure it is sorted */ @@ -1211,7 +1219,7 @@ void __init init_cpu_features(struct cpuinfo_arm64 *i= nfo) cpacr_restore(cpacr); } =20 - if (id_aa64pfr0_mpam(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { + if (detect_ftr_has_mpam()) { info->reg_mpamidr =3D read_cpuid(MPAMIDR_EL1); init_cpu_ftr_reg(SYS_MPAMIDR_EL1, info->reg_mpamidr); } @@ -1467,7 +1475,7 @@ void update_cpu_features(int cpu, cpacr_restore(cpacr); } =20 - if (id_aa64pfr0_mpam(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { + if (detect_ftr_has_mpam()) { info->reg_mpamidr =3D read_cpuid(MPAMIDR_EL1); taint |=3D check_update_ftr_reg(SYS_MPAMIDR_EL1, cpu, info->reg_mpamidr, boot->reg_mpamidr); @@ -2486,7 +2494,7 @@ cpucap_panic_on_conflict(const struct arm64_cpu_capab= ilities *cap) static bool test_has_mpam(const struct arm64_cpu_capabilities *entry, int scope) { - if (!has_cpuid_feature(entry, scope)) + if (!detect_ftr_has_mpam()) return false; =20 /* Check firmware actually enabled MPAM on this cpu. */ @@ -3093,7 +3101,6 @@ static const struct arm64_cpu_capabilities arm64_feat= ures[] =3D { .capability =3D ARM64_MPAM, .matches =3D test_has_mpam, .cpu_enable =3D cpu_enable_mpam, - ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, MPAM, 1) }, { .desc =3D "Memory Partitioning And Monitoring Virtualisation", --=20 2.53.0 From nobody Sat Jun 13 07:29:29 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DF8FA3FBEB3 for ; Fri, 8 May 2026 16:24:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778257449; cv=none; b=cHOSIhAysqZlQPH8LZv7y4sVn/zptcEuQxe0xRv/3/UG0KaZ93GtNi4VppjO2dzMV0OU7KrtH2s5Jfm79bkw7py62pHwSAU6Ic15Is+DtxcLUYt9dKEttl77HfKsfRbtO2HHoa+9VqTucT3YeAeZPgh3FFKOBiNhrr6MID3ICjw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Fri, 8 May 2026 09:24:02 -0700 (PDT) Received: from eglon.cambridge.arm.com (eglon.cambridge.arm.com [10.1.196.96]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7CF9B3F763; Fri, 8 May 2026 09:24:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778257447; bh=AgpT/PMm24zQgK02qmUXppicDWFKDhpG8UBcLe6yHcU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jRktqLQ0RzSZ06IKl42v3GvjvG8HmCguoX5mye4xi8qzEim/pxZCy+CtQsUff4F/A uF+6H7W+LRxJLDdD2uF6vtrKYhZovh58XhJEz8LnKB+98UyaSRQTW2uAGSM1mqSeTP XDIgQF+TD21hcmcQbuNC4gdI5DRnyFuZ1vS5u4y0= From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, zengheng4@huawei.com Cc: wangkefeng.wang@huawei.com, xry111@xry111.site, catalin.marinas@arm.com, yang@os.amperecomputing.com, reinette.chatre@intel.com, will@kernel.org, thuth@redhat.com, ben.horgan@arm.com, mrigendra.chaubey@gmail.com, fenghuay@nvidia.com, ahmed.genidi@arm.com Subject: [PATCH v3 4/4] arm_mpam: Update architecture version check for MPAM MSC Date: Fri, 8 May 2026 17:23:41 +0100 Message-ID: <20260508162341.3762549-5-james.morse@arm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260508162341.3762549-1-james.morse@arm.com> References: <20260508162341.3762549-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Zeng Heng In addition to updating the CPU MPAM version check, the MPAM MSC version check also need to be updated. mpam_msc_check_aidr() is added to check the MSC AIDR register, ensuring that both the major and minor version numbers fall within the supported range of the MPAM architecture version. Signed-off-by: Zeng Heng [ morse: changed mpam_msc_check_aidr() to accept versions like v1.2 ] Signed-off-by: James Morse Reviewed-by: Ben Horgan --- drivers/resctrl/mpam_devices.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index 916d8fd45ed5..1771e9712ca2 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -224,6 +224,24 @@ static inline void _mpam_write_monsel_reg(struct mpam_= msc *msc, u16 reg, u32 val =20 #define mpam_write_monsel_reg(msc, reg, val) _mpam_write_monsel_reg(msc,= MSMON_##reg, val) =20 +static bool mpam_msc_check_aidr(struct mpam_msc *msc) +{ + u32 aidr =3D __mpam_read_reg(msc, MPAMF_AIDR); + u32 major =3D FIELD_GET(MPAMF_AIDR_ARCH_MAJOR_REV, aidr); + u32 minor =3D FIELD_GET(MPAMF_AIDR_ARCH_MINOR_REV, aidr); + + /* + * v0.0 and >v2.x aren't supported, but anything else should be backward + * compatible to v0.1 or v1.0. + */ + if (!major && !minor) + return false; + if (major > 1) + return false; + + return true; +} + static u64 mpam_msc_read_idr(struct mpam_msc *msc) { u64 idr_high =3D 0, idr_low; @@ -951,9 +969,8 @@ static int mpam_msc_hw_probe(struct mpam_msc *msc) =20 lockdep_assert_held(&msc->probe_lock); =20 - idr =3D __mpam_read_reg(msc, MPAMF_AIDR); - if ((idr & MPAMF_AIDR_ARCH_MAJOR_REV) !=3D MPAM_ARCHITECTURE_V1) { - dev_err_once(dev, "MSC does not match MPAM architecture v1.x\n"); + if (!mpam_msc_check_aidr(msc)) { + dev_err_once(dev, "MSC does not match architecture v1.x\n"); return -EIO; } =20 --=20 2.53.0