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Wed, 13 May 2026 05:25:46 -0700 (PDT) Received: from hu-nandam-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-368eddf4d84sm3651894a91.3.2026.05.13.05.25.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 May 2026 05:25:45 -0700 (PDT) From: Ajay Kumar Nandam To: Bjorn Andersson , Linus Walleij Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, mohammad.rafi.shaik@oss.qualcomm.com, ajay.nandam@oss.qualcomm.com Subject: [PATCH v4 1/2] pinctrl: qcom: lpass-lpi: Enable runtime PM hooks on LPASS LPI SoCs Date: Wed, 13 May 2026 17:55:25 +0530 Message-Id: <20260513122542.3726319-1-ajay.nandam@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260508113636.3561383-1-ajay.nandam@oss.qualcomm.com> References: <20260508113636.3561383-1-ajay.nandam@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTEzMDEzMCBTYWx0ZWRfXz8f/5eqzuC1i BGRkqev9swjzjA+XywOS8iTq3KxdV/jXXh4+rLIrgYTLauynXUAspbkwA0FSmnDtZvhFbYrZA/4 +oNACBg1myZHIAo0EnmwD9PlXhHj2ENgt86PJGF4lxm9cPSwSbjBaedYo4RcP6OR1hlbhtFszyl fHcF/NsgxgXin6nYaOwr4zRZeGKsjwC3/ueQd3mHoUHZD4crWAxhJhJ5jG7SlIndGeUDxsS1BSQ YP18YgE3vXxAcrkW65VP0gttEwbpP4zgcYp/IWde+5S8le54jDPrY3hrQl3KKD9hBpKWxmXEuVB 4c0Z+XvXqDF4aXejwHPL/re8cxIu4/lkj/Xgaj7iCkXKfgQaw2CNlYeRSa9XoNI4T0y7cbu4TIE UGw495KelZMRxxMrFjqPC5EtPpoWMPIdeVfcrvJf7CCkCZLSGZNXpCfjW7f8ltiUHt8OUS4CkVR Gp/3c7m4a2TeqvBEzlw== X-Proofpoint-GUID: FuQnf3UHLIo6kbyqcfVDLpem_UzeOztj X-Authority-Analysis: v=2.4 cv=L68theT8 c=1 sm=1 tr=0 ts=6a046dcc cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=PNqn8kwc-IHmyLqyaEgA:9 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-ORIG-GUID: FuQnf3UHLIo6kbyqcfVDLpem_UzeOztj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-13_01,2026-05-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 impostorscore=0 adultscore=0 priorityscore=1501 suspectscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605130130 Content-Type: text/plain; charset="utf-8" The LPASS LPI core conversion to PM clock framework relies on variant drivers wiring runtime PM callbacks. Hook up runtime PM callbacks for the LPASS LPI variant drivers touched in this patch so they are prepared for the shared core conversion. sc7280 wiring is completed in the following patch. This commit is a preparatory NOP on its own, as runtime PM is still disabled on these devices until the following core conversion patch. This is a mechanical per-variant driver update that relies on the same generic PM clock flow (of_pm_clk_add_clks() + pm_clk_suspend/ pm_clk_resume()) and DT-provided clocks. Runtime behavior was validated on Kodiak (sc7280). Signed-off-by: Ajay Kumar Nandam --- drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c | 7 +++++++ drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c | 11 +++++++++-- drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c | 7 +++++++ drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c | 7 +++++++ drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c | 7 +++++++ drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c | 7 +++++++ drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c | 11 +++++++++-- drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c | 11 +++++++++-- drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c | 11 +++++++++-- drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c | 11 +++++++++-- 10 files changed, 80 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c b/drivers/pinct= rl/qcom/pinctrl-milos-lpass-lpi.c index 3bf6fe0cf1bb..72b8ffd97860 100644 --- a/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -203,10 +205,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { .name =3D "qcom-milos-lpass-lpi-pinctrl", .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c b/drivers/pi= nctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c index 0e839b6aaaf4..1a61316c8c47 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c @@ -6,6 +6,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -173,10 +175,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { - .name =3D "qcom-sc8280xp-lpass-lpi-pinctrl", - .of_match_table =3D lpi_pinctrl_of_match, + .name =3D "qcom-sc8280xp-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sdm660-lpass-lpi.c index 65411abfbfac..7b5aacaae7d7 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c @@ -10,6 +10,8 @@ #include #include #include +#include +#include #include =20 #include "pinctrl-lpass-lpi.h" @@ -145,10 +147,15 @@ static const struct of_device_id sdm660_lpi_pinctrl_o= f_match[] =3D { }; MODULE_DEVICE_TABLE(of, sdm660_lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver sdm660_lpi_pinctrl_driver =3D { .driver =3D { .name =3D "qcom-sdm660-lpass-lpi-pinctrl", .of_match_table =3D sdm660_lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sdm670-lpass-lpi.c index 858146c408d0..0a31f7ad2e0d 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include =20 #include "pinctrl-lpass-lpi.h" @@ -151,10 +153,15 @@ static const struct of_device_id sdm670_lpi_pinctrl_o= f_match[] =3D { }; MODULE_DEVICE_TABLE(of, sdm670_lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver sdm670_lpi_pinctrl_driver =3D { .driver =3D { .name =3D "qcom-sdm670-lpass-lpi-pinctrl", .of_match_table =3D sdm670_lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm4250-lpass-lpi.c index c0e178be9cfc..75bafa62426a 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -221,10 +223,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { .name =3D "qcom-sm4250-lpass-lpi-pinctrl", .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm6115-lpass-lpi.c index b7d9186861a2..05435ea6e17a 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -141,10 +143,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { .name =3D "qcom-sm6115-lpass-lpi-pinctrl", .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm8250-lpass-lpi.c index c27452eece3e..656f22da7dde 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -134,10 +136,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { - .name =3D "qcom-sm8250-lpass-lpi-pinctrl", - .of_match_table =3D lpi_pinctrl_of_match, + .name =3D "qcom-sm8250-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm8450-lpass-lpi.c index 439f6541622e..a79f99ec6df9 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c @@ -6,6 +6,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -202,10 +204,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { - .name =3D "qcom-sm8450-lpass-lpi-pinctrl", - .of_match_table =3D lpi_pinctrl_of_match, + .name =3D "qcom-sm8450-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm8550-lpass-lpi.c index 73065919c8c2..9037ef0020da 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c @@ -6,6 +6,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -210,10 +212,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { - .name =3D "qcom-sm8550-lpass-lpi-pinctrl", - .of_match_table =3D lpi_pinctrl_of_match, + .name =3D "qcom-sm8550-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm8650-lpass-lpi.c index f9fcedf5a65d..513ddc99dd37 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c @@ -6,6 +6,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -217,10 +219,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { - .name =3D "qcom-sm8650-lpass-lpi-pinctrl", - .of_match_table =3D lpi_pinctrl_of_match, + .name =3D "qcom-sm8650-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, --=20 2.34.1 From nobody Sat Jun 13 08:47:17 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 812743C945B for ; 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charset="utf-8" The LPASS LPI core conversion to PM clock framework relies on variant drivers wiring runtime PM callbacks. Hook up runtime PM callbacks for the remaining LPASS LPI variant drivers so all SoCs using the common core get consistent pm_clk based clock handling: - milos - sdm660 - sdm670 - sc8280xp - sm4250 - sm6115 - sm8250 - sm8450 - sm8550 - sm8650 This is a mechanical per-variant driver update that relies on the same generic PM clock flow (of_pm_clk_add_clks() + pm_clk_suspend/ pm_clk_resume()) and DT-provided clocks. Runtime behavior was validated on Kodiak (sc7280). Signed-off-by: Ajay Kumar Nandam --- drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c | 7 +++++++ drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c | 11 +++++++++-- drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c | 7 +++++++ drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c | 7 +++++++ drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c | 7 +++++++ drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c | 7 +++++++ drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c | 11 +++++++++-- drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c | 11 +++++++++-- drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c | 11 +++++++++-- drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c | 11 +++++++++-- 10 files changed, 80 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c b/drivers/pinct= rl/qcom/pinctrl-milos-lpass-lpi.c index 3bf6fe0cf1bb..72b8ffd97860 100644 --- a/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -203,10 +205,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { .name =3D "qcom-milos-lpass-lpi-pinctrl", .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c b/drivers/pi= nctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c index 0e839b6aaaf4..1a61316c8c47 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c @@ -6,6 +6,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -173,10 +175,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { - .name =3D "qcom-sc8280xp-lpass-lpi-pinctrl", - .of_match_table =3D lpi_pinctrl_of_match, + .name =3D "qcom-sc8280xp-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sdm660-lpass-lpi.c index 65411abfbfac..7b5aacaae7d7 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c @@ -10,6 +10,8 @@ #include #include #include +#include +#include #include =20 #include "pinctrl-lpass-lpi.h" @@ -145,10 +147,15 @@ static const struct of_device_id sdm660_lpi_pinctrl_o= f_match[] =3D { }; MODULE_DEVICE_TABLE(of, sdm660_lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver sdm660_lpi_pinctrl_driver =3D { .driver =3D { .name =3D "qcom-sdm660-lpass-lpi-pinctrl", .of_match_table =3D sdm660_lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sdm670-lpass-lpi.c index 858146c408d0..0a31f7ad2e0d 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include =20 #include "pinctrl-lpass-lpi.h" @@ -151,10 +153,15 @@ static const struct of_device_id sdm670_lpi_pinctrl_o= f_match[] =3D { }; MODULE_DEVICE_TABLE(of, sdm670_lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver sdm670_lpi_pinctrl_driver =3D { .driver =3D { .name =3D "qcom-sdm670-lpass-lpi-pinctrl", .of_match_table =3D sdm670_lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm4250-lpass-lpi.c index c0e178be9cfc..75bafa62426a 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -221,10 +223,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { .name =3D "qcom-sm4250-lpass-lpi-pinctrl", .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm6115-lpass-lpi.c index b7d9186861a2..05435ea6e17a 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -141,10 +143,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { .name =3D "qcom-sm6115-lpass-lpi-pinctrl", .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm8250-lpass-lpi.c index c27452eece3e..656f22da7dde 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -134,10 +136,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { - .name =3D "qcom-sm8250-lpass-lpi-pinctrl", - .of_match_table =3D lpi_pinctrl_of_match, + .name =3D "qcom-sm8250-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm8450-lpass-lpi.c index 439f6541622e..a79f99ec6df9 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c @@ -6,6 +6,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -202,10 +204,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { - .name =3D "qcom-sm8450-lpass-lpi-pinctrl", - .of_match_table =3D lpi_pinctrl_of_match, + .name =3D "qcom-sm8450-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm8550-lpass-lpi.c index 73065919c8c2..9037ef0020da 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c @@ -6,6 +6,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -210,10 +212,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { - .name =3D "qcom-sm8550-lpass-lpi-pinctrl", - .of_match_table =3D lpi_pinctrl_of_match, + .name =3D "qcom-sm8550-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm8650-lpass-lpi.c index f9fcedf5a65d..513ddc99dd37 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c @@ -6,6 +6,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -217,10 +219,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { - .name =3D "qcom-sm8650-lpass-lpi-pinctrl", - .of_match_table =3D lpi_pinctrl_of_match, + .name =3D "qcom-sm8650-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, --=20 2.34.1 From nobody Sat Jun 13 08:47:17 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 502273FE669 for ; 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charset="utf-8" Convert the LPASS LPI pinctrl driver to use the PM clock framework for runtime power management. This allows the LPASS LPI pinctrl driver to drop clock votes when idle, improves power efficiency on platforms using LPASS LPI island mode, and aligns the driver with common runtime PM patterns used across Qualcomm LPASS subsystems. Guard GPIO register read/write helpers and slew-rate register programming with synchronous runtime PM calls so the device is active during MMIO operations whenever autosuspend is enabled. Signed-off-by: Ajay Kumar Nandam --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 118 ++++++++++++------ .../pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 7 ++ 2 files changed, 88 insertions(+), 37 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qco= m/pinctrl-lpass-lpi.c index 15ced5027579..d95e28926d38 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -15,6 +15,9 @@ #include #include #include +#include +#include +#include =20 #include "../pinctrl-utils.h" =20 @@ -22,7 +25,6 @@ =20 #define MAX_NR_GPIO 32 #define GPIO_FUNC 0 -#define MAX_LPI_NUM_CLKS 2 =20 struct lpi_pinctrl { struct device *dev; @@ -31,7 +33,6 @@ struct lpi_pinctrl { struct pinctrl_desc desc; char __iomem *tlmm_base; char __iomem *slew_base; - struct clk_bulk_data clks[MAX_LPI_NUM_CLKS]; /* Protects from concurrent register updates */ struct mutex lock; DECLARE_BITMAP(ever_gpio, MAX_NR_GPIO); @@ -39,29 +40,47 @@ struct lpi_pinctrl { }; =20 static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, - unsigned int addr) + unsigned int addr, u32 *val) { u32 pin_offset; + int ret; =20 if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET) pin_offset =3D state->data->groups[pin].pin_offset; else pin_offset =3D LPI_TLMM_REG_OFFSET * pin; =20 - return ioread32(state->tlmm_base + pin_offset + addr); + ret =3D pm_runtime_resume_and_get(state->dev); + if (ret < 0) + return ret; + + *val =3D ioread32(state->tlmm_base + pin_offset + addr); + ret =3D pm_runtime_put_autosuspend(state->dev); + if (ret < 0) + return ret; + + return 0; } =20 static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin, unsigned int addr, unsigned int val) { u32 pin_offset; + int ret; =20 if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET) pin_offset =3D state->data->groups[pin].pin_offset; else pin_offset =3D LPI_TLMM_REG_OFFSET * pin; =20 + ret =3D pm_runtime_resume_and_get(state->dev); + if (ret < 0) + return ret; + iowrite32(val, state->tlmm_base + pin_offset + addr); + ret =3D pm_runtime_put_autosuspend(state->dev); + if (ret < 0) + return ret; =20 return 0; } @@ -107,8 +126,8 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev= , unsigned int function, { struct lpi_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctldev); const struct lpi_pingroup *g =3D &pctrl->data->groups[group]; - u32 val; - int i, pin =3D g->pin; + u32 val, io_val; + int i, pin =3D g->pin, ret; =20 for (i =3D 0; i < g->nfuncs; i++) { if (g->funcs[i] =3D=3D function) @@ -118,8 +137,10 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctlde= v, unsigned int function, if (WARN_ON(i =3D=3D g->nfuncs)) return -EINVAL; =20 - mutex_lock(&pctrl->lock); - val =3D lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG); + guard(mutex)(&pctrl->lock); + ret =3D lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG, &val); + if (ret) + return ret; =20 /* * If this is the first time muxing to GPIO and the direction is @@ -129,24 +150,27 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctld= ev, unsigned int function, */ if (i =3D=3D GPIO_FUNC && (val & LPI_GPIO_OE_MASK) && !test_and_set_bit(group, pctrl->ever_gpio)) { - u32 io_val =3D lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG); + ret =3D lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG, &io_val); + if (ret) + return ret; =20 if (io_val & LPI_GPIO_VALUE_IN_MASK) { if (!(io_val & LPI_GPIO_VALUE_OUT_MASK)) - lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, - io_val | LPI_GPIO_VALUE_OUT_MASK); + ret =3D lpi_gpio_write(pctrl, group, + LPI_GPIO_VALUE_REG, + io_val | LPI_GPIO_VALUE_OUT_MASK); } else { if (io_val & LPI_GPIO_VALUE_OUT_MASK) - lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, - io_val & ~LPI_GPIO_VALUE_OUT_MASK); + ret =3D lpi_gpio_write(pctrl, group, + LPI_GPIO_VALUE_REG, + io_val & ~LPI_GPIO_VALUE_OUT_MASK); } + if (ret) + return ret; } =20 u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK); - lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val); - mutex_unlock(&pctrl->lock); - - return 0; + return lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val); } =20 static const struct pinmux_ops lpi_gpio_pinmux_ops =3D { @@ -162,11 +186,15 @@ static int lpi_config_get(struct pinctrl_dev *pctldev, unsigned int param =3D pinconf_to_config_param(*config); struct lpi_pinctrl *state =3D dev_get_drvdata(pctldev->dev); unsigned int arg =3D 0; + int ret; int is_out; int pull; u32 ctl_reg; =20 - ctl_reg =3D lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG); + ret =3D lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG, &ctl_reg); + if (ret) + return ret; + is_out =3D ctl_reg & LPI_GPIO_OE_MASK; pull =3D FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg); =20 @@ -206,7 +234,7 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl = *pctrl, { unsigned long sval; void __iomem *reg; - int slew_offset; + int slew_offset, ret; =20 if (slew > LPI_SLEW_RATE_MAX) { dev_err(pctrl->dev, "invalid slew rate %u for pin: %d\n", @@ -225,6 +253,10 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl= *pctrl, else reg =3D pctrl->slew_base + LPI_SLEW_RATE_CTL_REG; =20 + ret =3D pm_runtime_resume_and_get(pctrl->dev); + if (ret < 0) + return ret; + mutex_lock(&pctrl->lock); =20 sval =3D ioread32(reg); @@ -233,6 +265,9 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl = *pctrl, iowrite32(sval, reg); =20 mutex_unlock(&pctrl->lock); + ret =3D pm_runtime_put_autosuspend(pctrl->dev); + if (ret < 0) + return ret; =20 return 0; } @@ -291,21 +326,22 @@ static int lpi_config_set(struct pinctrl_dev *pctldev= , unsigned int group, */ if (output_enabled) { val =3D u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK); - lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val); + ret =3D lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val); + if (ret) + return ret; } =20 - mutex_lock(&pctrl->lock); - val =3D lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG); + guard(mutex)(&pctrl->lock); + ret =3D lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG, &val); + if (ret) + return ret; =20 u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK); u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength), LPI_GPIO_OUT_STRENGTH_MASK); u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK); =20 - lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val); - mutex_unlock(&pctrl->lock); - - return 0; + return lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val); } =20 static const struct pinconf_ops lpi_gpio_pinconf_ops =3D { @@ -354,9 +390,14 @@ static int lpi_gpio_direction_output(struct gpio_chip = *chip, static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin) { struct lpi_pinctrl *state =3D gpiochip_get_data(chip); + u32 val; + int ret; + + ret =3D lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG, &val); + if (ret) + return ret; =20 - return lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG) & - LPI_GPIO_VALUE_IN_MASK; + return val & LPI_GPIO_VALUE_IN_MASK; } =20 static int lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int valu= e) @@ -399,7 +440,9 @@ static void lpi_gpio_dbg_show_one(struct seq_file *s, =20 pctldev =3D pctldev ? : state->ctrl; pindesc =3D pctldev->desc->pins[offset]; - ctl_reg =3D lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG); + if (lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG, &ctl_reg)) + return; + is_out =3D ctl_reg & LPI_GPIO_OE_MASK; =20 func =3D FIELD_GET(LPI_GPIO_FUNCTION_MASK, ctl_reg); @@ -482,9 +525,6 @@ int lpi_pinctrl_probe(struct platform_device *pdev) pctrl->data =3D data; pctrl->dev =3D &pdev->dev; =20 - pctrl->clks[0].id =3D "core"; - pctrl->clks[1].id =3D "audio"; - pctrl->tlmm_base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pctrl->tlmm_base)) return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base), @@ -497,13 +537,19 @@ int lpi_pinctrl_probe(struct platform_device *pdev) "Slew resource not provided\n"); } =20 - ret =3D devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks); + ret =3D devm_pm_clk_create(dev); if (ret) return ret; =20 - ret =3D clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks); + ret =3D of_pm_clk_add_clks(dev); + if (ret < 0 && ret !=3D -ENODEV) + return ret; + + pm_runtime_set_autosuspend_delay(dev, 100); + pm_runtime_use_autosuspend(dev); + ret =3D devm_pm_runtime_enable(dev); if (ret) - return dev_err_probe(dev, ret, "Can't enable clocks\n"); + return ret; =20 pctrl->desc.pctlops =3D &lpi_gpio_pinctrl_ops; pctrl->desc.pmxops =3D &lpi_gpio_pinmux_ops; @@ -542,7 +588,6 @@ int lpi_pinctrl_probe(struct platform_device *pdev) =20 err_pinctrl: mutex_destroy(&pctrl->lock); - clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks); =20 return ret; } @@ -554,7 +599,6 @@ void lpi_pinctrl_remove(struct platform_device *pdev) int i; =20 mutex_destroy(&pctrl->lock); - clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks); =20 for (i =3D 0; i < pctrl->data->npins; i++) pinctrl_generic_remove_group(pctrl->ctrl, i); diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sc7280-lpass-lpi.c index 750f410311a8..64a200dd8f41 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -139,10 +141,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { .name =3D "qcom-sc7280-lpass-lpi-pinctrl", .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, --=20 2.34.1 From nobody Sat Jun 13 08:47:17 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E7463CF688 for ; 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charset="utf-8" Convert the LPASS LPI pinctrl driver to use the PM clock framework for runtime power management. This allows the LPASS LPI pinctrl driver to drop clock votes when idle, improves power efficiency on platforms using LPASS LPI island mode, and aligns the driver with common runtime PM patterns used across Qualcomm LPASS subsystems. Guard GPIO register read/write helpers and slew-rate register programming with synchronous runtime PM calls so the device is active during MMIO operations whenever autosuspend is enabled. Signed-off-by: Ajay Kumar Nandam --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 109 +++++++++++++----- .../pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 7 ++ 2 files changed, 84 insertions(+), 32 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qco= m/pinctrl-lpass-lpi.c index 15ced5027579..cd5dd18fd149 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include =20 #include "../pinctrl-utils.h" =20 @@ -22,7 +24,6 @@ =20 #define MAX_NR_GPIO 32 #define GPIO_FUNC 0 -#define MAX_LPI_NUM_CLKS 2 =20 struct lpi_pinctrl { struct device *dev; @@ -31,7 +32,6 @@ struct lpi_pinctrl { struct pinctrl_desc desc; char __iomem *tlmm_base; char __iomem *slew_base; - struct clk_bulk_data clks[MAX_LPI_NUM_CLKS]; /* Protects from concurrent register updates */ struct mutex lock; DECLARE_BITMAP(ever_gpio, MAX_NR_GPIO); @@ -39,29 +39,43 @@ struct lpi_pinctrl { }; =20 static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, - unsigned int addr) + unsigned int addr, u32 *val) { u32 pin_offset; + int ret; =20 if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET) pin_offset =3D state->data->groups[pin].pin_offset; else pin_offset =3D LPI_TLMM_REG_OFFSET * pin; =20 - return ioread32(state->tlmm_base + pin_offset + addr); + ret =3D pm_runtime_resume_and_get(state->dev); + if (ret < 0) + return ret; + + *val =3D ioread32(state->tlmm_base + pin_offset + addr); + pm_runtime_put_autosuspend(state->dev); + + return 0; } =20 static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin, unsigned int addr, unsigned int val) { u32 pin_offset; + int ret; =20 if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET) pin_offset =3D state->data->groups[pin].pin_offset; else pin_offset =3D LPI_TLMM_REG_OFFSET * pin; =20 + ret =3D pm_runtime_resume_and_get(state->dev); + if (ret < 0) + return ret; + iowrite32(val, state->tlmm_base + pin_offset + addr); + pm_runtime_put_autosuspend(state->dev); =20 return 0; } @@ -107,8 +121,8 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev= , unsigned int function, { struct lpi_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctldev); const struct lpi_pingroup *g =3D &pctrl->data->groups[group]; - u32 val; - int i, pin =3D g->pin; + u32 val, io_val; + int i, pin =3D g->pin, ret; =20 for (i =3D 0; i < g->nfuncs; i++) { if (g->funcs[i] =3D=3D function) @@ -119,7 +133,9 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev= , unsigned int function, return -EINVAL; =20 mutex_lock(&pctrl->lock); - val =3D lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG); + ret =3D lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG, &val); + if (ret) + goto unlock; =20 /* * If this is the first time muxing to GPIO and the direction is @@ -129,24 +145,32 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctld= ev, unsigned int function, */ if (i =3D=3D GPIO_FUNC && (val & LPI_GPIO_OE_MASK) && !test_and_set_bit(group, pctrl->ever_gpio)) { - u32 io_val =3D lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG); + ret =3D lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG, &io_val); + if (ret) + goto unlock; =20 if (io_val & LPI_GPIO_VALUE_IN_MASK) { if (!(io_val & LPI_GPIO_VALUE_OUT_MASK)) - lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, - io_val | LPI_GPIO_VALUE_OUT_MASK); + ret =3D lpi_gpio_write(pctrl, group, + LPI_GPIO_VALUE_REG, + io_val | LPI_GPIO_VALUE_OUT_MASK); } else { if (io_val & LPI_GPIO_VALUE_OUT_MASK) - lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, - io_val & ~LPI_GPIO_VALUE_OUT_MASK); + ret =3D lpi_gpio_write(pctrl, group, + LPI_GPIO_VALUE_REG, + io_val & ~LPI_GPIO_VALUE_OUT_MASK); } + if (ret) + goto unlock; } =20 u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK); - lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val); + ret =3D lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val); + +unlock: mutex_unlock(&pctrl->lock); =20 - return 0; + return ret; } =20 static const struct pinmux_ops lpi_gpio_pinmux_ops =3D { @@ -162,11 +186,15 @@ static int lpi_config_get(struct pinctrl_dev *pctldev, unsigned int param =3D pinconf_to_config_param(*config); struct lpi_pinctrl *state =3D dev_get_drvdata(pctldev->dev); unsigned int arg =3D 0; + int ret; int is_out; int pull; u32 ctl_reg; =20 - ctl_reg =3D lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG); + ret =3D lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG, &ctl_reg); + if (ret) + return ret; + is_out =3D ctl_reg & LPI_GPIO_OE_MASK; pull =3D FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg); =20 @@ -206,7 +234,7 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl = *pctrl, { unsigned long sval; void __iomem *reg; - int slew_offset; + int slew_offset, ret; =20 if (slew > LPI_SLEW_RATE_MAX) { dev_err(pctrl->dev, "invalid slew rate %u for pin: %d\n", @@ -225,6 +253,10 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl= *pctrl, else reg =3D pctrl->slew_base + LPI_SLEW_RATE_CTL_REG; =20 + ret =3D pm_runtime_resume_and_get(pctrl->dev); + if (ret < 0) + return ret; + mutex_lock(&pctrl->lock); =20 sval =3D ioread32(reg); @@ -233,6 +265,7 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl = *pctrl, iowrite32(sval, reg); =20 mutex_unlock(&pctrl->lock); + pm_runtime_put_autosuspend(pctrl->dev); =20 return 0; } @@ -291,21 +324,27 @@ static int lpi_config_set(struct pinctrl_dev *pctldev= , unsigned int group, */ if (output_enabled) { val =3D u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK); - lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val); + ret =3D lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val); + if (ret) + return ret; } =20 mutex_lock(&pctrl->lock); - val =3D lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG); + ret =3D lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG, &val); + if (ret) + goto unlock; =20 u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK); u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength), LPI_GPIO_OUT_STRENGTH_MASK); u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK); =20 - lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val); + ret =3D lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val); + +unlock: mutex_unlock(&pctrl->lock); =20 - return 0; + return ret; } =20 static const struct pinconf_ops lpi_gpio_pinconf_ops =3D { @@ -354,9 +393,14 @@ static int lpi_gpio_direction_output(struct gpio_chip = *chip, static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin) { struct lpi_pinctrl *state =3D gpiochip_get_data(chip); + u32 val; + int ret; =20 - return lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG) & - LPI_GPIO_VALUE_IN_MASK; + ret =3D lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG, &val); + if (ret) + return ret; + + return val & LPI_GPIO_VALUE_IN_MASK; } =20 static int lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int valu= e) @@ -399,7 +443,9 @@ static void lpi_gpio_dbg_show_one(struct seq_file *s, =20 pctldev =3D pctldev ? : state->ctrl; pindesc =3D pctldev->desc->pins[offset]; - ctl_reg =3D lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG); + if (lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG, &ctl_reg)) + return; + is_out =3D ctl_reg & LPI_GPIO_OE_MASK; =20 func =3D FIELD_GET(LPI_GPIO_FUNCTION_MASK, ctl_reg); @@ -482,9 +528,6 @@ int lpi_pinctrl_probe(struct platform_device *pdev) pctrl->data =3D data; pctrl->dev =3D &pdev->dev; =20 - pctrl->clks[0].id =3D "core"; - pctrl->clks[1].id =3D "audio"; - pctrl->tlmm_base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pctrl->tlmm_base)) return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base), @@ -497,13 +540,17 @@ int lpi_pinctrl_probe(struct platform_device *pdev) "Slew resource not provided\n"); } =20 - ret =3D devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks); + ret =3D devm_pm_clk_create(dev); if (ret) return ret; =20 - ret =3D clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks); - if (ret) - return dev_err_probe(dev, ret, "Can't enable clocks\n"); + ret =3D of_pm_clk_add_clks(dev); + if (ret < 0 && ret !=3D -ENODEV) + return ret; + + pm_runtime_set_autosuspend_delay(dev, 100); + pm_runtime_use_autosuspend(dev); + devm_pm_runtime_enable(dev); =20 pctrl->desc.pctlops =3D &lpi_gpio_pinctrl_ops; pctrl->desc.pmxops =3D &lpi_gpio_pinmux_ops; @@ -542,7 +589,6 @@ int lpi_pinctrl_probe(struct platform_device *pdev) =20 err_pinctrl: mutex_destroy(&pctrl->lock); - clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks); =20 return ret; } @@ -554,7 +600,6 @@ void lpi_pinctrl_remove(struct platform_device *pdev) int i; =20 mutex_destroy(&pctrl->lock); - clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks); =20 for (i =3D 0; i < pctrl->data->npins; i++) pinctrl_generic_remove_group(pctrl->ctrl, i); diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sc7280-lpass-lpi.c index 750f410311a8..64a200dd8f41 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -139,10 +141,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { .name =3D "qcom-sc7280-lpass-lpi-pinctrl", .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, --=20 2.34.1