From nobody Wed Jun 10 18:53:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1318C3A9015 for ; Fri, 8 May 2026 09:42:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778233331; cv=none; b=geW0e/cPP5EqgQPLzRH1TnMlpsIQGZUynxXyJYSxuQjNXKYo5MzNATKW6tp2HnQ9vSdmolv/4IyTeeBnH0KgNc/T2syoqpfb1Grwp43OC/IVzfRQ8cs0B9/feAcBXTalcnSrmnfZ0diV7C8t7WF5x01xTVV4XGGLKMccRMn/Ac0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778233331; c=relaxed/simple; bh=GPhoEjDGFx9BVoj9SRTvn0iSRPYFTMcD7bFsJRUCGDU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SZi9YNej+N/Y2nakRv8+yycTuX2u6TevCKHj+RjlQ1V6OYgjD+VwvRntS/L1APh/wjfGSrnI4MZlfpLeRvClfZMv8eC3AQFRDgqpDOeWYbv2WyuC/lNh/adRk7wfTZV8Bm/AYEiU/OuLhWXHxOT40VIhA3cDAZ/Hbj0zr53IEG0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HGBShA2I; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HGBShA2I" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B6D2EC2BCC7; Fri, 8 May 2026 09:42:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778233330; bh=GPhoEjDGFx9BVoj9SRTvn0iSRPYFTMcD7bFsJRUCGDU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HGBShA2IUsCHC7V0xZ++hE7s8ZD6nOMXqgEvW8isg937ULi8Q9+1PtKVknw4ZL3WD lEfswV4JzbamRuk/uriNBrLWh3QCPr67JYCojfbik5GwCk+RRlRIveLwbeqWVilTI1 UG4g4fQpGMy77W5v/6VFz6jNTDF6FbYo+DnKHwHXqRgEDfK4dztPpWDCZrQNAv+uHy fBpY7lursarny30NUCvEG9b3BD51j/zDfWyq6xhNbh0usSoPGIN5lAuOpX1ctBVeOR sTbBuz8lBsTlxX5TT/85cgWV8CTkoZhBsQsUECYdiUdT2BThjV+y2EdIw1Me0N3vCD 4ghid/PY9B/XA== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wLHii-00000000HJz-37k0; Fri, 08 May 2026 09:42:08 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Thomas Gleixner , Ben Horgan , Daniel Lezcano Subject: [PATCH v2 1/5] clocksource/drivers/arm_arch_timer: Add a static key indicating the need for a runtime workaround Date: Fri, 8 May 2026 10:41:59 +0100 Message-ID: <20260508094203.2913880-2-maz@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260508094203.2913880-1-maz@kernel.org> References: <20260508094203.2913880-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, tglx@kernel.org, ben.horgan@arm.com, daniel.lezcano@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Content-Type: text/plain; charset="utf-8" In order to decide whether we can read the architected counter without disabling preemption to look up a workaround, introduce a static key that denotes whether a workaround is required at all. The behaviour of this new static key is a bit unusual: - it starts as 'true', indicating that workarounds are required - each time a new CPU boots, it is added to a cpumask - when all possible CPUs have booted at least once, and that it has been established that none of them require a workaround, the key flips to 'false' Of course, as long as not all the CPUs have booted once, you may end-up with slow accessors, but that's what you get for not sharing your toys. Things are made a bit complicated because static keys cannot be flipped from a CPUHP callback. Instead, schedule a deferred work from there. Yes, this is fun. Nothing is making use of this stuff yet, but watch this space. Signed-off-by: Marc Zyngier --- drivers/clocksource/arm_arch_timer.c | 33 ++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm= _arch_timer.c index 90aeff44a2764..c5b42001c9282 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -90,6 +90,8 @@ static int arch_counter_get_width(void) /* * Architected system timer support. */ +static inline bool arch_counter_broken_accessors(void); + static noinstr u64 raw_counter_get_cntpct_stable(void) { return __arch_counter_get_cntpct_stable(); @@ -555,10 +557,40 @@ static bool arch_timer_counter_has_wa(void) { return atomic_read(&timer_unstable_counter_workaround_in_use); } + +static DEFINE_STATIC_KEY_TRUE(broken_cnt_accessors); + +static inline bool arch_counter_broken_accessors(void) +{ + return static_branch_unlikely(&broken_cnt_accessors); +} + +static void enable_direct_accessors(struct work_struct *wk) +{ + pr_info("Enabling direct accessors\n"); + static_branch_disable(&broken_cnt_accessors); +} + +static int arch_timer_set_direct_accessors(unsigned int cpu) +{ + static DECLARE_WORK(enable_accessors_wk, enable_direct_accessors); + static cpumask_t seen_cpus; + + cpumask_set_cpu(cpu, &seen_cpus); + + if (arch_counter_broken_accessors() && + !arch_timer_counter_has_wa() && + cpumask_equal(&seen_cpus, cpu_possible_mask)) + schedule_work(&enable_accessors_wk); + + return 0; +} #else #define arch_timer_check_ool_workaround(t,a) do { } while(0) #define arch_timer_this_cpu_has_cntvct_wa() ({false;}) #define arch_timer_counter_has_wa() ({false;}) +static inline bool arch_counter_broken_accessors(void) { return false ; } +#define arch_timer_set_direct_accessors(c) do { } while(0) #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */ =20 static __always_inline irqreturn_t timer_handler(const int access, @@ -840,6 +872,7 @@ static int arch_timer_starting_cpu(unsigned int cpu) } =20 arch_counter_set_user_access(); + arch_timer_set_direct_accessors(cpu); =20 return 0; } --=20 2.47.3 From nobody Wed Jun 10 18:53:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 130853A6B77 for ; Fri, 8 May 2026 09:42:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778233331; cv=none; b=mSYWJq8kmY9uw1tcXmqDeASb6Ee3aww/0H0yxr0OqEweN8NvEcjLKRXVh7M/lJFQ+Jg0jJy5HOScYMAYN3LiDwKxW0XbLbHdgfm4yzC1WxXo6Qzy7vNvxWGVQbIV1j3lo5Xbnm7xfIdptX/MIY2M2HZYGhU9he9LuT8PZt0nprY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778233331; c=relaxed/simple; bh=PlhXgFp9jn4wn5ui/B/bv4QBDAuir3YiMvnBhoH2GEI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MhGMj1no6JQ/DYNcB+gh52b4n/9H0tUTEqs3PosZDvc1S2Zdkfm0DjuIgJYzwsNstg6vzqtLpmXOiUYSsQ2bznP54Qxei2V0d9LiROOez1nL5bOOJcSoLZpidKJTjIctwFE31I873+dsXWlF4zbIn8fnnZ2iBCItab2AlHTMq7Y= ARC-Authentication-Results: i=1; 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Fri, 08 May 2026 09:42:09 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Thomas Gleixner , Ben Horgan , Daniel Lezcano Subject: [PATCH v2 2/5] clocksource/drivers/arm_arch_timer: Convert counter accessors to a static key alternative Date: Fri, 8 May 2026 10:42:00 +0100 Message-ID: <20260508094203.2913880-3-maz@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260508094203.2913880-1-maz@kernel.org> References: <20260508094203.2913880-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, tglx@kernel.org, ben.horgan@arm.com, daniel.lezcano@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Content-Type: text/plain; charset="utf-8" Now that we have a reliable static key to control whether our counter accessors need to be worked around, use it in these accessors and simplify the logic that picks which accessor to use. Signed-off-by: Marc Zyngier --- drivers/clocksource/arm_arch_timer.c | 38 +++++++++++++++------------- 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm= _arch_timer.c index c5b42001c9282..723ba698b8c46 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -92,9 +92,12 @@ static int arch_counter_get_width(void) */ static inline bool arch_counter_broken_accessors(void); =20 -static noinstr u64 raw_counter_get_cntpct_stable(void) +static noinstr u64 raw_counter_get_cntpct(void) { - return __arch_counter_get_cntpct_stable(); + if (arch_counter_broken_accessors()) + return __arch_counter_get_cntpct_stable(); + + return __arch_counter_get_cntpct(); } =20 static notrace u64 arch_counter_get_cntpct_stable(void) @@ -108,12 +111,18 @@ static notrace u64 arch_counter_get_cntpct_stable(voi= d) =20 static noinstr u64 arch_counter_get_cntpct(void) { + if (arch_counter_broken_accessors()) + return arch_counter_get_cntpct_stable(); + return __arch_counter_get_cntpct(); } =20 -static noinstr u64 raw_counter_get_cntvct_stable(void) +static noinstr u64 raw_counter_get_cntvct(void) { - return __arch_counter_get_cntvct_stable(); + if (arch_counter_broken_accessors()) + return __arch_counter_get_cntvct_stable(); + + return __arch_counter_get_cntvct(); } =20 static notrace u64 arch_counter_get_cntvct_stable(void) @@ -127,6 +136,9 @@ static notrace u64 arch_counter_get_cntvct_stable(void) =20 static noinstr u64 arch_counter_get_cntvct(void) { + if (arch_counter_broken_accessors()) + return arch_counter_get_cntvct_stable(); + return __arch_counter_get_cntvct(); } =20 @@ -946,21 +958,11 @@ static void __init arch_counter_register(void) =20 if ((IS_ENABLED(CONFIG_ARM64) && !is_hyp_mode_available()) || arch_timer_uses_ppi =3D=3D ARCH_TIMER_VIRT_PPI) { - if (arch_timer_counter_has_wa()) { - rd =3D arch_counter_get_cntvct_stable; - scr =3D raw_counter_get_cntvct_stable; - } else { - rd =3D arch_counter_get_cntvct; - scr =3D arch_counter_get_cntvct; - } + rd =3D arch_counter_get_cntvct; + scr =3D raw_counter_get_cntvct; } else { - if (arch_timer_counter_has_wa()) { - rd =3D arch_counter_get_cntpct_stable; - scr =3D raw_counter_get_cntpct_stable; - } else { - rd =3D arch_counter_get_cntpct; - scr =3D arch_counter_get_cntpct; - } + rd =3D arch_counter_get_cntpct; + scr =3D raw_counter_get_cntpct; } =20 arch_timer_read_counter =3D rd; --=20 2.47.3 From nobody Wed Jun 10 18:53:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12FF13A5456 for ; Fri, 8 May 2026 09:42:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778233331; cv=none; b=Xv2Zi1brgkt0o9z+oVtfZPSOMYkIUnYUwJENcTgX9d+zh7WgcDCwV+l+z7+WmPzA/s9ZkIhrT021tMOmSBCgOT2fmZtnbKQ2Ln33dtKfsFyAbOX2wpKLczCf9xNi8tnKreyeN60EIAXQ7/2N1jfPDKbh9+yl5IYv109pGae4S0s= ARC-Message-Signature: i=1; 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b=Eqmf2fbsQbA2BWPyWIMWJfUkvGnX1XSkcqElAl/39PV8yUZVZKrsjcu6eyfzZ29PN PGSC1+cWZv0zzifpt79p8yA7mknws+KJmbQiEgjMIUOrhxh9BCVaA/ynvGEcjvHJ0r xhq9bt5O8a+v81ITtamh17GXTQkoYWZwvkC9Aghrzm6lEULDxqJFYOnCEXmbxbxoad Y9xJSM6JzwoLyW8uIvBNkpgbhQJ+IldsKxLWI4VSiEp1f+T02Vr5KgVVTTFCqxIbuP aUuy1r3N24ArnE31hwc0JtMdbdV+Em5G4+z83FRcXkHFYL4r8oDq259fNwijm2AwfN QxVGzH3i5hGiA== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wLHij-00000000HJz-0Yy7; Fri, 08 May 2026 09:42:09 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Thomas Gleixner , Ben Horgan , Daniel Lezcano Subject: [PATCH v2 3/5] clocksource/drivers/arm_arch_timer: Drop the arch_counter_get_cnt{p,v}ct_stable() accessors Date: Fri, 8 May 2026 10:42:01 +0100 Message-ID: <20260508094203.2913880-4-maz@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260508094203.2913880-1-maz@kernel.org> References: <20260508094203.2913880-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, tglx@kernel.org, ben.horgan@arm.com, daniel.lezcano@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Content-Type: text/plain; charset="utf-8" Further simplify the counter accessors by eliminating the *_stable() ones, which serve little purpose at this stage. Signed-off-by: Marc Zyngier --- drivers/clocksource/arm_arch_timer.c | 38 +++++++++------------------- 1 file changed, 12 insertions(+), 26 deletions(-) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm= _arch_timer.c index 723ba698b8c46..ee21804d6613c 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -100,19 +100,12 @@ static noinstr u64 raw_counter_get_cntpct(void) return __arch_counter_get_cntpct(); } =20 -static notrace u64 arch_counter_get_cntpct_stable(void) +static notrace u64 arch_counter_get_cntpct(void) { - u64 val; - preempt_disable_notrace(); - val =3D __arch_counter_get_cntpct_stable(); - preempt_enable_notrace(); - return val; -} - -static noinstr u64 arch_counter_get_cntpct(void) -{ - if (arch_counter_broken_accessors()) - return arch_counter_get_cntpct_stable(); + if (arch_counter_broken_accessors()) { + guard(preempt_notrace)(); + return __arch_counter_get_cntpct_stable(); + } =20 return __arch_counter_get_cntpct(); } @@ -125,19 +118,12 @@ static noinstr u64 raw_counter_get_cntvct(void) return __arch_counter_get_cntvct(); } =20 -static notrace u64 arch_counter_get_cntvct_stable(void) +static notrace u64 arch_counter_get_cntvct(void) { - u64 val; - preempt_disable_notrace(); - val =3D __arch_counter_get_cntvct_stable(); - preempt_enable_notrace(); - return val; -} - -static noinstr u64 arch_counter_get_cntvct(void) -{ - if (arch_counter_broken_accessors()) - return arch_counter_get_cntvct_stable(); + if (arch_counter_broken_accessors()) { + guard(preempt_notrace)(); + return __arch_counter_get_cntvct_stable(); + } =20 return __arch_counter_get_cntvct(); } @@ -342,10 +328,10 @@ void erratum_set_next_event_generic(const int access,= unsigned long evt, ctrl &=3D ~ARCH_TIMER_CTRL_IT_MASK; =20 if (access =3D=3D ARCH_TIMER_PHYS_ACCESS) { - cval =3D evt + arch_counter_get_cntpct_stable(); + cval =3D evt + arch_counter_get_cntpct(); write_sysreg(cval, cntp_cval_el0); } else { - cval =3D evt + arch_counter_get_cntvct_stable(); + cval =3D evt + arch_counter_get_cntvct(); write_sysreg(cval, cntv_cval_el0); } =20 --=20 2.47.3 From nobody Wed Jun 10 18:53:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F3B33C061D for ; Fri, 8 May 2026 09:42:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778233331; cv=none; b=raHa+1RF38rWRUE1TuMP/G5F3ESLpdv/7OumaOOE++zRGf6KbB0mWQ7zLP4jvEm9hkN/RzyFmiQJbixXOtag7PyJr4aYKcIGGgJXpnV+FXfdWmzzFiqM1C0XBnsbCqEwCJN0cU3UNAzPsQXdEtHJIHaJov6Qw5BRnUu+GT+QbdU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778233331; c=relaxed/simple; bh=Ng7f/Ng6zPtl5KJt5T+b4Vt/9C+9LhrfLa105ysMhuc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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Fri, 08 May 2026 09:42:09 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Thomas Gleixner , Ben Horgan , Daniel Lezcano Subject: [PATCH v2 4/5] clocksource/drivers/arm_arch_timer: Expose a direct accessor for the virtual counter Date: Fri, 8 May 2026 10:42:02 +0100 Message-ID: <20260508094203.2913880-5-maz@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260508094203.2913880-1-maz@kernel.org> References: <20260508094203.2913880-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, tglx@kernel.org, ben.horgan@arm.com, daniel.lezcano@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Content-Type: text/plain; charset="utf-8" We allow access to the architected counter via arch_timer_read_counter(). However, this accessor can either be the virtual or the physical view of the counter, depending on how the kernel has been booted. At the same time, we have some architectural features (such as WFIT, WFET) that rely on the virtual counter, and nothing else. If implementations were perfect, we'd rely on reading CNTVCT_EL0, and be done with it. However, we have a bunch of broken implementations in the wild, which rely on preemption being disabled and other costly workarounds. In order to provide decent performance on non-broken HW while still supporting the legacy horrors, expose arch_timer_read_vcounter() as a new helper that hides this complexity. Obviously, this is simply a global alias of arch_counter_get_cntvct(). Signed-off-by: Marc Zyngier --- drivers/clocksource/arm_arch_timer.c | 2 ++ include/clocksource/arm_arch_timer.h | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm= _arch_timer.c index ee21804d6613c..6fcd9afad38c2 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -137,6 +137,8 @@ static notrace u64 arch_counter_get_cntvct(void) u64 (*arch_timer_read_counter)(void) __ro_after_init =3D arch_counter_get_= cntvct; EXPORT_SYMBOL_GPL(arch_timer_read_counter); =20 +u64 arch_timer_read_vcounter(void) __attribute__((alias("arch_counter_get_= cntvct"))); + static u64 arch_counter_read(struct clocksource *cs) { return arch_timer_read_counter(); diff --git a/include/clocksource/arm_arch_timer.h b/include/clocksource/arm= _arch_timer.h index 2eda895f19f54..587314e584839 100644 --- a/include/clocksource/arm_arch_timer.h +++ b/include/clocksource/arm_arch_timer.h @@ -88,6 +88,7 @@ struct arch_timer_mem { =20 extern u32 arch_timer_get_rate(void); extern u64 (*arch_timer_read_counter)(void); +extern u64 arch_timer_read_vcounter(void); extern struct arch_timer_kvm_info *arch_timer_get_kvm_info(void); extern bool arch_timer_evtstrm_available(void); =20 --=20 2.47.3 From nobody Wed Jun 10 18:53:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E0A93C199A for ; Fri, 8 May 2026 09:42:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778233331; cv=none; b=Y7HXQfbp03Sa216U+guemPD2MuPAhVR+4N1VqCQmli8AdLFgPqY1XvpUILrx0LG5mGdKvaWx6s+xE/YZv6N4RT0LRMCBYpzsYAqOadC0nb2/NypYJiqgOaheEFuyVnsNo0SeNQnX7vo3tn5ruBhIKulyn0b7syVFUG5ZjO5ioWY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778233331; c=relaxed/simple; bh=gZfp7AFUDRuKyFzNq7gSRxIUj7Mf0Qt8SSGk362fa3U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XL1bAjpg3AZITVGwO/PIA8stHNo/i/9lbxJp55Ws+WpUOdSFEWNGDrzphCeXIgTRL+jq5PrkKKNB8Y5z3loRtAJpmh1AbM/iX+bt80UUdeG4z/QOF+kyQigT8zguxkEBD5PM2sljGLYxlvUNd3EKPa8TwfGyCAz6SlpduRRhuo4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pY9kvXnG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pY9kvXnG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4B62DC2BCB8; Fri, 8 May 2026 09:42:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778233331; bh=gZfp7AFUDRuKyFzNq7gSRxIUj7Mf0Qt8SSGk362fa3U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pY9kvXnGRso1B/12FM9wMLIIKOCuq1HszrTPq8bf6Mhfbmv8FSqm5Z2susf9fDC5z WDa8Og42BNii1l9w1zeF++GNWEg4BV/1UIoXC6Q6YTsVzE2nQEXlv1qvDO4EV4/Zww xDWJdkD6pkv56mHOn79/Qw8mmUGgtTxGhzMPdu/8q67Qz/tCGZ0wGGvzDCiOY1gkzA oDwTHvrAamg0zw150QYLRdJGgDO1AQsZB/XY3kcAvQVXE/0XhAHS3oQwcr1fHOSHkc Sx/Ox6BW0Q5jkkjIegShPFWs0YXs7QEWU8Kk77S97wMACk+hFQ5XWE4sXHiQL8u423 lekvwz9rJkBdA== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wLHij-00000000HJz-29OQ; Fri, 08 May 2026 09:42:09 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Thomas Gleixner , Ben Horgan , Daniel Lezcano Subject: [PATCH v2 5/5] arm64: Convert __delay_cycles() to arch_timer_read_vcounter() Date: Fri, 8 May 2026 10:42:03 +0100 Message-ID: <20260508094203.2913880-6-maz@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260508094203.2913880-1-maz@kernel.org> References: <20260508094203.2913880-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, tglx@kernel.org, ben.horgan@arm.com, daniel.lezcano@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Content-Type: text/plain; charset="utf-8" Relax the need for disabling preemption in __delay_cycles() by using arch_timer_read_vcounter(), which will disable preemption only when this is actually required. Signed-off-by: Marc Zyngier Acked-by: Catalin Marinas --- arch/arm64/lib/delay.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/lib/delay.c b/arch/arm64/lib/delay.c index e278e060e78a9..a667df920697d 100644 --- a/arch/arm64/lib/delay.c +++ b/arch/arm64/lib/delay.c @@ -32,10 +32,9 @@ static inline unsigned long xloops_to_cycles(unsigned lo= ng xloops) * Note that userspace cannot change the offset behind our back either, * as the vcpu mutex is held as long as KVM_RUN is in progress. */ -static cycles_t notrace __delay_cycles(void) +static cycles_t __delay_cycles(void) { - guard(preempt_notrace)(); - return __arch_counter_get_cntvct_stable(); + return arch_timer_read_vcounter(); } =20 void __delay(unsigned long cycles) --=20 2.47.3