From nobody Sat Jun 13 09:21:31 2026 Received: from out30-97.freemail.mail.aliyun.com (out30-97.freemail.mail.aliyun.com [115.124.30.97]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B56C1199D8; Fri, 8 May 2026 08:20:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.97 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778228435; cv=none; b=alcNLqupCwf1T1t12dLCQUDnaNgq5ObOjRyDDI1AkVsx/bMNWrifJJScBreVgGomkzArx2KaBqtF9tAJ/Xhe6DpUyDp9QbD1IMBJK5wrg1XTutWIuY6ETX1CQ+PkTYlgPe4h7a+nKwiPfGq9Qb5Rl1TLe/73THH/2RHoClwDv9Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778228435; c=relaxed/simple; bh=IgNldgSNJuH2+rIIQUxUrYE1LC7TJ2fKuJV1Gfi7Ce0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qpMHgPUl1HkV+1+1qw0hJIS6vLXEoA978bYg5FqeOWchnREwQMgwqA1/CXh42X5k+vZvf7I7C+f0+TkeX/Nv//ScSCgQVDoj54WGlUVJlb66ThBbabMDEDwj4M9RIcBQE4U3Q1qUUUsCwSK11wSllsNNgPoJlW6uTEZBiA5/yes= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=g56H8FY0; arc=none smtp.client-ip=115.124.30.97 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="g56H8FY0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1778228429; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=JFOE0oOtrup94m1Ct2dbwxOhyCe8CzDhIKZx+1CT/OA=; b=g56H8FY0VmPgebe/uFhqE+NQ9DKZ+CDCtNJ1WYybL3EA9mkL/Wc9YcIpnlKlSX5iGfGCZgtra9EdRs8j0dR3MESUdL/i9B36UxLTDsuAdzAMsOe1821DVvpiZblSPfGOf6gObWscyTf5SQ8e7SIgKn2bxN2L74Q3TGzMQ+TnBUo= X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R251e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam033037026112;MF=tianruidong@linux.alibaba.com;NM=1;PH=DS;RN=17;SR=0;TI=SMTPD_---0X2Wljwh_1778228426; Received: from localhost(mailfrom:tianruidong@linux.alibaba.com fp:SMTPD_---0X2Wljwh_1778228426 cluster:ay36) by smtp.aliyun-inc.com; Fri, 08 May 2026 16:20:28 +0800 From: Ruidong Tian To: pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, rafael@kernel.org, tony.luck@intel.com, bp@alien8.de, guohanjun@huawei.com, mchehab@kernel.org, xueshuai@linux.alibaba.com, lenb@kernel.org, saket.dumbre@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, Ruidong Tian Subject: [PATCH 1/3] acpi: Introduce HEE in HEST notification types Date: Fri, 8 May 2026 16:20:18 +0800 Message-ID: <20260508082020.3368109-2-tianruidong@linux.alibaba.com> X-Mailer: git-send-email 2.43.7 In-Reply-To: <20260508082020.3368109-1-tianruidong@linux.alibaba.com> References: <20260508082020.3368109-1-tianruidong@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce a new HEST notification type for RISC-V Hardware Error Exception. The GHES entry's notification structure contains the notification to be used for a given error source. Signed-off-by: Ruidong Tian --- include/acpi/actbl1.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index 14924383e2d0..2c1ad1d8587b 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -1793,7 +1793,8 @@ enum acpi_hest_notify_types { ACPI_HEST_NOTIFY_GSIV =3D 10, /* ACPI 6.1 */ ACPI_HEST_NOTIFY_SOFTWARE_DELEGATED =3D 11, /* ACPI 6.2 */ ACPI_HEST_NOTIFY_SSE =3D 12, /* RISCV SSE */ - ACPI_HEST_NOTIFY_RESERVED =3D 13 /* 13 and greater are reserved */ + ACPI_HEST_NOTIFY_HEE =3D 13, /* RISCV Hardware Error Exception */ + ACPI_HEST_NOTIFY_RESERVED =3D 14 /* 14 and greater are reserved */ }; =20 /* Values for config_write_enable bitfield above */ --=20 2.51.2.612.gdc70283dfc From nobody Sat Jun 13 09:21:31 2026 Received: from out30-101.freemail.mail.aliyun.com (out30-101.freemail.mail.aliyun.com [115.124.30.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 036D7355F43; Fri, 8 May 2026 08:20:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.101 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778228439; cv=none; b=cTXp+C4IekxeSn9Urh2grEyl6QNHwJrx+wofbxd4/Gq1yJ1zFUHuHyv5jj5+fKvWqJb5HhtOxOoNFrqyXc6boCPybcTN363/Qq6mWnGpBbff1gldRJX5xn85m5C9rINiPIiMKid4VhBDtWYjL9MEuhq3oIGp42QuFEvM77Rx2is= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778228439; c=relaxed/simple; bh=7CpcYWW59GNFu0zvHmne9YhOrdVY3oWN8KsAngA3nTU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TfePkoGnfWivTJfNse33kFbynrBvGRZwdRsKHD1cadiaEW8A318LL14QacblRc+GFsh/XesaVZI7I6xVJ2xQLIgOZE5ENiAt2+hyi2qsliIQN/MbyBW1buv/O1Gctj1IAsZDGucP0dQJOwqioJwdIpKJmygSj1NnOuYufVVEmoo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=VnSOs7JK; arc=none smtp.client-ip=115.124.30.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="VnSOs7JK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1778228433; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=DJjZjMBaJYjkF31HlOdl7z3vyeK8rjsgXy5CRpGf2GE=; b=VnSOs7JK56mb7+EI3IhWmXc8bYOh+R/AdwQwA31aD0iKcy5oWdfJAFbiZPcSNQKdUI9ZA9dfuaa2h5Id40T+FBMdYDlUIje8GBwE5huGvRFC1g+6IlQRIX5WR/C+fklJVeQl9VuaQuSrj5Dsyd4KLN3Oj1OwLa3HA7Y5w89/4oU= X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R821e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam033037009110;MF=tianruidong@linux.alibaba.com;NM=1;PH=DS;RN=17;SR=0;TI=SMTPD_---0X2WlMBj_1778228429; Received: from localhost(mailfrom:tianruidong@linux.alibaba.com fp:SMTPD_---0X2WlMBj_1778228429 cluster:ay36) by smtp.aliyun-inc.com; Fri, 08 May 2026 16:20:31 +0800 From: Ruidong Tian To: pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, rafael@kernel.org, tony.luck@intel.com, bp@alien8.de, guohanjun@huawei.com, mchehab@kernel.org, xueshuai@linux.alibaba.com, lenb@kernel.org, saket.dumbre@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, Ruidong Tian Subject: [PATCH 2/3] riscv: Introduce HEST HEE notification handlers for APEI Date: Fri, 8 May 2026 16:20:19 +0800 Message-ID: <20260508082020.3368109-3-tianruidong@linux.alibaba.com> X-Mailer: git-send-email 2.43.7 In-Reply-To: <20260508082020.3368109-1-tianruidong@linux.alibaba.com> References: <20260508082020.3368109-1-tianruidong@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add functions to register a ghes entry with HEE, allowing the OS to receive hardware error notifications from firmware through standardized ACPI interfaces. Signed-off-by: Ruidong Tian --- arch/riscv/include/asm/fixmap.h | 3 ++ drivers/acpi/apei/Kconfig | 12 ++++++ drivers/acpi/apei/ghes.c | 68 ++++++++++++++++++++++++++++++++- include/acpi/ghes.h | 6 +++ 4 files changed, 87 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/fixmap.h b/arch/riscv/include/asm/fixma= p.h index e874fd952286..9b3d5bbfda24 100644 --- a/arch/riscv/include/asm/fixmap.h +++ b/arch/riscv/include/asm/fixmap.h @@ -45,6 +45,9 @@ enum fixed_addresses { FIX_APEI_GHES_SSE_LOW_PRIORITY, FIX_APEI_GHES_SSE_HIGH_PRIORITY, #endif /* CONFIG_RISCV_SBI_SSE */ +#ifdef CONFIG_ACPI_APEI_HEE + FIX_APEI_GHES_HEE, +#endif /* CONFIG_ACPI_APEI_HEE */ #endif /* CONFIG_ACPI_APEI_GHES */ __end_of_permanent_fixed_addresses, /* diff --git a/drivers/acpi/apei/Kconfig b/drivers/acpi/apei/Kconfig index 895a843d0e36..ff487ab28a65 100644 --- a/drivers/acpi/apei/Kconfig +++ b/drivers/acpi/apei/Kconfig @@ -51,6 +51,18 @@ config ACPI_APEI_SSE depends on RISCV && RISCV_SBI_SSE && ACPI_APEI_GHES default y =20 +config ACPI_APEI_HEE + bool "APEI Hardware Error Exception support" + depends on RISCV && ACPI_APEI_GHES + default y + help + Enable support for RISC-V Hardware Error Exception (HEE) notification + in ACPI Platform Error Interface (APEI). This allows firmware + to report hardware errors through RISC-V exception mechanism. + + Say Y if you want to support firmware-first error handling + on RISC-V platforms with ACPI. + config ACPI_APEI_MEMORY_FAILURE bool "APEI memory error recovering support" depends on ACPI_APEI && MEMORY_FAILURE diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index f228640d3f25..e0a5db80e554 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -125,7 +125,8 @@ static inline bool is_hest_sync_notify(struct ghes *ghe= s) { u8 notify_type =3D ghes->generic->notify.type; =20 - return notify_type =3D=3D ACPI_HEST_NOTIFY_SEA; + return notify_type =3D=3D ACPI_HEST_NOTIFY_SEA || + notify_type =3D=3D ACPI_HEST_NOTIFY_HEE; } =20 /* @@ -1404,7 +1405,8 @@ static int ghes_in_nmi_queue_one_entry(struct ghes *g= hes, return rc; } =20 -#if defined(CONFIG_HAVE_ACPI_APEI_NMI) || defined(CONFIG_ACPI_APEI_SEA) +#if defined(CONFIG_HAVE_ACPI_APEI_NMI) || defined(CONFIG_ACPI_APEI_SEA) ||= \ + defined(CONFIG_ACPI_APEI_HEE) static int ghes_in_nmi_spool_from_list(struct list_head *rcu_list, enum fixed_addresses fixmap_idx) { @@ -1540,6 +1542,53 @@ static inline int ghes_sea_add(struct ghes *ghes) { = return -EINVAL; } static inline void ghes_sea_remove(struct ghes *ghes) { } #endif /* CONFIG_ACPI_APEI_SEA */ =20 +#ifdef CONFIG_ACPI_APEI_HEE +static LIST_HEAD(ghes_hee); + +/* + * Return 0 only if one of the HEE error sources successfully reported an = error + * record sent from the firmware. + */ +int ghes_notify_hee(void) +{ + static DEFINE_RAW_SPINLOCK(ghes_notify_lock_hee); + int rv; + + raw_spin_lock(&ghes_notify_lock_hee); + rv =3D ghes_in_nmi_spool_from_list(&ghes_hee, FIX_APEI_GHES_HEE); + raw_spin_unlock(&ghes_notify_lock_hee); + + return rv; +} +EXPORT_SYMBOL_GPL(ghes_notify_hee); + +static int ghes_hee_add(struct ghes *ghes) +{ + int rc; + + rc =3D ghes_map_error_status(ghes); + if (rc) + return rc; + + mutex_lock(&ghes_list_mutex); + list_add_rcu(&ghes->list, &ghes_hee); + mutex_unlock(&ghes_list_mutex); + + return 0; +} + +static void ghes_hee_remove(struct ghes *ghes) +{ + mutex_lock(&ghes_list_mutex); + list_del_rcu(&ghes->list); + mutex_unlock(&ghes_list_mutex); + synchronize_rcu(); +} +#else /* CONFIG_ACPI_APEI_HEE */ +static inline void ghes_hee_add(struct ghes *ghes) { } +static inline void ghes_hee_remove(struct ghes *ghes) { } +#endif /* CONFIG_ACPI_APEI_HEE */ + #ifdef CONFIG_HAVE_ACPI_APEI_NMI /* * NMI may be triggered on any CPU, so ghes_in_nmi is used for @@ -1754,6 +1803,13 @@ static int ghes_probe(struct platform_device *ghes_d= ev) goto err; } break; + case ACPI_HEST_NOTIFY_HEE: + if (!IS_ENABLED(CONFIG_ACPI_APEI_HEE)) { + pr_warn(GHES_PFX "Generic hardware error source: %d notified via HEE is= not supported\n", + generic->header.source_id); + goto err; + } + break; case ACPI_HEST_NOTIFY_NMI: if (!IS_ENABLED(CONFIG_HAVE_ACPI_APEI_NMI)) { pr_warn(GHES_PFX "Generic hardware error source: %d notified via NMI in= terrupt is not supported!\n", @@ -1837,6 +1893,11 @@ static int ghes_probe(struct platform_device *ghes_d= ev) if (rc) goto err; break; + case ACPI_HEST_NOTIFY_HEE: + rc =3D ghes_hee_add(ghes); + if (rc) + goto err; + break; case ACPI_HEST_NOTIFY_NMI: rc =3D ghes_nmi_add(ghes); if (rc) @@ -1917,6 +1978,9 @@ static void ghes_remove(struct platform_device *ghes_= dev) case ACPI_HEST_NOTIFY_SEA: ghes_sea_remove(ghes); break; + case ACPI_HEST_NOTIFY_HEE: + ghes_hee_remove(ghes); + break; case ACPI_HEST_NOTIFY_NMI: ghes_nmi_remove(ghes); break; diff --git a/include/acpi/ghes.h b/include/acpi/ghes.h index 8d7e5caef3f1..bf4f6077ca39 100644 --- a/include/acpi/ghes.h +++ b/include/acpi/ghes.h @@ -140,6 +140,12 @@ int ghes_notify_sea(void); static inline int ghes_notify_sea(void) { return -ENOENT; } #endif =20 +#ifdef CONFIG_ACPI_APEI_HEE +int ghes_notify_hee(void); +#else +static inline int ghes_notify_hee(void) { return -ENOENT; } +#endif + struct notifier_block; extern void ghes_register_report_chain(struct notifier_block *nb); extern void ghes_unregister_report_chain(struct notifier_block *nb); --=20 2.51.2.612.gdc70283dfc From nobody Sat Jun 13 09:21:31 2026 Received: from out30-112.freemail.mail.aliyun.com (out30-112.freemail.mail.aliyun.com [115.124.30.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09AD03845C4; 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Fri, 08 May 2026 16:20:34 +0800 From: Ruidong Tian To: pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, rafael@kernel.org, tony.luck@intel.com, bp@alien8.de, guohanjun@huawei.com, mchehab@kernel.org, xueshuai@linux.alibaba.com, lenb@kernel.org, saket.dumbre@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, Ruidong Tian Subject: [PATCH 3/3] riscv: collect hardware error information via APEI on HEE Date: Fri, 8 May 2026 16:20:20 +0800 Message-ID: <20260508082020.3368109-4-tianruidong@linux.alibaba.com> X-Mailer: git-send-email 2.43.7 In-Reply-To: <20260508082020.3368109-1-tianruidong@linux.alibaba.com> References: <20260508082020.3368109-1-tianruidong@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RISC-V already dispatches Hardware Error Exceptions through do_trap_hardware_error(), but the trap handler currently has no way to learn *what* went wrong: the user sees the offending task killed, or the kernel panic, with no diagnostic about the underlying hardware fault. No error record is logged, and the subsequent memory_failure() handling has no input. There are two principal ways to obtain that information on HEE: 1. Have firmware parse the platform error registers and hand the kernel a CPER record through APEI / GHES. 2. Have the kernel read the error registers directly. Option (2) is not yet viable on RISC-V: the architecture does not define a unified, mandatory layout for hardware error status registers across implementations, so there is nothing stable for common code to read. This patch therefore only implements option (1): collect hardware error information on HEE through the existing APEI / GHES path, mirroring how arm64 treats SEA. Signed-off-by: Ruidong Tian --- arch/riscv/include/asm/acpi.h | 2 ++ arch/riscv/kernel/acpi.c | 54 +++++++++++++++++++++++++++++++++++ arch/riscv/kernel/traps.c | 35 +++++++++++++++++++++-- 3 files changed, 89 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index aa889093f531..e4d18421063e 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -87,6 +87,7 @@ int acpi_get_riscv_isa(struct acpi_table_header *table, =20 void acpi_get_cbo_block_size(struct acpi_table_header *table, u32 *cbom_si= ze, u32 *cboz_size, u32 *cbop_size); +int apei_claim_hee(struct pt_regs *regs); #else static inline void acpi_init_rintc_map(void) { } static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) @@ -104,6 +105,7 @@ static inline void acpi_get_cbo_block_size(struct acpi_= table_header *table, u32 *cbom_size, u32 *cboz_size, u32 *cbop_size) { } =20 +static inline int apei_claim_hee(struct pt_regs *regs) { return -ENOENT; } #endif /* CONFIG_ACPI */ =20 #ifdef CONFIG_ACPI_NUMA diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c index 068e0b404b6f..77ad1e18a092 100644 --- a/arch/riscv/kernel/acpi.c +++ b/arch/riscv/kernel/acpi.c @@ -21,6 +21,9 @@ #include #include #include +#include +#include +#include =20 int acpi_noirq =3D 1; /* skip ACPI IRQ initialization */ int acpi_disabled =3D 1; @@ -353,3 +356,54 @@ int acpi_get_cpu_uid(unsigned int cpu, u32 *uid) return 0; } EXPORT_SYMBOL_GPL(acpi_get_cpu_uid); + +/* + * Claim Hardware Error Exception as a firmware first notification. + * + * Used by RISC-V exception handler for hardware error processing. + */ +int apei_claim_hee(struct pt_regs *regs) +{ + int err =3D -ENOENT; + unsigned long flags; + bool return_to_irqs_enabled; + bool need_nmi_ctx =3D !in_nmi(); + + if (!IS_ENABLED(CONFIG_ACPI_APEI_GHES)) + return err; + + local_irq_save(flags); + + /* + * Determine whether the interrupted context had IRQs enabled. + * This decides if we can run irq_work immediately after. + */ + return_to_irqs_enabled =3D false; + if (regs) + return_to_irqs_enabled =3D !regs_irqs_disabled(regs); + + if (need_nmi_ctx) + nmi_enter(); + err =3D ghes_notify_hee(); + if (need_nmi_ctx) + nmi_exit(); + + /* + * APEI NMI-like notifications are deferred to irq_work. Unless + * we interrupted irqs-masked code, we can do that now. + */ + if (!err) { + if (return_to_irqs_enabled) { + __irq_enter(); + irq_work_run(); + __irq_exit(); + } else { + pr_warn_ratelimited("APEI work queued but not completed"); + err =3D -EINPROGRESS; + } + } + + local_irq_restore(flags); + return err; +} +EXPORT_SYMBOL(apei_claim_hee); diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 8c62c771a656..5ee0ac8b0745 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -22,6 +22,7 @@ #include #include #include +#include =20 #include #include @@ -161,8 +162,6 @@ asmlinkage __visible __trap_section void name(struct pt= _regs *regs) \ =20 DO_ERROR_INFO(do_trap_unknown, SIGILL, ILL_ILLTRP, "unknown exception"); -DO_ERROR_INFO(do_trap_hardware_error, - SIGBUS, BUS_MCEERR_AR, "hardware error"); DO_ERROR_INFO(do_trap_insn_misaligned, SIGBUS, BUS_ADRALN, "instruction address misaligned"); DO_ERROR_INFO(do_trap_insn_fault, @@ -484,3 +483,35 @@ asmlinkage void handle_bad_stack(struct pt_regs *regs) wait_for_interrupt(); } #endif + +static int claim_hardware_error(struct pt_regs *regs) +{ + if (IS_ENABLED(CONFIG_ACPI_APEI_HEE)) + return apei_claim_hee(regs); + return -ENOENT; +} + +asmlinkage __visible __trap_section void do_trap_hardware_error(struct pt_= regs *regs) +{ + if (user_mode(regs)) { + irqentry_enter_from_user_mode(regs); + local_irq_enable(); + + if (claim_hardware_error(regs)) + do_trap_error(regs, SIGBUS, BUS_MCEERR_AR, + regs->badaddr, + "Hardware Error Exception"); + + local_irq_disable(); + irqentry_exit_to_user_mode(regs); + } else { + irqentry_state_t state =3D irqentry_nmi_enter(regs); + + claim_hardware_error(regs); + + if (!fixup_exception(regs)) + die(regs, "Hardware Error Exception"); + + irqentry_nmi_exit(regs, state); + } +} --=20 2.51.2.612.gdc70283dfc