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Fri, 08 May 2026 06:39:59 -0700 (PDT) From: "Markus Schneider-Pargmann (TI)" Date: Fri, 08 May 2026 15:39:27 +0200 Subject: [PATCH v5 1/3] clocksource/drivers/timer-ti-dm: Fix property name in comment Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260508-topic-ti-dm-clkevt-v6-16-v5-1-61d546a0aff9@baylibre.com> References: <20260508-topic-ti-dm-clkevt-v6-16-v5-0-61d546a0aff9@baylibre.com> In-Reply-To: <20260508-topic-ti-dm-clkevt-v6-16-v5-0-61d546a0aff9@baylibre.com> To: Thomas Gleixner , Daniel Lezcano Cc: Vishal Mahaveer , Kevin Hilman , Dhruva Gole , Sebin Francis , Kendall Willis , Akashdeep Kaur , linux-kernel@vger.kernel.org, "Markus Schneider-Pargmann (TI)" X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1230; i=msp@baylibre.com; h=from:subject:message-id; bh=NyCrzey4d4viiQimxIF8AT26tpF0A4pzaFBBowfAro8=; b=owGbwMvMwCXWejAsc4KoVzDjabUkhsy/z2ftKRbkWTFvwzHR56on1adk/+l8HazzsPCS47Pun T8uMvYxdJSyMIhxMciKKbJ0Joam/ZffeSx50bLNMHNYmUCGMHBxCsBE/kxh+B+46X+EzhE9izCV f6XTcoQt3jadqVwVaJByhL/Nl1dz2ReG/wXvrUzf2EwKOyLKNMk7db3MtjaL7SxTeg162uv4SqY WcwAA X-Developer-Key: i=msp@baylibre.com; a=openpgp; fpr=BADD88DB889FDC3E8A3D5FE612FA6A01E0A45B41 ti,always-on property doesn't exist. ti,timer-alwon is meant here. Fix this minor bug in the comment. Signed-off-by: Markus Schneider-Pargmann (TI) --- drivers/clocksource/timer-ti-dm-systimer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clocksource/timer-ti-dm-systimer.c b/drivers/clocksour= ce/timer-ti-dm-systimer.c index eb0dfe4b9b7caf31c21dd065a69f38641cb0c053..3804c1234522499bb43cf174afc= 017cedb79ea38 100644 --- a/drivers/clocksource/timer-ti-dm-systimer.c +++ b/drivers/clocksource/timer-ti-dm-systimer.c @@ -226,7 +226,7 @@ static bool __init dmtimer_is_preferred(struct device_n= ode *np) * Some omap3 boards with unreliable oscillator must not use the counter_3= 2k * or dmtimer1 with 32 KiHz source. Additionally, the boards with unreliab= le * oscillator should really set counter_32k as disabled, and delete dmtime= r1 - * ti,always-on property, but let's not count on it. For these quirky case= s, + * ti,timer-alwon property, but let's not count on it. For these quirky ca= ses, * we prefer using the always-on secure dmtimer12 with the internal 32 KiHz * clock as the clocksource, and any available dmtimer as clockevent. * --=20 2.53.0 From nobody Sat Jun 13 04:37:16 2026 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C16043E1D0B for ; Fri, 8 May 2026 13:40:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778247604; cv=none; b=gc/9qYwY/vdE2ECXUQQi/FQpe7W/EC/qCJP54jtzLgFPqOzU8rZ7mGGxd5X9kfy5XUTlUimHoO3o/f7Vk4OMAQT3lC0EuViLEhH60AJI7BQ192mOWIhJQKftTPG56gLQhf4m8w3SWAyFzYGZNcXkICsn6EX3Ra2b/vyLV5FVKwk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778247604; c=relaxed/simple; bh=yGB7oLZrlueZQZsrOCvw3z4Ei3n6BwQiJfz3R/SeqAU=; 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Fri, 08 May 2026 06:40:01 -0700 (PDT) Received: from localhost ([2001:4090:a246:83ca:1917:a47e:1872:2063]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48e68edca90sm71053205e9.5.2026.05.08.06.40.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 May 2026 06:40:00 -0700 (PDT) From: "Markus Schneider-Pargmann (TI)" Date: Fri, 08 May 2026 15:39:28 +0200 Subject: [PATCH v5 2/3] clocksource/drivers/timer-ti-dm: Add clocksource support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260508-topic-ti-dm-clkevt-v6-16-v5-2-61d546a0aff9@baylibre.com> References: <20260508-topic-ti-dm-clkevt-v6-16-v5-0-61d546a0aff9@baylibre.com> In-Reply-To: <20260508-topic-ti-dm-clkevt-v6-16-v5-0-61d546a0aff9@baylibre.com> To: Thomas Gleixner , Daniel Lezcano Cc: Vishal Mahaveer , Kevin Hilman , Dhruva Gole , Sebin Francis , Kendall Willis , Akashdeep Kaur , linux-kernel@vger.kernel.org, "Markus Schneider-Pargmann (TI)" X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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The driver automatically picks the first timer that is marked as always-on on with the "ti,timer-alwon" property to be the clocksource. The timer can then be used for CPU independent time keeping. Signed-off-by: Markus Schneider-Pargmann (TI) --- drivers/clocksource/timer-ti-dm.c | 103 ++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 103 insertions(+) diff --git a/drivers/clocksource/timer-ti-dm.c b/drivers/clocksource/timer-= ti-dm.c index 793e7cdcb1b16b58db3a81668e3c8144efc7baaf..98cc343087689d8ce208e2d105c= e5ed2c6722dd6 100644 --- a/drivers/clocksource/timer-ti-dm.c +++ b/drivers/clocksource/timer-ti-dm.c @@ -20,6 +20,7 @@ =20 #include #include +#include #include #include #include @@ -29,6 +30,7 @@ #include #include #include +#include =20 #include #include @@ -148,6 +150,14 @@ static u32 omap_reserved_systimers; static LIST_HEAD(omap_timer_list); static DEFINE_SPINLOCK(dm_timer_lock); =20 +struct dmtimer_clocksource { + struct clocksource dev; + struct dmtimer *timer; + unsigned int loadval; +}; + +static void __iomem *omap_dm_timer_sched_clock_counter; + enum { REQUEST_ANY =3D 0, REQUEST_BY_ID, @@ -1185,6 +1195,92 @@ static const struct dev_pm_ops omap_dm_timer_pm_ops = =3D { =20 static const struct of_device_id omap_timer_match[]; =20 +static struct dmtimer_clocksource *omap_dm_timer_to_clocksource(struct clo= cksource *cs) +{ + return container_of(cs, struct dmtimer_clocksource, dev); +} + +static u64 omap_dm_timer_read_cycles(struct clocksource *cs) +{ + struct dmtimer_clocksource *clksrc =3D omap_dm_timer_to_clocksource(cs); + struct dmtimer *timer =3D clksrc->timer; + + return (u64)__omap_dm_timer_read_counter(timer); +} + +static u64 notrace omap_dm_timer_read_sched_clock(void) +{ + /* Posted mode is not active here, so we can read directly */ + return readl_relaxed(omap_dm_timer_sched_clock_counter); +} + +static void omap_dm_timer_clocksource_suspend(struct clocksource *cs) +{ + struct dmtimer_clocksource *clksrc =3D omap_dm_timer_to_clocksource(cs); + struct dmtimer *timer =3D clksrc->timer; + + clksrc->loadval =3D __omap_dm_timer_read_counter(timer); + __omap_dm_timer_stop(timer); +} + +static void omap_dm_timer_clocksource_resume(struct clocksource *cs) +{ + struct dmtimer_clocksource *clksrc =3D omap_dm_timer_to_clocksource(cs); + struct dmtimer *timer =3D clksrc->timer; + + dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, clksrc->loadval); + dmtimer_write(timer, OMAP_TIMER_CTRL_REG, OMAP_TIMER_CTRL_ST | OMAP_TIMER= _CTRL_AR); +} + +static void omap_dm_timer_clocksource_unregister(void *data) +{ + struct clocksource *cs =3D data; + + clocksource_unregister(cs); +} + +static int omap_dm_timer_setup_clocksource(struct dmtimer *timer) +{ + struct device *dev =3D &timer->pdev->dev; + struct dmtimer_clocksource *clksrc; + int err; + + __omap_dm_timer_init_regs(timer); + + timer->reserved =3D 1; + + clksrc =3D devm_kzalloc(dev, sizeof(*clksrc), GFP_KERNEL); + if (!clksrc) + return -ENOMEM; + + clksrc->timer =3D timer; + + clksrc->dev.name =3D "omap_dm_timer"; + clksrc->dev.rating =3D 300; + clksrc->dev.read =3D omap_dm_timer_read_cycles; + clksrc->dev.mask =3D CLOCKSOURCE_MASK(32); + clksrc->dev.flags =3D CLOCK_SOURCE_IS_CONTINUOUS; + clksrc->dev.suspend =3D omap_dm_timer_clocksource_suspend; + clksrc->dev.resume =3D omap_dm_timer_clocksource_resume; + + dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, 0); + dmtimer_write(timer, OMAP_TIMER_LOAD_REG, 0); + dmtimer_write(timer, OMAP_TIMER_CTRL_REG, OMAP_TIMER_CTRL_ST | OMAP_TIMER= _CTRL_AR); + + omap_dm_timer_sched_clock_counter =3D timer->func_base + _OMAP_TIMER_COUN= TER_OFFSET; + sched_clock_register(omap_dm_timer_read_sched_clock, 32, timer->fclk_rate= ); + + err =3D clocksource_register_hz(&clksrc->dev, timer->fclk_rate); + if (err) + return dev_err_probe(dev, err, "Could not register as clocksource\n"); + + err =3D devm_add_action_or_reset(dev, omap_dm_timer_clocksource_unregiste= r, &clksrc->dev); + if (err) + return dev_err_probe(dev, err, "Could not register clocksource_unregiste= r action\n"); + + return 0; +} + /** * omap_dm_timer_probe - probe function called for every registered device * @pdev: pointer to current timer platform device @@ -1272,6 +1368,13 @@ static int omap_dm_timer_probe(struct platform_devic= e *pdev) =20 timer->pdev =3D pdev; =20 + if (timer->capability & OMAP_TIMER_ALWON && !IS_ERR_OR_NULL(timer->fclk) = && + !omap_dm_timer_sched_clock_counter) { + ret =3D omap_dm_timer_setup_clocksource(timer); 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Fri, 08 May 2026 06:40:02 -0700 (PDT) Received: from localhost ([2001:4090:a246:83ca:1917:a47e:1872:2063]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48e68f5104esm45664355e9.12.2026.05.08.06.40.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 May 2026 06:40:01 -0700 (PDT) From: "Markus Schneider-Pargmann (TI)" Date: Fri, 08 May 2026 15:39:29 +0200 Subject: [PATCH v5 3/3] clocksource/drivers/timer-ti-dm: Add clockevent support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260508-topic-ti-dm-clkevt-v6-16-v5-3-61d546a0aff9@baylibre.com> References: <20260508-topic-ti-dm-clkevt-v6-16-v5-0-61d546a0aff9@baylibre.com> In-Reply-To: <20260508-topic-ti-dm-clkevt-v6-16-v5-0-61d546a0aff9@baylibre.com> To: Thomas Gleixner , Daniel Lezcano Cc: Vishal Mahaveer , Kevin Hilman , Dhruva Gole , Sebin Francis , Kendall Willis , Akashdeep Kaur , linux-kernel@vger.kernel.org, "Markus Schneider-Pargmann (TI)" X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5501; i=msp@baylibre.com; h=from:subject:message-id; bh=KROzD7+7kv7aSjNCwuqHr6J10H1STRxL6RN87EpgLpI=; b=owGbwMvMwCXWejAsc4KoVzDjabUkhsy/z1fsUFmuYOy/8oXSi2RnD4O1z/kvHc54WSR2sXfnt yuvD/7Q7ihlYRDjYpAVU2TpTAxN+y+/81jyomWbYeawMoEMYeDiFICJ3PjHyPBZabJLyDPpKFm1 1k9qrY+uJv3b9XmLZtznVIWovzYpzi6MDF8WJ1g0HCvOm9gm6vlmeeWDjs6N2+du+V7pz/db7tj 2KGYA X-Developer-Key: i=msp@baylibre.com; a=openpgp; fpr=BADD88DB889FDC3E8A3D5FE612FA6A01E0A45B41 Add support for using the TI Dual-Mode Timer for clockevents. The second always on device with the "ti,timer-alwon" property is selected to be used for clockevents. The first one is used as clocksource. This allows clockevents to be setup independently of the CPU. Signed-off-by: Markus Schneider-Pargmann (TI) --- drivers/clocksource/timer-ti-dm.c | 124 ++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 119 insertions(+), 5 deletions(-) diff --git a/drivers/clocksource/timer-ti-dm.c b/drivers/clocksource/timer-= ti-dm.c index 98cc343087689d8ce208e2d105ce5ed2c6722dd6..bd06afb7d5226ac185ff2d14986= 3d00bedd0f609 100644 --- a/drivers/clocksource/timer-ti-dm.c +++ b/drivers/clocksource/timer-ti-dm.c @@ -21,8 +21,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -156,6 +158,13 @@ struct dmtimer_clocksource { unsigned int loadval; }; =20 +struct omap_dm_timer_clockevent { + struct clock_event_device dev; + struct dmtimer *timer; + u32 period; +}; + +static bool omap_dm_timer_clockevent_setup; static void __iomem *omap_dm_timer_sched_clock_counter; =20 enum { @@ -1281,6 +1290,106 @@ static int omap_dm_timer_setup_clocksource(struct d= mtimer *timer) return 0; } =20 +static struct omap_dm_timer_clockevent *to_dm_timer_clockevent(struct cloc= k_event_device *evt) +{ + return container_of(evt, struct omap_dm_timer_clockevent, dev); +} + +static int omap_dm_timer_evt_set_next_event(unsigned long cycles, + struct clock_event_device *evt) +{ + struct omap_dm_timer_clockevent *clkevt =3D to_dm_timer_clockevent(evt); + struct dmtimer *timer =3D clkevt->timer; + + dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, 0xffffffff - cycles); + dmtimer_write(timer, OMAP_TIMER_CTRL_REG, OMAP_TIMER_CTRL_ST); + + return 0; +} + +static int omap_dm_timer_evt_shutdown(struct clock_event_device *evt) +{ + struct omap_dm_timer_clockevent *clkevt =3D to_dm_timer_clockevent(evt); + struct dmtimer *timer =3D clkevt->timer; + + __omap_dm_timer_stop(timer); + + return 0; +} + +static int omap_dm_timer_evt_set_periodic(struct clock_event_device *evt) +{ + struct omap_dm_timer_clockevent *clkevt =3D to_dm_timer_clockevent(evt); + struct dmtimer *timer =3D clkevt->timer; + + omap_dm_timer_evt_shutdown(evt); + + omap_dm_timer_set_load(&timer->cookie, clkevt->period); + dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, clkevt->period); + dmtimer_write(timer, OMAP_TIMER_CTRL_REG, + OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST); + + return 0; +} + +static irqreturn_t omap_dm_timer_evt_interrupt(int irq, void *dev_id) +{ + struct omap_dm_timer_clockevent *clkevt =3D dev_id; + struct dmtimer *timer =3D clkevt->timer; + + __omap_dm_timer_write_status(timer, OMAP_TIMER_INT_OVERFLOW); + + clkevt->dev.event_handler(&clkevt->dev); + + return IRQ_HANDLED; +} + +static int omap_dm_timer_setup_clockevent(struct dmtimer *timer) +{ + struct device *dev =3D &timer->pdev->dev; + struct omap_dm_timer_clockevent *clkevt; + int ret; + + clkevt =3D devm_kzalloc(dev, sizeof(*clkevt), GFP_KERNEL); + if (!clkevt) + return -ENOMEM; + + timer->reserved =3D 1; + clkevt->timer =3D timer; + + clkevt->dev.name =3D "omap_dm_timer"; + clkevt->dev.features =3D CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; + clkevt->dev.rating =3D 300; + clkevt->dev.set_next_event =3D omap_dm_timer_evt_set_next_event; + clkevt->dev.set_state_shutdown =3D omap_dm_timer_evt_shutdown; + clkevt->dev.set_state_periodic =3D omap_dm_timer_evt_set_periodic; + clkevt->dev.set_state_oneshot =3D omap_dm_timer_evt_shutdown; + clkevt->dev.set_state_oneshot_stopped =3D omap_dm_timer_evt_shutdown; + clkevt->dev.tick_resume =3D omap_dm_timer_evt_shutdown; + clkevt->dev.cpumask =3D cpu_possible_mask; + clkevt->period =3D 0xffffffff - DIV_ROUND_CLOSEST(timer->fclk_rate, HZ); + + __omap_dm_timer_init_regs(timer); + __omap_dm_timer_stop(timer); + __omap_dm_timer_enable_posted(timer); + + ret =3D devm_request_irq(dev, timer->irq, omap_dm_timer_evt_interrupt, + IRQF_TIMER, "omap_dm_timer_clockevent", clkevt); + if (ret) { + dev_err(dev, "Failed to request interrupt: %d\n", ret); + return ret; + } + + __omap_dm_timer_int_enable(timer, OMAP_TIMER_INT_OVERFLOW); + + clockevents_config_and_register(&clkevt->dev, timer->fclk_rate, + 3, + 0xffffffff); + + omap_dm_timer_clockevent_setup =3D true; + return 0; +} + /** * omap_dm_timer_probe - probe function called for every registered device * @pdev: pointer to current timer platform device @@ -1368,11 +1477,16 @@ static int omap_dm_timer_probe(struct platform_devi= ce *pdev) =20 timer->pdev =3D pdev; =20 - if (timer->capability & OMAP_TIMER_ALWON && !IS_ERR_OR_NULL(timer->fclk) = && - !omap_dm_timer_sched_clock_counter) { - ret =3D omap_dm_timer_setup_clocksource(timer); - if (ret) - return ret; + if (timer->capability & OMAP_TIMER_ALWON && !IS_ERR_OR_NULL(timer->fclk))= { + if (!omap_dm_timer_sched_clock_counter) { + ret =3D omap_dm_timer_setup_clocksource(timer); + if (ret) + return ret; + } else if (!omap_dm_timer_clockevent_setup) { + ret =3D omap_dm_timer_setup_clockevent(timer); + if (ret) + return ret; + } } =20 pm_runtime_enable(dev); --=20 2.53.0