From nobody Sat May 30 12:37:14 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AAD3373BF8; Fri, 8 May 2026 07:35:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778225747; cv=none; b=hBiQhkf2paFxkw8caEQXbmy4qr5yEFPqJ9zVx9rdCBUqT00SC8KvOzJ9ty+wJmyzpxQkYh6e6fewLYr0elASkYrtmEnCc5AizqRpRHML+6G+hqZEqssNKiPCaDTemAGeEDbKQNJ2wp744dJ7nzki0t5sD/8sGKu1fc9WtyteuL0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778225747; c=relaxed/simple; bh=K7CdbMACiPlDHB8RlxXnZJxk8FWEkXQW2qAK2RLlDx4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=EeRLGAeYFzDPu7rrv+swx6foJbb9otgLJvo2m8UFA890YhlwCRDDffp4DADVaRln6X+T2xTGLVPVZOr/Coc61+u4mfYdMO0NtlaDjiCzULlpUGe7h0wpObRmTlDxunFL69aQMxtcHMPI5uBodynqehVWOluIXDc1cUair1pMS7Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=xuXQmc47; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="xuXQmc47" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1778225746; x=1809761746; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=K7CdbMACiPlDHB8RlxXnZJxk8FWEkXQW2qAK2RLlDx4=; b=xuXQmc47qYAmpZVxUXr/fAW5LBDGWTNhRT5f4QTrcxpUOc2WYLZFYaz5 SxiKVrYgFUTRafj9CtOjtK1YGQ5qi623d3gkZaQ3gtxxsNiKVVXlDHOjL yvaztP0GfLO8J3NngOACvxqJiOc/Vhfmnz4aJ5qV6SScKyGgvhvZVPqMd OhLzsi7WkujrKr1tA6u3dqe349E7ATHVfObE3zXe01mw3WolnFRfvlKb9 EmernpHjgVXRzH1h3enybzGXkDlEv5vtWYSHrYHt34P30AHuvqb8bKFTm TyeBQMA2e9UpvyIbeMzKNtyWTyddWQmWxbMm0Z6V6ugQ6apvPpd5YioPT w==; X-CSE-ConnectionGUID: INjIuE3vQvCQhHj6vUkegQ== X-CSE-MsgGUID: u8ob/P5lS/mb0XtkqhTp9g== X-IronPort-AV: E=Sophos;i="6.23,223,1770620400"; d="scan'208";a="57615660" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2026 00:35:46 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex2.mchp-main.com (10.10.87.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.37; Fri, 8 May 2026 00:35:45 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 8 May 2026 00:35:42 -0700 From: Daniel Machon Date: Fri, 8 May 2026 09:35:25 +0200 Subject: [PATCH net-next v4 01/13] MAINTAINERS: add FDMA library to Sparx5 SoC entry Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260508-lan966x-pci-fdma-v4-1-14e0c89d8d63@microchip.com> References: <20260508-lan966x-pci-fdma-v4-0-14e0c89d8d63@microchip.com> In-Reply-To: <20260508-lan966x-pci-fdma-v4-0-14e0c89d8d63@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: , , , X-Mailer: b4 0.14.3 The FDMA library under drivers/net/ethernet/microchip/fdma/ is shared by the lan966x, sparx5 and lan969x drivers, but is not covered by an entry in the MAINTAINERS file. A subsequent patch will add new files to the FDMA library, so let's make sure it's covered. Add drivers/net/ethernet/microchip/fdma/ to the Sparx5 SoC entry, since I am already listed there. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 27a073f53cea..2c5c248642c6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3101,6 +3101,7 @@ M: UNGLinuxDriver@microchip.com L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Supported F: arch/arm64/boot/dts/microchip/sparx* +F: drivers/net/ethernet/microchip/fdma/ F: drivers/net/ethernet/microchip/vcap/ F: drivers/pinctrl/pinctrl-microchip-sgpio.c N: sparx5 --=20 2.34.1 From nobody Sat May 30 12:37:14 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE9DA364023; Fri, 8 May 2026 07:35:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778225752; cv=none; b=eh6JpBgFRARd4g8wDfO38WUyVPzx8uRiac6pFavgZtzyTMK6PaVQEQOeuuOerscchCwKDgQJbg+Pft9TINLjJtZ1SJzZnn1h4JBKdt0lpE9HWWB/MYm9/YOvO0iEjFG0wH96S5nqiih2vZVdRYitRvA44fN26poVxO1sMI/TLlA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778225752; c=relaxed/simple; bh=EDw2BFUuUKmnY7vXM3KNgnA7TAgDYmQg1lhPInRD5kg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=bQBNqAyPemX9ioTToLrtnmfthLEbC5XCYl47lYQyWdwtyRqfi2M+AbAKkIktNSMv9HKNClZ9tdh/s4a/RpU/gO365aJRips0xcMVL2WVCKDPwl5aSqBTF3cPrtIBGqr/aU/iOb8jeb6vy8QTfRKn+pS3JeiI3mD7GhrqSp6B8o8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=0wbvcBwj; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="0wbvcBwj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1778225750; x=1809761750; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=EDw2BFUuUKmnY7vXM3KNgnA7TAgDYmQg1lhPInRD5kg=; b=0wbvcBwjtIYrPr0MM6mB8vPosuh3s/5q51Uerk2fWS+d4Q8KxZL7MsNL zqOcFswBDIn1vu2CxAkYbT2OaRQo0pJGLutWwZRk5ypWXGhIf392xFNBF 5CxrcYN9UFdzgMviDcfI9CVkdNIOvAKq20L2yXW/mlw5kllI9Gatu2eSl JXeAhJD+EjY6m1fuSXTDD3VvW/vkdKVFRAI+FsU4fzDEonLQe+3YuiDn6 CZCvHwXPX675/2QUEGAad9YQ8rne6ZUq5sZp+IGfdVpHb7NiAjLnMv/Bi Z8aPGRWwAOM99qkb9bQwPmNitvj65D7Kzuy8OVRBtE680PXQDiR8snJqj A==; X-CSE-ConnectionGUID: /9SFRMx2R/uu2TZjP/BFqQ== X-CSE-MsgGUID: yn5TYEdxQN6cKg3zUvWhqw== X-IronPort-AV: E=Sophos;i="6.23,223,1770620400"; d="scan'208";a="224455749" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2026 00:35:50 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.37; Fri, 8 May 2026 00:35:49 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 8 May 2026 00:35:45 -0700 From: Daniel Machon Date: Fri, 8 May 2026 09:35:26 +0200 Subject: [PATCH net-next v4 02/13] net: microchip: fdma: rename contiguous dataptr helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260508-lan966x-pci-fdma-v4-2-14e0c89d8d63@microchip.com> References: <20260508-lan966x-pci-fdma-v4-0-14e0c89d8d63@microchip.com> In-Reply-To: <20260508-lan966x-pci-fdma-v4-0-14e0c89d8d63@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: , , , X-Mailer: b4 0.14.3 When the FDMA library was introduced [1], two helpers to get the DMA and virtual address of a DCB, in contiguous memory, were added. These helpers have had no callers until this series. I found the naming I initially used confusing and inconsistent. Rename fdma_dataptr_get_contiguous() and fdma_dataptr_virt_get_contiguous() to fdma_dataptr_dma_addr_contiguous() and fdma_dataptr_virt_addr_contiguous(). This makes the pair symmetric and clarifies what type of address each returns. [1]: commit 30e48a75df9c ("net: microchip: add FDMA library") Tested-by: Herve Codina Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/fdma/fdma_api.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/microchip/fdma/fdma_api.h b/drivers/net/e= thernet/microchip/fdma/fdma_api.h index d91affe8bd98..94f1a6596097 100644 --- a/drivers/net/ethernet/microchip/fdma/fdma_api.h +++ b/drivers/net/ethernet/microchip/fdma/fdma_api.h @@ -197,8 +197,9 @@ static inline int fdma_nextptr_cb(struct fdma *fdma, in= t dcb_idx, u64 *nextptr) * if the dataptr addresses and DCB's are in contiguous memory and the dri= ver * supports XDP. */ -static inline u64 fdma_dataptr_get_contiguous(struct fdma *fdma, int dcb_i= dx, - int db_idx) +static inline u64 fdma_dataptr_dma_addr_contiguous(struct fdma *fdma, + int dcb_idx, + int db_idx) { return fdma->dma + (sizeof(struct fdma_dcb) * fdma->n_dcbs) + (dcb_idx * fdma->n_dbs + db_idx) * fdma->db_size + @@ -209,8 +210,8 @@ static inline u64 fdma_dataptr_get_contiguous(struct fd= ma *fdma, int dcb_idx, * applicable if the dataptr addresses and DCB's are in contiguous memory = and * the driver supports XDP. */ -static inline void *fdma_dataptr_virt_get_contiguous(struct fdma *fdma, - int dcb_idx, int db_idx) +static inline void *fdma_dataptr_virt_addr_contiguous(struct fdma *fdma, + int dcb_idx, int db_idx) { return (u8 *)fdma->dcbs + (sizeof(struct fdma_dcb) * fdma->n_dcbs) + (dcb_idx * fdma->n_dbs + db_idx) * fdma->db_size + --=20 2.34.1 From nobody Sat May 30 12:37:14 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70EBF33DEF9; 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X-CSE-ConnectionGUID: UbJ3J3pLR1Sqh2zKjxwFfA== X-CSE-MsgGUID: fqDW5RcQTkCr3h2XwTSAfg== X-IronPort-AV: E=Sophos;i="6.23,223,1770620400"; d="scan'208";a="56432152" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 08 May 2026 00:35:53 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Fri, 8 May 2026 00:35:53 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 8 May 2026 00:35:49 -0700 From: Daniel Machon Date: Fri, 8 May 2026 09:35:27 +0200 Subject: [PATCH net-next v4 03/13] net: microchip: fdma: add PCIe ATU support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260508-lan966x-pci-fdma-v4-3-14e0c89d8d63@microchip.com> References: <20260508-lan966x-pci-fdma-v4-0-14e0c89d8d63@microchip.com> In-Reply-To: <20260508-lan966x-pci-fdma-v4-0-14e0c89d8d63@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: , , , X-Mailer: b4 0.14.3 When lan966x or lan969x operates as a PCIe endpoint, the internal FDMA engine cannot directly access host memory. Instead, DMA addresses must be translated through the PCIe Address Translation Unit (ATU). The ATU provides outbound windows that map internal addresses to PCIe bus addresses. The ATU outbound address space (0x10000000-0x1fffffff) is divided into six equally-sized regions (~42MB each). When FDMA buffers are allocated, a free ATU region is claimed and programmed with the DMA target address. The FDMA engine then uses the region's base address in its descriptors, and the ATU translates these to the actual DMA addresses on the PCIe bus. Add the required functions and helpers that combine the DMA allocation with the ATU region mapping, effectively adding support for PCIe FDMA. This implementation will also be used by the lan969x, when PCIe FDMA is added for that platform in the future. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/fdma/Makefile | 4 + drivers/net/ethernet/microchip/fdma/fdma_api.c | 33 +++++ drivers/net/ethernet/microchip/fdma/fdma_api.h | 16 +++ drivers/net/ethernet/microchip/fdma/fdma_pci.c | 182 +++++++++++++++++++++= ++++ drivers/net/ethernet/microchip/fdma/fdma_pci.h | 42 ++++++ 5 files changed, 277 insertions(+) diff --git a/drivers/net/ethernet/microchip/fdma/Makefile b/drivers/net/eth= ernet/microchip/fdma/Makefile index cc9a736be357..eed4df6f7158 100644 --- a/drivers/net/ethernet/microchip/fdma/Makefile +++ b/drivers/net/ethernet/microchip/fdma/Makefile @@ -5,3 +5,7 @@ =20 obj-$(CONFIG_FDMA) +=3D fdma.o fdma-y +=3D fdma_api.o + +ifdef CONFIG_MCHP_LAN966X_PCI +fdma-y +=3D fdma_pci.o +endif diff --git a/drivers/net/ethernet/microchip/fdma/fdma_api.c b/drivers/net/e= thernet/microchip/fdma/fdma_api.c index e78c3590da9e..e0c2b137afef 100644 --- a/drivers/net/ethernet/microchip/fdma/fdma_api.c +++ b/drivers/net/ethernet/microchip/fdma/fdma_api.c @@ -127,6 +127,39 @@ void fdma_free_phys(struct fdma *fdma) } EXPORT_SYMBOL_GPL(fdma_free_phys); =20 +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) +/* Allocate coherent DMA memory and map it in the ATU. */ +int fdma_alloc_coherent_and_map(struct device *dev, struct fdma *fdma, + struct fdma_pci_atu *atu) +{ + struct fdma_pci_atu_region *region; + int err; + + err =3D fdma_alloc_coherent(dev, fdma); + if (err) + return err; + + region =3D fdma_pci_atu_region_map(atu, fdma->dma, fdma->size); + if (IS_ERR(region)) { + fdma_free_coherent(dev, fdma); + return PTR_ERR(region); + } + + fdma->atu_region =3D region; + + return 0; +} +EXPORT_SYMBOL_GPL(fdma_alloc_coherent_and_map); + +/* Free coherent DMA memory and unmap the memory in the ATU. */ +void fdma_free_coherent_and_unmap(struct device *dev, struct fdma *fdma) +{ + fdma_pci_atu_region_unmap(fdma->atu_region); + fdma_free_coherent(dev, fdma); +} +EXPORT_SYMBOL_GPL(fdma_free_coherent_and_unmap); +#endif + /* Get the size of the FDMA memory */ u32 fdma_get_size(struct fdma *fdma) { diff --git a/drivers/net/ethernet/microchip/fdma/fdma_api.h b/drivers/net/e= thernet/microchip/fdma/fdma_api.h index 94f1a6596097..0e0f8af7463f 100644 --- a/drivers/net/ethernet/microchip/fdma/fdma_api.h +++ b/drivers/net/ethernet/microchip/fdma/fdma_api.h @@ -7,6 +7,10 @@ #include #include =20 +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) +#include "fdma_pci.h" +#endif + /* This provides a common set of functions and data structures for interac= ting * with the Frame DMA engine on multiple Microchip switchcores. * @@ -109,6 +113,11 @@ struct fdma { u32 channel_id; =20 struct fdma_ops ops; + +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) + /* PCI ATU region for this FDMA instance. */ + struct fdma_pci_atu_region *atu_region; +#endif }; =20 /* Advance the DCB index and wrap if required. */ @@ -234,9 +243,16 @@ int __fdma_dcb_add(struct fdma *fdma, int dcb_idx, u64= info, u64 status, =20 int fdma_alloc_coherent(struct device *dev, struct fdma *fdma); int fdma_alloc_phys(struct fdma *fdma); +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) +int fdma_alloc_coherent_and_map(struct device *dev, struct fdma *fdma, + struct fdma_pci_atu *atu); +#endif =20 void fdma_free_coherent(struct device *dev, struct fdma *fdma); void fdma_free_phys(struct fdma *fdma); +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) +void fdma_free_coherent_and_unmap(struct device *dev, struct fdma *fdma); +#endif =20 u32 fdma_get_size(struct fdma *fdma); u32 fdma_get_size_contiguous(struct fdma *fdma); diff --git a/drivers/net/ethernet/microchip/fdma/fdma_pci.c b/drivers/net/e= thernet/microchip/fdma/fdma_pci.c new file mode 100644 index 000000000000..1bd41eaa58a4 --- /dev/null +++ b/drivers/net/ethernet/microchip/fdma/fdma_pci.c @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +#include +#include +#include + +#include "fdma_pci.h" + +/* When the switch operates as a PCIe endpoint, the FDMA engine needs to + * DMA to/from host memory. The FDMA writes to addresses within the endpoi= nt's + * internal Outbound (OB) address space, and the PCIe ATU translates these= to + * DMA addresses on the PCIe bus, targeting host memory. + * + * The ATU supports up to six outbound regions. This implementation divides + * the OB address space into six equally sized chunks. + * + * +-------------+------------+------------+-----+------------+ + * | Index | Region 0 | Region 1 | ... | Region 5 | + * +-------------+------------+------------+-----+------------+ + * | Base addr | 0x10000000 | 0x12aa0000 | ... | 0x1d500000 | + * | Limit addr | 0x12a9ffff | 0x1553ffff | ... | 0x1ff9ffff | + * | Target addr | host dma | host dma | ... | host dma | + * +-------------+------------+------------+-----+------------+ + * + * Base addr is the start address of the region within the OB address spac= e. + * Limit addr is the end address of the region within the OB address space. + * Target addr is the host DMA address that the base addr translates to. + */ + +#define FDMA_PCI_ATU_REGION_ALIGN BIT(16) /* 64KB */ +#define FDMA_PCI_ATU_OB_START 0x10000000 +#define FDMA_PCI_ATU_OB_END 0x1fffffff + +#define FDMA_PCI_ATU_ADDR 0x300000 +#define FDMA_PCI_ATU_IDX_SIZE 0x200 +#define FDMA_PCI_ATU_ENA_REG 0x4 +#define FDMA_PCI_ATU_ENA_BIT BIT(31) +#define FDMA_PCI_ATU_LWR_BASE_ADDR 0x8 +#define FDMA_PCI_ATU_UPP_BASE_ADDR 0xc +#define FDMA_PCI_ATU_LIMIT_ADDR 0x10 +#define FDMA_PCI_ATU_LWR_TARGET_ADDR 0x14 +#define FDMA_PCI_ATU_UPP_TARGET_ADDR 0x18 + +static u32 fdma_pci_atu_region_size(void) +{ + return round_down((FDMA_PCI_ATU_OB_END - FDMA_PCI_ATU_OB_START) / + FDMA_PCI_ATU_REGION_MAX, FDMA_PCI_ATU_REGION_ALIGN); +} + +static void __iomem *fdma_pci_atu_addr_get(void __iomem *addr, int offset, + int idx) +{ + return addr + FDMA_PCI_ATU_ADDR + FDMA_PCI_ATU_IDX_SIZE * idx + offset; +} + +static void fdma_pci_atu_region_enable(struct fdma_pci_atu_region *region) +{ + writel(FDMA_PCI_ATU_ENA_BIT, + fdma_pci_atu_addr_get(region->atu->addr, FDMA_PCI_ATU_ENA_REG, + region->idx)); +} + +static void fdma_pci_atu_region_disable(struct fdma_pci_atu_region *region) +{ + writel(0, fdma_pci_atu_addr_get(region->atu->addr, FDMA_PCI_ATU_ENA_REG, + region->idx)); +} + +/* Configure the address translation in the ATU. */ +static void +fdma_pci_atu_configure_translation(struct fdma_pci_atu_region *region) +{ + struct fdma_pci_atu *atu =3D region->atu; + int idx =3D region->idx; + + writel(lower_32_bits(region->base_addr), + fdma_pci_atu_addr_get(atu->addr, + FDMA_PCI_ATU_LWR_BASE_ADDR, idx)); + + writel(upper_32_bits(region->base_addr), + fdma_pci_atu_addr_get(atu->addr, + FDMA_PCI_ATU_UPP_BASE_ADDR, idx)); + + /* Upper limit register only needed with REGION_SIZE > 4GB. */ + writel(region->limit_addr, + fdma_pci_atu_addr_get(atu->addr, FDMA_PCI_ATU_LIMIT_ADDR, idx)); + + writel(lower_32_bits(region->target_addr), + fdma_pci_atu_addr_get(atu->addr, + FDMA_PCI_ATU_LWR_TARGET_ADDR, idx)); + + writel(upper_32_bits(region->target_addr), + fdma_pci_atu_addr_get(atu->addr, + FDMA_PCI_ATU_UPP_TARGET_ADDR, idx)); +} + +/* Find an unused ATU region. */ +static struct fdma_pci_atu_region * +fdma_pci_atu_region_get_free(struct fdma_pci_atu *atu) +{ + struct fdma_pci_atu_region *regions =3D atu->regions; + + for (int i =3D 0; i < FDMA_PCI_ATU_REGION_MAX; i++) { + if (regions[i].in_use) + continue; + + return ®ions[i]; + } + + return ERR_PTR(-ENOSPC); +} + +/* Unmap an ATU region, clearing its translation and disabling it. */ +void fdma_pci_atu_region_unmap(struct fdma_pci_atu_region *region) +{ + if (IS_ERR_OR_NULL(region)) + return; + + region->target_addr =3D 0; + region->in_use =3D false; + + fdma_pci_atu_region_disable(region); + fdma_pci_atu_configure_translation(region); +} +EXPORT_SYMBOL_GPL(fdma_pci_atu_region_unmap); + +/* Map a host DMA address into a free outbound region. */ +struct fdma_pci_atu_region * +fdma_pci_atu_region_map(struct fdma_pci_atu *atu, u64 target_addr, int siz= e) +{ + struct fdma_pci_atu_region *region; + + if (!atu) + return ERR_PTR(-EINVAL); + + if (size <=3D 0) + return ERR_PTR(-EINVAL); + + if (size > fdma_pci_atu_region_size()) + return ERR_PTR(-E2BIG); + + region =3D fdma_pci_atu_region_get_free(atu); + if (IS_ERR(region)) + return region; + + region->target_addr =3D target_addr; + region->in_use =3D true; + + /* Enable first, according to datasheet section 3.24.7.4.1 */ + fdma_pci_atu_region_enable(region); + fdma_pci_atu_configure_translation(region); + + return region; +} +EXPORT_SYMBOL_GPL(fdma_pci_atu_region_map); + +/* Translate a host DMA address to the corresponding OB address. */ +u64 fdma_pci_atu_translate_addr(struct fdma_pci_atu_region *region, u64 ad= dr) +{ + return region->base_addr + (addr - region->target_addr); +} +EXPORT_SYMBOL_GPL(fdma_pci_atu_translate_addr); + +/* Initialize ATU, dividing the OB space into equally sized regions. */ +void fdma_pci_atu_init(struct fdma_pci_atu *atu, void __iomem *addr) +{ + struct fdma_pci_atu_region *regions =3D atu->regions; + u32 region_size =3D fdma_pci_atu_region_size(); + + atu->addr =3D addr; + + for (int i =3D 0; i < FDMA_PCI_ATU_REGION_MAX; i++) { + regions[i].base_addr =3D + FDMA_PCI_ATU_OB_START + (i * region_size); + regions[i].limit_addr =3D + regions[i].base_addr + region_size - 1; + regions[i].idx =3D i; + regions[i].atu =3D atu; + } +} +EXPORT_SYMBOL_GPL(fdma_pci_atu_init); diff --git a/drivers/net/ethernet/microchip/fdma/fdma_pci.h b/drivers/net/e= thernet/microchip/fdma/fdma_pci.h new file mode 100644 index 000000000000..eccfe5dc25e7 --- /dev/null +++ b/drivers/net/ethernet/microchip/fdma/fdma_pci.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _FDMA_PCI_H_ +#define _FDMA_PCI_H_ + +#include + +#define FDMA_PCI_ATU_REGION_MAX 6 +#define FDMA_PCI_DB_ALIGN 128 +#define FDMA_PCI_DB_SIZE(mtu) ALIGN(mtu, FDMA_PCI_DB_ALIGN) + +struct fdma_pci_atu; + +struct fdma_pci_atu_region { + struct fdma_pci_atu *atu; + u64 base_addr; /* Base addr of the OB window */ + u64 limit_addr; /* Limit addr of the OB window */ + u64 target_addr; /* Host DMA address this region maps to */ + int idx; + bool in_use; +}; + +struct fdma_pci_atu { + void __iomem *addr; + struct fdma_pci_atu_region regions[FDMA_PCI_ATU_REGION_MAX]; +}; + +/* Initialize ATU, dividing OB space into regions. */ +void fdma_pci_atu_init(struct fdma_pci_atu *atu, void __iomem *addr); + +/* Unmap an ATU region, clearing its translation and disabling it. */ +void fdma_pci_atu_region_unmap(struct fdma_pci_atu_region *region); + +/* Map a host DMA address into a free ATU region. */ +struct fdma_pci_atu_region *fdma_pci_atu_region_map(struct fdma_pci_atu *a= tu, + u64 target_addr, + int size); + +/* Translate a host DMA address to the OB address space. */ +u64 fdma_pci_atu_translate_addr(struct fdma_pci_atu_region *region, u64 ad= dr); + +#endif --=20 2.34.1 From nobody Sat May 30 12:37:14 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02A5633D6F7; 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X-CSE-ConnectionGUID: gmC/E8OTQVitRXVR6EuuoA== X-CSE-MsgGUID: BfIWdon4TNuehDEsHct24A== X-IronPort-AV: E=Sophos;i="6.23,223,1770620400"; d="scan'208";a="56432155" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2026 00:35:57 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.37; Fri, 8 May 2026 00:35:57 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 8 May 2026 00:35:53 -0700 From: Daniel Machon Date: Fri, 8 May 2026 09:35:28 +0200 Subject: [PATCH net-next v4 04/13] net: lan966x: add FDMA LLP register write helper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260508-lan966x-pci-fdma-v4-4-14e0c89d8d63@microchip.com> References: <20260508-lan966x-pci-fdma-v4-0-14e0c89d8d63@microchip.com> In-Reply-To: <20260508-lan966x-pci-fdma-v4-0-14e0c89d8d63@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: , , , X-Mailer: b4 0.14.3 The FDMA Link List Pointer (LLP) register points to the first DCB in the chain and must be written before the channel is activated. This tells the FDMA engine where to begin DMA transfers. Move the LLP register writes from the channel start/activate functions into the allocation functions and introduce a shared lan966x_fdma_llp_configure() helper. This is needed because the upcoming PCIe FDMA path writes ATU-translated addresses to the LLP registers instead of DMA addresses. Keeping the writes in the shared start/activate path would overwrite these translated addresses. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- .../net/ethernet/microchip/lan966x/lan966x_fdma.c | 29 ++++++++++--------= ---- 1 file changed, 13 insertions(+), 16 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_fdma.c index f8ce735a7fc0..6c5761e886d4 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c @@ -109,6 +109,13 @@ static int lan966x_fdma_rx_alloc_page_pool(struct lan9= 66x_rx *rx) return PTR_ERR_OR_ZERO(rx->page_pool); } =20 +static void lan966x_fdma_llp_configure(struct lan966x *lan966x, u64 addr, + u8 channel_id) +{ + lan_wr(lower_32_bits(addr), lan966x, FDMA_DCB_LLP(channel_id)); + lan_wr(upper_32_bits(addr), lan966x, FDMA_DCB_LLP1(channel_id)); +} + static int lan966x_fdma_rx_alloc(struct lan966x_rx *rx) { struct lan966x *lan966x =3D rx->lan966x; @@ -127,6 +134,9 @@ static int lan966x_fdma_rx_alloc(struct lan966x_rx *rx) fdma_dcbs_init(fdma, FDMA_DCB_INFO_DATAL(fdma->db_size), FDMA_DCB_STATUS_INTR); =20 + lan966x_fdma_llp_configure(lan966x, (u64)fdma->dma, + fdma->channel_id); + return 0; } =20 @@ -136,14 +146,6 @@ static void lan966x_fdma_rx_start(struct lan966x_rx *r= x) struct fdma *fdma =3D &rx->fdma; u32 mask; =20 - /* When activating a channel, first is required to write the first DCB - * address and then to activate it - */ - lan_wr(lower_32_bits((u64)fdma->dma), lan966x, - FDMA_DCB_LLP(fdma->channel_id)); - lan_wr(upper_32_bits((u64)fdma->dma), lan966x, - FDMA_DCB_LLP1(fdma->channel_id)); - lan_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(fdma->n_dbs) | FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(1) | FDMA_CH_CFG_CH_INJ_PORT_SET(0) | @@ -214,6 +216,9 @@ static int lan966x_fdma_tx_alloc(struct lan966x_tx *tx) =20 fdma_dcbs_init(fdma, 0, 0); =20 + lan966x_fdma_llp_configure(lan966x, (u64)fdma->dma, + fdma->channel_id); + return 0; =20 out: @@ -235,14 +240,6 @@ static void lan966x_fdma_tx_activate(struct lan966x_tx= *tx) struct fdma *fdma =3D &tx->fdma; u32 mask; =20 - /* When activating a channel, first is required to write the first DCB - * address and then to activate it - */ - lan_wr(lower_32_bits((u64)fdma->dma), lan966x, - FDMA_DCB_LLP(fdma->channel_id)); - lan_wr(upper_32_bits((u64)fdma->dma), lan966x, - FDMA_DCB_LLP1(fdma->channel_id)); - lan_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(fdma->n_dbs) | FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(1) | FDMA_CH_CFG_CH_INJ_PORT_SET(0) | --=20 2.34.1 From nobody Sat May 30 12:37:14 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EF5837F73E; Fri, 8 May 2026 07:36:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778225763; cv=none; b=igEdn3gv1CsF9vrSgzGrqMZXGSnz6HwjatqSTyomQRdafRlF61Hms0ggt0fp63K0NJbVrRCvQjOApMjTuUeCEH192itW46QL+/rrJr20q+rQvK8Yv9IAVb+Yo4Vi3Nqy9xqlrzzQAY5tGZ6e1e7ucINUcyi/FmHU7Kg6MuF32+8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778225763; 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Fri, 8 May 2026 00:36:01 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 8 May 2026 00:35:57 -0700 From: Daniel Machon Date: Fri, 8 May 2026 09:35:29 +0200 Subject: [PATCH net-next v4 05/13] net: lan966x: export FDMA helpers for reuse Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260508-lan966x-pci-fdma-v4-5-14e0c89d8d63@microchip.com> References: <20260508-lan966x-pci-fdma-v4-0-14e0c89d8d63@microchip.com> In-Reply-To: <20260508-lan966x-pci-fdma-v4-0-14e0c89d8d63@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: , , , X-Mailer: b4 0.14.3 Make shared FDMA helpers non-static, so they can be reused by the PCIe FDMA implementation. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- .../net/ethernet/microchip/lan966x/lan966x_fdma.c | 22 +++++++++++-------= ---- .../net/ethernet/microchip/lan966x/lan966x_main.h | 11 +++++++++++ 2 files changed, 22 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_fdma.c index 6c5761e886d4..25e673bdf084 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c @@ -109,8 +109,8 @@ static int lan966x_fdma_rx_alloc_page_pool(struct lan96= 6x_rx *rx) return PTR_ERR_OR_ZERO(rx->page_pool); } =20 -static void lan966x_fdma_llp_configure(struct lan966x *lan966x, u64 addr, - u8 channel_id) +void lan966x_fdma_llp_configure(struct lan966x *lan966x, u64 addr, + u8 channel_id) { lan_wr(lower_32_bits(addr), lan966x, FDMA_DCB_LLP(channel_id)); lan_wr(upper_32_bits(addr), lan966x, FDMA_DCB_LLP1(channel_id)); @@ -140,7 +140,7 @@ static int lan966x_fdma_rx_alloc(struct lan966x_rx *rx) return 0; } =20 -static void lan966x_fdma_rx_start(struct lan966x_rx *rx) +void lan966x_fdma_rx_start(struct lan966x_rx *rx) { struct lan966x *lan966x =3D rx->lan966x; struct fdma *fdma =3D &rx->fdma; @@ -171,7 +171,7 @@ static void lan966x_fdma_rx_start(struct lan966x_rx *rx) lan966x, FDMA_CH_ACTIVATE); } =20 -static void lan966x_fdma_rx_disable(struct lan966x_rx *rx) +void lan966x_fdma_rx_disable(struct lan966x_rx *rx) { struct lan966x *lan966x =3D rx->lan966x; struct fdma *fdma =3D &rx->fdma; @@ -191,7 +191,7 @@ static void lan966x_fdma_rx_disable(struct lan966x_rx *= rx) lan966x, FDMA_CH_DB_DISCARD); } =20 -static void lan966x_fdma_rx_reload(struct lan966x_rx *rx) +void lan966x_fdma_rx_reload(struct lan966x_rx *rx) { struct lan966x *lan966x =3D rx->lan966x; =20 @@ -265,7 +265,7 @@ static void lan966x_fdma_tx_activate(struct lan966x_tx = *tx) lan966x, FDMA_CH_ACTIVATE); } =20 -static void lan966x_fdma_tx_disable(struct lan966x_tx *tx) +void lan966x_fdma_tx_disable(struct lan966x_tx *tx) { struct lan966x *lan966x =3D tx->lan966x; struct fdma *fdma =3D &tx->fdma; @@ -297,7 +297,7 @@ static void lan966x_fdma_tx_reload(struct lan966x_tx *t= x) lan966x, FDMA_CH_RELOAD); } =20 -static void lan966x_fdma_wakeup_netdev(struct lan966x *lan966x) +void lan966x_fdma_wakeup_netdev(struct lan966x *lan966x) { struct lan966x_port *port; int i; @@ -471,7 +471,7 @@ static struct sk_buff *lan966x_fdma_rx_get_frame(struct= lan966x_rx *rx, return NULL; } =20 -static int lan966x_fdma_napi_poll(struct napi_struct *napi, int weight) +int lan966x_fdma_napi_poll(struct napi_struct *napi, int weight) { struct lan966x *lan966x =3D container_of(napi, struct lan966x, napi); struct lan966x_rx *rx =3D &lan966x->rx; @@ -584,7 +584,7 @@ static int lan966x_fdma_get_next_dcb(struct lan966x_tx = *tx) return -1; } =20 -static void lan966x_fdma_tx_start(struct lan966x_tx *tx) +void lan966x_fdma_tx_start(struct lan966x_tx *tx) { struct lan966x *lan966x =3D tx->lan966x; =20 @@ -802,7 +802,7 @@ static int lan966x_fdma_get_max_mtu(struct lan966x *lan= 966x) return max_mtu; } =20 -static int lan966x_qsys_sw_status(struct lan966x *lan966x) +int lan966x_qsys_sw_status(struct lan966x *lan966x) { return lan_rd(lan966x, QSYS_SW_STATUS(CPU_PORT)); } @@ -861,7 +861,7 @@ static int lan966x_fdma_reload(struct lan966x *lan966x,= int new_mtu) return err; } =20 -static int lan966x_fdma_get_max_frame(struct lan966x *lan966x) +int lan966x_fdma_get_max_frame(struct lan966x *lan966x) { return lan966x_fdma_get_max_mtu(lan966x) + IFH_LEN_BYTES + diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.h index eea286c29474..83c361abb789 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.h @@ -561,6 +561,17 @@ int lan966x_fdma_init(struct lan966x *lan966x); void lan966x_fdma_deinit(struct lan966x *lan966x); irqreturn_t lan966x_fdma_irq_handler(int irq, void *args); int lan966x_fdma_reload_page_pool(struct lan966x *lan966x); +int lan966x_fdma_napi_poll(struct napi_struct *napi, int weight); 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d="scan'208";a="65494890" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 08 May 2026 00:36:05 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Fri, 8 May 2026 00:36:04 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 8 May 2026 00:36:01 -0700 From: Daniel Machon Date: Fri, 8 May 2026 09:35:30 +0200 Subject: [PATCH net-next v4 06/13] net: lan966x: add FDMA ops dispatch for PCIe support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260508-lan966x-pci-fdma-v4-6-14e0c89d8d63@microchip.com> References: <20260508-lan966x-pci-fdma-v4-0-14e0c89d8d63@microchip.com> In-Reply-To: <20260508-lan966x-pci-fdma-v4-0-14e0c89d8d63@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: , , , X-Mailer: b4 0.14.3 Introduce lan966x_fdma_ops to support different FDMA implementations for platform and PCIe. Plumb fdma_init, fdma_deinit, fdma_xmit, fdma_poll and fdma_resize through the ops table, and select the implementation at probe time based on runtime PCI bus detection. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- .../net/ethernet/microchip/lan966x/lan966x_fdma.c | 2 +- .../net/ethernet/microchip/lan966x/lan966x_main.c | 25 +++++++++++++++++-= ---- .../net/ethernet/microchip/lan966x/lan966x_main.h | 13 +++++++++++ 3 files changed, 34 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_fdma.c index 25e673bdf084..9bb40383aa56 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c @@ -925,7 +925,7 @@ void lan966x_fdma_netdev_init(struct lan966x *lan966x, = struct net_device *dev) return; =20 lan966x->fdma_ndev =3D dev; - netif_napi_add(dev, &lan966x->napi, lan966x_fdma_napi_poll); + netif_napi_add(dev, &lan966x->napi, lan966x->ops->fdma_poll); napi_enable(&lan966x->napi); } =20 diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.c index 47752d3fde0b..9f69634ebb0a 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c @@ -26,6 +26,14 @@ =20 #define IO_RANGES 2 =20 +static const struct lan966x_fdma_ops lan966x_fdma_ops =3D { + .fdma_init =3D &lan966x_fdma_init, + .fdma_deinit =3D &lan966x_fdma_deinit, + .fdma_xmit =3D &lan966x_fdma_xmit, + .fdma_poll =3D &lan966x_fdma_napi_poll, + .fdma_resize =3D &lan966x_fdma_change_mtu, +}; + static const struct of_device_id lan966x_match[] =3D { { .compatible =3D "microchip,lan966x-switch" }, { } @@ -391,7 +399,7 @@ static netdev_tx_t lan966x_port_xmit(struct sk_buff *sk= b, =20 spin_lock(&lan966x->tx_lock); if (port->lan966x->fdma) - err =3D lan966x_fdma_xmit(skb, ifh, dev); + err =3D lan966x->ops->fdma_xmit(skb, ifh, dev); else err =3D lan966x_port_ifh_xmit(skb, ifh, dev); spin_unlock(&lan966x->tx_lock); @@ -413,7 +421,7 @@ static int lan966x_port_change_mtu(struct net_device *d= ev, int new_mtu) if (!lan966x->fdma) return 0; =20 - err =3D lan966x_fdma_change_mtu(lan966x); + err =3D lan966x->ops->fdma_resize(lan966x); if (err) { lan_wr(DEV_MAC_MAXLEN_CFG_MAX_LEN_SET(LAN966X_HW_MTU(old_mtu)), lan966x, DEV_MAC_MAXLEN_CFG(port->chip_port)); @@ -1079,6 +1087,11 @@ static int lan966x_reset_switch(struct lan966x *lan9= 66x) return 0; } =20 +static const struct lan966x_fdma_ops *lan966x_get_fdma_ops(struct device *= dev) +{ + return &lan966x_fdma_ops; +} + static int lan966x_probe(struct platform_device *pdev) { struct fwnode_handle *ports, *portnp; @@ -1093,6 +1106,8 @@ static int lan966x_probe(struct platform_device *pdev) platform_set_drvdata(pdev, lan966x); lan966x->dev =3D &pdev->dev; =20 + lan966x->ops =3D lan966x_get_fdma_ops(&pdev->dev); + if (!device_get_mac_address(&pdev->dev, mac_addr)) { ether_addr_copy(lan966x->base_mac, mac_addr); } else { @@ -1232,7 +1247,7 @@ static int lan966x_probe(struct platform_device *pdev) if (err) goto cleanup_fdb; =20 - err =3D lan966x_fdma_init(lan966x); + err =3D lan966x->ops->fdma_init(lan966x); if (err) goto cleanup_ptp; =20 @@ -1245,7 +1260,7 @@ static int lan966x_probe(struct platform_device *pdev) return 0; =20 cleanup_fdma: - lan966x_fdma_deinit(lan966x); + lan966x->ops->fdma_deinit(lan966x); =20 cleanup_ptp: lan966x_ptp_deinit(lan966x); @@ -1273,7 +1288,7 @@ static void lan966x_remove(struct platform_device *pd= ev) =20 lan966x_taprio_deinit(lan966x); lan966x_vcap_deinit(lan966x); - lan966x_fdma_deinit(lan966x); + lan966x->ops->fdma_deinit(lan966x); lan966x_cleanup_ports(lan966x); =20 cancel_delayed_work_sync(&lan966x->stats_work); diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.h index 83c361abb789..5f4dbeda17cd 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.h @@ -193,6 +193,17 @@ enum vcap_is1_port_sel_rt { VCAP_IS1_PS_RT_FOLLOW_OTHER =3D 7, }; =20 +struct lan966x; + +struct lan966x_fdma_ops { + int (*fdma_init)(struct lan966x *lan966x); + void (*fdma_deinit)(struct lan966x *lan966x); + int (*fdma_xmit)(struct sk_buff *skb, __be32 *ifh, + struct net_device *dev); + int (*fdma_poll)(struct napi_struct *napi, int weight); + int (*fdma_resize)(struct lan966x *lan966x); +}; + struct lan966x_port; =20 struct lan966x_rx { @@ -270,6 +281,8 @@ struct lan966x_skb_cb { struct lan966x { struct device *dev; =20 + const struct lan966x_fdma_ops *ops; + u8 num_phys_ports; struct lan966x_port **ports; =20 --=20 2.34.1 From nobody Sat May 30 12:37:14 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C975736E49B; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260508-lan966x-pci-fdma-v4-7-14e0c89d8d63@microchip.com> References: <20260508-lan966x-pci-fdma-v4-0-14e0c89d8d63@microchip.com> In-Reply-To: <20260508-lan966x-pci-fdma-v4-0-14e0c89d8d63@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: , , , X-Mailer: b4 0.14.3 When in PCI mode, the GCB soft reset issued by the reset controller can latch spurious bits in the FDMA error stickies. The latched bits sit in FDMA_INTR_ERR until the FDMA IRQ is requested later in probe, at which point the handler fires immediately and WARNs. Clear FDMA_ERRORS, FDMA_INTR_ERR and FDMA_INTR_DB right after the switch reset so the FDMA comes out clean and the IRQ handler does not see ghost errors on probe. The clear runs on both the PCI and platform paths. On the platform path it has no effect =E2=80=94 there are no spurious stickies to clear =E2= =80=94 but keeping it unconditional avoids a PCI-specific code path here. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/lan966x/lan966x_main.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.c index 9f69634ebb0a..b3701953b090 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c @@ -1064,6 +1064,15 @@ static int lan966x_reset_switch(struct lan966x *lan9= 66x) =20 reset_control_reset(switch_reset); =20 + /* When in PCI mode, the GCB soft reset issued by the reset + * controller can latch spurious bits in the FDMA error stickies. + * Clear them before request_irq hooks up the FDMA IRQ line, + * otherwise the handler fires immediately on probe. + */ + lan_wr(lan_rd(lan966x, FDMA_ERRORS), lan966x, FDMA_ERRORS); + lan_wr(lan_rd(lan966x, FDMA_INTR_ERR), lan966x, FDMA_INTR_ERR); + lan_wr(lan_rd(lan966x, FDMA_INTR_DB), lan966x, FDMA_INTR_DB); + /* Don't reinitialize the switch core, if it is already initialized. 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: , , , X-Mailer: b4 0.14.3 When lan966x is used as a PCIe endpoint, the FDMA engine runs on the card and survives a host reboot. Without a shutdown callback, channels stay active and interrupt sources stay armed across the reset, causing the shared PCIe INTx to assert before the driver has re-probed. Add a shutdown callback, shared by the platform and PCI paths, that masks FDMA interrupts (FDMA_INTR_ENA and FDMA_INTR_DB_ENA) and disables the RX and TX channels. FDMA_INTR_ENA persists on the card across a warm reboot, so also restore the full enable in lan966x_fdma_rx_start() to re-arm interrupts after a previous shutdown(). rx_start() runs after both the RX and TX rings are allocated, so the same single-site re-arm works for both the platform and PCIe backends. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c | 4 ++++ drivers/net/ethernet/microchip/lan966x/lan966x_main.c | 18 +++++++++++++++= +++ drivers/net/ethernet/microchip/lan966x/lan966x_regs.h | 15 +++++++++++++++ 3 files changed, 37 insertions(+) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_fdma.c index 9bb40383aa56..493aef5ba8d1 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c @@ -146,6 +146,10 @@ void lan966x_fdma_rx_start(struct lan966x_rx *rx) struct fdma *fdma =3D &rx->fdma; u32 mask; =20 + lan_wr(FDMA_INTR_ENA_INTR_PORT_ENA_SET(GENMASK(1, 0)) | + FDMA_INTR_ENA_INTR_CH_ENA_SET(GENMASK(7, 0)), + lan966x, FDMA_INTR_ENA); + lan_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(fdma->n_dbs) | FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(1) | FDMA_CH_CFG_CH_INJ_PORT_SET(0) | diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.c index b3701953b090..271c023900db 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c @@ -1311,9 +1311,27 @@ static void lan966x_remove(struct platform_device *p= dev) debugfs_remove_recursive(lan966x->debugfs_root); } =20 +static void lan966x_shutdown(struct platform_device *pdev) +{ + struct lan966x *lan966x =3D platform_get_drvdata(pdev); + + if (!lan966x->fdma) + return; + + lan966x_fdma_rx_disable(&lan966x->rx); + lan966x_fdma_tx_disable(&lan966x->tx); + + napi_synchronize(&lan966x->napi); + napi_disable(&lan966x->napi); + + lan_wr(0, lan966x, FDMA_INTR_ENA); + lan_wr(0, lan966x, FDMA_INTR_DB_ENA); +} + static struct platform_driver lan966x_driver =3D { .probe =3D lan966x_probe, .remove =3D lan966x_remove, + .shutdown =3D lan966x_shutdown, .driver =3D { .name =3D "lan966x-switch", .of_match_table =3D lan966x_match, diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h b/driver= s/net/ethernet/microchip/lan966x/lan966x_regs.h index 4b553927d2e0..aba0d36ae6b5 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h @@ -1039,6 +1039,21 @@ enum lan966x_target { /* FDMA:FDMA:FDMA_INTR_ERR */ #define FDMA_INTR_ERR __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 4= 00, 0, 1, 4) =20 +/* FDMA:FDMA:FDMA_INTR_ENA */ +#define FDMA_INTR_ENA __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 4= 04, 0, 1, 4) + +#define FDMA_INTR_ENA_INTR_PORT_ENA GENMASK(9, 8) +#define FDMA_INTR_ENA_INTR_PORT_ENA_SET(x)\ + FIELD_PREP(FDMA_INTR_ENA_INTR_PORT_ENA, x) +#define FDMA_INTR_ENA_INTR_PORT_ENA_GET(x)\ + FIELD_GET(FDMA_INTR_ENA_INTR_PORT_ENA, x) + +#define FDMA_INTR_ENA_INTR_CH_ENA GENMASK(7, 0) +#define FDMA_INTR_ENA_INTR_CH_ENA_SET(x)\ + FIELD_PREP(FDMA_INTR_ENA_INTR_CH_ENA, x) +#define FDMA_INTR_ENA_INTR_CH_ENA_GET(x)\ + FIELD_GET(FDMA_INTR_ENA_INTR_CH_ENA, x) + /* FDMA:FDMA:FDMA_ERRORS */ #define FDMA_ERRORS __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 4= 12, 0, 1, 4) =20 --=20 2.34.1 From nobody Sat May 30 12:37:14 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4B1A382293; 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X-CSE-ConnectionGUID: QjIGFiiDQB2IoRo4HMCFdQ== X-CSE-MsgGUID: UECt5T+cQjGdvKdkAyjWyw== X-IronPort-AV: E=Sophos;i="6.23,223,1770620400"; d="scan'208";a="288583223" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 08 May 2026 00:36:16 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Fri, 8 May 2026 00:36:16 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 8 May 2026 00:36:12 -0700 From: Daniel Machon Date: Fri, 8 May 2026 09:35:33 +0200 Subject: [PATCH net-next v4 09/13] net: lan966x: add PCIe FDMA support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260508-lan966x-pci-fdma-v4-9-14e0c89d8d63@microchip.com> References: <20260508-lan966x-pci-fdma-v4-0-14e0c89d8d63@microchip.com> In-Reply-To: <20260508-lan966x-pci-fdma-v4-0-14e0c89d8d63@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: , , , X-Mailer: b4 0.14.3 Add PCIe FDMA support for lan966x. The PCIe FDMA path uses contiguous DMA buffers mapped through the endpoint's ATU, with memcpy-based frame transfer instead of per-page DMA mappings. With PCIe FDMA, throughput increases from ~33 Mbps (register-based I/O) to ~620 Mbps on an Intel x86 host with a lan966x PCIe card. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/lan966x/Makefile | 4 + .../ethernet/microchip/lan966x/lan966x_fdma_pci.c | 390 +++++++++++++++++= ++++ .../net/ethernet/microchip/lan966x/lan966x_main.c | 11 + .../net/ethernet/microchip/lan966x/lan966x_main.h | 11 + .../net/ethernet/microchip/lan966x/lan966x_regs.h | 10 + 5 files changed, 426 insertions(+) diff --git a/drivers/net/ethernet/microchip/lan966x/Makefile b/drivers/net/= ethernet/microchip/lan966x/Makefile index 4cdbe263502c..ac0beceb2a0d 100644 --- a/drivers/net/ethernet/microchip/lan966x/Makefile +++ b/drivers/net/ethernet/microchip/lan966x/Makefile @@ -18,6 +18,10 @@ lan966x-switch-objs :=3D lan966x_main.o lan966x_phylink= .o lan966x_port.o \ lan966x-switch-$(CONFIG_LAN966X_DCB) +=3D lan966x_dcb.o lan966x-switch-$(CONFIG_DEBUG_FS) +=3D lan966x_vcap_debugfs.o =20 +ifdef CONFIG_MCHP_LAN966X_PCI +lan966x-switch-y +=3D lan966x_fdma_pci.o +endif + # Provide include files ccflags-y +=3D -I$(srctree)/drivers/net/ethernet/microchip/vcap ccflags-y +=3D -I$(srctree)/drivers/net/ethernet/microchip/fdma diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c b/dr= ivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c new file mode 100644 index 000000000000..2e88d211073d --- /dev/null +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c @@ -0,0 +1,390 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "fdma_api.h" +#include "lan966x_main.h" + +static int lan966x_fdma_pci_dataptr_cb(struct fdma *fdma, int dcb, int db, + u64 *dataptr) +{ + u64 addr; + + addr =3D fdma_dataptr_dma_addr_contiguous(fdma, dcb, db); + + *dataptr =3D fdma_pci_atu_translate_addr(fdma->atu_region, addr); + + return 0; +} + +static int lan966x_fdma_pci_nextptr_cb(struct fdma *fdma, int dcb, u64 *ne= xtptr) +{ + u64 addr; + + fdma_nextptr_cb(fdma, dcb, &addr); + + *nextptr =3D fdma_pci_atu_translate_addr(fdma->atu_region, addr); + + return 0; +} + +static int lan966x_fdma_pci_rx_alloc(struct lan966x_rx *rx) +{ + struct lan966x *lan966x =3D rx->lan966x; + struct fdma *fdma =3D &rx->fdma; + int err; + + err =3D fdma_alloc_coherent_and_map(lan966x->dev, fdma, &lan966x->atu); + if (err) + return err; + + fdma_dcbs_init(fdma, + FDMA_DCB_INFO_DATAL(fdma->db_size), + FDMA_DCB_STATUS_INTR); + + lan966x_fdma_llp_configure(lan966x, + fdma->atu_region->base_addr, + fdma->channel_id); + + return 0; +} + +static int lan966x_fdma_pci_tx_alloc(struct lan966x_tx *tx) +{ + struct lan966x *lan966x =3D tx->lan966x; + struct fdma *fdma =3D &tx->fdma; + int err; + + err =3D fdma_alloc_coherent_and_map(lan966x->dev, fdma, &lan966x->atu); + if (err) + return err; + + fdma_dcbs_init(fdma, + FDMA_DCB_INFO_DATAL(fdma->db_size), + FDMA_DCB_STATUS_DONE); + + lan966x_fdma_llp_configure(lan966x, + fdma->atu_region->base_addr, + fdma->channel_id); + + return 0; +} + +static int lan966x_fdma_pci_get_next_dcb(struct fdma *fdma) +{ + struct fdma_db *db; + + for (int i =3D 0; i < fdma->n_dcbs; i++) { + db =3D fdma_db_get(fdma, i, 0); + + if (!fdma_db_is_done(db)) + continue; + if (fdma_is_last(fdma, &fdma->dcbs[i])) + continue; + + return i; + } + + return -ENOSPC; +} + +/* TX slot layout (sizes in bytes): + * + * +---------------------+-----+---------+-----+ + * | XDP_PACKET_HEADROOM | IFH | payload | FCS | + * | 256 | 28 | len | 4 | + * +---------------------+-----+---------+-----+ + * |<---------------- db_size ----------------->| + * + * Return true if the frame plus required overhead fits. + */ +static bool lan966x_fdma_pci_tx_size_fits(struct fdma *fdma, u32 len) +{ + return XDP_PACKET_HEADROOM + IFH_LEN_BYTES + len + ETH_FCS_LEN <=3D + fdma->db_size; +} + +/* Return true if blockl is a valid RX frame size. */ +static bool lan966x_fdma_pci_rx_size_fits(struct fdma *fdma, u32 blockl) +{ + return blockl >=3D IFH_LEN_BYTES + ETH_HLEN + ETH_FCS_LEN && + blockl <=3D fdma->db_size - XDP_PACKET_HEADROOM; +} + +static int lan966x_fdma_pci_rx_check_frame(struct lan966x_rx *rx, u64 *src= _port) +{ + struct lan966x *lan966x =3D rx->lan966x; + struct fdma *fdma =3D &rx->fdma; + struct lan966x_port *port; + struct fdma_db *db; + void *virt_addr; + u32 blockl; + + /* virt_addr points to the IFH. */ + virt_addr =3D fdma_dataptr_virt_addr_contiguous(fdma, + fdma->dcb_index, + fdma->db_index); + + lan966x_ifh_get_src_port(virt_addr, src_port); + + if (WARN_ON(*src_port >=3D lan966x->num_phys_ports)) + return FDMA_ERROR; + + port =3D lan966x->ports[*src_port]; + if (!port) + return FDMA_ERROR; + + db =3D fdma_db_next_get(fdma); + + /* BLOCKL is a 16-bit HW-populated field; reject obviously-bad + * values before they feed memcpy/XDP sizes. + */ + blockl =3D FDMA_DCB_STATUS_BLOCKL(db->status); + if (!lan966x_fdma_pci_rx_size_fits(fdma, blockl)) + return FDMA_ERROR; + + return FDMA_PASS; +} + +static struct sk_buff *lan966x_fdma_pci_rx_get_frame(struct lan966x_rx *rx, + u64 src_port) +{ + struct lan966x *lan966x =3D rx->lan966x; + struct fdma *fdma =3D &rx->fdma; + struct sk_buff *skb; + struct fdma_db *db; + u32 data_len; + + /* Get the received frame and create an SKB for it. */ + db =3D fdma_db_next_get(fdma); + data_len =3D FDMA_DCB_STATUS_BLOCKL(db->status); + + skb =3D napi_alloc_skb(&lan966x->napi, data_len); + if (unlikely(!skb)) + return NULL; + + memcpy(skb->data, + fdma_dataptr_virt_addr_contiguous(fdma, + fdma->dcb_index, + fdma->db_index), + data_len); + + skb_put(skb, data_len); + + skb->dev =3D lan966x->ports[src_port]->dev; + skb_pull(skb, IFH_LEN_BYTES); + + skb_trim(skb, skb->len - ETH_FCS_LEN); + + skb->protocol =3D eth_type_trans(skb, skb->dev); + + if (lan966x->bridge_mask & BIT(src_port)) { + skb->offload_fwd_mark =3D 1; + + skb_reset_network_header(skb); + if (!lan966x_hw_offload(lan966x, src_port, skb)) + skb->offload_fwd_mark =3D 0; + } + + skb->dev->stats.rx_bytes +=3D skb->len; + skb->dev->stats.rx_packets++; + + return skb; +} + +static int lan966x_fdma_pci_xmit(struct sk_buff *skb, __be32 *ifh, + struct net_device *dev) +{ + struct lan966x_port *port =3D netdev_priv(dev); + struct lan966x *lan966x =3D port->lan966x; + struct lan966x_tx *tx =3D &lan966x->tx; + struct fdma *fdma =3D &tx->fdma; + int next_to_use; + void *virt_addr; + + next_to_use =3D lan966x_fdma_pci_get_next_dcb(fdma); + + if (next_to_use < 0) { + netif_stop_queue(dev); + return NETDEV_TX_BUSY; + } + + if (skb_put_padto(skb, ETH_ZLEN)) { + dev->stats.tx_dropped++; + return NETDEV_TX_OK; + } + + if (!lan966x_fdma_pci_tx_size_fits(fdma, skb->len)) { + dev_kfree_skb_any(skb); + dev->stats.tx_dropped++; + return NETDEV_TX_OK; + } + + skb_tx_timestamp(skb); + + /* virt_addr points to the IFH. */ + virt_addr =3D fdma_dataptr_virt_addr_contiguous(fdma, next_to_use, 0); + memcpy(virt_addr, ifh, IFH_LEN_BYTES); + memcpy(virt_addr + IFH_LEN_BYTES, skb->data, skb->len); + + /* Order frame write before DCB status write below. */ + dma_wmb(); + + fdma_dcb_add(fdma, + next_to_use, + 0, + FDMA_DCB_STATUS_INTR | + FDMA_DCB_STATUS_SOF | + FDMA_DCB_STATUS_EOF | + FDMA_DCB_STATUS_BLOCKO(0) | + FDMA_DCB_STATUS_BLOCKL(IFH_LEN_BYTES + skb->len + ETH_FCS_LEN)); + + /* Start the transmission. */ + lan966x_fdma_tx_start(tx); + + dev->stats.tx_bytes +=3D skb->len; + dev->stats.tx_packets++; + + /* Safe to free: the PCIe DTBO does not enable the PTP interrupt, + * so lan966x->ptp stays 0 and lan966x_port_xmit() never enqueues + * this skb on port->tx_skbs for a TX timestamp. + */ + dev_consume_skb_any(skb); + + return NETDEV_TX_OK; +} + +static int lan966x_fdma_pci_napi_poll(struct napi_struct *napi, int weight) +{ + struct lan966x *lan966x =3D container_of(napi, struct lan966x, napi); + struct lan966x_rx *rx =3D &lan966x->rx; + struct fdma *fdma =3D &rx->fdma; + int dcb_reload, old_dcb; + struct sk_buff *skb; + int counter =3D 0; + u64 src_port; + + /* Wake any stopped TX queues if a TX DCB is available. */ + spin_lock(&lan966x->tx_lock); + if (lan966x_fdma_pci_get_next_dcb(&lan966x->tx.fdma) >=3D 0) + lan966x_fdma_wakeup_netdev(lan966x); + spin_unlock(&lan966x->tx_lock); + + dcb_reload =3D fdma->dcb_index; + + /* Get all received skbs. */ + while (counter < weight) { + if (!fdma_has_frames(fdma)) + break; + /* Order DONE read before DCB/frame reads below. */ + dma_rmb(); + counter++; + switch (lan966x_fdma_pci_rx_check_frame(rx, &src_port)) { + case FDMA_PASS: + break; + case FDMA_ERROR: + fdma_dcb_advance(fdma); + goto allocate_new; + } + skb =3D lan966x_fdma_pci_rx_get_frame(rx, src_port); + fdma_dcb_advance(fdma); + if (!skb) + goto allocate_new; + + napi_gro_receive(&lan966x->napi, skb); + } +allocate_new: + while (dcb_reload !=3D fdma->dcb_index) { + old_dcb =3D dcb_reload; + dcb_reload++; + dcb_reload &=3D fdma->n_dcbs - 1; + + fdma_dcb_add(fdma, + old_dcb, + FDMA_DCB_INFO_DATAL(fdma->db_size), + FDMA_DCB_STATUS_INTR); + + lan966x_fdma_rx_reload(rx); + } + + if (counter < weight && napi_complete_done(napi, counter)) + lan_wr(0xff, lan966x, FDMA_INTR_DB_ENA); + + return counter; +} + +static int lan966x_fdma_pci_init(struct lan966x *lan966x) +{ + struct fdma *rx_fdma =3D &lan966x->rx.fdma; + struct fdma *tx_fdma =3D &lan966x->tx.fdma; + int err; + + if (!lan966x->fdma) + return 0; + + lan_wr(FDMA_CTRL_NRESET_SET(0), lan966x, FDMA_CTRL); + lan_wr(FDMA_CTRL_NRESET_SET(1), lan966x, FDMA_CTRL); + + fdma_pci_atu_init(&lan966x->atu, lan966x->regs[TARGET_PCIE_DBI]); + + lan966x->rx.lan966x =3D lan966x; + lan966x->rx.max_mtu =3D lan966x_fdma_get_max_frame(lan966x); + rx_fdma->channel_id =3D FDMA_XTR_CHANNEL; + rx_fdma->n_dcbs =3D FDMA_DCB_MAX; + rx_fdma->n_dbs =3D FDMA_RX_DCB_MAX_DBS; + rx_fdma->priv =3D lan966x; + rx_fdma->db_size =3D FDMA_PCI_DB_SIZE(lan966x->rx.max_mtu); + rx_fdma->size =3D fdma_get_size_contiguous(rx_fdma); + rx_fdma->ops.nextptr_cb =3D &lan966x_fdma_pci_nextptr_cb; + rx_fdma->ops.dataptr_cb =3D &lan966x_fdma_pci_dataptr_cb; + + lan966x->tx.lan966x =3D lan966x; + tx_fdma->channel_id =3D FDMA_INJ_CHANNEL; + tx_fdma->n_dcbs =3D FDMA_DCB_MAX; + tx_fdma->n_dbs =3D FDMA_TX_DCB_MAX_DBS; + tx_fdma->priv =3D lan966x; + tx_fdma->db_size =3D FDMA_PCI_DB_SIZE(lan966x->rx.max_mtu); + tx_fdma->size =3D fdma_get_size_contiguous(tx_fdma); + tx_fdma->ops.nextptr_cb =3D &lan966x_fdma_pci_nextptr_cb; + tx_fdma->ops.dataptr_cb =3D &lan966x_fdma_pci_dataptr_cb; + + err =3D lan966x_fdma_pci_rx_alloc(&lan966x->rx); + if (err) + return err; + + err =3D lan966x_fdma_pci_tx_alloc(&lan966x->tx); + if (err) { + fdma_free_coherent_and_unmap(lan966x->dev, rx_fdma); + return err; + } + + lan966x_fdma_rx_start(&lan966x->rx); + + return 0; +} + +static int lan966x_fdma_pci_resize(struct lan966x *lan966x) +{ + return -EOPNOTSUPP; +} + +static void lan966x_fdma_pci_deinit(struct lan966x *lan966x) +{ + if (!lan966x->fdma) + return; + + lan966x_fdma_rx_disable(&lan966x->rx); + lan966x_fdma_tx_disable(&lan966x->tx); + + napi_synchronize(&lan966x->napi); + napi_disable(&lan966x->napi); + + fdma_free_coherent_and_unmap(lan966x->dev, &lan966x->rx.fdma); + fdma_free_coherent_and_unmap(lan966x->dev, &lan966x->tx.fdma); +} + +const struct lan966x_fdma_ops lan966x_fdma_pci_ops =3D { + .fdma_init =3D &lan966x_fdma_pci_init, + .fdma_deinit =3D &lan966x_fdma_pci_deinit, + .fdma_xmit =3D &lan966x_fdma_pci_xmit, + .fdma_poll =3D &lan966x_fdma_pci_napi_poll, + .fdma_resize =3D &lan966x_fdma_pci_resize, +}; diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.c index 271c023900db..0bbc9d40b69b 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -49,6 +50,9 @@ struct lan966x_main_io_resource { static const struct lan966x_main_io_resource lan966x_main_iomap[] =3D { { TARGET_CPU, 0xc0000, 0 }, /* 0xe00c0000 */ { TARGET_FDMA, 0xc0400, 0 }, /* 0xe00c0400 */ +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) + { TARGET_PCIE_DBI, 0x400000, 0 }, /* 0xe0400000 */ +#endif { TARGET_ORG, 0, 1 }, /* 0xe2000000 */ { TARGET_GCB, 0x4000, 1 }, /* 0xe2004000 */ { TARGET_QS, 0x8000, 1 }, /* 0xe2008000 */ @@ -1098,6 +1102,13 @@ static int lan966x_reset_switch(struct lan966x *lan9= 66x) =20 static const struct lan966x_fdma_ops *lan966x_get_fdma_ops(struct device *= dev) { +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) + for (struct device *p =3D dev->parent; p; p =3D p->parent) { + if (dev_is_pci(p)) + return &lan966x_fdma_pci_ops; + } +#endif + return &lan966x_fdma_ops; } =20 diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.h index 5f4dbeda17cd..e7fdd4447fb6 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.h @@ -17,6 +17,9 @@ #include =20 #include +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) +#include +#endif #include #include =20 @@ -288,6 +291,10 @@ struct lan966x { =20 void __iomem *regs[NUM_TARGETS]; =20 +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) + struct fdma_pci_atu atu; +#endif + int shared_queue_sz; =20 u8 base_mac[ETH_ALEN]; @@ -586,6 +593,10 @@ void lan966x_fdma_wakeup_netdev(struct lan966x *lan966= x); int lan966x_fdma_get_max_frame(struct lan966x *lan966x); int lan966x_qsys_sw_status(struct lan966x *lan966x); =20 +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) +extern const struct lan966x_fdma_ops lan966x_fdma_pci_ops; +#endif + int lan966x_lag_port_join(struct lan966x_port *port, struct net_device *brport_dev, struct net_device *bond, diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h b/driver= s/net/ethernet/microchip/lan966x/lan966x_regs.h index aba0d36ae6b5..4778ea217673 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h @@ -20,6 +20,7 @@ enum lan966x_target { TARGET_FDMA =3D 21, TARGET_GCB =3D 27, TARGET_ORG =3D 36, + TARGET_PCIE_DBI =3D 40, TARGET_PTP =3D 41, TARGET_QS =3D 42, TARGET_QSYS =3D 46, @@ -1009,6 +1010,15 @@ enum lan966x_target { #define FDMA_CH_CFG_CH_MEM_GET(x)\ FIELD_GET(FDMA_CH_CFG_CH_MEM, x) =20 +/* FDMA:FDMA:FDMA_CTRL */ +#define FDMA_CTRL __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 4= 24, 0, 1, 4) + +#define FDMA_CTRL_NRESET BIT(0) +#define FDMA_CTRL_NRESET_SET(x)\ + FIELD_PREP(FDMA_CTRL_NRESET, x) +#define FDMA_CTRL_NRESET_GET(x)\ + FIELD_GET(FDMA_CTRL_NRESET, x) + /* FDMA:FDMA:FDMA_PORT_CTRL */ #define FDMA_PORT_CTRL(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 3= 76, r, 2, 4) =20 --=20 2.34.1 From nobody Sat May 30 12:37:14 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 47082382395; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260508-lan966x-pci-fdma-v4-10-14e0c89d8d63@microchip.com> References: <20260508-lan966x-pci-fdma-v4-0-14e0c89d8d63@microchip.com> In-Reply-To: <20260508-lan966x-pci-fdma-v4-0-14e0c89d8d63@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: , , , X-Mailer: b4 0.14.3 Add MTU change support for the PCIe FDMA path. When the MTU changes, the contiguous ATU-mapped RX and TX buffers are reallocated with the new size. On allocation failure, the existing buffers are reused after being reset. Cap the PCIe DCB ring at 256 (FDMA_PCI_DCB_MAX) to keep the entire contiguous allocation under MAX_PAGE_ORDER at jumbo MTU, which 512 DCBs would overflow. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- .../ethernet/microchip/lan966x/lan966x_fdma_pci.c | 157 +++++++++++++++++= +++- 1 file changed, 154 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c b/dr= ivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c index 2e88d211073d..0568251a95d9 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c @@ -3,6 +3,11 @@ #include "fdma_api.h" #include "lan966x_main.h" =20 +/* Ring must fit in one MAX_PAGE_ORDER DMA block; 512 DCBs overflows + * at jumbo MTU. + */ +#define FDMA_PCI_DCB_MAX 256 + static int lan966x_fdma_pci_dataptr_cb(struct fdma *fdma, int dcb, int db, u64 *dataptr) { @@ -328,7 +333,7 @@ static int lan966x_fdma_pci_init(struct lan966x *lan966= x) lan966x->rx.lan966x =3D lan966x; lan966x->rx.max_mtu =3D lan966x_fdma_get_max_frame(lan966x); rx_fdma->channel_id =3D FDMA_XTR_CHANNEL; - rx_fdma->n_dcbs =3D FDMA_DCB_MAX; + rx_fdma->n_dcbs =3D FDMA_PCI_DCB_MAX; rx_fdma->n_dbs =3D FDMA_RX_DCB_MAX_DBS; rx_fdma->priv =3D lan966x; rx_fdma->db_size =3D FDMA_PCI_DB_SIZE(lan966x->rx.max_mtu); @@ -338,7 +343,7 @@ static int lan966x_fdma_pci_init(struct lan966x *lan966= x) =20 lan966x->tx.lan966x =3D lan966x; tx_fdma->channel_id =3D FDMA_INJ_CHANNEL; - tx_fdma->n_dcbs =3D FDMA_DCB_MAX; + tx_fdma->n_dcbs =3D FDMA_PCI_DCB_MAX; tx_fdma->n_dbs =3D FDMA_TX_DCB_MAX_DBS; tx_fdma->priv =3D lan966x; tx_fdma->db_size =3D FDMA_PCI_DB_SIZE(lan966x->rx.max_mtu); @@ -361,9 +366,155 @@ static int lan966x_fdma_pci_init(struct lan966x *lan9= 66x) return 0; } =20 +/* Reset existing rx and tx buffers. */ +static void lan966x_fdma_pci_reset_mem(struct lan966x *lan966x) +{ + struct lan966x_rx *rx =3D &lan966x->rx; + struct lan966x_tx *tx =3D &lan966x->tx; + + memset(rx->fdma.dcbs, 0, rx->fdma.size); + memset(tx->fdma.dcbs, 0, tx->fdma.size); + + fdma_dcbs_init(&rx->fdma, + FDMA_DCB_INFO_DATAL(rx->fdma.db_size), + FDMA_DCB_STATUS_INTR); + + fdma_dcbs_init(&tx->fdma, + FDMA_DCB_INFO_DATAL(tx->fdma.db_size), + FDMA_DCB_STATUS_DONE); + + lan966x_fdma_llp_configure(lan966x, + tx->fdma.atu_region->base_addr, + tx->fdma.channel_id); + lan966x_fdma_llp_configure(lan966x, + rx->fdma.atu_region->base_addr, + rx->fdma.channel_id); +} + +/* Drain in-flight xmit callers and stop all TX queues on every port. */ +static void lan966x_fdma_pci_stop_netdev(struct lan966x *lan966x) +{ + for (int i =3D 0; i < lan966x->num_phys_ports; ++i) { + struct lan966x_port *port =3D lan966x->ports[i]; + + if (port) + netif_tx_disable(port->dev); + } +} + +/* Wake all TX queues on every port (undoes lan966x_fdma_pci_stop_netdev).= */ +static void lan966x_fdma_pci_wakeup_netdev(struct lan966x *lan966x) +{ + for (int i =3D 0; i < lan966x->num_phys_ports; ++i) { + struct lan966x_port *port =3D lan966x->ports[i]; + + if (port) + netif_tx_wake_all_queues(port->dev); + } +} + +static int lan966x_fdma_pci_reload(struct lan966x *lan966x, int new_mtu) +{ + struct fdma tx_fdma_old =3D lan966x->tx.fdma; + struct fdma rx_fdma_old =3D lan966x->rx.fdma; + u32 old_mtu =3D lan966x->rx.max_mtu; + int err; + + napi_synchronize(&lan966x->napi); + napi_disable(&lan966x->napi); + lan966x_fdma_pci_stop_netdev(lan966x); + lan966x_fdma_rx_disable(&lan966x->rx); + lan966x_fdma_tx_disable(&lan966x->tx); + + lan966x->rx.max_mtu =3D new_mtu; + + lan966x->tx.fdma.db_size =3D FDMA_PCI_DB_SIZE(lan966x->rx.max_mtu); + lan966x->tx.fdma.size =3D fdma_get_size_contiguous(&lan966x->tx.fdma); + lan966x->rx.fdma.db_size =3D FDMA_PCI_DB_SIZE(lan966x->rx.max_mtu); + lan966x->rx.fdma.size =3D fdma_get_size_contiguous(&lan966x->rx.fdma); + + err =3D lan966x_fdma_pci_rx_alloc(&lan966x->rx); + if (err) + goto restore; + + err =3D lan966x_fdma_pci_tx_alloc(&lan966x->tx); + if (err) { + fdma_free_coherent_and_unmap(lan966x->dev, &lan966x->rx.fdma); + goto restore; + } + + /* Free and unmap old memory. */ + fdma_free_coherent_and_unmap(lan966x->dev, &rx_fdma_old); + fdma_free_coherent_and_unmap(lan966x->dev, &tx_fdma_old); + + /* Keep this order: rx_start, wakeup_netdev, napi_enable. */ + lan966x_fdma_rx_start(&lan966x->rx); + lan966x_fdma_pci_wakeup_netdev(lan966x); + napi_enable(&lan966x->napi); + + return err; +restore: + + /* No new buffers are allocated at this point. Use the old buffers, + * but reset them before starting the FDMA again. + */ + + memcpy(&lan966x->tx.fdma, &tx_fdma_old, sizeof(struct fdma)); + memcpy(&lan966x->rx.fdma, &rx_fdma_old, sizeof(struct fdma)); + + lan966x->rx.max_mtu =3D old_mtu; + + lan966x_fdma_pci_reset_mem(lan966x); + + /* Keep this order: rx_start, wakeup_netdev, napi_enable. */ + lan966x_fdma_rx_start(&lan966x->rx); + lan966x_fdma_pci_wakeup_netdev(lan966x); + napi_enable(&lan966x->napi); + + return err; +} + +static int __lan966x_fdma_pci_reload(struct lan966x *lan966x, int max_mtu) +{ + int err; + u32 val; + + /* Disable the CPU port. */ + lan_rmw(QSYS_SW_PORT_MODE_PORT_ENA_SET(0), + QSYS_SW_PORT_MODE_PORT_ENA, + lan966x, QSYS_SW_PORT_MODE(CPU_PORT)); + + /* Flush the CPU queues. */ + readx_poll_timeout(lan966x_qsys_sw_status, + lan966x, + val, + !(QSYS_SW_STATUS_EQ_AVAIL_GET(val)), + READL_SLEEP_US, READL_TIMEOUT_US); + + /* Add a sleep in case there are frames between the queues and the CPU + * port + */ + usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); + + err =3D lan966x_fdma_pci_reload(lan966x, max_mtu); + + /* Enable back the CPU port. */ + lan_rmw(QSYS_SW_PORT_MODE_PORT_ENA_SET(1), + QSYS_SW_PORT_MODE_PORT_ENA, + lan966x, QSYS_SW_PORT_MODE(CPU_PORT)); + + return err; +} + static int lan966x_fdma_pci_resize(struct lan966x *lan966x) { - return -EOPNOTSUPP; + int max_mtu; + + max_mtu =3D lan966x_fdma_get_max_frame(lan966x); + if (max_mtu =3D=3D lan966x->rx.max_mtu) + return 0; + + return __lan966x_fdma_pci_reload(lan966x, max_mtu); } =20 static void lan966x_fdma_pci_deinit(struct lan966x *lan966x) --=20 2.34.1 From nobody Sat May 30 12:37:14 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D1D837F726; Fri, 8 May 2026 07:36:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; 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d="scan'208";a="224455786" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2026 00:36:24 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.37; Fri, 8 May 2026 00:36:23 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 8 May 2026 00:36:20 -0700 From: Daniel Machon Date: Fri, 8 May 2026 09:35:35 +0200 Subject: [PATCH net-next v4 11/13] net: lan966x: add PCIe FDMA XDP support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260508-lan966x-pci-fdma-v4-11-14e0c89d8d63@microchip.com> References: <20260508-lan966x-pci-fdma-v4-0-14e0c89d8d63@microchip.com> In-Reply-To: <20260508-lan966x-pci-fdma-v4-0-14e0c89d8d63@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: , , , X-Mailer: b4 0.14.3 Add XDP support for the PCIe FDMA path. The implementation operates on contiguous ATU-mapped buffers with memcpy-based XDP_TX, unlike the platform path which uses page_pool. XDP sees the frame with IFH and FCS stripped. These are removed in lan966x_fdma_pci_rx_check_frame() before the BPF program runs, because after the program returns the driver cannot tell whether the tail region was modified. The skb_pull/skb_trim previously done in lan966x_fdma_pci_rx_get_frame() are removed for the same reason; the frame pointer and length are pre-computed by rx_check_frame() and passed through rx_get_frame() and lan966x_xdp_pci_run() to the caller. lan966x_fdma_pci_xmit_xdpf() handles XDP_TX: it rebuilds a fresh IFH in the TX slot, copies the post-XDP frame after it, and lets HW insert a new FCS. lan966x_xdp_setup() is extended so the PCIe path skips the page_pool reload that the platform path needs. Only XDP_ACT_BASIC is supported. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- .../ethernet/microchip/lan966x/lan966x_fdma_pci.c | 162 +++++++++++++++++= +--- .../net/ethernet/microchip/lan966x/lan966x_main.c | 11 +- .../net/ethernet/microchip/lan966x/lan966x_main.h | 10 ++ .../net/ethernet/microchip/lan966x/lan966x_xdp.c | 10 ++ 4 files changed, 169 insertions(+), 24 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c b/dr= ivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c index 0568251a95d9..cf3d3afbcc8a 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ =20 +#include + #include "fdma_api.h" #include "lan966x_main.h" =20 @@ -114,7 +116,118 @@ static bool lan966x_fdma_pci_rx_size_fits(struct fdma= *fdma, u32 blockl) blockl <=3D fdma->db_size - XDP_PACKET_HEADROOM; } =20 -static int lan966x_fdma_pci_rx_check_frame(struct lan966x_rx *rx, u64 *src= _port) +static int lan966x_fdma_pci_xmit_xdpf(struct lan966x_port *port, + void *ptr, u32 len) +{ + struct lan966x *lan966x =3D port->lan966x; + struct lan966x_tx *tx =3D &lan966x->tx; + struct fdma *fdma =3D &tx->fdma; + int next_to_use, ret =3D 0; + void *virt_addr; + + spin_lock(&lan966x->tx_lock); + + next_to_use =3D lan966x_fdma_pci_get_next_dcb(fdma); + + if (next_to_use < 0) { + netif_stop_queue(port->dev); + ret =3D NETDEV_TX_BUSY; + goto out; + } + + if (!lan966x_fdma_pci_tx_size_fits(fdma, len)) { + port->dev->stats.tx_dropped++; + ret =3D -EINVAL; + goto out; + } + + /* virt_addr points to the IFH. */ + virt_addr =3D fdma_dataptr_virt_addr_contiguous(fdma, next_to_use, 0); + + /* Construct a fresh IFH. */ + memset(virt_addr, 0, IFH_LEN_BYTES); + lan966x_ifh_set_bypass(virt_addr, 1); + lan966x_ifh_set_port(virt_addr, BIT_ULL(port->chip_port)); + + /* Copy the (post-XDP) frame after the IFH. */ + memcpy(virt_addr + IFH_LEN_BYTES, ptr, len); + + /* Order frame write before DCB status write below. */ + dma_wmb(); + + /* Reserve ETH_FCS_LEN for the HW-inserted FCS (len is FCS-stripped). */ + fdma_dcb_add(fdma, + next_to_use, + 0, + FDMA_DCB_STATUS_INTR | + FDMA_DCB_STATUS_SOF | + FDMA_DCB_STATUS_EOF | + FDMA_DCB_STATUS_BLOCKO(0) | + FDMA_DCB_STATUS_BLOCKL(IFH_LEN_BYTES + len + ETH_FCS_LEN)); + + /* Start the transmission. */ + lan966x_fdma_tx_start(tx); + + port->dev->stats.tx_bytes +=3D len; + port->dev->stats.tx_packets++; + +out: + spin_unlock(&lan966x->tx_lock); + + return ret; +} + +static int lan966x_xdp_pci_run(struct lan966x_port *port, void *data, + u32 data_len, void **xdp_data, u32 *xdp_len) +{ + /* Read once so the NULL check and bpf_prog_run_xdp() see the same + * pointer. + */ + struct bpf_prog *xdp_prog =3D READ_ONCE(port->xdp_prog); + struct lan966x *lan966x =3D port->lan966x; + struct fdma *fdma =3D &lan966x->rx.fdma; + struct xdp_buff xdp; + u32 act; + + if (!xdp_prog) + return FDMA_PASS; + + xdp_init_buff(&xdp, fdma->db_size, &port->xdp_rxq); + + /* hard_start is set to slot start (virt_addr is XDP_PACKET_HEADROOM + * into the slot). Headroom includes the IFH; BPF may grow into it + * via adjust_head. IFH is rebuilt on XDP_TX and unread on XDP_PASS. + */ + xdp_prepare_buff(&xdp, + data - XDP_PACKET_HEADROOM, + XDP_PACKET_HEADROOM + IFH_LEN_BYTES, + data_len, + false); + + act =3D bpf_prog_run_xdp(xdp_prog, &xdp); + + *xdp_data =3D xdp.data; + *xdp_len =3D xdp.data_end - xdp.data; + + switch (act) { + case XDP_PASS: + return FDMA_PASS; + case XDP_TX: + return lan966x_fdma_pci_xmit_xdpf(port, *xdp_data, *xdp_len) ? + FDMA_DROP : FDMA_TX; + default: + bpf_warn_invalid_xdp_action(port->dev, xdp_prog, act); + fallthrough; + case XDP_ABORTED: + trace_xdp_exception(port->dev, xdp_prog, act); + fallthrough; + case XDP_DROP: + return FDMA_DROP; + } +} + +static int lan966x_fdma_pci_rx_check_frame(struct lan966x_rx *rx, u64 *src= _port, + void **data, u32 *data_len) { struct lan966x *lan966x =3D rx->lan966x; struct fdma *fdma =3D &rx->fdma; @@ -146,38 +259,33 @@ static int lan966x_fdma_pci_rx_check_frame(struct lan= 966x_rx *rx, u64 *src_port) if (!lan966x_fdma_pci_rx_size_fits(fdma, blockl)) return FDMA_ERROR; =20 - return FDMA_PASS; + /* Present the Ethernet frame (no IFH, no FCS). HW re-inserts the + * FCS on TX; see lan966x_fdma_pci_xmit_xdpf(). May be overridden + * by XDP. The FCS strip is unconditional because NETIF_F_RXFCS + * is not advertised in hw_features. + */ + *data =3D virt_addr + IFH_LEN_BYTES; + *data_len =3D blockl - IFH_LEN_BYTES - ETH_FCS_LEN; + + return lan966x_xdp_pci_run(port, virt_addr, *data_len, data, data_len); } =20 static struct sk_buff *lan966x_fdma_pci_rx_get_frame(struct lan966x_rx *rx, - u64 src_port) + u64 src_port, void *data, + u32 data_len) { struct lan966x *lan966x =3D rx->lan966x; - struct fdma *fdma =3D &rx->fdma; struct sk_buff *skb; - struct fdma_db *db; - u32 data_len; - - /* Get the received frame and create an SKB for it. */ - db =3D fdma_db_next_get(fdma); - data_len =3D FDMA_DCB_STATUS_BLOCKL(db->status); =20 skb =3D napi_alloc_skb(&lan966x->napi, data_len); if (unlikely(!skb)) return NULL; =20 - memcpy(skb->data, - fdma_dataptr_virt_addr_contiguous(fdma, - fdma->dcb_index, - fdma->db_index), - data_len); + memcpy(skb->data, data, data_len); =20 skb_put(skb, data_len); =20 skb->dev =3D lan966x->ports[src_port]->dev; - skb_pull(skb, IFH_LEN_BYTES); - - skb_trim(skb, skb->len - ETH_FCS_LEN); =20 skb->protocol =3D eth_type_trans(skb, skb->dev); =20 @@ -266,6 +374,8 @@ static int lan966x_fdma_pci_napi_poll(struct napi_struc= t *napi, int weight) struct sk_buff *skb; int counter =3D 0; u64 src_port; + u32 data_len; + void *data; =20 /* Wake any stopped TX queues if a TX DCB is available. */ spin_lock(&lan966x->tx_lock); @@ -282,14 +392,26 @@ static int lan966x_fdma_pci_napi_poll(struct napi_str= uct *napi, int weight) /* Order DONE read before DCB/frame reads below. */ dma_rmb(); counter++; - switch (lan966x_fdma_pci_rx_check_frame(rx, &src_port)) { + switch (lan966x_fdma_pci_rx_check_frame(rx, + &src_port, + &data, + &data_len)) { case FDMA_PASS: break; case FDMA_ERROR: fdma_dcb_advance(fdma); goto allocate_new; + case FDMA_TX: + fdma_dcb_advance(fdma); + continue; + case FDMA_DROP: + fdma_dcb_advance(fdma); + continue; } - skb =3D lan966x_fdma_pci_rx_get_frame(rx, src_port); + skb =3D lan966x_fdma_pci_rx_get_frame(rx, + src_port, + data, + data_len); fdma_dcb_advance(fdma); if (!skb) goto allocate_new; diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.c index 0bbc9d40b69b..adbd16bab46d 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c @@ -877,10 +877,13 @@ static int lan966x_probe_port(struct lan966x *lan966x= , u32 p, =20 port->phylink =3D phylink; =20 - if (lan966x->fdma) - dev->xdp_features =3D NETDEV_XDP_ACT_BASIC | - NETDEV_XDP_ACT_REDIRECT | - NETDEV_XDP_ACT_NDO_XMIT; + if (lan966x->fdma) { + dev->xdp_features =3D NETDEV_XDP_ACT_BASIC; + + if (!lan966x_is_pci(lan966x)) + dev->xdp_features |=3D NETDEV_XDP_ACT_REDIRECT | + NETDEV_XDP_ACT_NDO_XMIT; + } =20 err =3D register_netdev(dev); if (err) { diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.h index e7fdd4447fb6..8911825eab77 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.h @@ -595,6 +595,16 @@ int lan966x_qsys_sw_status(struct lan966x *lan966x); =20 #if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) extern const struct lan966x_fdma_ops lan966x_fdma_pci_ops; + +static inline bool lan966x_is_pci(struct lan966x *lan966x) +{ + return lan966x->ops =3D=3D &lan966x_fdma_pci_ops; +} +#else +static inline bool lan966x_is_pci(struct lan966x *lan966x) +{ + return false; +} #endif =20 int lan966x_lag_port_join(struct lan966x_port *port, diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_xdp.c b/drivers= /net/ethernet/microchip/lan966x/lan966x_xdp.c index 9ee61db8690b..b470f731e25c 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_xdp.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_xdp.c @@ -24,6 +24,16 @@ static int lan966x_xdp_setup(struct net_device *dev, str= uct netdev_bpf *xdp) old_prog =3D xchg(&port->xdp_prog, xdp->prog); new_xdp =3D lan966x_xdp_present(lan966x); =20 + /* PCIe FDMA uses contiguous buffers, so no page_pool reload + * is needed. Drain NAPI before freeing the old program so + * no in-flight poll holds a stale pointer. + */ + if (lan966x_is_pci(lan966x)) { + if (old_prog) + napi_synchronize(&lan966x->napi); + goto out; + } + if (old_xdp =3D=3D new_xdp) goto out; =20 --=20 2.34.1 From nobody Sat May 30 12:37:14 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5AC2E346AC2; Fri, 8 May 2026 07:36:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778225789; cv=none; b=BMy0N1Me+N4OshrgQuEpEmKvmG2xs1u4xWqymEtpDe80ZY4v/a3CKnCDsYdtVJUULC5fRgw28jl5oPV83r2SEMjoKBoE0qeph3ipDS0HJKop0uIY3uW/9dczwdIsjiG5Lp10y8BtMgUSYxA/hekFIFHg9Gj5/a6HvdbZlGesOfY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778225789; c=relaxed/simple; bh=pLLUnpsQHk0XLLoB+wBplrU8A7WIjOzUca/wCfOw6mw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=cKKQ1dMfIGW27AuspwrSdim24vvkpBy5eRGKhAub7qgvEjWDsZBwipKWoGNW8ypXrUvu+c6CBw4g+LskBtCDvEsQrL60UwGOa/GRfT/bZJ2FexTiq2gqsqhx8XoQguFdulVaIAKyIXY0oTMti8GHyM+y1vDUNvFxIW3OeZh2Vrk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=o4kEODVc; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="o4kEODVc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1778225788; x=1809761788; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=pLLUnpsQHk0XLLoB+wBplrU8A7WIjOzUca/wCfOw6mw=; b=o4kEODVc1n5LnmlLujsdhyjkdRa4A+4+rSd/eKiL9wP46oQVTOH7U36X zNSPUKTbPlfmpfKsHWl1sEP+MMXdK++wqRBMXxhWGJZmrF0FVJRT6FHQh HHJSOUyEvmANl2CGkK3lGv6n350fHciikeZ9sxhoSJUdLpuweaSOEjYkq FIJOu/auIEO5+wS97azdR1rTikco0O7usUuK/WV/r3arwBd3xFmK55Nkh 0oFTFEWKiRqW7+RWQ5CZn4Ox9lcQFvLI/A9AEWYQZC4sG6zRKr3TizDSG +CjWXCzwiWmZknGoDysJmplAOMs4UMGha/YEnror6vb+oiFBv9RBB4/5L A==; X-CSE-ConnectionGUID: tREAqjtrRMmv2W0hgA17uQ== X-CSE-MsgGUID: hdL4aii1Sl6Jp/iE7AGrxA== X-IronPort-AV: E=Sophos;i="6.23,223,1770620400"; d="scan'208";a="224455790" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 08 May 2026 00:36:28 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Fri, 8 May 2026 00:36:27 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 8 May 2026 00:36:24 -0700 From: Daniel Machon Date: Fri, 8 May 2026 09:35:36 +0200 Subject: [PATCH net-next v4 12/13] misc: lan966x-pci: dts: extend cpu reg to cover PCIE DBI space Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260508-lan966x-pci-fdma-v4-12-14e0c89d8d63@microchip.com> References: <20260508-lan966x-pci-fdma-v4-0-14e0c89d8d63@microchip.com> In-Reply-To: <20260508-lan966x-pci-fdma-v4-0-14e0c89d8d63@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: , , , X-Mailer: b4 0.14.3 The ATU outbound windows used by the FDMA engine are programmed through registers at offset 0x400000+, which falls outside the current cpu reg mapping. Extend the cpu reg size from 0x100000 (1MB) to 0x800000 (8MB) to cover the full PCIE DBI and iATU register space. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- drivers/misc/lan966x_pci.dtso | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/lan966x_pci.dtso b/drivers/misc/lan966x_pci.dtso index 7b196b0a0eb6..7bb726550caf 100644 --- a/drivers/misc/lan966x_pci.dtso +++ b/drivers/misc/lan966x_pci.dtso @@ -135,7 +135,7 @@ lan966x_phy1: ethernet-lan966x_phy@2 { =20 switch: switch@e0000000 { compatible =3D "microchip,lan966x-switch"; - reg =3D <0xe0000000 0x0100000>, + reg =3D <0xe0000000 0x0800000>, <0xe2000000 0x0800000>; reg-names =3D "cpu", "gcb"; =20 --=20 2.34.1 From nobody Sat May 30 12:37:14 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C3D0346AC2; Fri, 8 May 2026 07:36:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778225794; cv=none; b=cjPTqEUndN2fs0605peLYGMoUYbJ49QFKEEdgFIkyHS16AEjYrQnJ2WMlPDF5KOw4c5aaTQv9vRQfRfqlmmv7e5U+g2nH2LPfl8gd95xDS6Vc1qoDNcPZLnja167eojTOIJgYdgvths88wY7fpZM5INwuszu9U7DPwou1+U2c4Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778225794; c=relaxed/simple; bh=wGxs+F/+5Vrhuyz2y5uEWLeuFrAw1YPbFSMnjR0PIic=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Uw2nIhQKOGHTQO5fs4NOlX1R5mnFkEYosIb7PbISOGDyIiuXdMkxZxi3kiTmG6bNiIkSGt0smfKfFSVnnNTcZCM6jDbxrc52ywVm70XkzGEjDPrpxPbliWybQ64ftoZ8e+WvcrOhPN2waoDxz8Ee4kTG3Y3GKRtAofjOWczda88= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=z3DRB6ty; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="z3DRB6ty" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1778225792; x=1809761792; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=wGxs+F/+5Vrhuyz2y5uEWLeuFrAw1YPbFSMnjR0PIic=; b=z3DRB6tyv8KeoZxm6uYn9DwwIS/C5DhkLctZhkSIXZQJ0bNcGR6lk8Pd agqWYc8nYpr78VQPVJ2MYeUnsaup2KyieMYrD+sKcfKTEEF+lyHaQud2v TewqVnTI3mbE/XDpTV3wSG43FQcqmon/gy/B+CW3UjL4v1ElnuoM9JK/c hGZa2JA7oSdSxVfAhAYCv8FvgG1AprKS4dzlXQfywn2O7eKFaF8zvzoQu EysLmZLxqvkLeRl9irDYpviIAoZfHinjXXpmB4hINg+DOq9RpzH9j1eOi jiG/gvcJb0C+ln9ycWk8rm2e4SXy5piPedtv59in8xUv6R2/jxcoiiVEA g==; X-CSE-ConnectionGUID: Si8tHD4XTWCeQ24m5HJjXg== X-CSE-MsgGUID: jKLFif6vSnGtMAwY3BSs3g== X-IronPort-AV: E=Sophos;i="6.23,223,1770620400"; d="scan'208";a="56432180" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 08 May 2026 00:36:31 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Fri, 8 May 2026 00:36:31 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 8 May 2026 00:36:27 -0700 From: Daniel Machon Date: Fri, 8 May 2026 09:35:37 +0200 Subject: [PATCH net-next v4 13/13] misc: lan966x-pci: dts: add fdma interrupt to overlay Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260508-lan966x-pci-fdma-v4-13-14e0c89d8d63@microchip.com> References: <20260508-lan966x-pci-fdma-v4-0-14e0c89d8d63@microchip.com> In-Reply-To: <20260508-lan966x-pci-fdma-v4-0-14e0c89d8d63@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: , , , X-Mailer: b4 0.14.3 Add the fdma interrupt (OIC interrupt 14) to the lan966x PCI device tree overlay, enabling FDMA-based frame injection/extraction when the switch is connected over PCIe. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- drivers/misc/lan966x_pci.dtso | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/misc/lan966x_pci.dtso b/drivers/misc/lan966x_pci.dtso index 7bb726550caf..5bb12dbc0843 100644 --- a/drivers/misc/lan966x_pci.dtso +++ b/drivers/misc/lan966x_pci.dtso @@ -141,8 +141,9 @@ switch: switch@e0000000 { =20 interrupt-parent =3D <&oic>; interrupts =3D <12 IRQ_TYPE_LEVEL_HIGH>, + <14 IRQ_TYPE_LEVEL_HIGH>, <9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names =3D "xtr", "ana"; + interrupt-names =3D "xtr", "fdma", "ana"; =20 resets =3D <&reset 0>; reset-names =3D "switch"; --=20 2.34.1