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Fri, 8 May 2026 07:56:03 -0400 From: Janani Sunil Date: Fri, 8 May 2026 13:55:47 +0200 Subject: [PATCH v2 1/3] dt-bindings: iio: dac: Add AD5529R Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260508-ad5529r-driver-v2-1-e315441685d7@analog.com> References: <20260508-ad5529r-driver-v2-0-e315441685d7@analog.com> In-Reply-To: <20260508-ad5529r-driver-v2-0-e315441685d7@analog.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , "David Lechner" , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , "Jonathan Corbet" , Shuah Khan CC: , , , , Janani Sunil , Janani Sunil X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1778241348; l=4172; i=janani.sunil@analog.com; s=20260507; h=from:subject:message-id; bh=9H5BNeVf9I/101WvuVw3JYEgApgCLJiV97a2V6+vvbM=; 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Signed-off-by: Janani Sunil --- .../devicetree/bindings/iio/dac/adi,ad5529r.yaml | 96 ++++++++++++++++++= ++++ MAINTAINERS | 7 ++ 2 files changed, 103 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad5529r.yaml b/D= ocumentation/devicetree/bindings/iio/dac/adi,ad5529r.yaml new file mode 100644 index 000000000000..f531b4865b01 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad5529r.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/dac/adi,ad5529r.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD5529R 16-Channel 12/16-bit High Voltage DAC + +maintainers: + - Janani Sunil + +description: | + The AD5529R is a 16-channel, 12-bit or 16-bit, high voltage, buffered vo= ltage output + digital-to-analog converter (DAC) with an integrated precision reference. + The device operates from unipolar and bipolar supplies. It is guaranteed + monotonic and has built-in rail-to-rail output buffers that can source or + sink up to 25mA. + + Specifications: + * 16 independent 12-bit or 16-bit DAC channels + * Independently programmable output ranges: 0V to 5V, 0V to 10V, 0V to 2= 0V, + 0V to 40V, =C2=B15V, =C2=B110V, =C2=B115V, and =C2=B120V + * The device supports SPI communication with Mode 0 and Mode 3. + * 4.096V precision reference, 12ppm/=C2=B0C maximum + * Built-in function generation: Toggle, Sinusoidal Dither, and Ramp wave= forms + * Multiplexer for output voltage, load current sense and die temperature + + Datasheet: https://www.analog.com/media/en/technical-documentation/data-= sheets/ad5529r.pdf + +properties: + compatible: + const: adi,ad5529r + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 50000000 + + reset-gpios: + maxItems: 1 + description: + GPIO connected to the RESET pin. Active low. When asserted low, + performs a power-on reset and initializes the device to its default = state. + + vdd-supply: + description: Digital power supply (typically 3.3V) + + avdd-supply: + description: Analog power supply (typically 5V) + + hvdd-supply: + description: High voltage positive supply (up to 40V for output range) + + hvss-supply: + description: High voltage negative supply (ground or negative voltage) + +required: + - compatible + - reg + - vdd-supply + - avdd-supply + - hvdd-supply + - hvss-supply + +dependencies: + spi-cpha: [ spi-cpol ] + spi-cpol: [ spi-cpha ] + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + dac@0 { + compatible =3D "adi,ad5529r"; + reg =3D <0>; + spi-max-frequency =3D <25000000>; + + vdd-supply =3D <&vdd_regulator>; + avdd-supply =3D <&avdd_regulator>; + hvdd-supply =3D <&hvdd_regulator>; + hvss-supply =3D <&hvss_regulator>; + + reset-gpios =3D <&gpio0 87 GPIO_ACTIVE_LOW>; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index d6c3c7d22403..320e84765ce6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1507,6 +1507,13 @@ W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad4851.yaml F: drivers/iio/adc/ad4851.c =20 +ANALOG DEVICES INC AD5529R DRIVER +M: Janani Sunil +L: linux-iio@vger.kernel.org +S: Supported +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/iio/dac/adi,ad5529r.yaml + ANALOG DEVICES INC AD5706R DRIVER M: Alexis Czezar Torreno L: linux-iio@vger.kernel.org --=20 2.43.0 From nobody Sat Jun 13 08:31:55 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 608143DBD54; Fri, 8 May 2026 11:56:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 8 May 2026 07:56:05 -0400 From: Janani Sunil Date: Fri, 8 May 2026 13:55:48 +0200 Subject: [PATCH v2 2/3] iio: dac: Add AD5529R DAC driver support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260508-ad5529r-driver-v2-2-e315441685d7@analog.com> References: <20260508-ad5529r-driver-v2-0-e315441685d7@analog.com> In-Reply-To: <20260508-ad5529r-driver-v2-0-e315441685d7@analog.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , "David Lechner" , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , "Jonathan Corbet" , Shuah Khan CC: , , , , Janani Sunil , Janani Sunil X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1778241348; l=22198; i=janani.sunil@analog.com; s=20260507; h=from:subject:message-id; bh=HSzUIJROzQ5gO8RKovQ5ZkfNf83EOf2L7N/ee2jVgfc=; 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Supports both 12-bit and 16-bit + resolution variants. + + To compile this driver as a module, choose M here: the + module will be called ad5529r. + config AD5592R_BASE tristate =20 diff --git a/drivers/iio/dac/Makefile b/drivers/iio/dac/Makefile index 003431798498..f35e060b3643 100644 --- a/drivers/iio/dac/Makefile +++ b/drivers/iio/dac/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_AD5446) +=3D ad5446.o obj-$(CONFIG_AD5446_SPI) +=3D ad5446-spi.o obj-$(CONFIG_AD5446_I2C) +=3D ad5446-i2c.o obj-$(CONFIG_AD5449) +=3D ad5449.o +obj-$(CONFIG_AD5529R) +=3D ad5529r.o obj-$(CONFIG_AD5592R_BASE) +=3D ad5592r-base.o obj-$(CONFIG_AD5592R) +=3D ad5592r.o obj-$(CONFIG_AD5593R) +=3D ad5593r.o diff --git a/drivers/iio/dac/ad5529r.c b/drivers/iio/dac/ad5529r.c new file mode 100644 index 000000000000..3676956f6eff --- /dev/null +++ b/drivers/iio/dac/ad5529r.c @@ -0,0 +1,564 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * AD5529R Digital-to-Analog Converter Driver + * 16-Channel, 12/16-Bit, 40V High Voltage Precision DAC + * + * Copyright 2026 Analog Devices Inc. + * Author: Janani Sunil + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Register Map */ +#define AD5529R_REG_INTERFACE_CONFIG_A 0x00 +#define AD5529R_REG_INTERFACE_CONFIG_B 0x01 +#define AD5529R_REG_DEVICE_CONFIG 0x02 +#define AD5529R_REG_CHIP_TYPE 0x03 +#define AD5529R_REG_PRODUCT_ID_L 0x04 +#define AD5529R_REG_PRODUCT_ID_H 0x05 +#define AD5529R_REG_CHIP_GRADE 0x06 +#define AD5529R_REG_SCRATCH_PAD 0x0A +#define AD5529R_REG_SPI_REVISION 0x0B +#define AD5529R_REG_VENDOR_L 0x0C +#define AD5529R_REG_VENDOR_H 0x0D +#define AD5529R_REG_STREAM_MODE 0x0E +#define AD5529R_REG_TRANSFER_CONFIG 0x0F +#define AD5529R_REG_INTERFACE_CONFIG_C 0x10 +#define AD5529R_REG_INTERFACE_STATUS_A 0x11 + +/* Configuration registers */ +#define AD5529R_REG_MULTI_DAC_CH_SEL (0x14 + 1) +#define AD5529R_REG_LDAC_SYNC_ASYNC (0x16 + 1) +#define AD5529R_REG_LDAC_HW_SW (0x18 + 1) + +/* Hardware LDAC source and edge select registers (per channel, 16-bit) */ +#define AD5529R_REG_LDAC_HW_SRC_EDGE_SEL_BASE (0x1A + 1) +#define AD5529R_REG_LDAC_HW_SRC_EDGE_SEL(ch) \ + (AD5529R_REG_LDAC_HW_SRC_EDGE_SEL_BASE + (ch) * 2) + +/* Output configuration */ +#define AD5529R_REG_OUT_OPERATING_MODE (0x3A + 1) +#define AD5529R_REG_OUT_RANGE_BASE (0x3C + 1) +#define AD5529R_REG_OUT_RANGE(ch) (AD5529R_REG_OUT_RANGE_BASE + (ch) * 2) + +/* Calibration registers */ +#define AD5529R_REG_CAL_GAIN_BASE (0x5C + 1) +#define AD5529R_REG_CAL_GAIN(ch) (AD5529R_REG_CAL_GAIN_BASE + (ch) * 2) + +#define AD5529R_REG_CAL_OFFSET_BASE (0x7C + 1) +#define AD5529R_REG_CAL_OFFSET(ch) (AD5529R_REG_CAL_OFFSET_BASE + (ch) * = 2) + +/* Function generator registers */ +#define AD5529R_REG_FUNC_EN (0x9C + 1) +#define AD5529R_REG_FUNC_MODE_SEL_BASE (0x9E + 1) +#define AD5529R_REG_FUNC_MODE_SEL(ch) \ + (AD5529R_REG_FUNC_MODE_SEL_BASE + (ch) * 2) + +#define AD5529R_REG_FUNC_DAC_INPUT_B_BASE (0xBE + 1) +#define AD5529R_REG_FUNC_DAC_INPUT_B(ch) \ + (AD5529R_REG_FUNC_DAC_INPUT_B_BASE + (ch) * 2) + +#define AD5529R_REG_FUNC_DITHER_PERIOD_BASE (0xDE + 1) +#define AD5529R_REG_FUNC_DITHER_PERIOD(ch) \ + (AD5529R_REG_FUNC_DITHER_PERIOD_BASE + (ch) * 2) + +#define AD5529R_REG_FUNC_DITHER_PHASE_BASE (0xFE + 1) +#define AD5529R_REG_FUNC_DITHER_PHASE(ch) \ + (AD5529R_REG_FUNC_DITHER_PHASE_BASE + (ch) * 2) + +#define AD5529R_REG_FUNC_RAMP_STEP_BASE (0x11E + 1) +#define AD5529R_REG_FUNC_RAMP_STEP(ch) \ + (AD5529R_REG_FUNC_RAMP_STEP_BASE + (ch) * 2) + +#define AD5529R_REG_FUNC_INT_EN (0x13E + 1) + +/* Multiplexer and main DAC registers */ +#define AD5529R_REG_MUX_OUT_SEL (0x140 + 1) +#define AD5529R_REG_MULTI_DAC_SW_LDAC (0x142 + 1) +#define AD5529R_REG_MULTI_DAC_INPUT_A (0x144 + 1) +#define AD5529R_REG_DAC_SW_LDAC (0x146 + 1) + +#define AD5529R_REG_DAC_INPUT_A_BASE (0x148 + 1) +#define AD5529R_REG_DAC_INPUT_A(ch) (AD5529R_REG_DAC_INPUT_A_BASE + (ch) = * 2) + +/* Status and readback registers */ +#define AD5529R_REG_FUNC_INT_STAT (0x168 + 1) +#define AD5529R_REG_DAC_DATA_READBACK_BASE (0x16A + 1) +#define AD5529R_REG_DAC_DATA_READBACK(ch) \ + (AD5529R_REG_DAC_DATA_READBACK_BASE + (ch) * 2) + +/* Temperature sensor registers */ +#define AD5529R_REG_TSENS_EN (0x18A + 1) +#define AD5529R_REG_TSENS_ALERT_FLAG (0x18C + 1) +#define AD5529R_REG_TSENS_SHTD_FLAG (0x18E + 1) +#define AD5529R_REG_TSENS_ALERT_STAT (0x190 + 1) +#define AD5529R_REG_TSENS_SHTD_STAT (0x192 + 1) +#define AD5529R_REG_ALARMB_TSENS_EN (0x194 + 1) +#define AD5529R_REG_ALARMB_TSENS_SEL (0x196 + 1) +#define AD5529R_REG_TSENS_SHTD_EN_CH (0x198 + 1) +#define AD5529R_REG_DAC_DIS_DEGLITCH_CH (0x19A + 1) +#define AD5529R_REG_DAC_INT_EN (0x19C + 1) +#define AD5529R_REG_ALL_FUNC_INT_STAT (0x19E + 1) +#define AD5529R_REG_FUNC_BUSY (0x1A0 + 1) +#define AD5529R_REG_REF_SRC_SEL (0x1A2 + 1) +#define AD5529R_REG_INIT_CRC_ERR_STAT (0x1A4 + 1) + +/* Hotpath registers for multi-device support */ +#define AD5529R_REG_MULTI_DAC_HOTPATH_SW_LDAC (0x1A8 + 1) +#define AD5529R_REG_MULTI_DAC_HOTPATH_INPUT_A_DIE_0 (0x1AA + 1) +#define AD5529R_REG_MULTI_DAC_HOTPATH_INPUT_A_DIE_1 (0x1AC + 1) +#define AD5529R_REG_MULTI_DAC_HOTPATH_INPUT_A_DIE_2 (0x1AE + 1) +#define AD5529R_REG_MULTI_DAC_HOTPATH_INPUT_A_DIE_3 (0x1B0 + 1) +#define AD5529R_REG_DAC_HOTPATH_SW_LDAC (0x1B2 + 1) + +/* Hotpath per-channel DAC input registers for each die */ +#define AD5529R_REG_DAC_HOTPATH_INPUT_A_DIE_0_BASE (0x1B4 + 1) +#define AD5529R_REG_DAC_HOTPATH_INPUT_A_DIE_0(ch) \ + (AD5529R_REG_DAC_HOTPATH_INPUT_A_DIE_0_BASE + (ch) * 2) + +#define AD5529R_REG_DAC_HOTPATH_INPUT_A_DIE_1_BASE (0x1D4 + 1) +#define AD5529R_REG_DAC_HOTPATH_INPUT_A_DIE_1(ch) \ + (AD5529R_REG_DAC_HOTPATH_INPUT_A_DIE_1_BASE + (ch) * 2) + +#define AD5529R_REG_DAC_HOTPATH_INPUT_A_DIE_2_BASE (0x1F4 + 1) +#define AD5529R_REG_DAC_HOTPATH_INPUT_A_DIE_2(ch) \ + (AD5529R_REG_DAC_HOTPATH_INPUT_A_DIE_2_BASE + (ch) * 2) + +#define AD5529R_REG_DAC_HOTPATH_INPUT_A_DIE_3_BASE (0x214 + 1) +#define AD5529R_REG_DAC_HOTPATH_INPUT_A_DIE_3(ch) \ + (AD5529R_REG_DAC_HOTPATH_INPUT_A_DIE_3_BASE + (ch) * 2) + +#define AD5529R_INTERFACE_CONFIG_A_SW_RESET (BIT(7) | BIT(0)) +#define AD5529R_INTERFACE_CONFIG_A_ADDR_ASCENSION BIT(5) +#define AD5529R_INTERFACE_CONFIG_A_SDO_ENABLE BIT(4) +#define AD5529R_INTERFACE_CONFIG_A_DEFAULT 0x10 +#define AD5529R_NUM_CHANNELS 16 +#define AD5529R_MAX_CHANNEL_INDEX (AD5529R_NUM_CHANNELS - 1) +#define AD5529R_MAX_REGISTER (0x232 + 1) +#define AD5529R_8BIT_REG_MAX 0x13 +#define AD5529R_ADDR(reg_addr) ((reg_addr) & 0xFFF) +#define AD5529R_RESET_PULSE_US 1000 +#define AD5529R_RESET_DELAY_US 10000 +#define AD5529R_SPI_BUF_SIZE 4 +#define AD5529R_NUM_SUPPLIES 4 +#define AD5529R_SPI_READ_FLAG 0x80 + +/* Device identification values */ +#define AD5529R_PRODUCT_ID_16BIT 0x4A +#define AD5529R_PRODUCT_ID_12BIT 0x49 + +struct ad5529r_model_data { + const char *model_name; + unsigned int resolution; + const struct iio_chan_spec *channels; +}; + +#define AD5529R_DAC_CHANNEL(chan, bits) { \ + .type =3D IIO_VOLTAGE, \ + .indexed =3D 1, \ + .output =3D 1, \ + .channel =3D (chan), \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE), \ + .scan_type =3D { \ + .sign =3D 'u', \ + .realbits =3D (bits), \ + .storagebits =3D 16, \ + }, \ +} + +static const char * const ad5529r_supply_names[AD5529R_NUM_SUPPLIES] =3D { + "vdd", + "avdd", + "hvdd", + "hvss", +}; + +static const struct iio_chan_spec ad5529r_channels_16bit[] =3D { + AD5529R_DAC_CHANNEL(0, 16), + AD5529R_DAC_CHANNEL(1, 16), + AD5529R_DAC_CHANNEL(2, 16), + AD5529R_DAC_CHANNEL(3, 16), + AD5529R_DAC_CHANNEL(4, 16), + AD5529R_DAC_CHANNEL(5, 16), + AD5529R_DAC_CHANNEL(6, 16), + AD5529R_DAC_CHANNEL(7, 16), + AD5529R_DAC_CHANNEL(8, 16), + AD5529R_DAC_CHANNEL(9, 16), + AD5529R_DAC_CHANNEL(10, 16), + AD5529R_DAC_CHANNEL(11, 16), + AD5529R_DAC_CHANNEL(12, 16), + AD5529R_DAC_CHANNEL(13, 16), + AD5529R_DAC_CHANNEL(14, 16), + AD5529R_DAC_CHANNEL(15, 16), +}; + +static const struct iio_chan_spec ad5529r_channels_12bit[] =3D { + AD5529R_DAC_CHANNEL(0, 12), + AD5529R_DAC_CHANNEL(1, 12), + AD5529R_DAC_CHANNEL(2, 12), + AD5529R_DAC_CHANNEL(3, 12), + AD5529R_DAC_CHANNEL(4, 12), + AD5529R_DAC_CHANNEL(5, 12), + AD5529R_DAC_CHANNEL(6, 12), + AD5529R_DAC_CHANNEL(7, 12), + AD5529R_DAC_CHANNEL(8, 12), + AD5529R_DAC_CHANNEL(9, 12), + AD5529R_DAC_CHANNEL(10, 12), + AD5529R_DAC_CHANNEL(11, 12), + AD5529R_DAC_CHANNEL(12, 12), + AD5529R_DAC_CHANNEL(13, 12), + AD5529R_DAC_CHANNEL(14, 12), + AD5529R_DAC_CHANNEL(15, 12), +}; + +static const struct ad5529r_model_data ad5529r_16bit_model_data =3D { + .model_name =3D "ad5529r-16", + .resolution =3D 16, + .channels =3D ad5529r_channels_16bit, +}; + +static const struct ad5529r_model_data ad5529r_12bit_model_data =3D { + .model_name =3D "ad5529r-12", + .resolution =3D 12, + .channels =3D ad5529r_channels_12bit, +}; + +struct ad5529r_state { + struct spi_device *spi; + const struct ad5529r_model_data *model_data; + struct regmap *regmap_8bit; + struct regmap *regmap_16bit; +}; + +static const struct regmap_range ad5529r_8bit_readable_ranges[] =3D { + regmap_reg_range(AD5529R_REG_INTERFACE_CONFIG_A, AD5529R_REG_CHIP_GRADE), + regmap_reg_range(AD5529R_REG_SCRATCH_PAD, AD5529R_REG_VENDOR_H), + regmap_reg_range(AD5529R_REG_STREAM_MODE, AD5529R_REG_INTERFACE_STATUS_A), +}; + +static const struct regmap_range ad5529r_16bit_readable_ranges[] =3D { + regmap_reg_range(AD5529R_REG_MULTI_DAC_CH_SEL, AD5529R_REG_LDAC_HW_SW), + regmap_reg_range(AD5529R_REG_LDAC_HW_SRC_EDGE_SEL_BASE, + AD5529R_REG_LDAC_HW_SRC_EDGE_SEL_BASE + AD5529R_MAX_CHANNEL_INDEX * 2), + regmap_reg_range(AD5529R_REG_OUT_OPERATING_MODE, AD5529R_REG_OUT_OPERATIN= G_MODE), + regmap_reg_range(AD5529R_REG_OUT_RANGE_BASE, + AD5529R_REG_OUT_RANGE_BASE + AD5529R_MAX_CHANNEL_INDEX * 2), + regmap_reg_range(AD5529R_REG_CAL_GAIN_BASE, + AD5529R_REG_CAL_GAIN_BASE + AD5529R_MAX_CHANNEL_INDEX * 2), + regmap_reg_range(AD5529R_REG_CAL_OFFSET_BASE, + AD5529R_REG_CAL_OFFSET_BASE + AD5529R_MAX_CHANNEL_INDEX * 2), + regmap_reg_range(AD5529R_REG_FUNC_EN, AD5529R_REG_FUNC_EN), + regmap_reg_range(AD5529R_REG_FUNC_MODE_SEL_BASE, + AD5529R_REG_FUNC_MODE_SEL_BASE + AD5529R_MAX_CHANNEL_INDEX * 2), + regmap_reg_range(AD5529R_REG_FUNC_DAC_INPUT_B_BASE, + AD5529R_REG_FUNC_DAC_INPUT_B_BASE + AD5529R_MAX_CHANNEL_INDEX * 2), + regmap_reg_range(AD5529R_REG_FUNC_DITHER_PERIOD_BASE, + AD5529R_REG_FUNC_DITHER_PERIOD_BASE + AD5529R_MAX_CHANNEL_INDEX * 2), + regmap_reg_range(AD5529R_REG_FUNC_DITHER_PHASE_BASE, + AD5529R_REG_FUNC_DITHER_PHASE_BASE + AD5529R_MAX_CHANNEL_INDEX * 2), + regmap_reg_range(AD5529R_REG_FUNC_RAMP_STEP_BASE, + AD5529R_REG_FUNC_RAMP_STEP_BASE + AD5529R_MAX_CHANNEL_INDEX * 2), + regmap_reg_range(AD5529R_REG_FUNC_INT_EN, AD5529R_REG_DAC_SW_LDAC), + regmap_reg_range(AD5529R_REG_DAC_INPUT_A_BASE, + AD5529R_REG_DAC_INPUT_A_BASE + AD5529R_MAX_CHANNEL_INDEX * 2), + regmap_reg_range(AD5529R_REG_FUNC_INT_STAT, AD5529R_REG_FUNC_INT_STAT), + regmap_reg_range(AD5529R_REG_DAC_DATA_READBACK_BASE, + AD5529R_REG_DAC_DATA_READBACK_BASE + AD5529R_MAX_CHANNEL_INDEX * 2), + regmap_reg_range(AD5529R_REG_TSENS_EN, AD5529R_REG_INIT_CRC_ERR_STAT), + regmap_reg_range(AD5529R_REG_MULTI_DAC_HOTPATH_SW_LDAC, AD5529R_REG_DAC_H= OTPATH_SW_LDAC), + regmap_reg_range(AD5529R_REG_DAC_HOTPATH_INPUT_A_DIE_0_BASE, + AD5529R_REG_DAC_HOTPATH_INPUT_A_DIE_0_BASE + + AD5529R_MAX_CHANNEL_INDEX * 2), + regmap_reg_range(AD5529R_REG_DAC_HOTPATH_INPUT_A_DIE_1_BASE, + AD5529R_REG_DAC_HOTPATH_INPUT_A_DIE_1_BASE + + AD5529R_MAX_CHANNEL_INDEX * 2), + regmap_reg_range(AD5529R_REG_DAC_HOTPATH_INPUT_A_DIE_2_BASE, + AD5529R_REG_DAC_HOTPATH_INPUT_A_DIE_2_BASE + + AD5529R_MAX_CHANNEL_INDEX * 2), + regmap_reg_range(AD5529R_REG_DAC_HOTPATH_INPUT_A_DIE_3_BASE, + AD5529R_REG_DAC_HOTPATH_INPUT_A_DIE_3_BASE + + AD5529R_MAX_CHANNEL_INDEX * 2), +}; + +static const struct regmap_access_table ad5529r_8bit_readable_table =3D { + .yes_ranges =3D ad5529r_8bit_readable_ranges, + .n_yes_ranges =3D ARRAY_SIZE(ad5529r_8bit_readable_ranges), +}; + +static const struct regmap_access_table ad5529r_16bit_readable_table =3D { + .yes_ranges =3D ad5529r_16bit_readable_ranges, + .n_yes_ranges =3D ARRAY_SIZE(ad5529r_16bit_readable_ranges), +}; + +static const struct regmap_range ad5529r_8bit_read_only_ranges[] =3D { + regmap_reg_range(AD5529R_REG_CHIP_TYPE, AD5529R_REG_CHIP_GRADE), + regmap_reg_range(AD5529R_REG_SPI_REVISION, AD5529R_REG_VENDOR_H), + regmap_reg_range(AD5529R_REG_DEVICE_CONFIG, AD5529R_REG_DEVICE_CONFIG), +}; + +static const struct regmap_range ad5529r_16bit_read_only_ranges[] =3D { + regmap_reg_range(AD5529R_REG_TSENS_ALERT_FLAG, AD5529R_REG_TSENS_SHTD_STA= T), + regmap_reg_range(AD5529R_REG_ALL_FUNC_INT_STAT, AD5529R_REG_FUNC_BUSY), + regmap_reg_range(AD5529R_REG_INIT_CRC_ERR_STAT, AD5529R_REG_INIT_CRC_ERR_= STAT), + regmap_reg_range(AD5529R_REG_DAC_DATA_READBACK_BASE, + AD5529R_REG_DAC_DATA_READBACK_BASE + AD5529R_MAX_CHANNEL_INDEX * 2), +}; + +static const struct regmap_access_table ad5529r_8bit_writeable_table =3D { + .no_ranges =3D ad5529r_8bit_read_only_ranges, + .n_no_ranges =3D ARRAY_SIZE(ad5529r_8bit_read_only_ranges), +}; + +static const struct regmap_access_table ad5529r_16bit_writeable_table =3D { + .no_ranges =3D ad5529r_16bit_read_only_ranges, + .n_no_ranges =3D ARRAY_SIZE(ad5529r_16bit_read_only_ranges), +}; + +static const struct regmap_config ad5529r_regmap_8bit_config =3D { + .name =3D "ad5529r-8bit", + .reg_bits =3D 16, + .val_bits =3D 8, + .max_register =3D AD5529R_8BIT_REG_MAX, + .read_flag_mask =3D AD5529R_SPI_READ_FLAG, + .rd_table =3D &ad5529r_8bit_readable_table, + .wr_table =3D &ad5529r_8bit_writeable_table, +}; + +static const struct regmap_config ad5529r_regmap_16bit_config =3D { + .name =3D "ad5529r-16bit", + .reg_bits =3D 16, + .val_bits =3D 16, + .max_register =3D AD5529R_MAX_REGISTER, + .read_flag_mask =3D AD5529R_SPI_READ_FLAG, + .rd_table =3D &ad5529r_16bit_readable_table, + .wr_table =3D &ad5529r_16bit_writeable_table, +}; + +static struct regmap *ad5529r_get_regmap(struct ad5529r_state *st, unsigne= d int reg) +{ + if (reg <=3D AD5529R_8BIT_REG_MAX) + return st->regmap_8bit; + + return st->regmap_16bit; +} + +static int ad5529r_debugfs_reg_read(struct ad5529r_state *st, unsigned int= reg, + unsigned int *val) +{ + return regmap_read(ad5529r_get_regmap(st, reg), reg, val); +} + +static int ad5529r_debugfs_reg_write(struct ad5529r_state *st, unsigned in= t reg, + unsigned int val) +{ + return regmap_write(ad5529r_get_regmap(st, reg), reg, val); +} + +static int ad5529r_detect_device(struct ad5529r_state *st) +{ + unsigned int product_id; + int ret; + + ret =3D regmap_read(st->regmap_8bit, AD5529R_REG_PRODUCT_ID_L, &product_i= d); + if (ret) + return ret; + + switch (product_id) { + case AD5529R_PRODUCT_ID_16BIT: + st->model_data =3D &ad5529r_16bit_model_data; + break; + case AD5529R_PRODUCT_ID_12BIT: + st->model_data =3D &ad5529r_12bit_model_data; + break; + default: + dev_err(&st->spi->dev, "Unknown product ID: 0x%02X\n", product_id); + return -ENODEV; + } + + dev_dbg(&st->spi->dev, "Detected %s variant (Product ID: 0x%02X)\n", + st->model_data->model_name, product_id); + + return 0; +} + +static int ad5529r_reset(struct ad5529r_state *st) +{ + struct reset_control *rst; + int ret; + + rst =3D devm_reset_control_get_optional_exclusive(&st->spi->dev, NULL); + if (IS_ERR(rst)) + return PTR_ERR(rst); + + if (rst) { + ret =3D reset_control_deassert(rst); + if (ret) + return ret; + } else { + ret =3D regmap_write(st->regmap_8bit, AD5529R_REG_INTERFACE_CONFIG_A, + AD5529R_INTERFACE_CONFIG_A_SW_RESET); + if (ret) + return ret; + } + + fsleep(AD5529R_RESET_DELAY_US); + + return regmap_write(st->regmap_8bit, AD5529R_REG_INTERFACE_CONFIG_A, + AD5529R_INTERFACE_CONFIG_A_DEFAULT); +} + +static int ad5529r_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct ad5529r_state *st =3D iio_priv(indio_dev); + unsigned int reg_addr; + unsigned int reg_val_h; + int ret; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + reg_addr =3D AD5529R_REG_DAC_INPUT_A(chan->channel); + ret =3D regmap_read(st->regmap_16bit, reg_addr, ®_val_h); + if (ret) + return ret; + + *val =3D reg_val_h; + + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + /* + * Using default 0-5V range: VOUTn =3D A =C3=97 D/2^N + B + * where A =3D 5V, B =3D 0V, D =3D digital code, N =3D resolution + * Scale =3D 5000mV / 2^resolution + */ + *val =3D 5000; + *val2 =3D st->model_data->resolution; + + return IIO_VAL_FRACTIONAL_LOG2; + default: + return -EINVAL; + } +} + +static int ad5529r_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long mask) +{ + struct ad5529r_state *st =3D iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_RAW: + if (val < 0 || val > GENMASK(st->model_data->resolution - 1, 0)) + return -EINVAL; + + return regmap_write(st->regmap_16bit, AD5529R_REG_DAC_INPUT_A(chan->chan= nel), val); + default: + return -EINVAL; + } +} + +static int ad5529r_reg_access(struct iio_dev *indio_dev, + unsigned int reg, + unsigned int writeval, + unsigned int *readval) +{ + struct ad5529r_state *st =3D iio_priv(indio_dev); + + if (!readval) + return ad5529r_debugfs_reg_write(st, reg, writeval); + + return ad5529r_debugfs_reg_read(st, reg, readval); +} + +static const struct iio_info ad5529r_info =3D { + .read_raw =3D ad5529r_read_raw, + .write_raw =3D ad5529r_write_raw, + .debugfs_reg_access =3D ad5529r_reg_access, +}; + +static int ad5529r_probe(struct spi_device *spi) +{ + struct device *dev =3D &spi->dev; + struct iio_dev *indio_dev; + struct ad5529r_state *st; + int ret; + + indio_dev =3D devm_iio_device_alloc(dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st =3D iio_priv(indio_dev); + + st->spi =3D spi; + + ret =3D devm_regulator_bulk_get_enable(dev, AD5529R_NUM_SUPPLIES, + ad5529r_supply_names); + if (ret) + return dev_err_probe(dev, ret, "Failed to get and enable regulators\n"); + + st->regmap_8bit =3D devm_regmap_init_spi(spi, &ad5529r_regmap_8bit_config= ); + if (IS_ERR(st->regmap_8bit)) + return dev_err_probe(dev, PTR_ERR(st->regmap_8bit), + "Failed to initialize 8-bit regmap\n"); + + st->regmap_16bit =3D devm_regmap_init_spi(spi, &ad5529r_regmap_16bit_conf= ig); + if (IS_ERR(st->regmap_16bit)) + return dev_err_probe(dev, PTR_ERR(st->regmap_16bit), + "Failed to initialize 16-bit regmap\n"); + + ret =3D ad5529r_reset(st); + if (ret) + return dev_err_probe(dev, ret, "Failed to reset device\n"); + + ret =3D ad5529r_detect_device(st); + if (ret) + return dev_err_probe(dev, ret, "Failed to detect device variant\n"); + + indio_dev->name =3D st->model_data->model_name; + indio_dev->info =3D &ad5529r_info; + indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->channels =3D st->model_data->channels; + indio_dev->num_channels =3D AD5529R_NUM_CHANNELS; + + return devm_iio_device_register(dev, indio_dev); +} + +static const struct of_device_id ad5529r_of_match[] =3D { + { .compatible =3D "adi,ad5529r" }, + { } +}; +MODULE_DEVICE_TABLE(of, ad5529r_of_match); + +static const struct spi_device_id ad5529r_id[] =3D { + { "ad5529r" }, + { } +}; +MODULE_DEVICE_TABLE(spi, ad5529r_id); + +static struct spi_driver ad5529r_driver =3D { + .driver =3D { + .name =3D "ad5529r", + .of_match_table =3D ad5529r_of_match, + }, + .probe =3D ad5529r_probe, + .id_table =3D ad5529r_id, +}; +module_spi_driver(ad5529r_driver); + +MODULE_AUTHOR("Janani Sunil "); +MODULE_DESCRIPTION("Analog Devices AD5529R 12/16-bit DAC driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Sat Jun 13 08:31:55 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by 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clxscore=1015 bulkscore=0 priorityscore=1501 phishscore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605080123 Add documentation for AD5529R high voltage, 16-channel 12/16 bit DAC Signed-off-by: Janani Sunil --- Documentation/iio/ad5529r.rst | 216 ++++++++++++++++++++++++++++++++++++++= ++++ Documentation/iio/index.rst | 1 + MAINTAINERS | 1 + 3 files changed, 218 insertions(+) diff --git a/Documentation/iio/ad5529r.rst b/Documentation/iio/ad5529r.rst new file mode 100644 index 000000000000..41fea1521790 --- /dev/null +++ b/Documentation/iio/ad5529r.rst @@ -0,0 +1,216 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +AD5529R driver +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Device driver for Analog Devices Inc. AD5529R 16-Channel 12/16-bit High Vo= ltage DAC. +The module name is ``ad5529r``. + +Supported devices +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +* `AD5529R `_ + +Description +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The AD5529R is a 16-channel, 12-bit or 16-bit, high voltage, buffered volt= age output +digital-to-analog converter (DAC) with an integrated precision reference. +The device operates from unipolar and bipolar supplies and is guaranteed +monotonic. It has built-in rail-to-rail output buffers that can source or +sink up to 25mA. + +Hardware Features +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +* 16 independent 12-bit or 16-bit DAC channels +* Independently programmable output ranges: + + - 0V to 5V (current driver default) + - 0V to 10V + - 0V to 20V + - 0V to 40V + - =C2=B15V + - =C2=B110V + - =C2=B115V + - =C2=B120V + +* 4.096V precision reference (12ppm/=C2=B0C maximum) +* Built-in function generation capabilities (hardware support) +* Output voltage and current monitoring (hardware support) +* Temperature monitoring with 8 on-chip sensors (hardware support) +* Over-temperature protection +* SPI interface with CRC error detection support + +Current Driver Implementation +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D + +The current driver provides basic DAC functionality with the following fea= tures: + +* Basic DAC output control for all 16 channels +* Scale attributes for voltage conversion (0-5V default range) +* SPI communication with regmap support +* Reset control framework support +* Automatic hardware variant detection (16-bit vs 12-bit) based on product= ID +* Debugfs register access for development + +SPI Configuration: + +* **Mode**: Supports SPI mode 0 and mode 3 (default: mode 0) +* **Frequency**: Up to 50 MHz (typically tested at lower frequencies) +* **Word Size**: 16-bit transactions + +.. note:: + The device default configuration uses address decrement mode (ADDR_ASCE= NSION=3D0) + for multi-byte SPI transactions. Therefore, all 16-bit register address= es are + incremented by 1 in the driver to access the last byte first, allowing = the + hardware to decrement and access the complete multi-byte register corre= ctly. + +IIO Attributes (Currently Implemented) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Basic DAC Control +----------------- + +For each of the 16 channels (0-15): + +**out_voltageY_raw** + Raw DAC code (12-bit: 0-4095, 16-bit: 0-65535) + + * Read: Returns the current DAC register value + * Write: Sets the DAC output code + +**out_voltageY_scale** + Scale factor for voltage conversion (millivolts per LSB) + + Based on the formula: VOUTn =3D A =C3=97 D/2^N + B, where A=3D5V, B=3D0V= , N=3Dresolution + + * 16-bit: 0.076294 mV/LSB (5V =C3=B7 2^16 =3D 5V =C3=B7 65536 =3D 0.0762= 94mV) + * 12-bit: 1.220703 mV/LSB (5V =C3=B7 2^12 =3D 5V =C3=B7 4096 =3D 1.22070= 3mV) + * Read-only attribute + +Debug Interface +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +**Register Access** + +The driver provides debugfs register access for debugging and development: + +``/sys/kernel/debug/iio/iio:deviceX/direct_reg_access`` + Direct register read/write access. Format: + + * Read: ``echo > direct_reg_access; cat direct_reg_ac= cess`` + * Write: ``echo > direct_reg_access`` + +Usage examples +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Basic DAC Output Control +------------------------ + +.. code-block:: bash + + # Set channel 0 to mid-scale (approximately 2.5V with 0V to 5V range) + echo "32768" > /sys/bus/iio/devices/iio:device0/out_voltage0_raw + + # Set channel 15 to full scale + echo "65535" > /sys/bus/iio/devices/iio:device0/out_voltage15_raw + + # Read current value from channel 5 + cat /sys/bus/iio/devices/iio:device0/out_voltage5_raw + +Scale Attributes +---------------- + +.. code-block:: bash + + # Read scale factor (millivolts per LSB) + cat /sys/bus/iio/devices/iio:device0/out_voltage0_scale + # Output: 0.076294 (for 16-bit) or 1.220703 (for 12-bit) + + # Convert raw to voltage: voltage_mv =3D raw * scale + # Formula: VOUTn =3D A =C3=97 D/2^N + B where A=3D5V, B=3D0V + +Register Access for Development +------------------------------- + +.. code-block:: bash + + # Navigate to debugfs directory + cd /sys/kernel/debug/iio/iio:device0/ + + # Read device product ID (register 0x04) + echo 4 > direct_reg_access + cat direct_reg_access + + # Write to a 16-bit configuration register (example: LDAC_HW_SW regist= er 0x19) + echo "0x019 0xAA11" > direct_reg_access + cat direct_reg_access + # Output: 0xAA11 + + # Write to DAC channel registers (16-bit values) + echo "0x149 32768" > direct_reg_access # DAC channel 0 mid-scale + echo "0x14B 65535" > direct_reg_access # DAC channel 1 full-scale + + # Read back DAC register values + echo 0x149 > direct_reg_access && cat direct_reg_access # Read channe= l 0 + echo 0x14B > direct_reg_access && cat direct_reg_access # Read channe= l 1 + +.. note:: + For 16-bit registers, use hexadecimal format for addresses (0x019, 0x14= 9, etc.). + Values can be decimal (32768) or hexadecimal (0xAA11). Register address= es shown + include the +1 offset required for decrement mode operation. + +Device Tree Configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + +Basic configuration example: + +.. code-block:: devicetree + + &spi0 { + status =3D "okay"; + + ad5529r@0 { + compatible =3D "adi,ad5529r"; + reg =3D <0>; + spi-max-frequency =3D <25000000>; + + vdd-supply =3D <&vdd_regulator>; + avdd-supply =3D <&avdd_regulator>; + hvdd-supply =3D <&hvdd_regulator>; + hvss-supply =3D <&hvss_regulator>; + + reset-gpios =3D <&gpio0 87 GPIO_ACTIVE_LOW>; + }; + }; + +For complete device tree binding documentation, see: +``Documentation/devicetree/bindings/iio/dac/adi,ad5529r.yaml`` + +Driver Architecture +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The driver is structured as follows: + +* **Core**: Basic SPI communication and device initialization +* **IIO Interface**: Standard IIO DAC channel interface with scale attribu= tes +* **Dual Regmap**: Uses standard regmap-spi for both 8-bit and 16-bit regi= ster access +* **Reset Framework**: Reset control support + +Development Notes +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +* The driver uses standard regmap-spi for both 8-bit and 16-bit register a= ccess +* SPI mode 0 (CPOL=3D0, CPHA=3D0) is typically used +* Reset control framework support for device initialization +* Register addresses are incremented by 1 for 16-bit registers due to decr= ement mode addressing +* Scale attributes provide voltage conversion for 0-5V range +* Automatic regmap selection based on register address (=E2=89=A40x13: 8-b= it, >0x13: 16-bit) + +References +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +* AD5529R Datasheet: https://www.analog.com/media/en/technical-documentati= on/data-sheets/ad5529r.pdf +* Linux IIO Subsystem: https://www.kernel.org/doc/html/latest/driver-api/i= io/index.html diff --git a/Documentation/iio/index.rst b/Documentation/iio/index.rst index 007e0a1fcc5a..27f2ab41f05e 100644 --- a/Documentation/iio/index.rst +++ b/Documentation/iio/index.rst @@ -25,6 +25,7 @@ Industrial I/O Kernel Drivers ad4062 ad4691 ad4695 + ad5529r ad7191 ad7380 ad7606 diff --git a/MAINTAINERS b/MAINTAINERS index 143714e27d51..41f42eb1adf2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1513,6 +1513,7 @@ L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/dac/adi,ad5529r.yaml +F: Documentation/iio/ad5529r.rst F: drivers/iio/dac/ad5529r.c =20 ANALOG DEVICES INC AD5706R DRIVER --=20 2.43.0