From nobody Sat May 30 12:37:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1785D358D00; Fri, 8 May 2026 07:36:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778225818; cv=none; b=FQ6pQvGMteLbgiQUnAmjixjXcbWpwGjLHgO/XNmL/rbwLRKU8ShLSJ+VBMDpWhFcdfe/k0hhehhau3vGv9R5fcPdNzUy2BOfwbaaTcSMLOg0KIc7k1UwkeujOSsnqMMZWIU8dvjCFk7MGVRC1FxQBuposZ59NgzKbjynvA5Ua20= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778225818; c=relaxed/simple; bh=5P3oB3t/H+M/VWPcldvUPMKT0Ow+fk7RIqkl6O2cI+0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ukcjdOgIr6vx+FJhqOH/E/VQHQlKzyFQYMeVTxKyYFBoKbzdSvDuPrGNoGm2pj7dX21MaEYoc3bNmcgZyx9MSkhO0ufN782upY2+LOIrqZOwpV+jLRDKJG5Fmq8MguOLX2EZJz0pCU8TuNHOfESLHyjExsbRh4f9b9V6LzJ2Qng= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XACC5UYV; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XACC5UYV" Received: by smtp.kernel.org (Postfix) with ESMTPS id C3DE5C2BCB4; Fri, 8 May 2026 07:36:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778225817; bh=5P3oB3t/H+M/VWPcldvUPMKT0Ow+fk7RIqkl6O2cI+0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=XACC5UYVvyKFUulCycU3Xkxd9WIMzOW58lMm1E+C/YcMTgBi7IcvSQ3K45jL/6KuB ihT9Nz8+sMLW0HxY9pC1bfSMu1YtSNh8iFCMAvrELKbN4jr8Ft+tHh2rF5FPXp5zQu OeRH97st8/PLPZcd2nHO9JN8etQiVCcFKjZNsFKd/qPXvWgbQsuoUDT5qee2WPG7IR HcXbKZhQTSYC37BBQ9buX22G8WRQUgiFKCFgPWSEL3BE+h5ox0VnGw1wunLpAJS0b3 t/90ZISWWr1y3Bjlp6QyG0hyc/wHaEyA8rXTRwhhbhp1t30S2W4F+JWAUQJpqNV90L NyY4PG2h9Vxzg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4515CD3436; Fri, 8 May 2026 07:36:57 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Fri, 08 May 2026 07:36:54 +0000 Subject: [PATCH 1/3] irqchip/meson-gpio: fix incorrect register address Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260508-a9-gpio-irqchip-v1-1-9dc5f3e022e0@amlogic.com> References: <20260508-a9-gpio-irqchip-v1-0-9dc5f3e022e0@amlogic.com> In-Reply-To: <20260508-a9-gpio-irqchip-v1-0-9dc5f3e022e0@amlogic.com> To: Thomas Gleixner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, Xianwei Zhao X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1778225816; l=1007; i=xianwei.zhao@amlogic.com; s=20251216; h=from:subject:message-id; bh=M9zM13CLYOdG+lkNB/tDdOWTKQ5cZ8tHYqZIsNYUo+4=; b=qZctPN2tSMJSPBgkkvRhlV2W+Ntn38soTuIOLXMPw7l1tQGc2KIYT5X8SsQjTaTjoAzgCj9i+ 3tfomMZgj8gASyXaPOMb3Rs1X/ws7vR2ku7AfIfYNw9mKkB/EB2f9SQ X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=dWwxtWCxC6FHRurOmxEtr34SuBYU+WJowV/ZmRJ7H+k= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20251216 with auth_id=578 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao When set gpio irq type(level and single-edge) for S4, register address is REG_EDGE_POL, not both-edge trigger register. This patch fix it. Fixes: bbd6fcc76b39 ("irqchip: Add support for Amlogic A4 and A5 SoCs") Signed-off-by: Xianwei Zhao --- drivers/irqchip/irq-meson-gpio.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-g= pio.c index f722e9c57e2e..74a376ef452e 100644 --- a/drivers/irqchip/irq-meson-gpio.c +++ b/drivers/irqchip/irq-meson-gpio.c @@ -415,8 +415,7 @@ static int meson_s4_gpio_irq_set_type(struct meson_gpio= _irq_controller *ctl, if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) val |=3D BIT(ctl->params->edge_single_offset + idx); =20 - meson_gpio_irq_update_bits(ctl, params->edge_pol_reg, - BIT(idx) | BIT(12 + idx), val); + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, BIT(idx) | BIT(12 + idx), v= al); return 0; }; =20 --=20 2.52.0 From nobody Sat May 30 12:37:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 178E8372662; Fri, 8 May 2026 07:36:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778225818; cv=none; b=VtJDl5sy+adA6xkxRmVwrARzKlp+w6jP2Fho8LJ3jRHF2RgckK7mW+QxwxfHsLUMHY614BtwuF9bHDPRaNIGii/D+1oAwrzwqewzC1WwkzZoB604qPamA/6MiXEtm4MYXZqAZdMYdmgkZ0kX2h1CHE/cQSkLIvtINICqiQATTQI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778225818; c=relaxed/simple; bh=KzRKiBbR6C7gp1fPdQcsXZjAFHQM3qTiU5u+nEQqa/c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Ivm3BY6HM7KydCCazWqu75zl235wp9tiPzT0qoOUz0my5PrgLmJkuudjAvfpFy5lPOOP7ME0if6unog1qYHP7pqCDu/0O7v83gY9rn9zyR8rPqPQ5aBeeI5yl/tYS2o2CyKYi8MOkKADrZpdlunEEKqs4T68s7Xforh4Uvpq3dU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=UkDeS5oC; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UkDeS5oC" Received: by smtp.kernel.org (Postfix) with ESMTPS id DA2F6C2BCF6; Fri, 8 May 2026 07:36:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778225817; bh=KzRKiBbR6C7gp1fPdQcsXZjAFHQM3qTiU5u+nEQqa/c=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=UkDeS5oCrNrzxKQew+G53HGTxB1MYTx6Co7IWuM1XckGXng9KljcoUY9S/RSCW/tB j0jq8sEbjzj07FjhVVXSMIwwMARkBn4uKKiKlu7E+TMyEIcbOa1w8mAwNQam2YUkre ZqGtXWltExH/LLOYNnpJpj3drEvn5XQD9onjUnVKxeMwlbDXfElz0j9s8WeyAZ+btW IQn/D597gzVsfopuCPhQ2a1ZlH+is02YtVWTmgKBks16RoOVpFIf0IFrfPXrfdLteE TwNQWdlwlxZqF0/+o1mYK1e4nS/zGQgI2FSu1ISEzaa6R/bzDNTqggy406akahzia2 m8NIJjjdyGS4g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5573CD37AA; Fri, 8 May 2026 07:36:57 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Fri, 08 May 2026 07:36:55 +0000 Subject: [PATCH 2/3] dt-bindings: interrupt-controller: Add support for Amlogic A9 SoCs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260508-a9-gpio-irqchip-v1-2-9dc5f3e022e0@amlogic.com> References: <20260508-a9-gpio-irqchip-v1-0-9dc5f3e022e0@amlogic.com> In-Reply-To: <20260508-a9-gpio-irqchip-v1-0-9dc5f3e022e0@amlogic.com> To: Thomas Gleixner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, Xianwei Zhao X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1778225816; l=1795; i=xianwei.zhao@amlogic.com; s=20251216; h=from:subject:message-id; bh=6Ljc1slqURABvNOkxflZQUxRIhozTfJrbGsFoDMyXeA=; b=FGj3PF7NeRbke8xYI6Q3J8mraEC49BIYBCUw3ET5JId6vNWy/5ET7h6d/GXrJJR3ROg1CM244 Ix0Lkab3dU4Au7D4014LTpdOow2YnWClYCdjc0VvCspyBWm2aqbmrT7 X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=dWwxtWCxC6FHRurOmxEtr34SuBYU+WJowV/ZmRJ7H+k= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20251216 with auth_id=578 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Update dt-binding document for GPIO interrupt controller of Amlogic A9 SoCs. Signed-off-by: Xianwei Zhao Acked-by: Conor Dooley --- .../amlogic,meson-gpio-intc.yaml | 21 +++++++++++++++++= ---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic= ,meson-gpio-intc.yaml b/Documentation/devicetree/bindings/interrupt-control= ler/amlogic,meson-gpio-intc.yaml index d0fad930de9d..d26671913e89 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-= gpio-intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-= gpio-intc.yaml @@ -38,6 +38,8 @@ properties: - amlogic,a4-gpio-intc - amlogic,a4-gpio-ao-intc - amlogic,a5-gpio-intc + - amlogic,a9-gpio-intc + - amlogic,a9-gpio-ao-intc - amlogic,c3-gpio-intc - amlogic,s6-gpio-intc - amlogic,s7-gpio-intc @@ -56,7 +58,7 @@ properties: amlogic,channel-interrupts: description: Array with the upstream hwirq numbers minItems: 2 - maxItems: 12 + maxItems: 20 $ref: /schemas/types.yaml#/definitions/uint32-array =20 required: @@ -76,9 +78,20 @@ then: amlogic,channel-interrupts: maxItems: 2 else: - properties: - amlogic,channel-interrupts: - minItems: 8 + if: + properties: + compatible: + contains: + const: amlogic,a9-gpio-ao-intc + then: + properties: + amlogic,channel-interrupts: + minItems: 20 + else: + properties: + amlogic,channel-interrupts: + minItems: 8 + maxItems: 12 =20 additionalProperties: false =20 --=20 2.52.0 From nobody Sat May 30 12:37:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13EB92F8E81; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VulP8Exm" Received: by smtp.kernel.org (Postfix) with ESMTPS id E3513C2BCF4; Fri, 8 May 2026 07:36:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778225817; bh=6orjSlY4lQ5CFkC+hhWVFf1lnIC3pYaTmYzO8tYxwmY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=VulP8Exm/qXA4VrKShU5O687SxxYmxF41/41De5w10oEgby2sQ3x1nrVkCQV7jWWo d8HAlsTnpZLjmb3oeXSwL0JuA7Ym/O9f0rpTzIAzbzfLgo0C+LDDcyg9uXphRdGjd0 vvPlAsQb7I0++yieL7afAS0WRz/igNcSnlP83NBxG357u3XfqqwbmhNLeIwlbjHkEA PHb7+2DDLp28QV+NpgQjJxodT1q2m5EmuW9ZL1I9gDasIbxhNwz8evkERSr9jehYzD RhIKbVxlmTzRCOhRFgCLVQxdONf5JPRlu0JWYCY0GwzxUa19uFyJUdxF7ltcFp5gUf R2L0ujltuqcrg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6DC5CD342F; Fri, 8 May 2026 07:36:57 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Fri, 08 May 2026 07:36:56 +0000 Subject: [PATCH 3/3] irqchip/meson-gpio: Add support for Amlogic A9 SoCs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260508-a9-gpio-irqchip-v1-3-9dc5f3e022e0@amlogic.com> References: <20260508-a9-gpio-irqchip-v1-0-9dc5f3e022e0@amlogic.com> In-Reply-To: <20260508-a9-gpio-irqchip-v1-0-9dc5f3e022e0@amlogic.com> To: Thomas Gleixner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, Xianwei Zhao X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1778225816; l=5139; i=xianwei.zhao@amlogic.com; s=20251216; h=from:subject:message-id; bh=nAfHIz6N7m4oMjB9PiZJjp678ZGWzDBR5xK3MB5dJRI=; b=LQqjSXVX5QTASAePP+dTc5VePmsxGw865S8yEFVsPZYttboDVp/QTlPgVoCGnoRWa2qnYkkxQ DSMvkv5e2qJAdEt0U+nTcK7fleZv3bDwgY8ic4O05kPcarkQYcRghC/ X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=dWwxtWCxC6FHRurOmxEtr34SuBYU+WJowV/ZmRJ7H+k= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20251216 with auth_id=578 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao The Amlogic A9 SoCs support GPIO interrupt lines: A9 IRQ Number: - 95:86 10 pins on bank Y - 85:84 2 pins on bank CC - 83:64 20 pins on bank A - 63:48 16 pins on bank Z - 47:30 18 pins on bank X - 29:22 8 pins on bank H - 21:14 8 pins on bank M - 13:0 14 pins on bank B A9 AO IRQ Number: - 38 1 pins on bank TESTN - 37:31 7 pins on bank C - 30:13 18 pins on bank D - 12:0 13 pins on bank AO Signed-off-by: Xianwei Zhao --- drivers/irqchip/irq-meson-gpio.c | 75 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 75 insertions(+) diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-g= pio.c index 74a376ef452e..f68476b2c538 100644 --- a/drivers/irqchip/irq-meson-gpio.c +++ b/drivers/irqchip/irq-meson-gpio.c @@ -27,6 +27,10 @@ /* use for A1 like chips */ #define REG_PIN_A1_SEL 0x04 =20 +/* use for A9 like chips */ +#define REG_A9_AO_POL 0x00 +#define REG_A9_AO_EDGE 0x30 + /* * Note: The S905X3 datasheet reports that BOTH_EDGE is controlled by * bits 24 to 31. Tests on the actual HW show that these bits are @@ -53,6 +57,8 @@ static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_i= rq_controller *ctl, static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl); static int meson8_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl, unsigned int type, u32 *channel_hwirq); +static int meson_a9_ao_gpio_irq_set_type(struct meson_gpio_irq_controller = *ctl, + unsigned int type, u32 *channel_hwirq); static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ct= l, unsigned int type, u32 *channel_hwirq); =20 @@ -116,6 +122,18 @@ struct meson_gpio_irq_params { .pin_sel_mask =3D 0xff, \ .nr_channels =3D 2, \ =20 +#define INIT_MESON_A9_AO_COMMON_DATA(irqs) \ + INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \ + meson_a1_gpio_irq_sel_pin, \ + meson_a9_ao_gpio_irq_set_type) \ + .support_edge_both =3D true, \ + .edge_both_offset =3D 0, \ + .edge_single_offset =3D 0, \ + .edge_pol_reg =3D 0x2c, \ + .pol_low_offset =3D 0, \ + .pin_sel_mask =3D 0xff, \ + .nr_channels =3D 20, \ + #define INIT_MESON_S4_COMMON_DATA(irqs) \ INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \ meson_a1_gpio_irq_sel_pin, \ @@ -170,6 +188,14 @@ static const struct meson_gpio_irq_params a5_params = =3D { INIT_MESON_S4_COMMON_DATA(99) }; =20 +static const struct meson_gpio_irq_params a9_params =3D { + INIT_MESON_S4_COMMON_DATA(96) +}; + +static const struct meson_gpio_irq_params a9_ao_params =3D { + INIT_MESON_A9_AO_COMMON_DATA(39) +}; + static const struct meson_gpio_irq_params s4_params =3D { INIT_MESON_S4_COMMON_DATA(82) }; @@ -203,6 +229,8 @@ static const struct of_device_id meson_irq_gpio_matches= [] __maybe_unused =3D { { .compatible =3D "amlogic,a4-gpio-ao-intc", .data =3D &a4_ao_params }, { .compatible =3D "amlogic,a4-gpio-intc", .data =3D &a4_params }, { .compatible =3D "amlogic,a5-gpio-intc", .data =3D &a5_params }, + { .compatible =3D "amlogic,a9-gpio-ao-intc", .data =3D &a9_ao_params }, + { .compatible =3D "amlogic,a9-gpio-intc", .data =3D &a9_params }, { .compatible =3D "amlogic,s6-gpio-intc", .data =3D &s6_params }, { .compatible =3D "amlogic,s7-gpio-intc", .data =3D &s7_params }, { .compatible =3D "amlogic,s7d-gpio-intc", .data =3D &s7_params }, @@ -375,6 +403,53 @@ static int meson8_gpio_irq_set_type(struct meson_gpio_= irq_controller *ctl, return 0; } =20 +/* + * gpio irq relative registers for a9_ao + * -PADCTRL_GPIO_IRQ_CTRL0 + * bit[31]: enable/disable all the irq lines + * bit[0-19]: polarity trigger + * + * -PADCTRL_GPIO_IRQ_CTRL[X] + * bit[0-5]: 6 bits to choose gpio source for irq line 2*[X] - 2 + * bit[16-21]:6 bits to choose gpio source for irq line 2*[X] - 1 + * where X =3D 1-10 + * + * -PADCTRL_GPIO_IRQ_CTRL[11] + * bit[0-19]: both edge trigger + * + * -PADCTRL_GPIO_IRQ_CTRL[12] + * bit[0-19]: single edge trigger + */ +static int meson_a9_ao_gpio_irq_set_type(struct meson_gpio_irq_controller = *ctl, + unsigned int type, u32 *channel_hwirq) +{ + const struct meson_gpio_irq_params *params =3D ctl->params; + unsigned int idx; + u32 val =3D 0; + + idx =3D meson_gpio_irq_get_channel_idx(ctl, channel_hwirq); + + type &=3D IRQ_TYPE_SENSE_MASK; + + meson_gpio_irq_update_bits(ctl, params->edge_pol_reg, BIT(idx), 0); + + if (type =3D=3D IRQ_TYPE_EDGE_BOTH) { + val =3D BIT(ctl->params->edge_both_offset + idx); + meson_gpio_irq_update_bits(ctl, params->edge_pol_reg, val, val); + return 0; + } + + if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) + val =3D BIT(idx); + meson_gpio_irq_update_bits(ctl, REG_A9_AO_POL, BIT(idx), val); + + val =3D 0; + if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) + val =3D BIT(idx); + meson_gpio_irq_update_bits(ctl, REG_A9_AO_EDGE, BIT(idx), val); + + return 0; +}; /* * gpio irq relative registers for s4 * -PADCTRL_GPIO_IRQ_CTRL0 --=20 2.52.0