From nobody Sat Jun 13 13:33:12 2026 Received: from out30-100.freemail.mail.aliyun.com (out30-100.freemail.mail.aliyun.com [115.124.30.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 046873EBF2D; Thu, 7 May 2026 11:37:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.100 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778153845; cv=none; b=blw/pyIHeU9l5NVosSUZu+EGYxgRTHx88zoom6jd8tHvu73phM+MWuoK2eKgdm+EnGU23HLasecTuQv8oyIUsvTnqGc0olbtYO0LcZugjRpr3u3ZOp2DWhuVtjEYa4lMkCaPxwDHAp4KHjwU4JRrqgUyhaLoU8dtJh7AoBAD3uc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778153845; c=relaxed/simple; bh=YyzgnuFA90twudD6q82NIg+uJNptTvPRS3eG8ZuX5oY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=JZVley/CBvFxrPE38fyiD9NMuX6HCdO82kpSeGlMB3UCPejc6U/vknsxkE0btQIBDQRnubGgLWxfOTDwOHYJmYaEHvxwc1zNXyFXsNXm2yESRQ0k69ciWjlnESlad2UCdZHgv2rb2mA8Ov3rJFq7qwpbSCfRtjJXdYCIZDtuiLo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=OOYcLXef; arc=none smtp.client-ip=115.124.30.100 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="OOYcLXef" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1778153834; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=oSq7eCXtjOsx2ohWmDqI2E1f3GZbwF4QYb8Qk+5aDsU=; b=OOYcLXefotFvgxDw1OhFy2TIVLyKybDybpyyq0YKe7DYd2hE9HlUl36oAjgJhRW69/YNCmyQcE1wjC1qsiWAP4cv7d3wjmBOeZ50Zh+dTsc09bOPVIJ/SboLsAvxvs4rSgvTD98wdRNM8AzSKbfioxzGDvuFId3UOFi3UQ30HhY= X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R191e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam033045133197;MF=fangyu.yu@linux.alibaba.com;NM=1;PH=DS;RN=24;SR=0;TI=SMTPD_---0X2UVF-A_1778153831; Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0X2UVF-A_1778153831 cluster:ay36) by smtp.aliyun-inc.com; Thu, 07 May 2026 19:37:12 +0800 From: fangyu.yu@linux.alibaba.com To: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, tjeznach@rivosinc.com, jgg@ziepe.ca, kevin.tian@intel.com, baolu.lu@linux.intel.com, vasant.hegde@amd.com, anup@brainfault.org, atish.patra@linux.dev, skhawaja@google.com, jgg@nvidia.com Cc: guoren@kernel.org, andrew.jones@oss.qualcomm.com, kvm@vger.kernel.org, iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Fangyu Yu Subject: [RFC PATCH v2 01/10] iommupt: Add RISC-V Second-stage (iohgatp) page table support Date: Thu, 7 May 2026 19:36:57 +0800 Message-Id: <20260507113706.11400-2-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com> References: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fangyu Yu Add support for Sv39x4/Sv48x4/Sv57x4 Second-stage page tables used by the RISC-V IOMMU iohgatp register. The x4 root page table is 16 KiB instead of the usual 4 KiB, covering 2 extra GPA bits (hw_max_vasz_lg2 =3D 41/50/59). Signed-off-by: Fangyu Yu --- drivers/iommu/generic_pt/fmt/riscv.h | 61 +++++++++++++++++++++++++--- include/linux/generic_pt/common.h | 5 ++- include/linux/generic_pt/iommu.h | 17 +++++++- 3 files changed, 76 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/generic_pt/fmt/riscv.h b/drivers/iommu/generic_p= t/fmt/riscv.h index a7fef6266a36..777887335696 100644 --- a/drivers/iommu/generic_pt/fmt/riscv.h +++ b/drivers/iommu/generic_pt/fmt/riscv.h @@ -37,7 +37,16 @@ enum { PT_MAX_OUTPUT_ADDRESS_LG2 =3D 34, PT_MAX_TOP_LEVEL =3D 1, #else - PT_MAX_VA_ADDRESS_LG2 =3D 57, + /* + * PT_MAX_VA_ADDRESS_LG2 is the upper bound accepted by the generic + * pt_iommu_init() range check. It must cover both first-stage and + * second-stage (G-stage) modes: + * + * First-stage (fsc/iosatp): Sv39=3D39, Sv48=3D48, Sv57=3D57 + * Second-stage (iohgatp): Sv39x4=3D41, Sv48x4=3D50, Sv57x4=3D59 + * + */ + PT_MAX_VA_ADDRESS_LG2 =3D 59, PT_MAX_OUTPUT_ADDRESS_LG2 =3D 56, PT_MAX_TOP_LEVEL =3D 4, #endif @@ -124,6 +133,14 @@ riscvpt_entry_num_contig_lg2(const struct pt_state *pt= s) =20 static inline unsigned int riscvpt_num_items_lg2(const struct pt_state *pt= s) { + /* + * Second-stage (iohgatp) root page tables have 4x the usual number of + * entries (2048 =3D 2^11 instead of 512 =3D 2^9) to cover the 2 extra GPA + * bits in Sv39x4/Sv48x4/Sv57x4. Only the root (top) level is + * enlarged; all other levels remain at the standard 9-bit index width. + */ + if (pts_feature(pts, PT_FEAT_RISCV_S2) && pts->level =3D=3D pts->range->t= op_level) + return PT_TABLEMEM_LG2SZ - ilog2(sizeof(u64)) + 2; return PT_TABLEMEM_LG2SZ - ilog2(sizeof(u64)); } #define pt_num_items_lg2 riscvpt_num_items_lg2 @@ -254,6 +271,7 @@ riscvpt_iommu_fmt_init(struct pt_iommu_riscv_64 *iommu_= table, struct pt_riscv *table =3D &iommu_table->riscv_64pt; =20 switch (cfg->common.hw_max_vasz_lg2) { + /* First-stage (fsc/iosatp): Sv39 / Sv48 / Sv57 */ case 39: pt_top_set_level(&table->common, 2); break; @@ -263,6 +281,19 @@ riscvpt_iommu_fmt_init(struct pt_iommu_riscv_64 *iommu= _table, case 57: pt_top_set_level(&table->common, 4); break; + /* + * Second-stage (iohgatp): Sv39x4 / Sv48x4 / Sv57x4. + * The top level is the same as for the first-stage counterpart. + */ + case 41: + pt_top_set_level(&table->common, 2); + break; + case 50: + pt_top_set_level(&table->common, 3); + break; + case 59: + pt_top_set_level(&table->common, 4); + break; default: return -EINVAL; } @@ -283,10 +314,17 @@ riscvpt_iommu_fmt_hw_info(struct pt_iommu_riscv_64 *t= able, PT_WARN_ON(top_phys & ~PT_TOP_PHYS_MASK); =20 /* - * See Table 3. Encodings of iosatp.MODE field" for DC.tx.SXL =3D 0: - * 8 =3D Sv39 =3D top level 2 - * 9 =3D Sv38 =3D top level 3 - * 10 =3D Sv57 =3D top level 4 + * Both first-stage (fsc/iosatp) and second-stage (iohgatp) share the + * same MODE numeric values for a given top level: + * top_level 2 -> MODE 8 (Sv39 / Sv39x4) + * top_level 3 -> MODE 9 (Sv48 / Sv48x4) + * top_level 4 -> MODE 10 (Sv57 / Sv57x4) + * + * The union members fsc_iosatp_mode and iohgatp_mode occupy the same + * byte; the caller selects the appropriate name based on domain type. + * + * See "Table 3. Encodings of iosatp.MODE field" (DC.tc.SXL =3D 0) and + * "Table 2. Encoding of iohgatp.MODE field" in the RISC-V IOMMU spec. */ info->fsc_iosatp_mode =3D top_range->top_level + 6; } @@ -294,6 +332,7 @@ riscvpt_iommu_fmt_hw_info(struct pt_iommu_riscv_64 *tab= le, =20 #if defined(GENERIC_PT_KUNIT) static const struct pt_iommu_riscv_64_cfg riscv_64_kunit_fmt_cfgs[] =3D { + /* First-stage (fsc/iosatp): Sv39 / Sv48 / Sv57 */ [0] =3D { .common.features =3D BIT(PT_FEAT_RISCV_SVNAPOT_64K), .common.hw_max_oasz_lg2 =3D 56, .common.hw_max_vasz_lg2 =3D 39 }, @@ -303,6 +342,18 @@ static const struct pt_iommu_riscv_64_cfg riscv_64_kun= it_fmt_cfgs[] =3D { [2] =3D { .common.features =3D BIT(PT_FEAT_RISCV_SVNAPOT_64K), .common.hw_max_oasz_lg2 =3D 56, .common.hw_max_vasz_lg2 =3D 57 }, + /* + * Second-stage (iohgatp): Sv39x4 / Sv48x4 / Sv57x4. + */ + [3] =3D { .common.features =3D BIT(PT_FEAT_RISCV_SVNAPOT_64K), + .common.hw_max_oasz_lg2 =3D 56, + .common.hw_max_vasz_lg2 =3D 41 }, + [4] =3D { .common.features =3D 0, + .common.hw_max_oasz_lg2 =3D 56, + .common.hw_max_vasz_lg2 =3D 50 }, + [5] =3D { .common.features =3D BIT(PT_FEAT_RISCV_SVNAPOT_64K), + .common.hw_max_oasz_lg2 =3D 56, + .common.hw_max_vasz_lg2 =3D 59 }, }; #define kunit_fmt_cfgs riscv_64_kunit_fmt_cfgs enum { diff --git a/include/linux/generic_pt/common.h b/include/linux/generic_pt/c= ommon.h index fc5d0b5edadc..59448125159e 100644 --- a/include/linux/generic_pt/common.h +++ b/include/linux/generic_pt/common.h @@ -188,7 +188,10 @@ enum { * Support the 64k contiguous page size following the Svnapot extension. */ PT_FEAT_RISCV_SVNAPOT_64K =3D PT_FEAT_FMT_START, - + /* + * Using second-stage / iohgatp address translation. + */ + PT_FEAT_RISCV_S2, }; =20 struct pt_x86_64 { diff --git a/include/linux/generic_pt/iommu.h b/include/linux/generic_pt/io= mmu.h index dd0edd02a48a..f27d229ff318 100644 --- a/include/linux/generic_pt/iommu.h +++ b/include/linux/generic_pt/iommu.h @@ -328,7 +328,22 @@ struct pt_iommu_riscv_64_cfg { =20 struct pt_iommu_riscv_64_hw_info { u64 ppn; - u8 fsc_iosatp_mode; + union { + /* + * First-stage (fsc/iosatp) MODE encoding: + * 8 =3D Sv39, 9 =3D Sv48, 10 =3D Sv57 + * Used to program DC.fsc.iosatp.MODE. + */ + u8 fsc_iosatp_mode; + /* + * Second-stage (iohgatp) MODE encoding: + * 8 =3D Sv39x4, 9 =3D Sv48x4, 10 =3D Sv57x4 + * Used to program DC.iohgatp.MODE. + * The numeric values are identical to fsc_iosatp_mode; + * the caller selects the interpretation based on domain type. + */ + u8 iohgatp_mode; + }; }; =20 IOMMU_FORMAT(riscv_64, riscv_64pt); --=20 2.50.1 From nobody Sat Jun 13 13:33:12 2026 Received: from out30-131.freemail.mail.aliyun.com (out30-131.freemail.mail.aliyun.com [115.124.30.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23EC719539F; Thu, 7 May 2026 11:37:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778153841; cv=none; b=GL7zC+qBbx+gabnDnmD7sRPqFu29aCa1+iOH/3WssggG9KUOq+57OStX35bu5rxqAMNNWGY41VaUJtbz9qmJ5wojRXV5CaYJPEAA0iGWMUvdx8pNiVRxP4aKLRPJPLlbUOlGKYtJgzgKgNu3O4sAKvWOEB55GdGNtqTwT3U/9Wg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778153841; c=relaxed/simple; bh=t85LW6cpp4slZIdvI389Dyz9FRcdOHaqr2UsCHIUy+s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NXD8c3dnsV9XsDsIPg/CIgrmv95/cxLgrouNl+dMLGrSSZCnXq8mgL+Ez44/tk7CzIwQUhjfNWQIfO5s5JWyaznKJLJDylES8wFeJwf66TOQSt9OKACQ3OfWeNatFl+O9gZED94ZOSMjqMMuotjDfR+q28q/WNAUgpv9Alrh+fM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=DvJJpxoZ; arc=none smtp.client-ip=115.124.30.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="DvJJpxoZ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1778153836; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=e4f5X+R7i8qSI7NXq8cp591M8sz5EYh7qAQjjFxZJsY=; b=DvJJpxoZq1uJsDuQ+OvDbX0JyWSrUJDekFQVqonvnHcoyVanfXsiHbPquSAJlZGb+Yuju8q8NBqIeJ6mLLS6IMZAiP8/kBhJo+dhu8OYvKMwynluPrGgGc6h0Exg1U4qNbY9Soh2BDY8YY/cjiQEup3XecHl2MaEvPWvujNlDG4= X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R111e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam033045098064;MF=fangyu.yu@linux.alibaba.com;NM=1;PH=DS;RN=24;SR=0;TI=SMTPD_---0X2UVF-c_1778153833; Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0X2UVF-c_1778153833 cluster:ay36) by smtp.aliyun-inc.com; Thu, 07 May 2026 19:37:14 +0800 From: fangyu.yu@linux.alibaba.com To: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, tjeznach@rivosinc.com, jgg@ziepe.ca, kevin.tian@intel.com, baolu.lu@linux.intel.com, vasant.hegde@amd.com, anup@brainfault.org, atish.patra@linux.dev, skhawaja@google.com, jgg@nvidia.com Cc: guoren@kernel.org, andrew.jones@oss.qualcomm.com, kvm@vger.kernel.org, iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Fangyu Yu Subject: [RFC PATCH v2 02/10] iommupt: Add RISC-V dirty tracking PTE ops Date: Thu, 7 May 2026 19:36:58 +0800 Message-Id: <20260507113706.11400-3-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com> References: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fangyu Yu Implement the three dirty-tracking hooks required by the generic page table framework for the RISC-V format: pt_entry_is_write_dirty(): Check the D bit (bit 7) in the PTE. pt_entry_make_write_clean(): Clear the D bit across the full contiguous range. pt_entry_make_write_dirty(): Atomically set D via try_cmpxchg64() on a single PTE. Signed-off-by: Fangyu Yu --- drivers/iommu/generic_pt/fmt/riscv.h | 43 ++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/drivers/iommu/generic_pt/fmt/riscv.h b/drivers/iommu/generic_p= t/fmt/riscv.h index 777887335696..866b922f7e13 100644 --- a/drivers/iommu/generic_pt/fmt/riscv.h +++ b/drivers/iommu/generic_pt/fmt/riscv.h @@ -222,6 +222,49 @@ static inline void riscvpt_attr_from_entry(const struc= t pt_state *pts, } #define pt_attr_from_entry riscvpt_attr_from_entry =20 +/* + * Dirty tracking: RISC-V PTEs use D (bit 7) as the hardware dirty bit. + * When Svnapot 64K is active a leaf entry spans 16 consecutive PTEs; we + * must check / clear all of them so that no dirty indication is lost. + */ +static inline bool riscvpt_entry_is_write_dirty(const struct pt_state *pts) +{ + unsigned int num_contig_lg2 =3D riscvpt_entry_num_contig_lg2(pts); + const pt_riscv_entry_t *tablep =3D + pt_cur_table(pts, pt_riscv_entry_t) + + log2_set_mod(pts->index, 0, num_contig_lg2); + const pt_riscv_entry_t *end =3D tablep + log2_to_int(num_contig_lg2); + + for (; tablep !=3D end; tablep++) + if (READ_ONCE(*tablep) & RISCVPT_D) + return true; + return false; +} +#define pt_entry_is_write_dirty riscvpt_entry_is_write_dirty + +static inline void riscvpt_entry_make_write_clean(struct pt_state *pts) +{ + unsigned int num_contig_lg2 =3D riscvpt_entry_num_contig_lg2(pts); + pt_riscv_entry_t *tablep =3D + pt_cur_table(pts, pt_riscv_entry_t) + + log2_set_mod(pts->index, 0, num_contig_lg2); + pt_riscv_entry_t *end =3D tablep + log2_to_int(num_contig_lg2); + + for (; tablep !=3D end; tablep++) + WRITE_ONCE(*tablep, READ_ONCE(*tablep) & ~(pt_riscv_entry_t)RISCVPT_D); +} +#define pt_entry_make_write_clean riscvpt_entry_make_write_clean + +static inline bool riscvpt_entry_make_write_dirty(struct pt_state *pts) +{ + pt_riscv_entry_t *tablep =3D + pt_cur_table(pts, pt_riscv_entry_t) + pts->index; + pt_riscv_entry_t new =3D pts->entry | RISCVPT_D; + + return try_cmpxchg64(tablep, &pts->entry, new); +} +#define pt_entry_make_write_dirty riscvpt_entry_make_write_dirty + /* --- iommu */ #include #include --=20 2.50.1 From nobody Sat Jun 13 13:33:12 2026 Received: from out30-124.freemail.mail.aliyun.com (out30-124.freemail.mail.aliyun.com [115.124.30.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A84B1352F95; Thu, 7 May 2026 11:37:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778153842; cv=none; b=Z9eBxYCz8i4cmoGD3D4joECsL0Y8LBRby8dZmt9OX9M60RFQzKaAOllXZRprPPxy+EQLv+nhQIxo4b0sPxfLYOiiet3zY6kkA/ahV5/ybhYtN9hgBEuv5ULB1tbOkzaLyQCNmTyCcZSTIU2CePKdeB8xQn6TmRFfXppJDHxUpsk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778153842; c=relaxed/simple; bh=hPPEJWpqwcsCvFcsSjXs2lsoWzuWtKcWOt/3dw8I5Sw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=sA+zBAGkMDMgO0IrsuVacWlhxkJEFXhnuqAdxyLu8mwBkLYqG39IMMl6jHmQ9yv0iCE7+YzU4CowvwiuS0vOxM42rC3pFea0h3NjVFDtbZ0I/s/235bJslzblDyErsKJnkfvxyaagVnbQ8nO4TkdM7yy/LjedRuK7ShUDUtpFLA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=RSX4BvwY; arc=none smtp.client-ip=115.124.30.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="RSX4BvwY" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1778153837; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=tFAMKZYz1nJYVHM70HUe0OYd4bRWfYYuKOfYQU7XBks=; b=RSX4BvwYeEHCNtgbWc5I/ytxbCmD9PK12UsigpTX1mql4jho1ttTtg9wN4mkYYEBlpapS8xptZIeOY29O3nwQH2qiCAJ8r8VTWB2LY1kzODrIF8jMbMjGOunGmr4JnKlzu2fwN5ygcc2zvZV7T+iJKQTmp8aH2oywaLhuwK/x3A= X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R201e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam033045098064;MF=fangyu.yu@linux.alibaba.com;NM=1;PH=DS;RN=24;SR=0;TI=SMTPD_---0X2UVF.3_1778153834; Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0X2UVF.3_1778153834 cluster:ay36) by smtp.aliyun-inc.com; Thu, 07 May 2026 19:37:15 +0800 From: fangyu.yu@linux.alibaba.com To: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, tjeznach@rivosinc.com, jgg@ziepe.ca, kevin.tian@intel.com, baolu.lu@linux.intel.com, vasant.hegde@amd.com, anup@brainfault.org, atish.patra@linux.dev, skhawaja@google.com, jgg@nvidia.com Cc: guoren@kernel.org, andrew.jones@oss.qualcomm.com, kvm@vger.kernel.org, iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Fangyu Yu Subject: [RFC PATCH v2 03/10] iommu/riscv: report iommu capabilities Date: Thu, 7 May 2026 19:36:59 +0800 Message-Id: <20260507113706.11400-4-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com> References: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Tomasz Jeznach Report RISC-V IOMMU capabilities required by VFIO subsystem to enable PCIe device assignment. Signed-off-by: Tomasz Jeznach Signed-off-by: Fangyu Yu --- drivers/iommu/riscv/iommu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index a31f50bbad35..bd36e3b5d13f 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1336,6 +1336,16 @@ static struct iommu_group *riscv_iommu_device_group(= struct device *dev) return generic_device_group(dev); } =20 +static bool riscv_iommu_capable(struct device *dev, enum iommu_cap cap) +{ + switch (cap) { + case IOMMU_CAP_CACHE_COHERENCY: + return true; + default: + return false; + } +} + static int riscv_iommu_of_xlate(struct device *dev, const struct of_phandl= e_args *args) { return iommu_fwspec_add_ids(dev, args->args, 1); @@ -1397,6 +1407,7 @@ static void riscv_iommu_release_device(struct device = *dev) =20 static const struct iommu_ops riscv_iommu_ops =3D { .of_xlate =3D riscv_iommu_of_xlate, + .capable =3D riscv_iommu_capable, .identity_domain =3D &riscv_iommu_identity_domain, .blocked_domain =3D &riscv_iommu_blocking_domain, .release_domain =3D &riscv_iommu_blocking_domain, --=20 2.50.1 From nobody Sat Jun 13 13:33:12 2026 Received: from out30-97.freemail.mail.aliyun.com (out30-97.freemail.mail.aliyun.com [115.124.30.97]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1C8F3E958D; Thu, 7 May 2026 11:42:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.97 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778154165; cv=none; b=H0womjjebebjA8/kZj6mU9G6PU1V7dmHKKquCfuh+QkSKHDDS3FfbclqcqRzUFshjF2ieqooTsOXnw8y/Ka/B/+K2NAUucqtEnOwprWepZTNLoqYmIxfaFShZBiMayM4nGOhpZDIcvU+4gYSAx3kHhVZugQv7E6Guy8nPyAFwoA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778154165; c=relaxed/simple; bh=0weoe+7B7l74zCruuU68kFf1KoJhK7Oc4BVkageR76c=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Bfr6777WA74auEN+HkH4yuWhwan35rtZb14IcQyG4xRU7cp+uC1/+I1nb3XMBrtOmyltNBEXrlyAb2SkkGj5CchUVoeTDJ0EMP0f23UJqhASVMwVaOo6f/Yx+Gez/Ul3KjYkjmw6tXSKeZfWSfBZ6tGQ03cA7ro+FrMLNCSdxaA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=I4KmnaRu; arc=none smtp.client-ip=115.124.30.97 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="I4KmnaRu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1778154159; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=F51Id+NmnokdCAoFLH+RndXo5++Xd5bwtOM8r+G9Jts=; b=I4KmnaRu4UDpD0I2P+1q3xtG9N9/WeIHwEfflw/2emUj/K44z8EZUd+3GaUXJf0WRu90KI1QaQt66NkjUnwKTnPGFqn7447C/IfudPHFBd/oDMSqmHzW0r2fLLpxYbbwyIf14fZmJMq2DgUdj4WxjMYFsg2uQdsD0CzwYO67fZE= X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R181e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam011083073210;MF=fangyu.yu@linux.alibaba.com;NM=1;PH=DS;RN=25;SR=0;TI=SMTPD_---0X2UVF.m_1778153836; Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0X2UVF.m_1778153836 cluster:ay36) by smtp.aliyun-inc.com; Thu, 07 May 2026 19:37:17 +0800 From: fangyu.yu@linux.alibaba.com To: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, tjeznach@rivosinc.com, jgg@ziepe.ca, kevin.tian@intel.com, baolu.lu@linux.intel.com, vasant.hegde@amd.com, anup@brainfault.org, atish.patra@linux.dev, skhawaja@google.com, jgg@nvidia.com Cc: guoren@kernel.org, andrew.jones@oss.qualcomm.com, kvm@vger.kernel.org, iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Zong Li , Fangyu Yu Subject: [RFC PATCH v2 04/10] iommu/riscv: use data structure instead of individual values Date: Thu, 7 May 2026 19:37:00 +0800 Message-Id: <20260507113706.11400-5-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com> References: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Zong Li The parameter will be increased when we need to set up more bit fields in the device context. Use a data structure to wrap them up. Signed-off-by: Zong Li Signed-off-by: Fangyu Yu --- drivers/iommu/riscv/iommu.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index bd36e3b5d13f..5b8e0072cd1a 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1077,7 +1077,7 @@ static void riscv_iommu_iodir_iotinval(struct riscv_i= ommu_device *iommu, * interim translation faults. */ static void riscv_iommu_iodir_update(struct riscv_iommu_device *iommu, - struct device *dev, u64 fsc, u64 ta) + struct device *dev, struct riscv_iommu_dc *new_dc) { struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(dev); struct riscv_iommu_dc *dc; @@ -1116,10 +1116,10 @@ static void riscv_iommu_iodir_update(struct riscv_i= ommu_device *iommu, for (i =3D 0; i < fwspec->num_ids; i++) { dc =3D riscv_iommu_get_dc(iommu, fwspec->ids[i]); tc =3D READ_ONCE(dc->tc); - tc |=3D ta & RISCV_IOMMU_DC_TC_V; + tc |=3D new_dc->ta & RISCV_IOMMU_DC_TC_V; =20 - WRITE_ONCE(dc->fsc, fsc); - WRITE_ONCE(dc->ta, ta & RISCV_IOMMU_PC_TA_PSCID); + WRITE_ONCE(dc->fsc, new_dc->fsc); + WRITE_ONCE(dc->ta, new_dc->ta & RISCV_IOMMU_PC_TA_PSCID); /* Update device context, write TC.V as the last step. */ dma_wmb(); WRITE_ONCE(dc->tc, tc); @@ -1205,22 +1205,22 @@ static int riscv_iommu_attach_paging_domain(struct = iommu_domain *iommu_domain, struct riscv_iommu_device *iommu =3D dev_to_iommu(dev); struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); struct pt_iommu_riscv_64_hw_info pt_info; - u64 fsc, ta; + struct riscv_iommu_dc dc =3D {0}; =20 pt_iommu_riscv_64_hw_info(&domain->riscvpt, &pt_info); =20 if (!riscv_iommu_pt_supported(iommu, pt_info.fsc_iosatp_mode)) return -ENODEV; =20 - fsc =3D FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, pt_info.fsc_iosatp_mode) | + dc.fsc =3D FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, pt_info.fsc_iosatp_mode) | FIELD_PREP(RISCV_IOMMU_PC_FSC_PPN, pt_info.ppn); - ta =3D FIELD_PREP(RISCV_IOMMU_PC_TA_PSCID, domain->pscid) | + dc.ta =3D FIELD_PREP(RISCV_IOMMU_PC_TA_PSCID, domain->pscid) | RISCV_IOMMU_PC_TA_V; =20 if (riscv_iommu_bond_link(domain, dev)) return -ENOMEM; =20 - riscv_iommu_iodir_update(iommu, dev, fsc, ta); + riscv_iommu_iodir_update(iommu, dev, &dc); riscv_iommu_bond_unlink(info->domain, dev); info->domain =3D domain; =20 @@ -1292,9 +1292,12 @@ static int riscv_iommu_attach_blocking_domain(struct= iommu_domain *iommu_domain, { struct riscv_iommu_device *iommu =3D dev_to_iommu(dev); struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); + struct riscv_iommu_dc dc =3D {0}; + + dc.fsc =3D RISCV_IOMMU_FSC_BARE; =20 /* Make device context invalid, translation requests will fault w/ #258 */ - riscv_iommu_iodir_update(iommu, dev, RISCV_IOMMU_FSC_BARE, 0); + riscv_iommu_iodir_update(iommu, dev, &dc); riscv_iommu_bond_unlink(info->domain, dev); info->domain =3D NULL; =20 @@ -1314,8 +1317,12 @@ static int riscv_iommu_attach_identity_domain(struct= iommu_domain *iommu_domain, { struct riscv_iommu_device *iommu =3D dev_to_iommu(dev); struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); + struct riscv_iommu_dc dc =3D {0}; + + dc.fsc =3D RISCV_IOMMU_FSC_BARE; + dc.ta =3D RISCV_IOMMU_PC_TA_V; =20 - riscv_iommu_iodir_update(iommu, dev, RISCV_IOMMU_FSC_BARE, RISCV_IOMMU_PC= _TA_V); + riscv_iommu_iodir_update(iommu, dev, &dc); riscv_iommu_bond_unlink(info->domain, dev); info->domain =3D NULL; =20 --=20 2.50.1 From nobody Sat Jun 13 13:33:12 2026 Received: from out199-5.us.a.mail.aliyun.com (out199-5.us.a.mail.aliyun.com [47.90.199.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A22E23EFD07; Thu, 7 May 2026 11:37:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=47.90.199.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778153857; cv=none; b=OboS22+sV/nZ/9InEyirYv/UCpyzz6WKU6fn6gYfV8nBoDJjRrBWHasTfyH45w2gbFA9UWZ8CZFQOccEZxgxKndtk/DYM5YG8gFEvSqaWYJln/W3jic+3oTyKUnXj4yBxblKi6GD6hdyZ+ORy5MeQFPmeHA/GrQ5WShs7PRjtNc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778153857; c=relaxed/simple; bh=UyFaqJ00J4fuCCRms7LRc8VrIuiQ2A93KlVuctM/HvM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=CLHLgLqd/1RcsMbq9zA86VorPpgn2azM6p5WAOUp2zMtM/MepF8qdLmn8Ce4VHt82BvYWCdnVBPUdMnveRplEc6sZk0JllZvUm0NdNy4POeuL9YTkyOKn6ngTSP+qlWFPJdepYHLYvu0JHRrttt6PiYFGW+aVQDB2KnoRUz45e4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=ihcPbUFM; arc=none smtp.client-ip=47.90.199.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="ihcPbUFM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1778153842; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=QiHxRCda9Kr0q0RbsXLFQPtUw1DfSKYL9S+IOeDr3fU=; b=ihcPbUFMt34FmREyD993f6c8tDbOAsHqM9MJrGoc5hRHUOrfivvLvQcOEbU8iE+210udDva2McbYpsCU+MMsaDyp43Khrx/ia4M0tmQRJjWCk2m3nMA6Hp9Dl0H9IBgNHIxipAsLfqUoSxs9i5+NdrJdcJsXI7bO1uypq5vhr10= X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R451e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam033037026112;MF=fangyu.yu@linux.alibaba.com;NM=1;PH=DS;RN=25;SR=0;TI=SMTPD_---0X2UVF0L_1778153837; Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0X2UVF0L_1778153837 cluster:ay36) by smtp.aliyun-inc.com; Thu, 07 May 2026 19:37:18 +0800 From: fangyu.yu@linux.alibaba.com To: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, tjeznach@rivosinc.com, jgg@ziepe.ca, kevin.tian@intel.com, baolu.lu@linux.intel.com, vasant.hegde@amd.com, anup@brainfault.org, atish.patra@linux.dev, skhawaja@google.com, jgg@nvidia.com Cc: guoren@kernel.org, andrew.jones@oss.qualcomm.com, kvm@vger.kernel.org, iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Zong Li , Fangyu Yu Subject: [RFC PATCH v2 05/10] iommu/riscv: support GSCID and GVMA invalidation command Date: Thu, 7 May 2026 19:37:01 +0800 Message-Id: <20260507113706.11400-6-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com> References: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Zong Li This patch adds a ID Allocator for GSCID and a wrap for setting up GSCID in IOTLB invalidation command. Set up iohgatp to enable second stage table and flush stage-2 table if the GSCID is set. The GSCID of domain should be freed when release domain. GSCID will be allocated for parent domain in nested IOMMU process. Signed-off-by: Zong Li Signed-off-by: Fangyu Yu --- drivers/iommu/riscv/iommu-bits.h | 7 +++++++ drivers/iommu/riscv/iommu.c | 32 ++++++++++++++++++++++++++------ 2 files changed, 33 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/riscv/iommu-bits.h b/drivers/iommu/riscv/iommu-b= its.h index 29a0040b1c32..7c440926fa23 100644 --- a/drivers/iommu/riscv/iommu-bits.h +++ b/drivers/iommu/riscv/iommu-bits.h @@ -716,6 +716,13 @@ static inline void riscv_iommu_cmd_inval_vma(struct ri= scv_iommu_command *cmd) cmd->dword1 =3D 0; } =20 +static inline void riscv_iommu_cmd_inval_gvma(struct riscv_iommu_command *= cmd) +{ + cmd->dword0 =3D FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IOTINV= AL_OPCODE) | + FIELD_PREP(RISCV_IOMMU_CMD_FUNC, RISCV_IOMMU_CMD_IOTINVAL_FUNC_GVM= A); + cmd->dword1 =3D 0; +} + static inline void riscv_iommu_cmd_inval_set_addr(struct riscv_iommu_comma= nd *cmd, u64 addr) { diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 5b8e0072cd1a..e883ace2f4f1 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -48,6 +48,10 @@ static DEFINE_IDA(riscv_iommu_pscids); #define RISCV_IOMMU_MAX_PSCID (BIT(20) - 1) =20 +/* IOMMU GSCID allocation namespace. */ +static DEFINE_IDA(riscv_iommu_gscids); +#define RISCV_IOMMU_MAX_GSCID (BIT(16) - 1) + /* Device resource-managed allocations */ struct riscv_iommu_devres { void *addr; @@ -819,6 +823,7 @@ struct riscv_iommu_domain { struct list_head bonds; spinlock_t lock; /* protect bonds list updates. */ int pscid; + int gscid; }; PT_IOMMU_CHECK_DOMAIN(struct riscv_iommu_domain, riscvpt.iommu, domain); =20 @@ -967,15 +972,20 @@ static void riscv_iommu_iotlb_inval(struct riscv_iomm= u_domain *domain, =20 /* * IOTLB invalidation request can be safely omitted if already sent - * to the IOMMU for the same PSCID, and with domain->bonds list + * to the IOMMU for the same PSCID/GSCID, and with domain->bonds list * arranged based on the device's IOMMU, it's sufficient to check * last device the invalidation was sent to. */ if (iommu =3D=3D prev) continue; =20 - riscv_iommu_cmd_inval_vma(&cmd); - riscv_iommu_cmd_inval_set_pscid(&cmd, domain->pscid); + if (domain->gscid) { + riscv_iommu_cmd_inval_gvma(&cmd); + riscv_iommu_cmd_inval_set_gscid(&cmd, domain->gscid); + } else { + riscv_iommu_cmd_inval_vma(&cmd); + riscv_iommu_cmd_inval_set_pscid(&cmd, domain->pscid); + } if (end - start < RISCV_IOMMU_IOTLB_INVAL_LIMIT - 1) { unsigned long iova =3D start; =20 @@ -1120,6 +1130,7 @@ static void riscv_iommu_iodir_update(struct riscv_iom= mu_device *iommu, =20 WRITE_ONCE(dc->fsc, new_dc->fsc); WRITE_ONCE(dc->ta, new_dc->ta & RISCV_IOMMU_PC_TA_PSCID); + WRITE_ONCE(dc->iohgatp, new_dc->iohgatp); /* Update device context, write TC.V as the last step. */ dma_wmb(); WRITE_ONCE(dc->tc, tc); @@ -1175,8 +1186,10 @@ static void riscv_iommu_free_paging_domain(struct io= mmu_domain *iommu_domain) =20 WARN_ON(!list_empty(&domain->bonds)); =20 - if ((int)domain->pscid > 0) + if (domain->pscid > 0) ida_free(&riscv_iommu_pscids, domain->pscid); + if (domain->gscid > 0) + ida_free(&riscv_iommu_gscids, domain->gscid); =20 pt_iommu_deinit(&domain->riscvpt.iommu); kfree(domain); @@ -1212,8 +1225,15 @@ static int riscv_iommu_attach_paging_domain(struct i= ommu_domain *iommu_domain, if (!riscv_iommu_pt_supported(iommu, pt_info.fsc_iosatp_mode)) return -ENODEV; =20 - dc.fsc =3D FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, pt_info.fsc_iosatp_mode) | - FIELD_PREP(RISCV_IOMMU_PC_FSC_PPN, pt_info.ppn); + if (domain->gscid) { + dc.iohgatp =3D FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_MODE, pt_info.iohgatp_m= ode) | + FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_GSCID, domain->gscid) | + FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_PPN, pt_info.ppn); + } else { + dc.fsc =3D FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, pt_info.fsc_iosatp_mode) | + FIELD_PREP(RISCV_IOMMU_PC_FSC_PPN, pt_info.ppn); + } + dc.ta =3D FIELD_PREP(RISCV_IOMMU_PC_TA_PSCID, domain->pscid) | RISCV_IOMMU_PC_TA_V; =20 --=20 2.50.1 From nobody Sat Jun 13 13:33:12 2026 Received: from out30-131.freemail.mail.aliyun.com (out30-131.freemail.mail.aliyun.com [115.124.30.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0FDD3176FD; Thu, 7 May 2026 11:42:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778154166; cv=none; b=BPo7Lv0qqB0rRqQCRNnAAH8ALrlNNAAhB2C741R/eILiOtcmkjfeeg9MArCSKCBpXfesXDhJLncmA5VC3Le4XZ+le8EfuLEIhDyU4DlJYhn+Dp8BCIL/orA83cca2SRSpmpdsXXJlAN0d6vdkdwDmIgDx2wwY0zC5eaH95Bc398= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778154166; c=relaxed/simple; bh=TJtwwmOes+WMqZV10KyeFqw49c64kqL7395J+MxsNMo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=r0LlREcFNCpwZ6UlTPxsKmuxzTWwaWaTyS96Qpgtgcap5XFi2cWGJODwJy5KgcI192gJUr3d2mslA0+J6GbDWqAq2rXu0WQrogwo2OtKInpsDEdKDjr6IBmKHc3oaGmXu+2maUSW1RNcsjraE4JUthQnp30A7zcoKy2vu6CTNLA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=AnPxoCWp; arc=none smtp.client-ip=115.124.30.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="AnPxoCWp" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1778154162; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=RWu/puVJ24xC3wGWoddID7UrDVPs6J4eX8hoo+uZKZs=; b=AnPxoCWpfFM/yePvzqCMIUPUuonuquE03ZJo0regZSqJGOHQEZ8Q5NWSFhT1kyhblEgFTH7RfQ6eEMV0BSmaxo3Vm5qnZblNRwWBskoNf2INfjkS7oTvV7Ig/gqaqr1Nbd3q8WSZ+ZIfrOYVM096r0V1AfrQiBAKn78FC5dRn6U= X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R181e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam033037033178;MF=fangyu.yu@linux.alibaba.com;NM=1;PH=DS;RN=25;SR=0;TI=SMTPD_---0X2UVF0q_1778153839; Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0X2UVF0q_1778153839 cluster:ay36) by smtp.aliyun-inc.com; Thu, 07 May 2026 19:37:20 +0800 From: fangyu.yu@linux.alibaba.com To: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, tjeznach@rivosinc.com, jgg@ziepe.ca, kevin.tian@intel.com, baolu.lu@linux.intel.com, vasant.hegde@amd.com, anup@brainfault.org, atish.patra@linux.dev, skhawaja@google.com, jgg@nvidia.com Cc: guoren@kernel.org, andrew.jones@oss.qualcomm.com, kvm@vger.kernel.org, iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Andrew Jones , Fangyu Yu Subject: [RFC PATCH v2 06/10] RISC-V: KVM: Enable KVM_VFIO interfaces on RISC-V arch Date: Thu, 7 May 2026 19:37:02 +0800 Message-Id: <20260507113706.11400-7-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com> References: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Tomasz Jeznach Enable KVM/VFIO support on RISC-V architecture. Signed-off-by: Tomasz Jeznach Signed-off-by: Andrew Jones Signed-off-by: Fangyu Yu --- arch/riscv/kvm/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/kvm/Kconfig b/arch/riscv/kvm/Kconfig index ec2cee0a39e0..54ee90f010ef 100644 --- a/arch/riscv/kvm/Kconfig +++ b/arch/riscv/kvm/Kconfig @@ -30,8 +30,10 @@ config KVM select KVM_GENERIC_HARDWARE_ENABLING select KVM_MMIO select VIRT_XFER_TO_GUEST_WORK + select KVM_VFIO select SCHED_INFO select GUEST_PERF_EVENTS if PERF_EVENTS + select SRCU help Support hosting virtualized guest machines. =20 --=20 2.50.1 From nobody Sat Jun 13 13:33:12 2026 Received: from out30-118.freemail.mail.aliyun.com (out30-118.freemail.mail.aliyun.com [115.124.30.118]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 822733E9295; Thu, 7 May 2026 11:37:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.118 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778153852; cv=none; b=WWQagZRZItdtJAyJhHiEnpvJFU3ccbyLZyqYjLKH9AwyNn9y48ZOKdKeowFBeGcmZXZk2lJEkfSTUCdVoSwqTsts7AZv7RTPyCLDydZliAKeysrUDRTX7uEmheQhdW5Ot5Gr7ExSch34UlfpodVockcs4WGZsZs5YpVhH/mIe4k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778153852; c=relaxed/simple; bh=pdT7jqaAaQjXrLDxPcXMYYjXh6e3rWtPFl0ETtBT2bk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=O1HZ0pHTD269tP+pZqbZ3a2O8rkT5HrL51WUzYnp4Vqq1MEUalrsWpVmKCR0yZg0f3POvYaMwjbJr8M7+qdVLIV2+dlw+HhvEnldHzlDcJGRvuXpMwo8nx04kKYD5/D+REE+Do8yTlEL9mhCB1UFLQLkWBuJSzNwvmuEOaYgtaE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=LIp0wB84; arc=none smtp.client-ip=115.124.30.118 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="LIp0wB84" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1778153843; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=E95HEUv+RbcOdtj9NlIbuNX1uhYBJ2+6cETCe8Jytbc=; b=LIp0wB842VwYXNykg3LzL+cSLtQFHJ/rPPmgLW6WdtO/C9mzVgzpaqHOfoq11IMfNXlYusEEUKuXo8mAFPZtuV8hcPpyML6jlKMYTeFiXQixG2hrmmuo85Pm4M0Hi/MjUjuy26nFDdRMNO5lXCXRHezQGRUSYaaklhOt9p0HmI0= X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R261e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam033037026112;MF=fangyu.yu@linux.alibaba.com;NM=1;PH=DS;RN=24;SR=0;TI=SMTPD_---0X2UVF1L_1778153840; Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0X2UVF1L_1778153840 cluster:ay36) by smtp.aliyun-inc.com; Thu, 07 May 2026 19:37:21 +0800 From: fangyu.yu@linux.alibaba.com To: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, tjeznach@rivosinc.com, jgg@ziepe.ca, kevin.tian@intel.com, baolu.lu@linux.intel.com, vasant.hegde@amd.com, anup@brainfault.org, atish.patra@linux.dev, skhawaja@google.com, jgg@nvidia.com Cc: guoren@kernel.org, andrew.jones@oss.qualcomm.com, kvm@vger.kernel.org, iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Fangyu Yu Subject: [RFC PATCH v2 07/10] iommu/riscv: Add domain_alloc_paging_flags for second-stage domain Date: Thu, 7 May 2026 19:37:03 +0800 Message-Id: <20260507113706.11400-8-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com> References: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fangyu Yu Replace .domain_alloc_paging with .domain_alloc_paging_flags so callers can pass allocation flags to select the appropriate page-table type. When IOMMU_HWPT_ALLOC_NEST_PARENT or IOMMU_HWPT_ALLOC_DIRTY_TRACKING is set in @flags, allocate a second-stage (iohgatp) domain. When @flags is 0 the behaviour is identical to the previous domain_alloc_paging: first-stage (iosatp) domain. Signed-off-by: Fangyu Yu --- drivers/iommu/riscv/iommu.c | 90 +++++++++++++++++++++++++++---------- 1 file changed, 67 insertions(+), 23 deletions(-) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index e883ace2f4f1..ebf42f74e194 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1255,25 +1255,21 @@ static const struct iommu_domain_ops riscv_iommu_pa= ging_domain_ops =3D { .flush_iotlb_all =3D riscv_iommu_iotlb_flush_all, }; =20 -static struct iommu_domain *riscv_iommu_alloc_paging_domain(struct device = *dev) +static struct iommu_domain *riscv_iommu_domain_alloc_paging_flags( + struct device *dev, u32 flags, + const struct iommu_user_data *user_data) { struct pt_iommu_riscv_64_cfg cfg =3D {}; struct riscv_iommu_domain *domain; struct riscv_iommu_device *iommu; int ret; + const u32 supported_flags =3D IOMMU_HWPT_ALLOC_DIRTY_TRACKING | + IOMMU_HWPT_ALLOC_NEST_PARENT; =20 - iommu =3D dev_to_iommu(dev); - if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV57) { - cfg.common.hw_max_vasz_lg2 =3D 57; - } else if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV48) { - cfg.common.hw_max_vasz_lg2 =3D 48; - } else if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV39) { - cfg.common.hw_max_vasz_lg2 =3D 39; - } else { - dev_err(dev, "cannot find supported page table mode\n"); - return ERR_PTR(-ENODEV); - } - cfg.common.hw_max_oasz_lg2 =3D 56; + if (flags & ~supported_flags) + return ERR_PTR(-EOPNOTSUPP); + if (user_data) + return ERR_PTR(-EOPNOTSUPP); =20 domain =3D kzalloc_obj(*domain); if (!domain) @@ -1281,6 +1277,8 @@ static struct iommu_domain *riscv_iommu_alloc_paging_= domain(struct device *dev) =20 INIT_LIST_HEAD_RCU(&domain->bonds); spin_lock_init(&domain->lock); + iommu =3D dev_to_iommu(dev); + cfg.common.hw_max_oasz_lg2 =3D 56; /* * 6.4 IOMMU capabilities [..] IOMMU implementations must support the * Svnapot standard extension for NAPOT Translation Contiguity. @@ -1291,19 +1289,65 @@ static struct iommu_domain *riscv_iommu_alloc_pagin= g_domain(struct device *dev) domain->riscvpt.iommu.nid =3D dev_to_node(iommu->dev); domain->domain.ops =3D &riscv_iommu_paging_domain_ops; =20 - domain->pscid =3D ida_alloc_range(&riscv_iommu_pscids, 1, - RISCV_IOMMU_MAX_PSCID, GFP_KERNEL); - if (domain->pscid < 0) { - riscv_iommu_free_paging_domain(&domain->domain); - return ERR_PTR(-ENOMEM); + switch (flags) { + case 0: + if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV57) { + cfg.common.hw_max_vasz_lg2 =3D 57; + } else if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV48) { + cfg.common.hw_max_vasz_lg2 =3D 48; + } else if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV39) { + cfg.common.hw_max_vasz_lg2 =3D 39; + } else { + ret =3D -ENODEV; + goto err_free; + } + domain->pscid =3D ida_alloc_range(&riscv_iommu_pscids, 1, + RISCV_IOMMU_MAX_PSCID, GFP_KERNEL); + if (domain->pscid < 0) { + ret =3D -ENOMEM; + goto err_free; + } + break; + case IOMMU_HWPT_ALLOC_NEST_PARENT: + case IOMMU_HWPT_ALLOC_DIRTY_TRACKING: + case IOMMU_HWPT_ALLOC_DIRTY_TRACKING | IOMMU_HWPT_ALLOC_NEST_PARENT: + /* + * Second-stage (iohgatp) page table for KVM VFIO device + * pass-through and dirty tracking. The GPA space is 2 bits + * wider than the corresponding first-stage VA space (x4 root + * page table), so hw_max_vasz_lg2 values are 41/50/59. + */ + if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV57X4) { + cfg.common.hw_max_vasz_lg2 =3D 59; + } else if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV48X4) { + cfg.common.hw_max_vasz_lg2 =3D 50; + } else if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV39X4) { + cfg.common.hw_max_vasz_lg2 =3D 41; + } else { + ret =3D -ENODEV; + goto err_free; + } + domain->gscid =3D ida_alloc_range(&riscv_iommu_gscids, 1, + RISCV_IOMMU_MAX_GSCID, GFP_KERNEL); + if (domain->gscid < 0) { + ret =3D -ENOMEM; + goto err_free; + } + cfg.common.features |=3D BIT(PT_FEAT_RISCV_S2); + break; + default: + ret =3D -EOPNOTSUPP; + goto err_free; } =20 ret =3D pt_iommu_riscv_64_init(&domain->riscvpt, &cfg, GFP_KERNEL); - if (ret) { - riscv_iommu_free_paging_domain(&domain->domain); - return ERR_PTR(ret); - } + if (ret) + goto err_free; return &domain->domain; + +err_free: + riscv_iommu_free_paging_domain(&domain->domain); + return ERR_PTR(ret); } =20 static int riscv_iommu_attach_blocking_domain(struct iommu_domain *iommu_d= omain, @@ -1438,7 +1482,7 @@ static const struct iommu_ops riscv_iommu_ops =3D { .identity_domain =3D &riscv_iommu_identity_domain, .blocked_domain =3D &riscv_iommu_blocking_domain, .release_domain =3D &riscv_iommu_blocking_domain, - .domain_alloc_paging =3D riscv_iommu_alloc_paging_domain, + .domain_alloc_paging_flags =3D riscv_iommu_domain_alloc_paging_flags, .device_group =3D riscv_iommu_device_group, .probe_device =3D riscv_iommu_probe_device, .release_device =3D riscv_iommu_release_device, --=20 2.50.1 From nobody Sat Jun 13 13:33:12 2026 Received: from out199-18.us.a.mail.aliyun.com (out199-18.us.a.mail.aliyun.com [47.90.199.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 529E63ED5A2; Thu, 7 May 2026 11:37:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=47.90.199.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778153864; cv=none; b=VzmnALl9YVES0WvpZ89CT2d3ezOoaiX3MV9YouXlFH7N/YGiAz7VHULriQf1Rr9HCkrdlg54ll7kUQr7gk0ZeFNb4Ofk9mbUMB+WfmVF7BskFj2YhljTndy5P/CgSnnNeBTy8Pn/lleRbtT5Uxo7aVYKyXwGc1e4+JhWNjHlXrk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778153864; c=relaxed/simple; bh=4L98WCIJ8YSmz2dY3GscFFhNm2QaDovoJH5IOK3fi+4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=dpKrpAeCdrXHr+1x2nZ83jWSznCIqlp5wP4O5HcmxIY+4thbqNWm9yE0ED+KkM3o8Vj+7twUBYjLn8tmCeLPMhPllILcxOM9p5FEJuE07FBwpn+VWkRTEzCSJ6IcvNMNC2swsf7jRVWOTEAfC2rhtI/bRhfAXUq8cIQ1Zgj1fzc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=JLZRCKGO; arc=none smtp.client-ip=47.90.199.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="JLZRCKGO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1778153845; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=hesx5mr3hyIU597nzAcEZE25NXb5nnN09Ut/PVDl82s=; b=JLZRCKGOYXjaDJ/iERJ9nTMtGqRHKGeOxZmTCFSnbMplFVl+f4W7zY122s7n4TL1LljTrQlj/i1rAcPQvv4h2wqzwdCI9oHAlHx5eIdv29ezXPefeZNOloovUbd7kfdzFct8rgx/MkIbned5/FLUh7nHEObHx6+7hIX62nnUfnU= X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R121e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam011083073210;MF=fangyu.yu@linux.alibaba.com;NM=1;PH=DS;RN=24;SR=0;TI=SMTPD_---0X2UVF1m_1778153842; Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0X2UVF1m_1778153842 cluster:ay36) by smtp.aliyun-inc.com; Thu, 07 May 2026 19:37:23 +0800 From: fangyu.yu@linux.alibaba.com To: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, tjeznach@rivosinc.com, jgg@ziepe.ca, kevin.tian@intel.com, baolu.lu@linux.intel.com, vasant.hegde@amd.com, anup@brainfault.org, atish.patra@linux.dev, skhawaja@google.com, jgg@nvidia.com Cc: guoren@kernel.org, andrew.jones@oss.qualcomm.com, kvm@vger.kernel.org, iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Fangyu Yu Subject: [RFC PATCH v2 08/10] iommu/riscv: Pre-enable GADE for second-stage domains Date: Thu, 7 May 2026 19:37:04 +0800 Message-Id: <20260507113706.11400-9-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com> References: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fangyu Yu Pre-enable RISCV_IOMMU_DC_TC_GADE in the device context when attaching a second-stage domain, if the IOMMU supports AMO_HWAD. Software pre-populates second-stage page tables with D set, so enabling GADE by default does not change normal behavior. When dirty tracking is enabled, iommufd clears the pre-set D bits and GADE becomes necessary for hardware to update the dirty bit on write access. This avoids toggling GADE dynamically and keeps device context setup consistent with second-stage domain attachment. Signed-off-by: Fangyu Yu --- drivers/iommu/riscv/iommu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index ebf42f74e194..4adf2b6be89b 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1229,6 +1229,8 @@ static int riscv_iommu_attach_paging_domain(struct io= mmu_domain *iommu_domain, dc.iohgatp =3D FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_MODE, pt_info.iohgatp_m= ode) | FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_GSCID, domain->gscid) | FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_PPN, pt_info.ppn); + if (iommu->caps & RISCV_IOMMU_CAPABILITIES_AMO_HWAD) + dc.tc |=3D RISCV_IOMMU_DC_TC_GADE; } else { dc.fsc =3D FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, pt_info.fsc_iosatp_mode) | FIELD_PREP(RISCV_IOMMU_PC_FSC_PPN, pt_info.ppn); --=20 2.50.1 From nobody Sat Jun 13 13:33:12 2026 Received: from out30-101.freemail.mail.aliyun.com (out30-101.freemail.mail.aliyun.com [115.124.30.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5719A3E8C54; Thu, 7 May 2026 11:42:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.101 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778154171; cv=none; b=gNt1ZKGbaMMsRfEPUf/A2pFBO+2o3dP1Z85o2fQk8OxaRs3JVtXWOfnDmJYaqZlAfEh6mmYO0kaQS4QmPHCai+VHBjWj4gZBo4yr4d8CJAE04QuePNt7LmvwWUR0GJRlRvJQHmCN+GT2hVsiZ5QmokR6LpF90nuhRQqIa15gzic= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778154171; c=relaxed/simple; bh=ZyXErRgSeRi8Vb/chLbgc5T4YKtqYWjqc6cFpWaklCc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=lqueqG7IwojTb96MYn1NM11dfrR1fMIJUaG/YDWBURr21ZGRzpo1d37ZPG7qeHPuRDQf5MMPeBxGDJYaM4ns+z6mr05gDKamocoC6Uj9QlSOX++L8Lb/kIycpqANUOlJvpPeRejjISQZSPrUBOPrV49I2l0/uf8dbU/nyzxqdMw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=bHcMdTyN; arc=none smtp.client-ip=115.124.30.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="bHcMdTyN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1778154167; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=ymvPBhIqjH6VI2cF6B82ob0998YC79NL7DciLWQChAk=; b=bHcMdTyNpxjlVaIvLWItfq2PeidhkNUcSzpuiIkcu6ckMrHhdFIfnplr8pwhwso+d70pohdDYD4tLezBEP5JQqpdZYgw+oZw1FoXIU3tkeLRcBe4sa4zG4VyBXmvJZ4CywG8C5lE/0PJ1qx07vB6JQ1bdBkJvEu8DXkzoqDGJNs= X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R101e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam033037033178;MF=fangyu.yu@linux.alibaba.com;NM=1;PH=DS;RN=24;SR=0;TI=SMTPD_---0X2UVF2E_1778153843; Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0X2UVF2E_1778153843 cluster:ay36) by smtp.aliyun-inc.com; Thu, 07 May 2026 19:37:24 +0800 From: fangyu.yu@linux.alibaba.com To: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, tjeznach@rivosinc.com, jgg@ziepe.ca, kevin.tian@intel.com, baolu.lu@linux.intel.com, vasant.hegde@amd.com, anup@brainfault.org, atish.patra@linux.dev, skhawaja@google.com, jgg@nvidia.com Cc: guoren@kernel.org, andrew.jones@oss.qualcomm.com, kvm@vger.kernel.org, iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Fangyu Yu Subject: [RFC PATCH v2 09/10] iommu/riscv: Add dirty tracking support for second-stage domains Date: Thu, 7 May 2026 19:37:05 +0800 Message-Id: <20260507113706.11400-10-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com> References: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fangyu Yu Add hardware dirty tracking support for second-stage (iohgatp) domains used in KVM VFIO device pass-through. The RISC-V IOMMU can automatically set the dirty bit in PTEs on write access when DC.tc.GADE is set and the hardware has AMO_HWAD capability. Wire this up to the iommufd dirty tracking interface: - riscv_iommu_set_dirty_tracking(): Always enabled dirty tracking for second-stage domain. - riscv_iommu_dirty_ops: Exposes set_dirty_tracking and the generic page-table read_and_clear_dirty via IOMMU_PT_DIRTY_OPS(riscv_64). - domain_alloc_paging_flags: Assigns dirty_ops to second-stage domains when AMO_HWAD is advertised in hardware capabilities. - riscv_iommu_capable: Reports IOMMU_CAP_DIRTY_TRACKING when AMO_HWAD is present. Signed-off-by: Fangyu Yu --- drivers/iommu/riscv/iommu.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 4adf2b6be89b..b7944149dcfe 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1249,6 +1249,21 @@ static int riscv_iommu_attach_paging_domain(struct i= ommu_domain *iommu_domain, return 0; } =20 +static int riscv_iommu_set_dirty_tracking(struct iommu_domain *iommu_domai= n, + bool enable) +{ + /* + * Always enabled and the dirty bitmap is cleared prior to + * set_dirty_tracking(). + */ + return 0; +} + +static const struct iommu_dirty_ops riscv_iommu_dirty_ops =3D { + IOMMU_PT_DIRTY_OPS(riscv_64), + .set_dirty_tracking =3D riscv_iommu_set_dirty_tracking, +}; + static const struct iommu_domain_ops riscv_iommu_paging_domain_ops =3D { IOMMU_PT_DOMAIN_OPS(riscv_64), .attach_dev =3D riscv_iommu_attach_paging_domain, @@ -1336,6 +1351,8 @@ static struct iommu_domain *riscv_iommu_domain_alloc_= paging_flags( goto err_free; } cfg.common.features |=3D BIT(PT_FEAT_RISCV_S2); + if (iommu->caps & RISCV_IOMMU_CAPABILITIES_AMO_HWAD) + domain->domain.dirty_ops =3D &riscv_iommu_dirty_ops; break; default: ret =3D -EOPNOTSUPP; @@ -1411,9 +1428,13 @@ static struct iommu_group *riscv_iommu_device_group(= struct device *dev) =20 static bool riscv_iommu_capable(struct device *dev, enum iommu_cap cap) { + struct riscv_iommu_device *iommu =3D dev_to_iommu(dev); + switch (cap) { case IOMMU_CAP_CACHE_COHERENCY: return true; + case IOMMU_CAP_DIRTY_TRACKING: + return !!(iommu->caps & RISCV_IOMMU_CAPABILITIES_AMO_HWAD); default: return false; } --=20 2.50.1 From nobody Sat Jun 13 13:33:12 2026 Received: from out30-100.freemail.mail.aliyun.com (out30-100.freemail.mail.aliyun.com [115.124.30.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A10453E8C56; Thu, 7 May 2026 11:37:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.100 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778153854; cv=none; b=htKcKyDuAmopjikIEyCuk1FLmLyqKLkS8/ZGC2qL1M0Z6KcukJsDg/f+fpuKJwiGt95rWDUC7FvUJAR94knolIGopj66d+e9yZI7YGtA+XHFDkrE9m8blT3mcz9wG8GqXvZ4iEUPBT9EIyluLWvCs1OmoAdVWP1pW4dI2oLkhYw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778153854; c=relaxed/simple; bh=pkbLjK68To7SXmDhh10F9ZkF7vWh9NezqZcwWX8xiSU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DzQ8JPNg0tPy4ZqjXYdOUnIK3Qtvf8vqQIhY3eGMTTM+956O9uuf/0jm/gin03rcpevC2OlOwfR2/L7Ck9fWllKjgaAdJ2Y0RlWPYg7ENiA8iTxWSsgjtNc7/lrYmfAVfKPgt6/7Usds5WOjmn98jIgJd3cuKNwOK5XvRyqZ0/E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=JkS7lnTQ; arc=none smtp.client-ip=115.124.30.100 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="JkS7lnTQ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1778153850; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=iJ95MOqqUstSXPIf+KA1zXZMnjUDZYM6/cGTcZoBUgk=; b=JkS7lnTQZ79OnGApxQfGqQwK1IhiVA7PkXGfnGWyKgeP9ZofHSkceZ70t/m3LXaGmvPjJmcRkB5aK+XwBh6f3P2gIBD47cBjZr+JNIuKAE6JFwyo7O1/+gcImMlhh6MWWKIWlpAO4lb47cVn/h3/chuSpAKBQ4SfPGMWK9YXYx0= X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R201e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam033032089153;MF=fangyu.yu@linux.alibaba.com;NM=1;PH=DS;RN=24;SR=0;TI=SMTPD_---0X2UVF2t_1778153845; Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0X2UVF2t_1778153845 cluster:ay36) by smtp.aliyun-inc.com; Thu, 07 May 2026 19:37:26 +0800 From: fangyu.yu@linux.alibaba.com To: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, tjeznach@rivosinc.com, jgg@ziepe.ca, kevin.tian@intel.com, baolu.lu@linux.intel.com, vasant.hegde@amd.com, anup@brainfault.org, atish.patra@linux.dev, skhawaja@google.com, jgg@nvidia.com Cc: guoren@kernel.org, andrew.jones@oss.qualcomm.com, kvm@vger.kernel.org, iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Fangyu Yu Subject: [RFC PATCH v2 10/10] iommu/riscv: Add IOTINVAL.GVMA after updating DDT/PDT entries Date: Thu, 7 May 2026 19:37:06 +0800 Message-Id: <20260507113706.11400-11-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com> References: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fangyu Yu Previously, only IOTINVAL.VMA was issued, which is insufficient for second-stage address translation consistency. Signed-off-by: Fangyu Yu --- drivers/iommu/riscv/iommu.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index b7944149dcfe..44dd268cc3ce 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1065,12 +1065,15 @@ static void riscv_iommu_iodir_iotinval(struct riscv= _iommu_device *iommu, /* * else: IOTINVAL.VMA with GV=3D1,AV=3DPSCV=3D0,and * GSCID=3DDC.iohgatp.GSCID - * + */ + riscv_iommu_cmd_send(iommu, &cmd); + /* * IOTINVAL.GVMA with GV=3D1,AV=3D0,and * GSCID=3DDC.iohgatp.GSCID - * TODO: For now, the Second-Stage feature have not yet been merged, - * also issue IOTINVAL.GVMA once second-stage support is merged. */ + riscv_iommu_cmd_inval_gvma(&cmd); + riscv_iommu_cmd_inval_set_gscid(&cmd, + FIELD_GET(RISCV_IOMMU_DC_IOHGATP_GSCID, iohgatp)); } riscv_iommu_cmd_send(iommu, &cmd); } --=20 2.50.1