From nobody Sat Jun 13 13:04:18 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 114D0399346; Thu, 7 May 2026 08:48:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778143724; cv=none; b=MWfinBHxLj8EdHNlFqGiuxRgQraUMpNhj2srBlfg90wm2fwwqIFv/FdhZXEUn65sdEJgdRGOyoiNK+HyZMjY3uN8y4DwFa3TFHuW/eRl9FZPa43I/D43XPpLBpPCpyreL+MT2RloE5q2p623/XlQsT1r7qfK1sAjaHDoA77TXr4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778143724; c=relaxed/simple; bh=e6+r/QdPR9NJFj3rUyTNdm/XmRnAt3TKg+ioKiCz1vY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=FIP11elcEjtzeyWL8SrpjOLN7DoLVz+VSGUT0YAg3OiTP1ZuKvcverYSuv+nTSIOFBQxbe5WcTBz0SjceEJnWYJAIDMMcUUZi/hS6v1FNGXuy2/EUwIwFWjw6XZPsX6RKmD/8v89lWOWYyxTUDtvmpBecYBBYFhpQ8ki9OPGLxU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=HoI2tHVc; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="HoI2tHVc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1778143722; x=1809679722; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=e6+r/QdPR9NJFj3rUyTNdm/XmRnAt3TKg+ioKiCz1vY=; b=HoI2tHVco4/aP+4c/RlVNxB3R8FFAX+u4QpuMpba9okuEIS1B6B0Isyr z5wzx5WTf5DJfdckC/Q/NSl8Z46ZXDZ0eomYgkZ7ds1PIkKKfdG+01xgV jWjJV0xOjKRu49/CEVTRaCap8LYD0cT9hH+BLK2fXHTE6Zv9Pal3hzbg8 qdEAqdFNZPmjDKh7luH2erbUEkIvsJSQjddces1/KvsT2cXyxXM8tXvle 4q8fCtyLw423tlgRCysg6tgnkk4/mEQy9shuTm2Xf1Z9Pp/QRE4dva7xy QOV/Q2dUVnvqxFPrP2xeeG8efhFmTaDjnb9V/6d2uEvslivRnLk5iMPLm w==; X-CSE-ConnectionGUID: 35bV4bnxS76SfUlFjmSmPw== X-CSE-MsgGUID: 29N9x0CYRCm9JEu96lXXaA== X-IronPort-AV: E=Sophos;i="6.23,221,1770620400"; d="scan'208";a="56385248" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 May 2026 01:48:30 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.87.71) by chn-vm-ex1.mchp-main.com (10.10.87.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.37; Thu, 7 May 2026 01:48:30 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Thu, 7 May 2026 01:48:21 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , , CC: , Conor Dooley Subject: [PATCH v6 1/5] dt-bindings: i3c: mipi-i3c-hci: add Microchip SAMA7D65 compatible Date: Thu, 7 May 2026 14:18:01 +0530 Message-ID: <20260507084805.481737-2-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260507084805.481737-1-manikandan.m@microchip.com> References: <20260507084805.481737-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the microchip,sama7d65-i3c-hci compatible string to the MIPI I3C HCI binding. The Microchip SAMA7D65 I3C controller is based on the MIPI HCI specification but requires two clocks, so add a conditional constraint when this compatible is present. Acked-by: Conor Dooley Signed-off-by: Manikandan Muralidharan Reviewed-by: Frank Li --- Changes in v5: - drop min/maxItems around clock - use else clause - cosmetic fixes Changes in v4: - Define and describe the clock in the top-level properties .../devicetree/bindings/i3c/mipi-i3c-hci.yaml | 27 ++++++++++++++++--- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml b/Docu= mentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml index 39bb1a1784c9..d488fb420945 100644 --- a/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml +++ b/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml @@ -9,9 +9,6 @@ title: MIPI I3C HCI maintainers: - Nicolas Pitre =20 -allOf: - - $ref: /schemas/i3c/i3c.yaml# - description: | MIPI I3C Host Controller Interface =20 @@ -28,9 +25,17 @@ description: | =20 properties: compatible: - const: mipi-i3c-hci + enum: + - mipi-i3c-hci + - microchip,sama7d65-i3c-hci reg: maxItems: 1 + + clocks: + items: + - description: Peripheral bus clock + - description: System Generic clock + interrupts: maxItems: 1 =20 @@ -39,6 +44,20 @@ required: - reg - interrupts =20 +allOf: + - $ref: /schemas/i3c/i3c.yaml# + - if: + properties: + compatible: + contains: + const: microchip,sama7d65-i3c-hci + then: + required: + - clocks + else: + properties: + clocks: false + unevaluatedProperties: false =20 examples: --=20 2.25.1 From nobody Sat Jun 13 13:04:18 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D41A39A7E7; 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charset="utf-8" From: Durai Manickam KR Add peripheral clock description for I3C. Signed-off-by: Durai Manickam KR Signed-off-by: Manikandan Muralidharan Reviewed-by: Claudiu Beznea --- Changes in v3: - Fixed indentation issues drivers/clk/at91/sama7d65.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c index 7dee2b160ffb..ba8ff413fa2c 100644 --- a/drivers/clk/at91/sama7d65.c +++ b/drivers/clk/at91/sama7d65.c @@ -677,6 +677,7 @@ static struct { { .n =3D "uhphs_clk", .p =3D PCK_PARENT_HW_MCK5, .id =3D 101, }, { .n =3D "dsi_clk", .p =3D PCK_PARENT_HW_MCK3, .id =3D 103, }, { .n =3D "lvdsc_clk", .p =3D PCK_PARENT_HW_MCK3, .id =3D 104, }, + { .n =3D "i3cc_clk", .p =3D PCK_PARENT_HW_MCK8, .id =3D 105, }, }; =20 /* --=20 2.25.1 From nobody Sat Jun 13 13:04:18 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95AE539A05D; Thu, 7 May 2026 08:48:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Add support for microchip sama7d65 SoC I3C HCI master only IP with additional clock support to enable bulk clock acquisition Reviewed-by: Adrian Hunter Signed-off-by: Manikandan Muralidharan --- Changes in v6: - Reorder local variable definitions in i3c_hci_probe in descending order of line length Changes in v5: - Remove HCI_QUIRK_CLK_SUPPORT quirk and call devm_clk_bulk_get_all_enabled unconditionally Changes in v4: - Remove the clock index variable MCHP_I3C_CLK_IDX Changes in v3: - Make use of existing HCI_QUIRK_* code base - Introduce HCI_QUIRK_CLK_SUPPORT to handle/enable the required Peripheral and system generic clk in bulk Changes in v2: - Platform specific changes are integrated in the existing mipi-i3c-hci driver by introducing separate MCHP_HCI_QUIRK_* quirks and vendor specific quirk files drivers/i3c/master/mipi-i3c-hci/core.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index b781dbed2165..093a85eedfcb 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -8,6 +8,7 @@ */ =20 #include +#include #include #include #include @@ -969,6 +970,7 @@ static int i3c_hci_init(struct i3c_hci *hci) static int i3c_hci_probe(struct platform_device *pdev) { const struct mipi_i3c_hci_platform_data *pdata =3D pdev->dev.platform_dat= a; + struct clk_bulk_data *clks; struct i3c_hci *hci; int irq, ret; =20 @@ -1001,6 +1003,11 @@ static int i3c_hci_probe(struct platform_device *pde= v) if (!hci->quirks && platform_get_device_id(pdev)) hci->quirks =3D platform_get_device_id(pdev)->driver_data; =20 + ret =3D devm_clk_bulk_get_all_enabled(&pdev->dev, &clks); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, + "Failed to get clocks\n"); + ret =3D i3c_hci_init(hci); if (ret) return ret; @@ -1031,6 +1038,9 @@ static void i3c_hci_remove(struct platform_device *pd= ev) =20 static const __maybe_unused struct of_device_id i3c_hci_of_match[] =3D { { .compatible =3D "mipi-i3c-hci", }, + { .compatible =3D "microchip,sama7d65-i3c-hci", + .data =3D (void *)(HCI_QUIRK_PIO_MODE | HCI_QUIRK_OD_PP_TIMING | + HCI_QUIRK_RESP_BUF_THLD) }, {}, }; MODULE_DEVICE_TABLE(of, i3c_hci_of_match); --=20 2.25.1 From nobody Sat Jun 13 13:04:18 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D608539B4BE; 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charset="utf-8" From: Durai Manickam KR Add I3C controller for sama7d65 SoC. Signed-off-by: Durai Manickam KR Signed-off-by: Manikandan Muralidharan --- Changes in v3: - Remove clock-names property as driver enables the clk in bulk arch/arm/boot/dts/microchip/sama7d65.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index 67253bbc08df..ec200848c153 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -1055,5 +1055,13 @@ gic: interrupt-controller@e8c11000 { #address-cells =3D <0>; interrupt-controller; }; + + i3c: i3c@e9000000 { + compatible =3D "microchip,sama7d65-i3c-hci"; + reg =3D <0xe9000000 0x300>; + interrupts =3D ; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 105>, <&pmc PMC_TYPE_GCK 105>; + status =3D "disabled"; + }; }; }; --=20 2.25.1 From nobody Sat Jun 13 13:04:18 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DA8437B3E1; Thu, 7 May 2026 08:49:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778143754; cv=none; b=I2/0xWmuJ2XOV+CVIPtnGpFF8amT8B+bRHqaDr/yHf5zRnVJ8+8+jgQEIezH9xkex6+Qn/fj6iJco2TReTlI11C/lSjlHScYuLDV2yd93uBAHf3l7snR3Aeg3mx36xAmz3vhhVYwrxlKGl/HUr19ewU5BRhwgsRqz+c63REQXv8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778143754; c=relaxed/simple; bh=IjmyKrRs5bSU2CVMI2YglfCQfHmycQAZGSeoqpQ2FxM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=EsfRK6oCIUM/OMCQGEJw+0x7ayaFZFGyWY8Pd8xzCFLfZrGddwWRLmzt7/qDuYTy50IbvAJN1F9x131ybmI81gtkiXGMVzY8O8d7Jop2JUkiP6s7bObL52OoIo3pAYV6HbSGPAmFSRnj2FmqHFcbHy2sfVujiPoCz73zDIzoDjg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=XniS21eZ; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="XniS21eZ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1778143749; x=1809679749; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IjmyKrRs5bSU2CVMI2YglfCQfHmycQAZGSeoqpQ2FxM=; b=XniS21eZg1J6Aydjrs421BPjkWh2UcdkuxnMrKRpVrWKXntzTLgaT9Gq n/lPupHRSObyWPrk8BozHB251NPM+FAXAjRHWrFQjJS7bmdfaQnz1BP1n HDCz/asokJ4xFzCP26vw0Z32Ng2sCJZVRDMkyxIT2il5JAuqVeSR1004K DNhoVD6Anok/5ehAQArAoKls1LxTkJms/I8PbuEK3hwd8E8v/GAnotb/h XQvGlGmwU43O/Q7Co5dnXyVSStXvyr0xvuU09x/XJT+L0hqX0bvfDosUK UUcMpeGWOnRfKzUoA4AEqGKOTBrIsTBwKZKUE6vHl8SE2R5QDq4kVHb3X w==; X-CSE-ConnectionGUID: 5g54zo4oSXqjCAVENxCvvA== X-CSE-MsgGUID: MISv4/VQQWmMAERkCqQgxg== X-IronPort-AV: E=Sophos;i="6.23,221,1770620400"; d="scan'208";a="65430976" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 07 May 2026 01:49:04 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Thu, 7 May 2026 01:49:05 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Thu, 7 May 2026 01:48:57 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v6 5/5] ARM: configs: at91: sama7: add sama7d65 i3c-hci Date: Thu, 7 May 2026 14:18:05 +0530 Message-ID: <20260507084805.481737-6-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260507084805.481737-1-manikandan.m@microchip.com> References: <20260507084805.481737-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable the configs needed for I3C framework and microchip sama7d65 i3c-hci driver. Signed-off-by: Durai Manickam KR Signed-off-by: Manikandan Muralidharan Reviewed-by: Claudiu Beznea --- arch/arm/configs/sama7_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/sama7_defconfig b/arch/arm/configs/sama7_defc= onfig index e52f671ccec4..6470c7d3fe8a 100644 --- a/arch/arm/configs/sama7_defconfig +++ b/arch/arm/configs/sama7_defconfig @@ -117,6 +117,8 @@ CONFIG_HW_RANDOM=3Dy CONFIG_I2C=3Dy CONFIG_I2C_CHARDEV=3Dy CONFIG_I2C_AT91=3Dy +CONFIG_I3C=3Dy +CONFIG_MIPI_I3C_HCI=3Dy CONFIG_SPI=3Dy CONFIG_SPI_ATMEL=3Dy CONFIG_SPI_ATMEL_QUADSPI=3Dy --=20 2.25.1