From nobody Sat Jun 13 13:01:42 2026 Received: from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net [52.237.72.81]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0A225386555; Thu, 7 May 2026 08:32:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=52.237.72.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778142738; cv=none; b=ULuaH5kPJGSzxSEY8r87Pndj2R6dY8anSV0yTDDG9h5zlR3ALwuvu6isjQX2IGqm5cl/eqmGFzjZvNEeZ4chrxz0CPMPeokNY/7G30tm1mPIwyd0StV/NimYx24Dev2ZEzw45oTbo5exYEIvp0e/3QJEMBSSVHPM6CeItH8V9Sk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778142738; c=relaxed/simple; bh=kZNz8D4IGT+eFY2JcP2OOApgEMNiuDGxKcaZxPVSL3U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Yn4RV1OYQu5z0H6AQnWoKDfbRyRImKbRK1RM0HgbYzMIuHnc6EFGfve6MI7BC547SFsHkq//1cMqmPFCCz+4J+ZW9ZQDWxN2ZRb0Ts4sigfIzyNNAiftpkZ256YvXjV1jZYyku0mcWfnaFgngAyooIZoX56ofOmLMUgXBnUtDsU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com; spf=pass smtp.mailfrom=eswincomputing.com; arc=none smtp.client-ip=52.237.72.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from E0004057DT.eswin.cn (unknown [10.11.96.26]) by app1 (Coremail) with SMTP id TAJkCgC3THH6TfxpQ34XAA--.24500S2; Thu, 07 May 2026 16:31:55 +0800 (CST) From: lizhi2@eswincomputing.com To: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, rmk+kernel@armlinux.org.uk, maxime.chevallier@bootlin.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Cc: ningyu@eswincomputing.com, linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com, pritesh.patel@einfochips.com, weishangjuan@eswincomputing.com, Zhi Li Subject: [PATCH net v1 1/2] dt-bindings: ethernet: eswin: refine delay model and HSP register description Date: Thu, 7 May 2026 16:31:36 +0800 Message-ID: <20260507083136.175-1-lizhi2@eswincomputing.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260507083037.152-1-lizhi2@eswincomputing.com> References: <20260507083037.152-1-lizhi2@eswincomputing.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: TAJkCgC3THH6TfxpQ34XAA--.24500S2 X-Coremail-Antispam: 1UD129KBjvJXoWxuw1DAryxXw48KFyUGry5twb_yoW7ury7pa y5CrW5Grn8Xr4fWanrtw109ryaqan3WF43Cr18Jr97Xan09F9Yqr13tFy5Xa4UCrWxZFyU urZ0ga1rZ34qk3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBv14x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2 Y2ka0xkIwI1lw4CEc2x0rVAKj4xxMxkF7I0En4kS14v26r4a6rW5MxkIecxEwVCm-wCF04 k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18 MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr4 1lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l IxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4 A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0pRuHqcUUUUU= X-CM-SenderInfo: xol2xx2s6h245lqf0zpsxwx03jof0z/ Content-Type: text/plain; charset="utf-8" From: Zhi Li Refine the EIC7700 Ethernet dt-binding based on observed hardware behavior and clarify the original delay model for eth0. The previous binding used an enum-based definition for rx-internal-delay-ps and tx-internal-delay-ps. Replace it with a range-based model using: - minimum: 0 - maximum: 2540 - multipleOf: 20 This better reflects the actual hardware implementation, which supports 20ps granularity delay steps in the MAC RGMII interface. The tx/rx internal delay values are clarified as MAC-side programmable delay components applied on the RGMII clock/data path, representing the effective delay seen at the MAC interface. This does not change the intended hardware semantics, but aligns the binding with the actual hardware implementation. These properties are optional and only required when MAC-side fine tuning is needed; otherwise delay alignment is provided by PHY or board design. Depending on the selected RGMII timing mode, delay alignment may be provided by the PHY (e.g. rgmii-id) or by board/MAC-side configuration. When PHY or board design already provides the required delay, these MAC-side properties may be omitted. When MAC-side fine tuning is required, they should be provided to describe the internal RGMII timing adjustment. Additionally, extend the description of the HSP subsystem register layout used by the MAC glue logic. This includes explicit TXD and RXD delay control registers to ensure deterministic initialization and to override any residual configuration potentially left by bootloaders. Add reference to the EIC7700X SoC Technical Reference Manual, Chapter 10 ("High-Speed Interface"), Part 4 for background of the HSP CSR block: https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/r= eleases There are no in-tree users of this binding, so no ABI impact is expected. Fixes: 888bd0eca93c ("dt-bindings: ethernet: eswin: Document for EIC7700 So= C") Signed-off-by: Zhi Li Acked-by tags. Acked-by: Conor Dooley --- .../bindings/net/eswin,eic7700-eth.yaml | 50 +++++++++++++------ 1 file changed, 36 insertions(+), 14 deletions(-) diff --git a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml b= /Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml index 91e8cd1db67b..fab95603bd82 100644 --- a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml +++ b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml @@ -63,16 +63,39 @@ properties: - const: stmmaceth =20 rx-internal-delay-ps: - enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400] + minimum: 0 + maximum: 2540 + multipleOf: 20 + description: + RX internal delay in picoseconds applied on the RGMII clock at the M= AC + side. The hardware supports 20 ps steps. + This property is optional and only needed when MAC-side delay tuning + is required. =20 tx-internal-delay-ps: - enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400] + minimum: 0 + maximum: 2540 + multipleOf: 20 + description: + TX internal delay in picoseconds applied on the RGMII clock at the M= AC + side. The hardware supports 20 ps steps. + This property is optional and only needed when MAC-side delay tuning + is required. =20 eswin,hsp-sp-csr: description: HSP CSR is to control and get status of different high-speed periphe= rals (such as Ethernet, USB, SATA, etc.) via register, which can tune board-level's parameters of PHY, etc. + + Additional background information about the High-Speed Subsystem + and the HSP CSR block is available in Chapter 10 ("High-Speed Interf= ace") + of the EIC7700X SoC Technical Reference Manual, Part 4 + (EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf). The manual is + publicly available at + https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-M= anual/releases + + This reference is provided for background information only. $ref: /schemas/types.yaml#/definitions/phandle-array items: - items: @@ -82,6 +105,8 @@ properties: - description: Offset of AXI clock controller Low-Power request register - description: Offset of register controlling TX/RX clock delay + - description: Offset of register controlling TXD delay + - description: Offset of register controlling RXD delay =20 required: - compatible @@ -93,8 +118,6 @@ required: - phy-mode - resets - reset-names - - rx-internal-delay-ps - - tx-internal-delay-ps - eswin,hsp-sp-csr =20 unevaluatedProperties: false @@ -104,24 +127,23 @@ examples: ethernet@50400000 { compatible =3D "eswin,eic7700-qos-eth", "snps,dwmac-5.20"; reg =3D <0x50400000 0x10000>; - clocks =3D <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>, - <&d0_clock 193>; - clock-names =3D "axi", "cfg", "stmmaceth", "tx"; interrupt-parent =3D <&plic>; interrupts =3D <61>; interrupt-names =3D "macirq"; - phy-mode =3D "rgmii-id"; - phy-handle =3D <&phy0>; + clocks =3D <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>, + <&d0_clock 193>; + clock-names =3D "axi", "cfg", "stmmaceth", "tx"; resets =3D <&reset 95>; reset-names =3D "stmmaceth"; - rx-internal-delay-ps =3D <200>; - tx-internal-delay-ps =3D <200>; - eswin,hsp-sp-csr =3D <&hsp_sp_csr 0x100 0x108 0x118>; - snps,axi-config =3D <&stmmac_axi_setup>; + eswin,hsp-sp-csr =3D <&hsp_sp_csr 0x100 0x108 0x118 0x114 0x11c>; + phy-handle =3D <&phy0>; + phy-mode =3D "rgmii-id"; snps,aal; snps,fixed-burst; snps,tso; - stmmac_axi_setup: stmmac-axi-config { + snps,axi-config =3D <&stmmac_axi_setup_gmac0>; + + stmmac_axi_setup_gmac0: stmmac-axi-config { snps,blen =3D <0 0 0 0 16 8 4>; snps,rd_osr_lmt =3D <2>; snps,wr_osr_lmt =3D <2>; --=20 2.25.1 From nobody Sat Jun 13 13:01:42 2026 Received: from zg8tmtyylji0my4xnjeumjiw.icoremail.net (zg8tmtyylji0my4xnjeumjiw.icoremail.net [162.243.161.220]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CB0903806B2; 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dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from E0004057DT.eswin.cn (unknown [10.11.96.26]) by app2 (Coremail) with SMTP id TQJkCgDX7J8QTvxpvXkXAA--.8522S2; Thu, 07 May 2026 16:32:18 +0800 (CST) From: lizhi2@eswincomputing.com To: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, rmk+kernel@armlinux.org.uk, maxime.chevallier@bootlin.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Cc: ningyu@eswincomputing.com, linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com, pritesh.patel@einfochips.com, weishangjuan@eswincomputing.com, Zhi Li Subject: [PATCH net v1 2/2] net: stmmac: eic7700: fix delay step calculation and ensure safe register initialization Date: Thu, 7 May 2026 16:32:10 +0800 Message-ID: <20260507083214.192-1-lizhi2@eswincomputing.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260507083037.152-1-lizhi2@eswincomputing.com> References: <20260507083037.152-1-lizhi2@eswincomputing.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: TQJkCgDX7J8QTvxpvXkXAA--.8522S2 X-Coremail-Antispam: 1UD129KBjvJXoW3CFW7GF4UtFyxuF13JFWDurg_yoWDWw1xpF WkAFy5tr1jqF1fG3yvyF40qa4Fkw47WF1fArZ3GFn2vF90yrn8XayjyayakF98Wry7ZF15 J3yUJFyxuF129FJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBm14x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2 Y2ka0xkIwI1lw4CEc2x0rVAKj4xxMxkF7I0En4kS14v26r4a6rW5MxkIecxEwVCm-wCF04 k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18 MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr4 1lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1U MIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I 8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjTRNSdgDUUUU X-CM-SenderInfo: xol2xx2s6h245lqf0zpsxwx03jof0z/ From: Zhi Li Fix several issues in the EIC7700 DWMAC glue driver related to delay configuration and register initialization. The hardware implements TX/RX delay with a granularity of 20 ps per step, but the driver previously assumed a 100 ps step. Update the definitions to match the actual hardware behaviour and align with the binding constraints. Introduce explicit definitions for the maximum programmable delay range based on the hardware limits. Move HSP CSR configuration into the initialization path after clocks are enabled. This ensures that all register accesses occur with the required clocks active, avoiding undefined behaviour. Clear the TXD and RXD delay control registers during initialization to override any residual configuration left by the bootloader. This ensures deterministic RGMII timing and prevents unintended delay being applied. The MAC RGMII delay programming is only required for 100Mbps and 1000Mbps modes, where precise clock-to-data alignment is necessary for reliable sampling. For 10Mbps operation, timing margins are sufficiently relaxed and no additional delay compensation is required. In this case, the driver falls back to a safe default configuration with delay disabled. For unsupported or unexpected link speeds, the driver avoids programming invalid delay values and falls back to a safe default state by explicitly clearing the delay configuration. Explicitly programming zero ensures that no residual delay settings from previous configurations or bootloader state remain active. These changes fix incorrect delay programming and initialization ordering for existing users. This also aligns the driver implementation with the updated device tree binding. Fixes: ea77dbbdbc4e ("net: stmmac: add Eswin EIC7700 glue driver") Signed-off-by: Zhi Li --- .../ethernet/stmicro/stmmac/dwmac-eic7700.c | 154 +++++++++++++----- 1 file changed, 112 insertions(+), 42 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c b/drivers/= net/ethernet/stmicro/stmmac/dwmac-eic7700.c index bcb8e000e720..0f1c62062797 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c @@ -28,20 +28,31 @@ =20 /* * TX/RX Clock Delay Bit Masks: - * - TX Delay: bits [14:8] =E2=80=94 TX_CLK delay (unit: 0.1ns per bit) - * - RX Delay: bits [30:24] =E2=80=94 RX_CLK delay (unit: 0.1ns per bit) + * - TX Delay: bits [14:8] =E2=80=94 TX_CLK delay (unit: 0.02ns per bit) + * - RX Delay: bits [30:24] =E2=80=94 RX_CLK delay (unit: 0.02ns per bit) */ #define EIC7700_ETH_TX_ADJ_DELAY GENMASK(14, 8) #define EIC7700_ETH_RX_ADJ_DELAY GENMASK(30, 24) =20 -#define EIC7700_MAX_DELAY_UNIT 0x7F +#define EIC7700_MAX_DELAY_STEPS 0x7F +#define EIC7700_DELAY_STEP_PS 20 +#define EIC7700_MAX_DELAY_PS \ + (EIC7700_MAX_DELAY_STEPS * EIC7700_DELAY_STEP_PS) =20 static const char * const eic7700_clk_names[] =3D { "tx", "axi", "cfg", }; =20 struct eic7700_qos_priv { + struct device *dev; struct plat_stmmacenet_data *plat_dat; + struct regmap *eic7700_hsp_regmap; + u32 eth_axi_lp_ctrl_offset; + u32 eth_phy_ctrl_offset; + u32 eth_txd_offset; + u32 eth_clk_offset; + u32 eth_rxd_offset; + u32 eth_clk_dly_param; }; =20 static int eic7700_clks_config(void *priv, bool enabled) @@ -61,8 +72,28 @@ static int eic7700_clks_config(void *priv, bool enabled) static int eic7700_dwmac_init(struct device *dev, void *priv) { struct eic7700_qos_priv *dwc =3D priv; + int ret; + + ret =3D eic7700_clks_config(dwc, true); + if (ret) + return ret; + + ret =3D regmap_set_bits(dwc->eic7700_hsp_regmap, + dwc->eth_phy_ctrl_offset, + EIC7700_ETH_TX_CLK_SEL | + EIC7700_ETH_PHY_INTF_SELI); + if (ret) { + eic7700_clks_config(dwc, false); + return ret; + } + + regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_axi_lp_ctrl_offset, + EIC7700_ETH_CSYSREQ_VAL); + + regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_txd_offset, 0); + regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_rxd_offset, 0); =20 - return eic7700_clks_config(dwc, true); + return 0; } =20 static void eic7700_dwmac_exit(struct device *dev, void *priv) @@ -88,18 +119,38 @@ static int eic7700_dwmac_resume(struct device *dev, vo= id *priv) return ret; } =20 +static void eic7700_dwmac_fix_speed(void *priv, phy_interface_t interface, + int speed, unsigned int mode) +{ + struct eic7700_qos_priv *dwc =3D (struct eic7700_qos_priv *)priv; + bool needs_calibration =3D false; + + switch (speed) { + case SPEED_1000: + case SPEED_100: + needs_calibration =3D true; + fallthrough; + case SPEED_10: + break; + default: + dev_err(dwc->dev, "invalid speed %u\n", speed); + break; + } + + if (needs_calibration) { + regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_clk_offset, + dwc->eth_clk_dly_param); + } else { + regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_clk_offset, 0); + } +} + static int eic7700_dwmac_probe(struct platform_device *pdev) { struct plat_stmmacenet_data *plat_dat; struct stmmac_resources stmmac_res; struct eic7700_qos_priv *dwc_priv; - struct regmap *eic7700_hsp_regmap; - u32 eth_axi_lp_ctrl_offset; - u32 eth_phy_ctrl_offset; - u32 eth_phy_ctrl_regset; - u32 eth_rxd_dly_offset; - u32 eth_dly_param =3D 0; - u32 delay_ps; + u32 delay_ps, val; int i, ret; =20 ret =3D stmmac_get_platform_resources(pdev, &stmmac_res); @@ -116,70 +167,88 @@ static int eic7700_dwmac_probe(struct platform_device= *pdev) if (!dwc_priv) return -ENOMEM; =20 + dwc_priv->dev =3D &pdev->dev; + /* Read rx-internal-delay-ps and update rx_clk delay */ if (!of_property_read_u32(pdev->dev.of_node, "rx-internal-delay-ps", &delay_ps)) { - u32 val =3D min(delay_ps / 100, EIC7700_MAX_DELAY_UNIT); + if (delay_ps % EIC7700_DELAY_STEP_PS) + return dev_err_probe(&pdev->dev, -EINVAL, + "rx delay must be multiple of %dps\n", + EIC7700_DELAY_STEP_PS); =20 - eth_dly_param &=3D ~EIC7700_ETH_RX_ADJ_DELAY; - eth_dly_param |=3D FIELD_PREP(EIC7700_ETH_RX_ADJ_DELAY, val); - } else { - return dev_err_probe(&pdev->dev, -EINVAL, - "missing required property rx-internal-delay-ps\n"); + if (delay_ps > EIC7700_MAX_DELAY_PS) + return dev_err_probe(&pdev->dev, -EINVAL, + "rx delay out of range\n"); + + val =3D delay_ps / EIC7700_DELAY_STEP_PS; + + dwc_priv->eth_clk_dly_param &=3D ~EIC7700_ETH_RX_ADJ_DELAY; + dwc_priv->eth_clk_dly_param |=3D + FIELD_PREP(EIC7700_ETH_RX_ADJ_DELAY, val); } =20 /* Read tx-internal-delay-ps and update tx_clk delay */ if (!of_property_read_u32(pdev->dev.of_node, "tx-internal-delay-ps", &delay_ps)) { - u32 val =3D min(delay_ps / 100, EIC7700_MAX_DELAY_UNIT); + if (delay_ps % EIC7700_DELAY_STEP_PS) + return dev_err_probe(&pdev->dev, -EINVAL, + "tx delay must be multiple of %dps\n", + EIC7700_DELAY_STEP_PS); =20 - eth_dly_param &=3D ~EIC7700_ETH_TX_ADJ_DELAY; - eth_dly_param |=3D FIELD_PREP(EIC7700_ETH_TX_ADJ_DELAY, val); - } else { - return dev_err_probe(&pdev->dev, -EINVAL, - "missing required property tx-internal-delay-ps\n"); + if (delay_ps > EIC7700_MAX_DELAY_PS) + return dev_err_probe(&pdev->dev, -EINVAL, + "tx delay out of range\n"); + + val =3D delay_ps / EIC7700_DELAY_STEP_PS; + + dwc_priv->eth_clk_dly_param &=3D ~EIC7700_ETH_TX_ADJ_DELAY; + dwc_priv->eth_clk_dly_param |=3D + FIELD_PREP(EIC7700_ETH_TX_ADJ_DELAY, val); } =20 - eic7700_hsp_regmap =3D syscon_regmap_lookup_by_phandle(pdev->dev.of_node, - "eswin,hsp-sp-csr"); - if (IS_ERR(eic7700_hsp_regmap)) + dwc_priv->eic7700_hsp_regmap =3D + syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "eswin,hsp-sp-csr"); + if (IS_ERR(dwc_priv->eic7700_hsp_regmap)) return dev_err_probe(&pdev->dev, - PTR_ERR(eic7700_hsp_regmap), + PTR_ERR(dwc_priv->eic7700_hsp_regmap), "Failed to get hsp-sp-csr regmap\n"); =20 ret =3D of_property_read_u32_index(pdev->dev.of_node, "eswin,hsp-sp-csr", - 1, ð_phy_ctrl_offset); + 1, &dwc_priv->eth_phy_ctrl_offset); if (ret) return dev_err_probe(&pdev->dev, ret, "can't get eth_phy_ctrl_offset\n"); =20 - regmap_read(eic7700_hsp_regmap, eth_phy_ctrl_offset, - ð_phy_ctrl_regset); - eth_phy_ctrl_regset |=3D - (EIC7700_ETH_TX_CLK_SEL | EIC7700_ETH_PHY_INTF_SELI); - regmap_write(eic7700_hsp_regmap, eth_phy_ctrl_offset, - eth_phy_ctrl_regset); - ret =3D of_property_read_u32_index(pdev->dev.of_node, "eswin,hsp-sp-csr", - 2, ð_axi_lp_ctrl_offset); + 2, &dwc_priv->eth_axi_lp_ctrl_offset); if (ret) return dev_err_probe(&pdev->dev, ret, "can't get eth_axi_lp_ctrl_offset\n"); =20 - regmap_write(eic7700_hsp_regmap, eth_axi_lp_ctrl_offset, - EIC7700_ETH_CSYSREQ_VAL); + ret =3D of_property_read_u32_index(pdev->dev.of_node, + "eswin,hsp-sp-csr", + 3, &dwc_priv->eth_clk_offset); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "can't get eth_clk_offset\n"); =20 ret =3D of_property_read_u32_index(pdev->dev.of_node, "eswin,hsp-sp-csr", - 3, ð_rxd_dly_offset); + 4, &dwc_priv->eth_txd_offset); if (ret) return dev_err_probe(&pdev->dev, ret, - "can't get eth_rxd_dly_offset\n"); + "can't get eth_txd_offset\n"); =20 - regmap_write(eic7700_hsp_regmap, eth_rxd_dly_offset, - eth_dly_param); + ret =3D of_property_read_u32_index(pdev->dev.of_node, + "eswin,hsp-sp-csr", + 5, &dwc_priv->eth_rxd_offset); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "can't get eth_rxd_offset\n"); =20 plat_dat->num_clks =3D ARRAY_SIZE(eic7700_clk_names); plat_dat->clks =3D devm_kcalloc(&pdev->dev, @@ -208,6 +277,7 @@ static int eic7700_dwmac_probe(struct platform_device *= pdev) plat_dat->exit =3D eic7700_dwmac_exit; plat_dat->suspend =3D eic7700_dwmac_suspend; plat_dat->resume =3D eic7700_dwmac_resume; + plat_dat->fix_mac_speed =3D eic7700_dwmac_fix_speed; =20 return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); } --=20 2.25.1