From nobody Sat Jun 13 13:41:38 2026 Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DE9034E763; Thu, 7 May 2026 08:18:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778141894; cv=none; b=kvlLST2RjY1Q9SScQcVfqXSR++S68db3l0H5xYAVpLwht8Ekhrwovg+FZPnVt6DdlxlxbB+jxdwUEJzNYjYeNSylp540B4YloNpHbcyJd4MDWj4c9Qk75A3pXwMIALlJTtx1sl3d4PteBa6PShekkX9BVw5o5mX9+ldkQQt1fPM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778141894; c=relaxed/simple; bh=mL0t1GQDP3kEjnk3ZWV8xHn31sIE9uW+kqlS8Sf1Awg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=g5G/hRdNSWE+Evjp+M7B+ZRMwrD+pwDaA4+HNJ19W4XBDpmVOuqepOz/h46n2YFxP+upmInGA93fKfhmdHaIb/B3wclxU9TB/DsU2anvU1PWEMVAEHxAiLR7Fq8fYRU0NZ4Y9IUl9VlQ+T6R89WlYXXRKPxmpbVPXtTTp2QW5Pg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.100.82]) by APP-03 (Coremail) with SMTP id rQCowAC3m+KLSvxpI_pNEA--.42168S3; Thu, 07 May 2026 16:17:19 +0800 (CST) From: Icenowy Zheng To: Drew Fustini , Guo Ren , Fu Wei , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Neil Armstrong , Greg Kroah-Hartman , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jisheng Zhang Cc: Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-phy@lists.infradead.org, linux-usb@vger.kernel.org, Icenowy Zheng , Han Gao , Yao Zi , Icenowy Zheng Subject: [PATCH 01/12] dt-bindings: clock: thead: add TH1520 MISC subsys clock controller Date: Thu, 7 May 2026 16:16:59 +0800 Message-ID: <20260507081710.4090814-2-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260507081710.4090814-1-zhengxingda@iscas.ac.cn> References: <20260507081710.4090814-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: rQCowAC3m+KLSvxpI_pNEA--.42168S3 X-Coremail-Antispam: 1UD129KBjvJXoW7Kw13Ww4xJw4xCF4rCw1fXrb_yoW8Zw4kp3 9xAFW8tF4vvFZ3Ww4xt3Z2kwsrWFWkWFnxta1UCFyIy3WSgF1ftayagF4jgFyfJFWxAF9r uF1jgr4fZry2kw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmY14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Ar0_tr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4UJw A2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2kIc2 xKxwCY1x0262kKe7AKxVW8ZVWrXwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWU JVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67 kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY 6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42 IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIev Ja73UjIFyTuYvjTRMfOzDUUUU X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" TH1520 has a subsystem clock controller called MISC_SUBSYS in its manual, mainly controlling clocks for USB and MMC/SD in non-TEE environment. Add device tree binding for it. Signed-off-by: Icenowy Zheng Acked-by: Conor Dooley Reviewed-by: Drew Fustini --- .../devicetree/bindings/clock/thead,th1520-clk-ap.yaml | 5 +++-- include/dt-bindings/clock/thead,th1520-clk-ap.h | 10 ++++++++++ 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.ya= ml b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml index 9d058c00ab3d5..d46d13597466f 100644 --- a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml +++ b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml @@ -23,6 +23,7 @@ properties: compatible: enum: - thead,th1520-clk-ap + - thead,th1520-clk-misc - thead,th1520-clk-vo =20 reg: @@ -32,8 +33,8 @@ properties: items: - description: | One input clock: - - For "thead,th1520-clk-ap": the clock input must be the 24 MHz - main oscillator. + - For "thead,th1520-clk-ap" and "thead,th1520-clk-misc": the clo= ck + input must be the 24 MHz main oscillator. - For "thead,th1520-clk-vo": the clock input must be the VIDEO_P= LL, which is configured by the AP clock controller. According to t= he TH1520 manual, VIDEO_PLL is a Silicon Creations Sigma-Delta PLL diff --git a/include/dt-bindings/clock/thead,th1520-clk-ap.h b/include/dt-b= indings/clock/thead,th1520-clk-ap.h index 68b35cc612041..642c2a69a5797 100644 --- a/include/dt-bindings/clock/thead,th1520-clk-ap.h +++ b/include/dt-bindings/clock/thead,th1520-clk-ap.h @@ -128,4 +128,14 @@ #define CLK_MIPIDSI1_PIXCLK 29 #define CLK_HDMI_PIXCLK 30 =20 +/* MISC clocks */ +#define CLK_MISCSYS_ACLK 0 +#define CLK_USB 1 +#define CLK_USB_CTL_REF 2 +#define CLK_USB_PHY_REF 3 +#define CLK_USB_SUSPEND 4 +#define CLK_EMMC 5 +#define CLK_SDIO0 6 +#define CLK_SDIO1 7 + #endif --=20 2.52.0 From nobody Sat Jun 13 13:41:38 2026 Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF47A34B669; Thu, 7 May 2026 08:18:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778141894; cv=none; b=qtffwow4V/b57JAv6X4zlx5hy9MUgUWeLcE7KA4NOi5z2fKcKkaGoaSaj1ZGExRXdrlECTd4nbvS/tsnYnl/lUnWM5EQDTXso82KKaMaCks2RGmTMLPHAWSzxFZvx2crfdspf/HA/mgzDnERlTByfT7hv24odw4fxwy4SpwI5mM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778141894; c=relaxed/simple; bh=XYEg952b0hjEyzJ0OgEKo56+HxGgDbQSdgBO/pbUnIM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=n64Bz0jlv0BkNjLR9yy5oJczHYaIjHm7oz0zNtlF/UB6AIzrqsQ5m5QM2PgqKnl/ocJXcnyGwuukwFgCKitM+qxr9CNDCLUOqgmPlfwPqa+YQ3MHxpOpaHZIp5ruDGjm3kJp/+SXT1A9QUmgKW+kUJL9x0AQfstmRh9Q9IZYigA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.100.82]) by APP-03 (Coremail) with SMTP id rQCowAC3m+KLSvxpI_pNEA--.42168S4; Thu, 07 May 2026 16:17:21 +0800 (CST) From: Icenowy Zheng To: Drew Fustini , Guo Ren , Fu Wei , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Neil Armstrong , Greg Kroah-Hartman , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jisheng Zhang Cc: Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-phy@lists.infradead.org, linux-usb@vger.kernel.org, Icenowy Zheng , Han Gao , Yao Zi , Icenowy Zheng Subject: [PATCH 02/12] clk: thead: th1520-ap: add support for MISC subsys clocks Date: Thu, 7 May 2026 16:17:00 +0800 Message-ID: <20260507081710.4090814-3-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260507081710.4090814-1-zhengxingda@iscas.ac.cn> References: <20260507081710.4090814-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: rQCowAC3m+KLSvxpI_pNEA--.42168S4 X-Coremail-Antispam: 1UD129KBjvJXoWxJFWftrW7XFW8GFWxtrWrZrb_yoWrJFyUpa yrGrWftF4kXF4rWay3Jr1IyFsxuF4SqFyqqa9rG34xKw4fWry5JFy0kayFyF4Fg34fCay7 Jrs8KrW5CFs8GFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmF14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Ar0_tr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4UJw A2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2kIc2 xKxwCY1x0262kKe7AKxVW8ZVWrXwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWU JVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67 kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY 6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42 IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r4UJVWxJrUvcSsGvfC2 KfnxnUUI43ZEXa7sRipB-tUUUUU== X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" The TH1520 SoC contains a MISC_SUBSYS clock controller, which allows controlling of USB related clocks and MMC/SD controller AHB bus clocks. Add support for this clock controller, in order to enable USB support. Signed-off-by: Icenowy Zheng Reviewed-by: Drew Fusini --- drivers/clk/thead/clk-th1520-ap.c | 64 +++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th15= 20-ap.c index 3a6847f1c950f..24f785f0b329a 100644 --- a/drivers/clk/thead/clk-th1520-ap.c +++ b/drivers/clk/thead/clk-th1520-ap.c @@ -1266,6 +1266,41 @@ static CCU_GATE(CLK_MIPIDSI1_PIXCLK, mipi_dsi1_pixcl= k, "mipi-dsi1-pixclk", static CCU_GATE(CLK_HDMI_PIXCLK, hdmi_pixclk, "hdmi-pixclk", video_pll_clk= _pd, 0x4, 0, 0); =20 +static struct clk_fixed_factor usb_suspend_div_clk =3D { + .div =3D 24, + .mult =3D 1, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("usb-suspend-div", + osc_24m_clk, + &clk_fixed_factor_ops, + 0), +}; + +static const struct clk_parent_data usb_suspend_parents[] =3D { + { .hw =3D &usb_suspend_div_clk.hw }, +}; + +static CCU_GATE(CLK_MISCSYS_ACLK, miscsys_aclk, "miscsys-aclk", axi_aclk_p= d, + 0x0, 0, CLK_IS_CRITICAL); + +static const struct clk_parent_data miscsys_aclk_pd[] =3D { + { .hw =3D &miscsys_aclk.gate.hw }, +}; + +static CCU_GATE(CLK_USB, usb_clk, "usb", miscsys_aclk_pd, 0x4, 0, + CLK_IS_CRITICAL); +static CCU_GATE(CLK_USB_CTL_REF, usb_ctl_ref_clk, "usb-ctl-ref", osc_24m_c= lk, + 0x4, 1, 0); +static CCU_GATE(CLK_USB_PHY_REF, usb_phy_ref_clk, "usb-phy-ref", osc_24m_c= lk, + 0x4, 2, 0); +static CCU_GATE(CLK_USB_SUSPEND, usb_suspend_clk, "usb-suspend", + usb_suspend_parents, 0x4, 3, 0); +static CCU_GATE(CLK_EMMC, emmc_clk, "emmc", perisys_ahb_hclk_pd, 0x8, 0, + 0); +static CCU_GATE(CLK_SDIO0, sdio0_clk, "sdio0", perisys_ahb_hclk_pd, 0xc, 0, + 0); +static CCU_GATE(CLK_SDIO1, sdio1_clk, "sdio1", perisys_ahb_hclk_pd, 0x10, = 0, + 0); + static CLK_FIXED_FACTOR_HW(gmac_pll_clk_100m, "gmac-pll-clk-100m", &gmac_pll_clk.common.hw, 10, 1, 0); =20 @@ -1410,6 +1445,17 @@ static struct ccu_gate *th1520_vo_gate_clks[] =3D { &hdmi_pixclk }; =20 +static struct ccu_gate *th1520_misc_gate_clks[] =3D { + &miscsys_aclk, + &usb_clk, + &usb_ctl_ref_clk, + &usb_phy_ref_clk, + &usb_suspend_clk, + &emmc_clk, + &sdio0_clk, + &sdio1_clk +}; + static const struct regmap_config th1520_clk_regmap_config =3D { .reg_bits =3D 32, .val_bits =3D 32, @@ -1451,6 +1497,14 @@ static const struct th1520_plat_data th1520_vo_platd= ata =3D { .nr_gate_clks =3D ARRAY_SIZE(th1520_vo_gate_clks), }; =20 +static const struct th1520_plat_data th1520_misc_platdata =3D { + .th1520_gate_clks =3D th1520_misc_gate_clks, + + .nr_clks =3D CLK_SDIO1 + 1, + + .nr_gate_clks =3D ARRAY_SIZE(th1520_misc_gate_clks), +}; + /* * Maintain clock rate of c910_bus_clk below TH1520_C910_BUS_MAX_RATE (750= MHz) * when its parent, c910_clk, changes the rate. @@ -1609,6 +1663,12 @@ static int th1520_clk_probe(struct platform_device *= pdev) return ret; } =20 + if (plat_data =3D=3D &th1520_ap_platdata) { + ret =3D devm_clk_hw_register(dev, &usb_suspend_div_clk.hw); + if (ret) + return ret; + } + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, priv); if (ret) return ret; @@ -1625,6 +1685,10 @@ static const struct of_device_id th1520_clk_match[] = =3D { .compatible =3D "thead,th1520-clk-vo", .data =3D &th1520_vo_platdata, }, + { + .compatible =3D "thead,th1520-clk-misc", + .data =3D &th1520_misc_platdata, + }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, th1520_clk_match); --=20 2.52.0 From nobody Sat Jun 13 13:41:38 2026 Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 547BF31F98C; Thu, 7 May 2026 08:18:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778141895; cv=none; b=jWZ9a1P3yEcjmwTWBGF25osM71VqbStT6kiLRTr5JYVr1VGDEGxoi66DiAdnPfE3UXh98mWsfkoPiclsqgpwRtdBNm6JKI9nx72mV2+dxfQnVcL42EIx1jpRnD2QY1dhEX9vaehjt3zy4XWOL8elox6u0ifA5DRoEzzqOnQElFY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778141895; c=relaxed/simple; bh=OAfobsCoi/ZUK5Ppe1EQhmw0Gu6Uy0vOtLkIZ6UcaCc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BbO7hy/Xas2fBG+Bzw6zGxEjqas/Qk44C81Rc8XrIh7lloUhIuY/TBKPnmjNYfYkOQnyyVEHXrlzWKVd5ZFwhfu7WHLcQ75BSMyMdjQs94lA06bYJKPH+BfEiogbcElJMpQ9ta9uGAF3pNKueiJA4uNCy5OFUQoLpNtEwLNBj74= ARC-Authentication-Results: i=1; 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charset="utf-8" The MISC_SUBSYS clock controller on TH1520 SoC is a clock controller mainly controlling USB-related clocks (which isn't utilized yet) and MMC/SD controllers' AHB bus clocks. Add the device tree node for it along with the missing bus clock references for MMC/SD controllers. Signed-off-by: Icenowy Zheng --- arch/riscv/boot/dts/thead/th1520.dtsi | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index 5e91dc1d2b9b7..c9930e63bbe93 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -366,8 +366,8 @@ emmc: mmc@ffe7080000 { compatible =3D "thead,th1520-dwcmshc"; reg =3D <0xff 0xe7080000 0x0 0x10000>; interrupts =3D <62 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&clk CLK_EMMC_SDIO>; - clock-names =3D "core"; + clocks =3D <&clk CLK_EMMC_SDIO>, <&clk_misc CLK_EMMC>; + clock-names =3D "core", "bus"; status =3D "disabled"; }; =20 @@ -375,8 +375,8 @@ sdio0: mmc@ffe7090000 { compatible =3D "thead,th1520-dwcmshc"; reg =3D <0xff 0xe7090000 0x0 0x10000>; interrupts =3D <64 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&clk CLK_EMMC_SDIO>; - clock-names =3D "core"; + clocks =3D <&clk CLK_EMMC_SDIO>, <&clk_misc CLK_SDIO0>; + clock-names =3D "core", "bus"; status =3D "disabled"; }; =20 @@ -384,8 +384,8 @@ sdio1: mmc@ffe70a0000 { compatible =3D "thead,th1520-dwcmshc"; reg =3D <0xff 0xe70a0000 0x0 0x10000>; interrupts =3D <71 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&clk CLK_EMMC_SDIO>; - clock-names =3D "core"; + clocks =3D <&clk CLK_EMMC_SDIO>, <&clk_misc CLK_SDIO1>; + clock-names =3D "core", "bus"; status =3D "disabled"; }; =20 @@ -533,6 +533,13 @@ rst_misc: reset-controller@ffec02c000 { #reset-cells =3D <1>; }; =20 + clk_misc: clock-controller@ffec02c100 { + compatible =3D "thead,th1520-clk-misc"; + reg =3D <0xff 0xec02c100 0x0 0x100>; + clocks =3D <&osc>; + #clock-cells =3D <1>; + }; + rst_vp: reset-controller@ffecc30000 { compatible =3D "thead,th1520-reset-vp"; reg =3D <0xff 0xecc30000 0x0 0x14>; --=20 2.52.0 From nobody Sat Jun 13 13:41:38 2026 Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D95AF347533; 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dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.100.82]) by APP-03 (Coremail) with SMTP id rQCowAC3m+KLSvxpI_pNEA--.42168S6; Thu, 07 May 2026 16:17:25 +0800 (CST) From: Icenowy Zheng To: Drew Fustini , Guo Ren , Fu Wei , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Neil Armstrong , Greg Kroah-Hartman , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jisheng Zhang Cc: Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-phy@lists.infradead.org, linux-usb@vger.kernel.org, Icenowy Zheng , Han Gao , Yao Zi , Icenowy Zheng Subject: [PATCH 04/12] dt-bindings: phy: add binding for T-Head TH1520 USB PHY Date: Thu, 7 May 2026 16:17:02 +0800 Message-ID: <20260507081710.4090814-5-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260507081710.4090814-1-zhengxingda@iscas.ac.cn> References: <20260507081710.4090814-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: rQCowAC3m+KLSvxpI_pNEA--.42168S6 X-Coremail-Antispam: 1UD129KBjvJXoW7Kw1kZrW3uryUJFW5Ww4kWFg_yoW8tF43pa 93GFyfJFnagFn3uw4SqF10kF1ftrZ5ZF15tr12gw10gws0g3WSqa9IkFy5uF48Jr48XFW7 uF4Y9ry7KF12kw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmS14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Ar0_tr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2 kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkE bVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67 AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI 42IY6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4UJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF 4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8Jr0_Cr1UYxBI daVFxhVjvjDU0xZFpf9x0pRQJ5wUUUUU= X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" The TH1520 SoC features a Synopsys USB 3.0 FemtoPHY with some custom glue logic configuring PHY parameters. Add a binding for it. Signed-off-by: Icenowy Zheng Reviewed-by: Conor Dooley --- .../bindings/phy/thead,th1520-usb-phy.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/thead,th1520-usb-= phy.yaml diff --git a/Documentation/devicetree/bindings/phy/thead,th1520-usb-phy.yam= l b/Documentation/devicetree/bindings/phy/thead,th1520-usb-phy.yaml new file mode 100644 index 0000000000000..37f5cfb95bad0 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/thead,th1520-usb-phy.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/thead,th1520-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-Head TH1520 USB PHY + +description: | + The T-HEAD TH1520 USB PHY is a Synopsys USB 3.0 FemtoPHY glued with some + custom logic to configure PHY parameters. + +maintainers: + - Icenowy Zheng + - Wei Fu + - Drew Fustini + +properties: + compatible: + const: thead,th1520-usb-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + clocks: + items: + - description: PHY bus clock + - description: PHY reference clock + + clock-names: + items: + - const: bus + - const: ref + + resets: + items: + - description: PHY bus reset + - description: PHY reset + + reset-names: + items: + - const: bus + - const: phy + + avdd33-usb3-supply: + description: | + 3.3V power supply for the PHY, named AVDD33_USB3 in the SoC pin list. + +required: + - compatible + - "#phy-cells" + - clocks + - clock-names + - resets + - reset-names + - avdd33-usb3-supply + +additionalProperties: false + +examples: + - | + phy@ec030000 { + compatible =3D "thead,th1520-usb-phy"; + reg =3D <0xec030000 0x10000>; + #phy-cells =3D <0>; + clocks =3D <&clk_misc 1>, <&clk_misc 3>; + clock-names =3D "bus", "ref"; + resets =3D <&rst_misc 6>, <&rst_misc 7>; + reset-names =3D "bus", "phy"; + avdd33-usb3-supply =3D <&avdd33_usb3>; + }; --=20 2.52.0 From nobody Sat Jun 13 13:41:38 2026 Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A6D4346FCA; Thu, 7 May 2026 08:18:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778141897; cv=none; b=GtlALXLkY2NFMjvO+QsHs9FrI2lAPeE23EdCF+VJRJIzhE7uUvjegJlRreBOlyAhzNuiaCerImbvnmCB2/XP1eSjUtNlmbfylrEZlI9zW7hKs6FSehb4jK1Iv5on8nSs7prOo5uIWMv9i4YukwFAlZ6jgOpVFkf0MjZ59NS9pqA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778141897; c=relaxed/simple; bh=slz3b5E8oY2N7lAmYCiFN9uRLmSreujaw7K4jRu0oiM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EjErmu3roSiwKt+PE4q8wrbeVASbBcEwZcPQBr+0iDwsjY6v/7SuniUdIdaXP/V8hHXtrOeT/D9BzLjsK2xSd6pYhrR0T3TKeNg7qMMlHjlDQ/Jl6qlFX6bNYLB/e+RLzgMstnWrc3MxekPn3urn99SmCu/aiITdZ9OWCEGvgbQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.100.82]) by APP-03 (Coremail) with SMTP id rQCowAC3m+KLSvxpI_pNEA--.42168S7; Thu, 07 May 2026 16:17:26 +0800 (CST) From: Icenowy Zheng To: Drew Fustini , Guo Ren , Fu Wei , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Neil Armstrong , Greg Kroah-Hartman , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jisheng Zhang Cc: Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-phy@lists.infradead.org, linux-usb@vger.kernel.org, Icenowy Zheng , Han Gao , Yao Zi , Icenowy Zheng Subject: [PATCH 05/12] phy: add a driver for T-Head TH1520 USB PHY Date: Thu, 7 May 2026 16:17:03 +0800 Message-ID: <20260507081710.4090814-6-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260507081710.4090814-1-zhengxingda@iscas.ac.cn> References: <20260507081710.4090814-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: rQCowAC3m+KLSvxpI_pNEA--.42168S7 X-Coremail-Antispam: 1UD129KBjvJXoW3Xr15uw17tFW3KrWxJw4Dtwb_yoW3Zw1xpa nxAFWFyr4ktFsxWw4xJw1UCFWSqa17t34aqry7W3WfZFy3JryrXas8WFW5ZryvvFs7ZrW3 tr95GFW7CF17JwUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmS14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Ar0_tr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2 kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkE bVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67 AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUCVW8JwCI 42IY6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4UJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF 4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8Jr0_Cr1UYxBI daVFxhVjvjDU0xZFpf9x0pRQJ5wUUUUU= X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" The USB PHY on T-Head TH1520 SoC is a Synopsys USB 3.0 FemtoPHY, with some PHY parameters exported as another system controller along with it. As a few PHY parameters' default value isn't ready to work, add a driver configuring them before letting the PHY run, in addition to clock/reset/regulator management. Signed-off-by: Icenowy Zheng --- drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/thead/Kconfig | 12 ++ drivers/phy/thead/Makefile | 2 + drivers/phy/thead/phy-th1520-usb.c | 197 +++++++++++++++++++++++++++++ 5 files changed, 213 insertions(+) create mode 100644 drivers/phy/thead/Kconfig create mode 100644 drivers/phy/thead/Makefile create mode 100644 drivers/phy/thead/phy-th1520-usb.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 227b9a4c612e8..ea1a52e14b839 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -164,6 +164,7 @@ source "drivers/phy/st/Kconfig" source "drivers/phy/starfive/Kconfig" source "drivers/phy/sunplus/Kconfig" source "drivers/phy/tegra/Kconfig" +source "drivers/phy/thead/Kconfig" source "drivers/phy/ti/Kconfig" source "drivers/phy/xilinx/Kconfig" =20 diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index f49d83f00a3d8..4604522548c91 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -48,5 +48,6 @@ obj-$(CONFIG_GENERIC_PHY) +=3D allwinner/ \ starfive/ \ sunplus/ \ tegra/ \ + thead/ \ ti/ \ xilinx/ diff --git a/drivers/phy/thead/Kconfig b/drivers/phy/thead/Kconfig new file mode 100644 index 0000000000000..14012db5973c4 --- /dev/null +++ b/drivers/phy/thead/Kconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only +config PHY_TH1520_USB + tristate "USB PHY driver for T-Head TH1520 SoC" + depends on ARCH_THEAD || COMPILE_TEST + depends on COMMON_CLK + depends on HAS_IOMEM + depends on OF + depends on RESET_CONTROLLER + select GENERIC_PHY + default ARCH_THEAD + help + Enable support for the USB PHY on the T-Head TH1520 SoC. diff --git a/drivers/phy/thead/Makefile b/drivers/phy/thead/Makefile new file mode 100644 index 0000000000000..5b459bc7004bd --- /dev/null +++ b/drivers/phy/thead/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_PHY_TH1520_USB) +=3D phy-th1520-usb.o diff --git a/drivers/phy/thead/phy-th1520-usb.c b/drivers/phy/thead/phy-th1= 520-usb.c new file mode 100644 index 0000000000000..c87bd779bbb74 --- /dev/null +++ b/drivers/phy/thead/phy-th1520-usb.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Institute of Software, Chinese Academy of Sciences (= ISCAS) + * + * Authors: + * Icenowy Zheng + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define USB_SYSCON_OFFSET 0xf000 + +/* All the below registers are in the USB syscon region */ +#define USB_CLK_GATE_STS 0x0 +#define USB_LOGIC_ANALYZER_TRACE_STS0 0x4 +#define USB_LOGIC_ANALYZER_TRACE_STS1 0x8 +#define USB_GPIO 0xc +#define USB_DEBUG_STS0 0x10 +#define USB_DEBUG_STS1 0x14 +#define USB_DEBUG_STS2 0x18 +#define USBCTL_CLK_CTRL0 0x1c +#define USBPHY_CLK_CTRL1 0x20 +#define USBPHY_TEST_CTRL0 0x24 +#define USBPHY_TEST_CTRL1 0x28 +#define USBPHY_TEST_CTRL2 0x2c +#define USBPHY_TEST_CTRL3 0x30 +#define USB_SSP_EN 0x34 +#define USB_HADDR_SEL 0x38 +#define USB_SYS 0x3c +#define USB_HOST_STATUS 0x40 +#define USB_HOST_CTRL 0x44 +#define USBPHY_HOST_CTRL 0x48 +#define USBPHY_HOST_STATUS 0x4c +#define USB_TEST_REG0 0x50 +#define USB_TEST_REG1 0x54 +#define USB_TEST_REG2 0x58 +#define USB_TEST_REG3 0x5c + +#define USB_SYS_COMMONONN BIT(0) + +#define USB_SSP_EN_REF_SSP_EN BIT(0) + +struct th1520_usb_phy { + struct platform_device *pdev; + struct phy *phy; + struct regmap *regmap; + struct clk *ref_clk; + struct reset_control *phy_reset; +}; + +static int th1520_usb_phy_init(struct phy *phy) +{ + struct th1520_usb_phy *th1520_phy =3D phy_get_drvdata(phy); + int ret; + + ret =3D clk_prepare_enable(th1520_phy->ref_clk); + if (ret) + return ret; + + ret =3D reset_control_assert(th1520_phy->phy_reset); + if (ret) + goto err_disable_clk; + + /* + * Do some initial PHY setup: + * - Set COMMONONN to allow the PHY to automatically power down. + * - Set REF_SSP_EN to enable feeding reference clock to SuperSpeed + * PHY clock PLL. + */ + regmap_set_bits(th1520_phy->regmap, USB_SYS, USB_SYS_COMMONONN); + regmap_set_bits(th1520_phy->regmap, USB_SSP_EN, USB_SSP_EN_REF_SSP_EN); + + ret =3D reset_control_deassert(th1520_phy->phy_reset); + if (ret) + goto err_disable_clk; + + udelay(10); + + return 0; + +err_disable_clk: + clk_disable_unprepare(th1520_phy->ref_clk); + return ret; +} + +static int th1520_usb_phy_exit(struct phy *phy) +{ + struct th1520_usb_phy *th1520_phy =3D phy_get_drvdata(phy); + int ret; + + ret =3D reset_control_assert(th1520_phy->phy_reset); + if (ret) + return ret; + + clk_disable_unprepare(th1520_phy->ref_clk); + + return 0; +} + +static const struct phy_ops th1520_usb_phy_ops =3D { + .init =3D th1520_usb_phy_init, + .exit =3D th1520_usb_phy_exit, + .owner =3D THIS_MODULE, +}; + +static const struct regmap_config phy_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .max_register =3D USB_TEST_REG3, +}; + +static int th1520_usb_phy_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + struct device *dev =3D &pdev->dev; + struct th1520_usb_phy *th1520_phy; + struct reset_control *bus_reset; + void __iomem *base; + int ret; + + th1520_phy =3D devm_kzalloc(dev, sizeof(*th1520_phy), GFP_KERNEL); + if (!th1520_phy) + return -ENOMEM; + + th1520_phy->pdev =3D pdev; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + th1520_phy->ref_clk =3D devm_clk_get(dev, "ref"); + if (IS_ERR(th1520_phy->ref_clk)) + return PTR_ERR(th1520_phy->ref_clk); + + /* De-assert the bus reset and leave it that way */ + bus_reset =3D devm_reset_control_get_exclusive_deasserted(dev, "bus"); + if (IS_ERR(bus_reset)) + return PTR_ERR(bus_reset); + + th1520_phy->phy_reset =3D devm_reset_control_get_exclusive(dev, "phy"); + if (IS_ERR(th1520_phy->phy_reset)) + return PTR_ERR(th1520_phy->phy_reset); + + /* + * Schematics of several boards (Lichee Module 4A/Milk-V Meles) + * describe this power rail as always-on. + */ + ret =3D devm_regulator_get_enable(dev, "avdd33-usb3"); + if (ret) + return ret; + + th1520_phy->regmap =3D devm_regmap_init_mmio_clk(dev, "bus", + base + USB_SYSCON_OFFSET, + &phy_regmap_config); + if (IS_ERR(th1520_phy->regmap)) + return dev_err_probe(dev, PTR_ERR(th1520_phy->regmap), + "Failed to init regmap\n"); + + th1520_phy->phy =3D devm_phy_create(dev, dev->of_node, &th1520_usb_phy_op= s); + if (IS_ERR(th1520_phy->phy)) { + dev_err(dev, "failed to create PHY\n"); + return PTR_ERR(th1520_phy->phy); + } + + phy_set_drvdata(th1520_phy->phy, th1520_phy); + + phy_provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id th1520_usb_phy_of_table[] =3D { + { .compatible =3D "thead,th1520-usb-phy" }, + { } +}; +MODULE_DEVICE_TABLE(of, th1520_usb_phy_of_table); + +static struct platform_driver th1520_usb_phy_driver =3D { + .driver =3D { + .name =3D "th1520-usb-phy", + .of_match_table =3D th1520_usb_phy_of_table, + }, + .probe =3D th1520_usb_phy_probe, +}; + +module_platform_driver(th1520_usb_phy_driver); + +MODULE_DESCRIPTION("T-Head TH1520 USB PHY driver"); +MODULE_LICENSE("GPL"); --=20 2.52.0 From nobody Sat Jun 13 13:41:38 2026 Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4085A348896; Thu, 7 May 2026 08:18:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.100.82]) by APP-03 (Coremail) with SMTP id rQCowAC3m+KLSvxpI_pNEA--.42168S8; Thu, 07 May 2026 16:17:28 +0800 (CST) From: Icenowy Zheng To: Drew Fustini , Guo Ren , Fu Wei , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Neil Armstrong , Greg Kroah-Hartman , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jisheng Zhang Cc: Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-phy@lists.infradead.org, linux-usb@vger.kernel.org, Icenowy Zheng , Han Gao , Yao Zi , Icenowy Zheng Subject: [PATCH 06/12] riscv: dts: thead: add device nodes for USB Date: Thu, 7 May 2026 16:17:04 +0800 Message-ID: <20260507081710.4090814-7-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260507081710.4090814-1-zhengxingda@iscas.ac.cn> References: <20260507081710.4090814-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: rQCowAC3m+KLSvxpI_pNEA--.42168S8 X-Coremail-Antispam: 1UD129KBjvJXoW7tF4xWryDXFW5Jr15Cr43Awb_yoW8ZF4kpw 47CrZ3ArsagFsa9anIyr1jgFs3XF4rCF1vgFnFka48CrsagrWjvrWxKa1fZFW8Jrs7Zw43 CFyUK340kr1qyw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmS14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Ar0_tr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2 kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkE bVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67 AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUCVW8JwCI 42IY6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4UJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF 4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY1x0267AKxVW8Jr0_Cr1UYxBI daVFxhVjvjDU0xZFpf9x0pRQJ5wUUUUU= X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" The TH1520 SoC contains a Synopsys DesignWare Cores SuperSpeed USB3.0 Dual Role Device controller in addition to a USB2+USB3 combo PHY based on Synopsys USB3.0 FemtoPHY. Add device tree nodes for them. The USB controller is quite generic, new and properly configured during silicon design, but the PHY is a little quirky. Signed-off-by: Icenowy Zheng --- arch/riscv/boot/dts/thead/th1520.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index c9930e63bbe93..a6a3e114d0d2f 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -316,6 +316,20 @@ uart0: serial@ffe7014000 { status =3D "disabled"; }; =20 + usb: usb@ffe7040000 { + compatible =3D "snps,dwc3"; + reg =3D <0xff 0xe7040000 0x0 0x10000>; + interrupts =3D <68 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&clk_misc CLK_USB>, + <&clk_misc CLK_USB_CTL_REF>, + <&clk_misc CLK_USB_SUSPEND>; + clock-names =3D "bus_early", "ref", "suspend"; + resets =3D <&rst_misc TH1520_RESET_ID_USB3_VCC>; + phys =3D <&usb_phy>; + phy-names =3D "usb3-phy"; + status =3D "disabled"; + }; + gmac1: ethernet@ffe7060000 { compatible =3D "thead,th1520-gmac", "snps,dwmac-3.70a"; reg =3D <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>; @@ -540,6 +554,19 @@ clk_misc: clock-controller@ffec02c100 { #clock-cells =3D <1>; }; =20 + usb_phy: phy@ffec030000 { + compatible =3D "thead,th1520-usb-phy"; + reg =3D <0xff 0xec030000 0x0 0x10000>; + clocks =3D <&clk_misc CLK_USB>, + <&clk_misc CLK_USB_PHY_REF>; + clock-names =3D "bus", "ref"; + resets =3D <&rst_misc TH1520_RESET_ID_USB3_APB>, + <&rst_misc TH1520_RESET_ID_USB3_PHY>; + reset-names =3D "bus", "phy"; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + rst_vp: reset-controller@ffecc30000 { compatible =3D "thead,th1520-reset-vp"; reg =3D <0xff 0xecc30000 0x0 0x14>; --=20 2.52.0 From nobody Sat Jun 13 13:41:38 2026 Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9ED25383C7E; Thu, 7 May 2026 08:18:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.81 ARC-Seal: i=1; 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spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.100.82]) by APP-03 (Coremail) with SMTP id rQCowAC3m+KLSvxpI_pNEA--.42168S9; Thu, 07 May 2026 16:17:29 +0800 (CST) From: Icenowy Zheng To: Drew Fustini , Guo Ren , Fu Wei , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Neil Armstrong , Greg Kroah-Hartman , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jisheng Zhang Cc: Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-phy@lists.infradead.org, linux-usb@vger.kernel.org, Icenowy Zheng , Han Gao , Yao Zi , Icenowy Zheng , Hoan Tran , Linus Walleij , Bartosz Golaszewski , Serge Semin Subject: [PATCH 07/12] dt-bindings: gpio: dwapb: allow GPIO hogs Date: Thu, 7 May 2026 16:17:05 +0800 Message-ID: <20260507081710.4090814-8-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260507081710.4090814-1-zhengxingda@iscas.ac.cn> References: <20260507081710.4090814-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: rQCowAC3m+KLSvxpI_pNEA--.42168S9 X-Coremail-Antispam: 1UD129KBjvdXoW7XF13ArWkZry5ZFy8Kw4UArb_yoWDKrX_CF s3Za1DCFWktFyYkws0yF4xAFyYy3y7GF1kCwn8Krn3Cwn2v3Z8GFZ3J345ArW7Wa1fuFyr CF93AryqqFs7GjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJTRUUUb98FF20E14v26rWj6s0DM7CY07I20VC2zVCF04k26cxKx2IYs7xG 6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAVCq3wA2048vs2 IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28E F7xvwVC0I7IYx2IY67AKxVW7JVWDJwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVW8Jr0_Cr 1UM28EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0D M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2 IY04v7MxkF7I0En4kS14v26r4a6rW5MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY 6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17 CEb7AF67AKxVWrXVW8Jr1lIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUCVW8JwCI 42IY6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4UJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF 4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY1x0267AKxVW8Jr0_Cr1UYxBI daVFxhVjvjDU0xZFpf9x0pRQJ5wUUUUU= X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" GPIO hogs are described in the gpio.txt binding as automatic default GPIO configuration items. Allow them for GPIO ports in DesignWare APB GPIO controller nodes. Cc: Hoan Tran Cc: Linus Walleij Cc: Bartosz Golaszewski Cc: Serge Semin Signed-off-by: Icenowy Zheng Acked-by: Conor Dooley --- .../devicetree/bindings/gpio/snps,dw-apb-gpio.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml b= /Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml index bba6f5b6606fd..55069533f6d91 100644 --- a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml @@ -95,6 +95,12 @@ patternProperties: '#interrupt-cells': const: 2 =20 + patternProperties: + "^.+-hog(-[0-9]+)?$": + type: object + required: + - gpio-hog + required: - compatible - reg --=20 2.52.0 From nobody Sat Jun 13 13:41:38 2026 Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0773383C84; Thu, 7 May 2026 08:18:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778141905; cv=none; b=CdXDgpL0ND+foij6u3XPu0gfllrAz3nmKfbnAEYd4OI+aRCNczFoe11G9z21HGxYHeyhKBTccUddcOQ4QGfE81PY1Z9AB/1upjFSq7c2StA8abRdgGNnkIwSvvWrMg87UXHIFIZaxZrqFV6Bq4d10xHmA8i8VBXIgMWEO+gbvbQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778141905; c=relaxed/simple; bh=I7GhDoZ5Gz4L9bIQlXfzl7V3iuTfhIc3DyWoU/YAiMo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MaSycidbpk/qz3sKOx5BrTk5uR+wq/kiLnnEKgsdPtXVMsQpkS/jElgs/0B+2+k6uBSeE4VHY0tL/2xqlipNrmPaOU9dPhYM93VnF/ahXJlmECt3u57Ao1/LYyd78AmYyejkxVRdXi9eY8IvDHc3cNqmWIdtT8l76VhEacArIT0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.100.82]) by APP-03 (Coremail) with SMTP id rQCowAC3m+KLSvxpI_pNEA--.42168S10; Thu, 07 May 2026 16:17:31 +0800 (CST) From: Icenowy Zheng To: Drew Fustini , Guo Ren , Fu Wei , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Neil Armstrong , Greg Kroah-Hartman , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jisheng Zhang Cc: Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-phy@lists.infradead.org, linux-usb@vger.kernel.org, Icenowy Zheng , Han Gao , Yao Zi , Icenowy Zheng , Anand Moon Subject: [PATCH 08/12] dt-bindings: usb: vialab,vl817: allow ports property Date: Thu, 7 May 2026 16:17:06 +0800 Message-ID: <20260507081710.4090814-9-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260507081710.4090814-1-zhengxingda@iscas.ac.cn> References: <20260507081710.4090814-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: rQCowAC3m+KLSvxpI_pNEA--.42168S10 X-Coremail-Antispam: 1UD129KBjvJXoW7AF13uF4rJFWkAFWkAry3CFg_yoW8Jw43pF WxKFyxJFn3tF13W34kKF48C3W3ZayDJr1DGFZrZrsrKFn8u3Z8trs8Kr98X3WkCr1kuFW3 Cryqkr45Ka42k3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmS14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Ar0_tr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2 kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkE bVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67 AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUCVW8JwCI 42IY6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4UJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF 4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY1x0267AKxVW8Jr0_Cr1UYxBI daVFxhVjvjDU0xZFpf9x0pRQJ5wUUUUU= X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" As a USB hub device, VL817 can surely be connected to external USB connectors. The binding for such connectors connection is already described in the generic usb-hub.yaml binding with ports subnode, but it's not yet allowed in the VL817 binding. Switch the reference binding from usb-device.yaml to usb-hub.yaml (which recursively references usb-device.yaml and contains definition for ports subnode) and allow ports subnode in VL817 binding. Cc: Anand Moon Signed-off-by: Icenowy Zheng Acked-by: Conor Dooley --- Documentation/devicetree/bindings/usb/vialab,vl817.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/usb/vialab,vl817.yaml b/Docu= mentation/devicetree/bindings/usb/vialab,vl817.yaml index c815010ba9c2e..7387f4fae54d1 100644 --- a/Documentation/devicetree/bindings/usb/vialab,vl817.yaml +++ b/Documentation/devicetree/bindings/usb/vialab,vl817.yaml @@ -10,7 +10,7 @@ maintainers: - Anand Moon =20 allOf: - - $ref: usb-device.yaml# + - $ref: usb-hub.yaml# =20 properties: compatible: @@ -34,6 +34,8 @@ properties: description: phandle to the peer hub on the controller. =20 + ports: true + required: - compatible - reg --=20 2.52.0 From nobody Sat Jun 13 13:41:38 2026 Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1EA2F38B135; Thu, 7 May 2026 08:18:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778141909; cv=none; b=TjbJd3lV2BYta9F3QX3S2zEAEkvRxJR1c52Js6bvwRq0dDoNcUfyyuh0jOJMMaXtk+rq3hyisdD69idgctZ3jMELEPgNkZhBGAOLTq/ZCHlFlwQJ8U7UVQai7lpFWGemDKzHDydjyqUKbKBQ7OTPjoUC3LY5wLq1X0n2ZKUM93A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778141909; c=relaxed/simple; bh=o16OqT39XvO3q8x6EYPtyYgTx7Bxj5I3KhszAp66kCY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UdtCoFvZjXt5C8w7XB05ruwFzJqbPoD0rIcLCe6qJ7F13X8I7lYln3DZOirnOC6aBkX/dnTXZCDbtbyckvfisNuoLwf4sPb9/tVej6XOXMzYbmVdk7PQp6QVSM8S0IbwwU2LZ/GKxLxl1fZIUYk7pREGwgUjYRsDmdFkhtTFIS4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.100.82]) by APP-03 (Coremail) with SMTP id rQCowAC3m+KLSvxpI_pNEA--.42168S11; Thu, 07 May 2026 16:17:33 +0800 (CST) From: Icenowy Zheng To: Drew Fustini , Guo Ren , Fu Wei , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Neil Armstrong , Greg Kroah-Hartman , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jisheng Zhang Cc: Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-phy@lists.infradead.org, linux-usb@vger.kernel.org, Icenowy Zheng , Han Gao , Yao Zi , Icenowy Zheng Subject: [PATCH 09/12] riscv: dts: thead: lpi4a: sort nodes Date: Thu, 7 May 2026 16:17:07 +0800 Message-ID: <20260507081710.4090814-10-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260507081710.4090814-1-zhengxingda@iscas.ac.cn> References: <20260507081710.4090814-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: rQCowAC3m+KLSvxpI_pNEA--.42168S11 X-Coremail-Antispam: 1UD129KBjvdXoW7Jw4DWF17tFy5Kr15uF1rJFb_yoWktFcEkF W5ua95Zw1xGF1fJF9Fqr4xJ34kG3yS9a4kKFyIqr1UGF15ur4jqrWkt3yruw1F9rWYgFWx Aw4DAryrtrnFkjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJTRUUUbvAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k26cxKx2IYs7xG 6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUAVCq3wA2048vs2 IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28E F7xvwVC0I7IYx2IY67AKxVW7JVWDJwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVW8Jr0_Cr 1UM28EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0D M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2 IY04v7MxkF7I0En4kS14v26r4a6rW5MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY 6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17 CEb7AF67AKxVW8ZVWrXwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1I6r4UMIIF 0xvE2Ix0cI8IcVCY1x0267AKxVW8Jr0_Cr1UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCw CI42IY6I8E87Iv67AKxVW8JVWxJwCI42IY6I8E87Iv6xkF7I0E14v26r4UJVWxJrUvcSsG vfC2KfnxnUUI43ZEXa7sRiHUDtUUUUU== X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" Although "D" and "H" are earlier in the alphabet than "P", the DPU and HDMI nodes were added after PADCTRL node in the Lichee Pi 4A device tree. Sort the nodes in this device tree. Signed-off-by: Icenowy Zheng --- .../boot/dts/thead/th1520-lichee-pi-4a.dts | 28 +++++++++---------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv= /boot/dts/thead/th1520-lichee-pi-4a.dts index 7cb7d28683bce..4198dbf953f06 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -96,6 +96,20 @@ fan: pwm-fan { =20 }; =20 +&dpu { + status =3D "okay"; +}; + +&hdmi { + status =3D "okay"; +}; + +&hdmi_out_port { + hdmi_out_con: endpoint { + remote-endpoint =3D <&hdmi_con_in>; + }; +}; + &padctrl0_apsys { fan_pins: fan-0 { pwm1-pins { @@ -132,20 +146,6 @@ rx-pins { }; }; =20 -&dpu { - status =3D "okay"; -}; - -&hdmi { - status =3D "okay"; -}; - -&hdmi_out_port { - hdmi_out_con: endpoint { - remote-endpoint =3D <&hdmi_con_in>; - }; -}; - &uart0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&uart0_pins>; --=20 2.52.0 From nobody Sat Jun 13 13:41:38 2026 Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2B7838F630; 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dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.100.82]) by APP-03 (Coremail) with SMTP id rQCowAC3m+KLSvxpI_pNEA--.42168S12; Thu, 07 May 2026 16:17:38 +0800 (CST) From: Icenowy Zheng To: Drew Fustini , Guo Ren , Fu Wei , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Neil Armstrong , Greg Kroah-Hartman , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jisheng Zhang Cc: Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-phy@lists.infradead.org, linux-usb@vger.kernel.org, Icenowy Zheng , Han Gao , Yao Zi , Thomas Bonnefille , Drew Fustini , Icenowy Zheng Subject: [PATCH 10/12] riscv: dts: thead: Add TH1520 I2C nodes Date: Thu, 7 May 2026 16:17:08 +0800 Message-ID: <20260507081710.4090814-11-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260507081710.4090814-1-zhengxingda@iscas.ac.cn> References: <20260507081710.4090814-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: rQCowAC3m+KLSvxpI_pNEA--.42168S12 X-Coremail-Antispam: 1UD129KBjvJXoWxCry3ArWxJryrKw45WrWfKrg_yoW5CryDpa srArZ5Aws5XF1I93W3XFy2kFZxJan5uF92grnFkFWUCw1YgF4YvrW8tFyIvF1kXFWUXw1a qFn3Cr10yrn8tw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmS14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Ar0_tr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2 kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkE bVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67 AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVW8JVW5JwCI 42IY6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4UJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF 4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY1x0267AKxVW8Jr0_Cr1UYxBI daVFxhVjvjDU0xZFpf9x0pRQJ5wUUUUU= X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" From: Thomas Bonnefille Add nodes for the six I2C on the T-Head TH1520 RISCV SoC. Signed-off-by: Thomas Bonnefille Reviewed-by: Drew Fustini [Icenowy: rebase on top of v7.1-rc2] Signed-off-by: Icenowy Zheng --- arch/riscv/boot/dts/thead/th1520.dtsi | 60 +++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index a6a3e114d0d2f..df49f8f749ef7 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -425,6 +425,36 @@ uart3: serial@ffe7f04000 { status =3D "disabled"; }; =20 + i2c0: i2c@ffe7f20000 { + compatible =3D "thead,th1520-i2c", "snps,designware-i2c"; + reg =3D <0xff 0xe7f20000 0x0 0x4000>; + interrupts =3D <44 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&clk CLK_I2C0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c1: i2c@ffe7f24000 { + compatible =3D "thead,th1520-i2c", "snps,designware-i2c"; + reg =3D <0xff 0xe7f24000 0x0 0x4000>; + interrupts =3D <45 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&clk CLK_I2C1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c4: i2c@ffe7f28000 { + compatible =3D "thead,th1520-i2c", "snps,designware-i2c"; + reg =3D <0xff 0xe7f28000 0x0 0x4000>; + interrupts =3D <48 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&clk CLK_I2C4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + gpio@ffe7f34000 { compatible =3D "snps,dw-apb-gpio"; reg =3D <0xff 0xe7f34000 0x0 0x1000>; @@ -523,6 +553,16 @@ padctrl0_apsys: pinctrl@ffec007000 { thead,pad-group =3D <3>; }; =20 + i2c2: i2c@ffec00c000 { + compatible =3D "thead,th1520-i2c", "snps,designware-i2c"; + reg =3D <0xff 0xec00c000 0x0 0x4000>; + interrupts =3D <46 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&clk CLK_I2C2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + uart2: serial@ffec010000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xec010000 0x0 0x4000>; @@ -534,6 +574,16 @@ uart2: serial@ffec010000 { status =3D "disabled"; }; =20 + i2c3: i2c@ffec014000 { + compatible =3D "thead,th1520-i2c", "snps,designware-i2c"; + reg =3D <0xff 0xec014000 0x0 0x4000>; + interrupts =3D <47 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&clk CLK_I2C3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + pwm: pwm@ffec01c000 { compatible =3D "thead,th1520-pwm"; reg =3D <0xff 0xec01c000 0x0 0x4000>; @@ -759,6 +809,16 @@ uart5: serial@fff7f0c000 { status =3D "disabled"; }; =20 + i2c5: i2c@fff7f2c000 { + compatible =3D "thead,th1520-i2c", "snps,designware-i2c"; + reg =3D <0xff 0xf7f2c000 0x0 0x4000>; + interrupts =3D <49 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&clk CLK_I2C5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + timer4: timer@ffffc33000 { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xffc33000 0x0 0x14>; --=20 2.52.0 From nobody Sat Jun 13 13:41:38 2026 Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D229E348866; 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dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.100.82]) by APP-03 (Coremail) with SMTP id rQCowAC3m+KLSvxpI_pNEA--.42168S13; Thu, 07 May 2026 16:17:40 +0800 (CST) From: Icenowy Zheng To: Drew Fustini , Guo Ren , Fu Wei , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Neil Armstrong , Greg Kroah-Hartman , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jisheng Zhang Cc: Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-phy@lists.infradead.org, linux-usb@vger.kernel.org, Icenowy Zheng , Han Gao , Yao Zi , Emil Renner Berthing , Icenowy Zheng Subject: [PATCH 11/12] riscv: dts: thead: Add Lichee Pi 4A IO expansions Date: Thu, 7 May 2026 16:17:09 +0800 Message-ID: <20260507081710.4090814-12-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260507081710.4090814-1-zhengxingda@iscas.ac.cn> References: <20260507081710.4090814-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: rQCowAC3m+KLSvxpI_pNEA--.42168S13 X-Coremail-Antispam: 1UD129KBjvJXoWxXw13Xr4rAF4xCFyrGF13XFb_yoW5uF1Dpa 1IgrZ5t34kCrW7u34Yvr109F1rWF4kJF95KwsrCF1Iv3yFgFWvq340q3WfuF1DXrWrWw43 Zrs3GF92kF1qvwUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmS14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Ar0_tr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2 kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkE bVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67 AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVW8JVW5JwCI 42IY6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4UJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF 4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY1x0267AKxVW8Jr0_Cr1UYxBI daVFxhVjvjDU0xZFpf9x0pRQJ5wUUUUU= X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" From: Emil Renner Berthing Lichee Pi 4A has 3 I2C IO expansion chips onboard, connected to the I2C0/1/3 busses. Add device tree nodes for them. Signed-off-by: Emil Renner Berthing [Icenowy: added commit description] Signed-off-by: Icenowy Zheng --- .../boot/dts/thead/th1520-lichee-pi-4a.dts | 111 ++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv= /boot/dts/thead/th1520-lichee-pi-4a.dts index 4198dbf953f06..354f3893aa8cf 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -16,6 +16,9 @@ aliases { gpio3 =3D &gpio3; gpio4 =3D &gpio4; gpio5 =3D &aogpio; + i2c0 =3D &i2c0; + i2c1 =3D &i2c1; + i2c3 =3D &i2c3; serial0 =3D &uart0; serial1 =3D &uart1; serial2 =3D &uart2; @@ -110,6 +113,76 @@ hdmi_out_con: endpoint { }; }; =20 +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins>; + clock-frequency =3D <100000>; + i2c-sda-hold-time-ns =3D <300>; + i2c-sda-falling-time-ns =3D <510>; + i2c-scl-falling-time-ns =3D <510>; + status =3D "okay"; + + ioexp1: gpio@18 { + compatible =3D "nxp,pca9557"; + reg =3D <0x18>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "cam0_dvdd12", + "cam0_avdd28", + "cam0_dovdd18"; + }; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_pins>; + clock-frequency =3D <100000>; + i2c-sda-hold-time-ns =3D <300>; + i2c-sda-falling-time-ns =3D <510>; + i2c-scl-falling-time-ns =3D <510>; + status =3D "okay"; + + ioexp2: gpio@18 { + compatible =3D "nxp,pca9557"; + reg =3D <0x18>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "", + "cam0_reset", + "cam1_reset", + "cam2_reset", + "wl_host_wake", + "bt_resetn", + "", + "bt_host_wake"; + }; +}; + +&i2c3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3_pins>; + clock-frequency =3D <100000>; + i2c-sda-hold-time-ns =3D <300>; + i2c-sda-falling-time-ns =3D <510>; + i2c-scl-falling-time-ns =3D <510>; + status =3D "okay"; + + ioexp3: gpio@18 { + compatible =3D "nxp,pca9557"; + reg =3D <0x18>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "tp0_rst", + "", + "", + "vcc5v_usb", + "vdd28_tp0", + "vdd33_lcd0", + "vdd18_lcd0", + "lcd0_reset"; + }; +}; + &padctrl0_apsys { fan_pins: fan-0 { pwm1-pins { @@ -123,6 +196,18 @@ pwm1-pins { }; }; =20 + i2c3_pins: i2c3-0 { + i2c-pins { + pins =3D "I2C3_SCL", "I2C3_SDA"; + function =3D "i2c"; + bias-disable; /* external pull-up */ + drive-strength =3D <7>; + input-enable; + input-schmitt-enable; + slew-rate =3D <0>; + }; + }; + uart0_pins: uart0-0 { tx-pins { pins =3D "UART0_TXD"; @@ -146,6 +231,32 @@ rx-pins { }; }; =20 +&padctrl1_apsys { + i2c0_pins: i2c0-0 { + i2c-pins { + pins =3D "I2C0_SCL", "I2C0_SDA"; + function =3D "i2c"; + bias-disable; /* external pull-up */ + drive-strength =3D <7>; + input-enable; + input-schmitt-enable; + slew-rate =3D <0>; + }; + }; + + i2c1_pins: i2c1-0 { + i2c-pins { + pins =3D "I2C1_SCL", "I2C1_SDA"; + function =3D "i2c"; + bias-disable; /* external pull-up */ + drive-strength =3D <7>; + input-enable; + input-schmitt-enable; + slew-rate =3D <0>; + }; + }; +}; + &uart0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&uart0_pins>; --=20 2.52.0 From nobody Sat Jun 13 13:41:38 2026 Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61E6739479B; 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dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.100.82]) by APP-03 (Coremail) with SMTP id rQCowAC3m+KLSvxpI_pNEA--.42168S14; Thu, 07 May 2026 16:17:42 +0800 (CST) From: Icenowy Zheng To: Drew Fustini , Guo Ren , Fu Wei , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Neil Armstrong , Greg Kroah-Hartman , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jisheng Zhang Cc: Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-phy@lists.infradead.org, linux-usb@vger.kernel.org, Icenowy Zheng , Han Gao , Yao Zi , Icenowy Zheng Subject: [PATCH 12/12] riscv: dts: thead: enable USB3 ports on Lichee Pi 4A Date: Thu, 7 May 2026 16:17:10 +0800 Message-ID: <20260507081710.4090814-13-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260507081710.4090814-1-zhengxingda@iscas.ac.cn> References: <20260507081710.4090814-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: rQCowAC3m+KLSvxpI_pNEA--.42168S14 X-Coremail-Antispam: 1UD129KBjvJXoWxuw1rWw15ZF1rXr4xWF1fXrb_yoW7Cr4Dp3 ZxCFsY9FWrCryUKw43Zryvqa15Grs5ua4kCr15GryUA3y7XFZrK34SyFsYyF1kJF4xX3sI yr4DZr1Iqr17K3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUma14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Ar0_tr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr1j6r xdM28EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0D M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2 IY04v7MxkF7I0En4kS14v26r4a6rW5MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY 6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17 CEb7AF67AKxVW8ZVWrXwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r4j6ryUMIIF 0xvE2Ix0cI8IcVCY1x0267AKxVW8Jr0_Cr1UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCw CI42IY6I8E87Iv67AKxVW8JVWxJwCI42IY6I8E87Iv6xkF7I0E14v26r4UJVWxJrUvcSsG vfC2KfnxnUUI43ZEXa7sRiHUDtUUUUU== X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" The Lichee Pi 4A board features an onboard VIA VL817 hub connected to the SoC's USB3 as upstream and 4 USB-3.0-capable Type-A ports as downstream. Enable SoC USB3 and the hub on Lichee Pi 4A. Signed-off-by: Icenowy Zheng --- .../dts/thead/th1520-lichee-module-4a.dtsi | 15 ++ .../boot/dts/thead/th1520-lichee-pi-4a.dts | 231 ++++++++++++++++++ 2 files changed, 246 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/= riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index 8e76b63e0100a..bfda5a6b56b8f 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -20,6 +20,16 @@ memory@0 { device_type =3D "memory"; reg =3D <0x0 0x00000000 0x2 0x00000000>; }; + + /* TODO: Switch to AON regulator when it's available. */ + avdd33_usb3: regulator-avdd33-usb3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "AVDD33_USB3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + /* Marked as always on on the schematics */ + regulator-always-on; + }; }; =20 &osc { @@ -202,3 +212,8 @@ &sdio0 { max-frequency =3D <198000000>; status =3D "okay"; }; + +&usb_phy { + avdd33-usb3-supply =3D <&avdd33_usb3>; + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv= /boot/dts/thead/th1520-lichee-pi-4a.dts index 354f3893aa8cf..de38f1f457e6b 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -4,6 +4,7 @@ */ =20 #include "th1520-lichee-module-4a.dtsi" +#include =20 / { model =3D "Sipeed Lichee Pi 4A"; @@ -97,6 +98,141 @@ fan: pwm-fan { cooling-levels =3D <0 66 196 255>; }; =20 + hub_5v: regulator-hub-5v { + compatible =3D "regulator-fixed"; + regulator-name =3D "HUB_5V"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&ioexp3 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vcc5v_usb: regulator-vcc5v-usb { + compatible =3D "regulator-fixed"; + regulator-name =3D "VCC5V_USB"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpio1 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * Workaround for Linux currently being not able to power on + * Vbus for USB Type-A connectors. + */ + regulator-always-on; + }; + + connector-usb-a-1 { + compatible =3D "usb-a-connector"; + vbus-supply =3D <&vcc5v_usb>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb_a_1_hs_ep: endpoint { + remote-endpoint =3D <&hub_hs_port1_ep>; + }; + }; + + port@1 { + reg =3D <1>; + + usb_a_1_ss_ep: endpoint { + remote-endpoint =3D <&hub_ss_port1_ep>; + }; + }; + }; + }; + + connector-usb-a-2 { + compatible =3D "usb-a-connector"; + vbus-supply =3D <&vcc5v_usb>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb_a_2_hs_ep: endpoint { + remote-endpoint =3D <&hub_hs_port2_ep>; + }; + }; + + port@1 { + reg =3D <1>; + + usb_a_2_ss_ep: endpoint { + remote-endpoint =3D <&hub_ss_port2_ep>; + }; + }; + }; + }; + + connector-usb-a-3 { + compatible =3D "usb-a-connector"; + vbus-supply =3D <&vcc5v_usb>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb_a_3_hs_ep: endpoint { + remote-endpoint =3D <&hub_hs_port3_ep>; + }; + }; + + port@1 { + reg =3D <1>; + + usb_a_3_ss_ep: endpoint { + remote-endpoint =3D <&hub_ss_port3_ep>; + }; + }; + }; + }; + + connector-usb-a-4 { + compatible =3D "usb-a-connector"; + vbus-supply =3D <&vcc5v_usb>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb_a_4_hs_ep: endpoint { + remote-endpoint =3D <&hub_hs_port4_ep>; + }; + }; + + port@1 { + reg =3D <1>; + + usb_a_4_ss_ep: endpoint { + remote-endpoint =3D <&hub_ss_port4_ep>; + }; + }; + }; + }; +}; + +&aogpio { + /* Route USB2 to the onboard hub for normal operation */ + sel-usb-hub-hog { + gpio-hog; + gpios =3D <4 GPIO_ACTIVE_HIGH>; + output-high; + }; }; =20 &dpu { @@ -262,3 +398,98 @@ &uart0 { pinctrl-0 =3D <&uart0_pins>; status =3D "okay"; }; + +&usb { + dr_mode =3D "host"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + hub_hs: hub@1 { + compatible =3D "usb2109,2817"; + reg =3D <1>; + peer-hub =3D <&hub_ss>; + vdd-supply =3D <&hub_5v>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@1 { + reg =3D <1>; + + hub_hs_port1_ep: endpoint { + remote-endpoint =3D <&usb_a_1_hs_ep>; + }; + }; + + port@2 { + reg =3D <2>; + + hub_hs_port2_ep: endpoint { + remote-endpoint =3D <&usb_a_2_hs_ep>; + }; + }; + + port@3 { + reg =3D <3>; + + hub_hs_port3_ep: endpoint { + remote-endpoint =3D <&usb_a_3_hs_ep>; + }; + }; + + port@4 { + reg =3D <4>; + + hub_hs_port4_ep: endpoint { + remote-endpoint =3D <&usb_a_4_hs_ep>; + }; + }; + }; + }; + + hub_ss: hub@2 { + compatible =3D "usb2109,817"; + reg =3D <2>; + peer-hub =3D <&hub_hs>; + vdd-supply =3D <&hub_5v>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@1 { + reg =3D <1>; + + hub_ss_port1_ep: endpoint { + remote-endpoint =3D <&usb_a_1_ss_ep>; + }; + }; + + port@2 { + reg =3D <2>; + + hub_ss_port2_ep: endpoint { + remote-endpoint =3D <&usb_a_2_ss_ep>; + }; + }; + + port@3 { + reg =3D <3>; + + hub_ss_port3_ep: endpoint { + remote-endpoint =3D <&usb_a_3_ss_ep>; + }; + }; + + port@4 { + reg =3D <4>; + + hub_ss_port4_ep: endpoint { + remote-endpoint =3D <&usb_a_4_ss_ep>; + }; + }; + }; + }; +}; --=20 2.52.0