From nobody Sat Jun 13 13:10:18 2026 Received: from mail.ispras.ru (mail.ispras.ru [83.149.199.84]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B85F32F770; Thu, 7 May 2026 08:06:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=83.149.199.84 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778141177; cv=none; b=f8jst0UbtxFVgQxhR/jUKif4959iWgNSaez+cHak92fvozQZemewB3WjhqyIYV7ucVIQ7mRgK+UPE40QpcfSBpHW9w4AQ90wuKf3OQcNyAmU608KqcLWLQQQQTTqCg0bgHOK7NstDYupLDG49RC2PFiucJZCZqpoL4VAdSfLnV0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778141177; c=relaxed/simple; bh=ObHsI6yvsJqtZrX66uSHRsPF3X2UzW09Pssks/HsHFQ=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=PrTlUO7CJy1JLKvL2Pg3iLkaIEB7jcPkL3aoifiVRNnivr82QTxsfZF0FuabLpza2u7jp/0gzIeHL7wX0j0D5wBgKtluDxRayZWx4MbCO2HlE9sh940xthwYw2YQ1005kmtVfze6+mrZccUYsE1ju7+MWNyvvsA1Mmev6SFN9pg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ispras.ru; spf=pass smtp.mailfrom=ispras.ru; dkim=pass (1024-bit key) header.d=ispras.ru header.i=@ispras.ru header.b=VaR7Nx4i; arc=none smtp.client-ip=83.149.199.84 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ispras.ru Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ispras.ru Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ispras.ru header.i=@ispras.ru header.b="VaR7Nx4i" Received: from debian.lan (unknown [95.24.24.108]) by mail.ispras.ru (Postfix) with ESMTPSA id 0FEE945A1D2A; Thu, 7 May 2026 08:06:04 +0000 (UTC) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.ispras.ru 0FEE945A1D2A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ispras.ru; s=default; t=1778141164; bh=t6msmjqawU/IEsj5CPxud70TuqJjAjCucEWvMJ3Guhk=; h=From:To:Cc:Subject:Date:From; b=VaR7Nx4iurJc2k38ZCC7sKPUbG60TZzh7zWCskj64/r4czrnXDx1pFOSS1dizzxNP wBq7v7eOONtbPocEz7tHcevL23XJV6XUduTbRQL971Nov5XqcgXBwRfmg4XIKQdCUS +SkSk6FIcNQkkmyra6AbeboWACBXhpWV3ReiyMnA= From: Fedor Pchelkin To: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin Cc: Fedor Pchelkin , David Airlie , Simona Vetter , =?UTF-8?q?Micha=C5=82=20Grzelak?= , Matt Roper , Michael Cheng , intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, lvc-project@linuxtesting.org, stable@vger.kernel.org Subject: [PATCH] drm/i915/gt: fix up region size calculation for flushing dcache lines Date: Thu, 7 May 2026 11:05:43 +0300 Message-ID: <20260507080544.57053-1-pchelkin@ispras.ru> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Computing region size for flushing dcache lines currently involves execlists->csb_size * sizeof(execlists->csb_status) while the second operand should represent the size of the csb status array element (u64), not the size of the pointer variable. It works on a 64-bit kernel, but it's not correct for exotic 32-bit ones and may result in an incomplete flush when the number of csb entries covers more than a single cacheline. Found by Linux Verification Center (linuxtesting.org) with Svace static analysis tool. Fixes: dc0406820ee7 ("drm/i915/gt: Drop invalidate_csb_entries") Cc: stable@vger.kernel.org Signed-off-by: Fedor Pchelkin --- The patch is against drm-intel/drm-intel-next, HEAD:775fb670745015d679a65f948b3da0fbff3f100c drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers= /gpu/drm/i915/gt/intel_execlists_submission.c index 1359fc9cb88e..31037ee3c2c4 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -2833,7 +2833,7 @@ static void reset_csb_pointers(struct intel_engine_cs= *engine) memset(execlists->csb_status, -1, (reset_value + 1) * sizeof(u64)); drm_clflush_virt_range(execlists->csb_status, execlists->csb_size * - sizeof(execlists->csb_status)); + sizeof(execlists->csb_status[0])); =20 /* Once more for luck and our trusty paranoia */ ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR, --=20 2.53.0