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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83965945101sm7346557b3a.13.2026.05.06.23.22.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2026 23:22:56 -0700 (PDT) From: Sibi Sankar To: cristian.marussi@arm.com, sudeep.holla@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, myungjoo.ham@samsung.com, konradybcio@kernel.org, andersson@kernel.org Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, arm-scmi@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, dmitry.baryshkov@oss.qualcomm.com, jonathanh@nvidia.com, thierry.reding@kernel.org, digetx@gmail.com, conor+dt@kernel.org, krzk+dt@kernel.org, robh@kernel.org Subject: [RFC V6 1/8] firmware: arm_scmi: Add QCOM Generic Vendor Protocol documentation Date: Thu, 7 May 2026 11:52:30 +0530 Message-Id: <20260507062237.78051-2-sibi.sankar@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260507062237.78051-1-sibi.sankar@oss.qualcomm.com> References: <20260507062237.78051-1-sibi.sankar@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA3MDA2MCBTYWx0ZWRfXzihS+BlunvNv zOCOoytlhzGo+AkHqWuemF2q5t57lMEKXLp7AMDh9s8Jd/czOR/gSZATw04uoh2gX4JMD8qeytY zAl+06m1EmjSsQVznkBAShvn3RHNoOA1mLBFIhBB3GLQzlGFDIhtkSzcNwxDmDUWc9YIMNQhQxx D/6EaokB0T3GqxXC1arrnorlJ7MAdgQYfdez5vupJ3psqGad6Ax3wd8tRbTU7WmEXVSHD0pMFgi 7uEI7Cd/D0MSxrt/+zM/9D7MHJKm1O6zYWh/cvCyThcbLQdpa6bblDjJdd2uWuwExOi16mOYQY9 wubNVkFt+OtJ0CaonauMpdbLuvKDuJRgOY6rllfBJSp9auPxuAyHE9cmpKi/oF/svJv+ttMe7TW dsT0MHeAOG1eRazCZo7x5ztUwOUnK7mLb3TRGuXmw6x/IhN/rQujJ0vohf0ri8599ZoDtF2TO1L xKrKuCHSboQgq3nR69g== X-Proofpoint-ORIG-GUID: MBqhmyGBgsN5MWjvUy3UVUJKLhzyMl6O X-Authority-Analysis: v=2.4 cv=SuagLvO0 c=1 sm=1 tr=0 ts=69fc2fc3 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=fRH0SyXitDLK6ufOgm8A:9 a=3WC7DwWrALyhR5TkjVHa:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: MBqhmyGBgsN5MWjvUy3UVUJKLhzyMl6O X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-06_02,2026-05-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 adultscore=0 phishscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605070060 Content-Type: text/plain; charset="utf-8" Add QCOM System Control Management Interface (SCMI) Generic Vendor Extensions Protocol documentation. Signed-off-by: Sibi Sankar --- @Sudeep/@Christian, Just moving the series back in RFC mode to get feedback on the devfreq part of the series. Will add a lot more documentation in the next re-spin, so definitely not ignoring your earlier comments :). .../arm_scmi/vendors/qcom/qcom_generic.rst | 211 ++++++++++++++++++ 1 file changed, 211 insertions(+) create mode 100644 drivers/firmware/arm_scmi/vendors/qcom/qcom_generic.rst diff --git a/drivers/firmware/arm_scmi/vendors/qcom/qcom_generic.rst b/driv= ers/firmware/arm_scmi/vendors/qcom/qcom_generic.rst new file mode 100644 index 000000000000..141bc932e30f --- /dev/null +++ b/drivers/firmware/arm_scmi/vendors/qcom/qcom_generic.rst @@ -0,0 +1,211 @@ +.. SPDX-License-Identifier: GPL-2.0 +.. include:: + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D +QCOM System Control and Management Interface(SCMI) Vendor Protocols Extens= ion +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D + +:Copyright: |copy| 2024, Qualcomm Innovation Center, Inc. All rights reser= ved. + +:Author: Sibi Sankar + +SCMI_GENERIC: System Control and Management Interface QCOM Generic Vendor = Protocol +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D + +This protocol is intended as a generic way of exposing a number of Qualcomm +SoC specific features through a mixture of pre-determined algorithm string= and +param_id pairs hosted on the SCMI controller. It implements an interface c= ompliant +with the Arm SCMI Specification with additional vendor specific commands as +detailed below. + +Commands: +_________ + +PROTOCOL_VERSION +~~~~~~~~~~~~~~~~ + +message_id: 0x0 +protocol_id: 0x80 + ++---------------+---------------------------------------------------------= -----+ +|Return values = | ++---------------+---------------------------------------------------------= -----+ +|Name |Description = | ++---------------+---------------------------------------------------------= -----+ +|int32 status |See ARM SCMI Specification for status code definitions. = | ++---------------+---------------------------------------------------------= -----+ +|uint32 version |For this revision of the specification, this value must b= e | +| |0x10000. = | ++---------------+---------------------------------------------------------= -----+ + +PROTOCOL_ATTRIBUTES +~~~~~~~~~~~~~~~~~~~ + +message_id: 0x1 +protocol_id: 0x80 + ++---------------+---------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 status |See ARM SCMI Specification for status code definitions= . | ++------------------+------------------------------------------------------= -----+ +|uint32 attributes |Bits[31:16] Reserved, must be to 0. = | +| |Bits[15:8] Number of agents in the system = | +| |Bits[7:0] Number of vendor protocols in the system = | ++------------------+------------------------------------------------------= -----+ + +PROTOCOL_MESSAGE_ATTRIBUTES +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +message_id: 0x2 +protocol_id: 0x80 + ++---------------+---------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 status |See ARM SCMI Specification for status code definitions= . | ++------------------+------------------------------------------------------= -----+ +|uint32 attributes |For all message id's the parameter has a value of 0. = | ++------------------+------------------------------------------------------= -----+ + +QCOM_SCMI_SET_PARAM +~~~~~~~~~~~~~~~~~~~ + +message_id: 0x10 +protocol_id: 0x80 + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 ext_id |Reserved, must be zero. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_low |Lower 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_high |Upper 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 param_id |Serves as the token message id for the algorithm strin= g | +| |and is used to set various parameters supported by it.= | ++------------------+------------------------------------------------------= -----+ +|uint32 buf[] |Serves as the payload for the specified param_id and = | +| |algorithm string pair. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS: if the param_id and buf[] is parsed successfu= lly | +| |by the chosen algorithm string. = | +| |NOT_SUPPORTED: if the algorithm string does not have a= ny | +| |matches. = | +| |INVALID_PARAMETERS: if the param_id and the buf[] pass= ed | +| |is rejected by the algorithm string. = | ++------------------+------------------------------------------------------= -----+ + +QCOM_SCMI_GET_PARAM +~~~~~~~~~~~~~~~~~~~ + +message_id: 0x11 +protocol_id: 0x80 + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 ext_id |Reserved, must be zero. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_low |Lower 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_high |Upper 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 param_id |Serves as the token message id for the algorithm strin= g. | ++------------------+------------------------------------------------------= -----+ +|uint32 buf[] |Serves as the payload and store of value for the speci= fied | +| |param_id and algorithm string pair. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS: if the param_id and buf[] is parsed successfu= lly | +| |by the chosen algorithm string and the result is copie= d | +| |into buf[]. = | +| |NOT_SUPPORTED: if the algorithm string does not have a= ny | +| |matches. = | +| |INVALID_PARAMETERS: if the param_id and the buf[] pass= ed | +| |is rejected by the algorithm string. = | ++------------------+------------------------------------------------------= -----+ + +QCOM_SCMI_START_ACTIVITY +~~~~~~~~~~~~~~~~~~~~~~~~ + +message_id: 0x12 +protocol_id: 0x80 + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 ext_id |Reserved, must be zero. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_low |Lower 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_high |Upper 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 param_id |Serves as the token message id for the algorithm strin= g | +| |and is generally used to start the activity performed = by | +| |the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 buf[] |Serves as the payload for the specified param_id and = | +| |algorithm string pair. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS: if the activity performed by the algorithm st= ring | +| |starts successfully. = | +| |NOT_SUPPORTED: if the algorithm string does not have a= ny. | +| |matches or if the activity is already running. = | ++------------------+------------------------------------------------------= -----+ + +QCOM_SCMI_STOP_ACTIVITY +~~~~~~~~~~~~~~~~~~~~~~~ + +message_id: 0x13 +protocol_id: 0x80 + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 ext_id |Reserved, must be zero. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_low |Lower 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_high |Upper 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 param_id |Serves as the token message id for the algorithm strin= g | +| |and is generally used to stop the activity performed b= y | +| |the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 buf[] |Serves as the payload for the specified param_id and = | +| |algorithm string pair. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS: if the activity performed by the algorithm st= ring | +| |stops successfully. = | +| |NOT_SUPPORTED: if the algorithm string does not have a= ny | +| |matches or if the activity isn't running. = | ++------------------+------------------------------------------------------= -----+ --=20 2.34.1 From nobody Sat Jun 13 14:03:16 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D58A33970F 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83965945101sm7346557b3a.13.2026.05.06.23.22.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2026 23:23:04 -0700 (PDT) From: Sibi Sankar To: cristian.marussi@arm.com, sudeep.holla@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, myungjoo.ham@samsung.com, konradybcio@kernel.org, andersson@kernel.org Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, arm-scmi@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, dmitry.baryshkov@oss.qualcomm.com, jonathanh@nvidia.com, thierry.reding@kernel.org, digetx@gmail.com, conor+dt@kernel.org, krzk+dt@kernel.org, robh@kernel.org, Shivnandan Kumar , Ramakrishna Gottimukkula , Amir Vajid Subject: [RFC V6 2/8] firmware: arm_scmi: vendors: Add QCOM SCMI Generic Extensions Date: Thu, 7 May 2026 11:52:31 +0530 Message-Id: <20260507062237.78051-3-sibi.sankar@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260507062237.78051-1-sibi.sankar@oss.qualcomm.com> References: <20260507062237.78051-1-sibi.sankar@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=XsPK/1F9 c=1 sm=1 tr=0 ts=69fc2fca cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=5qo32d-oOMBYuVP3DBMA:9 a=zc0IvFSfCIW2DFIPzwfm:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: wHzj6Tm3W42lwtDn1nGO2kGKWgQVKMk5 X-Proofpoint-ORIG-GUID: wHzj6Tm3W42lwtDn1nGO2kGKWgQVKMk5 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA3MDA2MCBTYWx0ZWRfX4zYkKg7SS/nE z4p0XATe6dVzkTsDvzYXr4RrGrkF7a3PJUYxIaySV7VbMPO65sprxqfbKKNPC1eH37hK6IXaJSe Fx8xXLgxiLeS14zXJuruDztkiVApFd2BTRwTNX6hIhW//JyVIzRuJHl6pTAvshsxh37dU7JSEKy A0do6ZDKOcKHqP0ihMrcVR2+SFvtw7b1uXs/54ghai0NXd9yQzy0/cMnvU7zIAkXp1TFhXKR4l/ +FbSVvt7Mo5gs/hSILg2cFgfdDDGKqLwz9pQxTxiR4kMECTSnQJCoVecjHWiqVCHQ+6yQj9Eqcw fKhky9M3u6BVtR3d3VhXkbFZaAKiFVgN3xVQ4cqnLumbB1LFk1QqRbcZ9rFRsV2NsubsRq5/qeQ GA534825ZX5mkxefYlJDzSSpumkGLLa5w/cyKvOut/NS/5uZY9QQE7t5GgO28EQsbC+5igyQxTr Iu1szg7SENn0XnkRtQA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-06_02,2026-05-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 adultscore=0 suspectscore=0 phishscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605070060 Content-Type: text/plain; charset="utf-8" The QCOM SCMI Generic Extensions Protocol provides a generic way of exposing a number of Qualcomm SoC specific features (like memory bus scaling) through a mixture of pre-determined algorithm strings and param_id pairs hosted on the SCMI controller. Co-developed-by: Shivnandan Kumar Signed-off-by: Shivnandan Kumar Co-developed-by: Ramakrishna Gottimukkula Signed-off-by: Ramakrishna Gottimukkula Co-developed-by: Amir Vajid Signed-off-by: Amir Vajid Signed-off-by: Sibi Sankar --- @Sudeep/@Christian, Just moving the series back in RFC mode to get feedback on the devfreq part of the series. Will add a lot more documentation in the next re-spin, so definitely not ignoring your earlier comments :). drivers/firmware/arm_scmi/Kconfig | 1 + drivers/firmware/arm_scmi/Makefile | 1 + .../firmware/arm_scmi/vendors/qcom/Kconfig | 15 ++ .../firmware/arm_scmi/vendors/qcom/Makefile | 2 + .../arm_scmi/vendors/qcom/qcom-generic-ext.c | 135 ++++++++++++++++++ include/linux/scmi_qcom_protocol.h | 37 +++++ 6 files changed, 191 insertions(+) create mode 100644 drivers/firmware/arm_scmi/vendors/qcom/Kconfig create mode 100644 drivers/firmware/arm_scmi/vendors/qcom/Makefile create mode 100644 drivers/firmware/arm_scmi/vendors/qcom/qcom-generic-ext= .c create mode 100644 include/linux/scmi_qcom_protocol.h diff --git a/drivers/firmware/arm_scmi/Kconfig b/drivers/firmware/arm_scmi/= Kconfig index e3fb36825978..a52f4d1b8b2c 100644 --- a/drivers/firmware/arm_scmi/Kconfig +++ b/drivers/firmware/arm_scmi/Kconfig @@ -84,6 +84,7 @@ config ARM_SCMI_QUIRKS =20 source "drivers/firmware/arm_scmi/transports/Kconfig" source "drivers/firmware/arm_scmi/vendors/imx/Kconfig" +source "drivers/firmware/arm_scmi/vendors/qcom/Kconfig" =20 endif #ARM_SCMI_PROTOCOL =20 diff --git a/drivers/firmware/arm_scmi/Makefile b/drivers/firmware/arm_scmi= /Makefile index 780cd62b2f78..5a0e003c2477 100644 --- a/drivers/firmware/arm_scmi/Makefile +++ b/drivers/firmware/arm_scmi/Makefile @@ -13,6 +13,7 @@ scmi-module-objs :=3D $(scmi-driver-y) $(scmi-protocols-y= ) $(scmi-transport-y) =20 obj-$(CONFIG_ARM_SCMI_PROTOCOL) +=3D transports/ obj-$(CONFIG_ARM_SCMI_PROTOCOL) +=3D vendors/imx/ +obj-$(CONFIG_ARM_SCMI_PROTOCOL) +=3D vendors/qcom/ =20 obj-$(CONFIG_ARM_SCMI_PROTOCOL) +=3D scmi-core.o obj-$(CONFIG_ARM_SCMI_PROTOCOL) +=3D scmi-module.o diff --git a/drivers/firmware/arm_scmi/vendors/qcom/Kconfig b/drivers/firmw= are/arm_scmi/vendors/qcom/Kconfig new file mode 100644 index 000000000000..5dd9e8a6b75f --- /dev/null +++ b/drivers/firmware/arm_scmi/vendors/qcom/Kconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "ARM SCMI QCOM Vendor Protocols" + +config QCOM_SCMI_GENERIC_EXT + tristate "Qualcomm Technologies, Inc. Qcom SCMI vendor Protocol" + depends on ARM_SCMI_PROTOCOL || COMPILE_TEST + help + The QCOM SCMI vendor protocol provides a generic way of exposing + a number of Qualcomm SoC specific features (like memory bus scaling) + through a mixture of pre-determined algorithm strings and param_id + pairs hosted on the SCMI controller. + + This driver defines/documents the message ID's used for this + communication and also exposes the operations used by the clients. +endmenu diff --git a/drivers/firmware/arm_scmi/vendors/qcom/Makefile b/drivers/firm= ware/arm_scmi/vendors/qcom/Makefile new file mode 100644 index 000000000000..6b98fabbebb8 --- /dev/null +++ b/drivers/firmware/arm_scmi/vendors/qcom/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_QCOM_SCMI_GENERIC_EXT) +=3D qcom-generic-ext.o diff --git a/drivers/firmware/arm_scmi/vendors/qcom/qcom-generic-ext.c b/dr= ivers/firmware/arm_scmi/vendors/qcom/qcom-generic-ext.c new file mode 100644 index 000000000000..4f9eba8ff4bd --- /dev/null +++ b/drivers/firmware/arm_scmi/vendors/qcom/qcom-generic-ext.c @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +#include "../../common.h" + +/** + * enum qcom_generic_ext_protocol_cmd - vendor specific commands supported= by SCMI Qualcomm + * generic vendor protocol. + * + * This protocol is intended as a generic way of exposing a number of Qual= comm SoC + * specific features through a mixture of pre-determined algorithm string = and param_id + * pairs hosted on the SCMI controller. + * + * The QCOM SCMI Vendor Protocol has the protocol id as 0x80 and vendor id= set to + * Qualcomm and the supported version is set to 0x10000. The PROTOCOL_VERS= ION command + * returns version 1.0. + * + * @QCOM_SCMI_SET_PARAM: is used to set the parameter of a specific algo_s= tr hosted on + * QCOM SCMI Vendor Protocol. The tx len depends on the algo_str used. + * @QCOM_SCMI_GET_PARAM: is used to get parameter information of a specifi= c algo_str + * hosted on QCOM SCMI Vendor Protocol. The tx and rx len depends + * on the algo_str used. + * @QCOM_SCMI_START_ACTIVITY: is used to start the activity performed by t= he algo_str. + * @QCOM_SCMI_STOP_ACTIVITY: is used to stop a pre-existing activity perfo= rmed by the algo_str. + */ +enum qcom_generic_ext_protocol_cmd { + QCOM_SCMI_SET_PARAM =3D 0x10, + QCOM_SCMI_GET_PARAM =3D 0x11, + QCOM_SCMI_START_ACTIVITY =3D 0x12, + QCOM_SCMI_STOP_ACTIVITY =3D 0x13, +}; + +/** + * struct qcom_scmi_msg - represents the various parameters to be populated + * for using the QCOM SCMI Vendor Protocol + * + * @ext_id: reserved, must be zero + * @algo_low: lower 32 bits of the algo_str + * @algo_high: upper 32 bits of the algo_str + * @param_id: serves as token message id to the specific algo_str + * @buf: serves as the payload to the specified param_id and algo_str pair + */ +struct qcom_scmi_msg { + __le32 ext_id; + __le32 algo_low; + __le32 algo_high; + __le32 param_id; + __le32 buf[]; +}; + +static int qcom_scmi_common_xfer(const struct scmi_protocol_handle *ph, + enum qcom_generic_ext_protocol_cmd cmd_id, void *buf, + size_t buf_len, u64 algo_str, u32 param_id, size_t rx_size) +{ + struct scmi_xfer *t; + struct qcom_scmi_msg *msg; + int ret; + + ret =3D ph->xops->xfer_get_init(ph, cmd_id, buf_len + sizeof(*msg), rx_si= ze, &t); + if (ret) + return ret; + + msg =3D t->tx.buf; + msg->algo_low =3D cpu_to_le32(lower_32_bits(algo_str)); + msg->algo_high =3D cpu_to_le32(upper_32_bits(algo_str)); + msg->param_id =3D cpu_to_le32(param_id); + memcpy(msg->buf, buf, buf_len); + + ret =3D ph->xops->do_xfer(ph, t); + if (!ret && rx_size) + memcpy(buf, t->rx.buf, t->rx.len); + ph->xops->xfer_put(ph, t); + + return ret; +} + +static int qcom_scmi_set_param(const struct scmi_protocol_handle *ph, void= *buf, size_t buf_len, + u64 algo_str, u32 param_id) +{ + return qcom_scmi_common_xfer(ph, QCOM_SCMI_SET_PARAM, buf, buf_len, algo_= str, + param_id, 0); +} + +static int qcom_scmi_get_param(const struct scmi_protocol_handle *ph, void= *buf, size_t buf_len, + u64 algo_str, u32 param_id, size_t rx_size) +{ + return qcom_scmi_common_xfer(ph, QCOM_SCMI_GET_PARAM, buf, buf_len, algo_= str, + param_id, rx_size); +} + +static int qcom_scmi_start_activity(const struct scmi_protocol_handle *ph,= void *buf, + size_t buf_len, u64 algo_str, u32 param_id) +{ + return qcom_scmi_common_xfer(ph, QCOM_SCMI_START_ACTIVITY, buf, buf_len, = algo_str, + param_id, 0); +} + +static int qcom_scmi_stop_activity(const struct scmi_protocol_handle *ph, = void *buf, + size_t buf_len, u64 algo_str, u32 param_id) +{ + return qcom_scmi_common_xfer(ph, QCOM_SCMI_STOP_ACTIVITY, buf, buf_len, a= lgo_str, + param_id, 0); +} + +static struct qcom_generic_ext_ops qcom_proto_ops =3D { + .set_param =3D qcom_scmi_set_param, + .get_param =3D qcom_scmi_get_param, + .start_activity =3D qcom_scmi_start_activity, + .stop_activity =3D qcom_scmi_stop_activity, +}; + +static int qcom_generic_ext_protocol_init(const struct scmi_protocol_handl= e *ph) +{ + dev_dbg(ph->dev, "QCOM Generic Vendor Version %d.%d\n", + PROTOCOL_REV_MAJOR(ph->version), PROTOCOL_REV_MINOR(ph->version)); + + return 0; +} + +static const struct scmi_protocol qcom_generic_ext =3D { + .id =3D SCMI_PROTOCOL_QCOM_GENERIC, + .owner =3D THIS_MODULE, + .instance_init =3D &qcom_generic_ext_protocol_init, + .ops =3D &qcom_proto_ops, + .vendor_id =3D "Qualcomm", + .supported_version =3D 0x10000, +}; +module_scmi_protocol(qcom_generic_ext); + +MODULE_DESCRIPTION("QCOM SCMI Generic Vendor protocol"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/scmi_qcom_protocol.h b/include/linux/scmi_qcom_p= rotocol.h new file mode 100644 index 000000000000..465b2522ca29 --- /dev/null +++ b/include/linux/scmi_qcom_protocol.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * SCMI Message Protocol driver QCOM extension header + * + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#ifndef _LINUX_SCMI_QCOM_PROTOCOL_H +#define _LINUX_SCMI_QCOM_PROTOCOL_H + +#include + +#define SCMI_PROTOCOL_QCOM_GENERIC 0x80 + +struct scmi_protocol_handle; + +/** + * struct qcom_generic_ext_ops - represents the various operations provided + * by QCOM Generic Vendor Protocol + * + * @set_param: set parameter specified by param_id and algo_str pair. + * @get_param: retrieve parameter specified by param_id and algo_str pair. + * @start_activity: initiate a specific activity defined by algo_str. + * @stop_activity: halt previously initiated activity defined by algo_str. + */ +struct qcom_generic_ext_ops { + int (*set_param)(const struct scmi_protocol_handle *ph, void *buf, size_t= buf_len, + u64 algo_str, u32 param_id); + int (*get_param)(const struct scmi_protocol_handle *ph, void *buf, size_t= buf_len, + u64 algo_str, u32 param_id, size_t rx_size); + int (*start_activity)(const struct scmi_protocol_handle *ph, void *buf, s= ize_t buf_len, + u64 algo_str, u32 param_id); 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83965945101sm7346557b3a.13.2026.05.06.23.23.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2026 23:23:10 -0700 (PDT) From: Sibi Sankar To: cristian.marussi@arm.com, sudeep.holla@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, myungjoo.ham@samsung.com, konradybcio@kernel.org, andersson@kernel.org Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, arm-scmi@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, dmitry.baryshkov@oss.qualcomm.com, jonathanh@nvidia.com, thierry.reding@kernel.org, digetx@gmail.com, conor+dt@kernel.org, krzk+dt@kernel.org, robh@kernel.org Subject: [RFC V6 3/8] PM / devfreq: Add new target_freq attribute flag for governors Date: Thu, 7 May 2026 11:52:32 +0530 Message-Id: <20260507062237.78051-4-sibi.sankar@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260507062237.78051-1-sibi.sankar@oss.qualcomm.com> References: <20260507062237.78051-1-sibi.sankar@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=Wv4b99fv c=1 sm=1 tr=0 ts=69fc2fcf cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=K3uUPCIpGL4zgFOSzcMA:9 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-ORIG-GUID: 0KQHntC46yFSab8g1sHPY9pUHa5KHKym X-Proofpoint-GUID: 0KQHntC46yFSab8g1sHPY9pUHa5KHKym X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA3MDA2MCBTYWx0ZWRfX34+hxNSd3zgX VGifnMz7k5NxUXhstpba0iQJtmx1RacUn/JtbQ1KEqc0mdhhqH96sryrw4eZFQY0lwfFiptBUwY IrF9Krgug+C42EjoXOooc/MhubKJ89fX1pNdF3RovBcDdnjhX84h9RCQj3kTOptvds54adPCsXp YZkRq5hzK0gBcMxoBd0kGSaEdr5874xMe8NXo5dM/08186AgknNugfcipnvzxymsdtap7JhaKU3 nvNHFxYoavQSZlnh3oOOlJumkQFkckzcbP8GhQ0BazZLWQWMdsl/MCzsQxhfhg6XYGwQrWXhHVD VKQGnybLcbe6WgMqLcf0Z2jwt46HuC9Rhc+CFaOkjJlyaWBVVmHIdHuMz9umQGAbtHTP4k323sL zOOj4eJX2iTPx3xvby5qAvEr6X3w42Qp4pfIr37XRsn6NRM/KXfrmuU3Wd6CD50QLr1UKDajIF3 7apefrrvIrREwgBNvrA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-06_02,2026-05-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 impostorscore=0 spamscore=0 phishscore=0 priorityscore=1501 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605070060 Content-Type: text/plain; charset="utf-8" Introduce the target_freq attribute flag as a pre-cursor to adding support for devfreq governors who do not explicitly allow for a method to get/set target frequency. Signed-off-by: Sibi Sankar --- drivers/devfreq/devfreq.c | 4 ++++ drivers/devfreq/governor_passive.c | 1 + drivers/devfreq/governor_performance.c | 1 + drivers/devfreq/governor_powersave.c | 1 + drivers/devfreq/governor_simpleondemand.c | 1 + drivers/devfreq/governor_userspace.c | 1 + drivers/devfreq/hisi_uncore_freq.c | 1 + drivers/devfreq/tegra30-devfreq.c | 3 ++- include/linux/devfreq-governor.h | 3 +++ 9 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c index e5d3f9cf94dc..85e937e321e8 100644 --- a/drivers/devfreq/devfreq.c +++ b/drivers/devfreq/devfreq.c @@ -1526,6 +1526,10 @@ static ssize_t target_freq_show(struct device *dev, { struct devfreq *df =3D to_devfreq(dev); =20 + if (!df->profile || !df->governor || + !IS_SUPPORTED_ATTR(df->governor->attrs, TARGET_FREQ)) + return -EINVAL; + return sprintf(buf, "%lu\n", df->previous_freq); } static DEVICE_ATTR_RO(target_freq); diff --git a/drivers/devfreq/governor_passive.c b/drivers/devfreq/governor_= passive.c index d7feecd900f1..b75e4bbee4b1 100644 --- a/drivers/devfreq/governor_passive.c +++ b/drivers/devfreq/governor_passive.c @@ -448,6 +448,7 @@ static int devfreq_passive_event_handler(struct devfreq= *devfreq, =20 static struct devfreq_governor devfreq_passive =3D { .name =3D DEVFREQ_GOV_PASSIVE, + .attrs =3D DEVFREQ_GOV_ATTR_TARGET_FREQ, .flags =3D DEVFREQ_GOV_FLAG_IMMUTABLE, .get_target_freq =3D devfreq_passive_get_target_freq, .event_handler =3D devfreq_passive_event_handler, diff --git a/drivers/devfreq/governor_performance.c b/drivers/devfreq/gover= nor_performance.c index fdb22bf512cf..b9ec587f582c 100644 --- a/drivers/devfreq/governor_performance.c +++ b/drivers/devfreq/governor_performance.c @@ -37,6 +37,7 @@ static int devfreq_performance_handler(struct devfreq *de= vfreq, =20 static struct devfreq_governor devfreq_performance =3D { .name =3D DEVFREQ_GOV_PERFORMANCE, + .attrs =3D DEVFREQ_GOV_ATTR_TARGET_FREQ, .get_target_freq =3D devfreq_performance_func, .event_handler =3D devfreq_performance_handler, }; diff --git a/drivers/devfreq/governor_powersave.c b/drivers/devfreq/governo= r_powersave.c index ee2d6ec8a512..69eab1d0a7fc 100644 --- a/drivers/devfreq/governor_powersave.c +++ b/drivers/devfreq/governor_powersave.c @@ -37,6 +37,7 @@ static int devfreq_powersave_handler(struct devfreq *devf= req, =20 static struct devfreq_governor devfreq_powersave =3D { .name =3D DEVFREQ_GOV_POWERSAVE, + .attrs =3D DEVFREQ_GOV_ATTR_TARGET_FREQ, .get_target_freq =3D devfreq_powersave_func, .event_handler =3D devfreq_powersave_handler, }; diff --git a/drivers/devfreq/governor_simpleondemand.c b/drivers/devfreq/go= vernor_simpleondemand.c index ac9c5e9e51a4..65ff9d912ef9 100644 --- a/drivers/devfreq/governor_simpleondemand.c +++ b/drivers/devfreq/governor_simpleondemand.c @@ -118,6 +118,7 @@ static int devfreq_simple_ondemand_handler(struct devfr= eq *devfreq, static struct devfreq_governor devfreq_simple_ondemand =3D { .name =3D DEVFREQ_GOV_SIMPLE_ONDEMAND, .attrs =3D DEVFREQ_GOV_ATTR_POLLING_INTERVAL + | DEVFREQ_GOV_ATTR_TARGET_FREQ | DEVFREQ_GOV_ATTR_TIMER, .get_target_freq =3D devfreq_simple_ondemand_func, .event_handler =3D devfreq_simple_ondemand_handler, diff --git a/drivers/devfreq/governor_userspace.c b/drivers/devfreq/governo= r_userspace.c index 3906ebedbae8..d1b765a7b8e5 100644 --- a/drivers/devfreq/governor_userspace.c +++ b/drivers/devfreq/governor_userspace.c @@ -135,6 +135,7 @@ static int devfreq_userspace_handler(struct devfreq *de= vfreq, =20 static struct devfreq_governor devfreq_userspace =3D { .name =3D DEVFREQ_GOV_USERSPACE, + .attrs =3D DEVFREQ_GOV_ATTR_TARGET_FREQ, .get_target_freq =3D devfreq_userspace_func, .event_handler =3D devfreq_userspace_handler, }; diff --git a/drivers/devfreq/hisi_uncore_freq.c b/drivers/devfreq/hisi_unco= re_freq.c index 4d00d813c8ac..0800116e3334 100644 --- a/drivers/devfreq/hisi_uncore_freq.c +++ b/drivers/devfreq/hisi_uncore_freq.c @@ -399,6 +399,7 @@ static struct devfreq_governor hisi_platform_governor = =3D { * Set interrupt_driven to skip the devfreq monitor mechanism, though * this governor is not interrupt-driven. */ + .attrs =3D DEVFREQ_GOV_ATTR_TARGET_FREQ, .flags =3D DEVFREQ_GOV_FLAG_IRQ_DRIVEN, .get_target_freq =3D hisi_platform_gov_func, .event_handler =3D hisi_platform_gov_handler, diff --git a/drivers/devfreq/tegra30-devfreq.c b/drivers/devfreq/tegra30-de= vfreq.c index 401aac6a9f07..fcb278c4a74c 100644 --- a/drivers/devfreq/tegra30-devfreq.c +++ b/drivers/devfreq/tegra30-devfreq.c @@ -776,7 +776,8 @@ static int tegra_governor_event_handler(struct devfreq = *devfreq, =20 static struct devfreq_governor tegra_devfreq_governor =3D { .name =3D "tegra_actmon", - .attrs =3D DEVFREQ_GOV_ATTR_POLLING_INTERVAL, + .attrs =3D DEVFREQ_GOV_ATTR_POLLING_INTERVAL + | DEVFREQ_GOV_ATTR_TARGET_FREQ, .flags =3D DEVFREQ_GOV_FLAG_IMMUTABLE | DEVFREQ_GOV_FLAG_IRQ_DRIVEN, .get_target_freq =3D tegra_governor_get_target, diff --git a/include/linux/devfreq-governor.h b/include/linux/devfreq-gover= nor.h index dfdd0160a29f..2853f571dfdf 100644 --- a/include/linux/devfreq-governor.h +++ b/include/linux/devfreq-governor.h @@ -43,9 +43,12 @@ * : Indicate polling_interval sysfs attribute * - DEVFREQ_GOV_ATTR_TIMER * : Indicate timer sysfs attribute + * - DEVFREQ_GOV_ATTR_TARGET_FREQ + * : Indicate the target freq sysfs attribute */ #define DEVFREQ_GOV_ATTR_POLLING_INTERVAL BIT(0) #define DEVFREQ_GOV_ATTR_TIMER BIT(1) +#define DEVFREQ_GOV_ATTR_TARGET_FREQ BIT(2) =20 /** * struct devfreq_governor - Devfreq policy governor --=20 2.34.1 From nobody Sat Jun 13 14:03:16 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BCD82242D9B for ; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83965945101sm7346557b3a.13.2026.05.06.23.23.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2026 23:23:16 -0700 (PDT) From: Sibi Sankar To: cristian.marussi@arm.com, sudeep.holla@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, myungjoo.ham@samsung.com, konradybcio@kernel.org, andersson@kernel.org Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, arm-scmi@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, dmitry.baryshkov@oss.qualcomm.com, jonathanh@nvidia.com, thierry.reding@kernel.org, digetx@gmail.com, conor+dt@kernel.org, krzk+dt@kernel.org, robh@kernel.org Subject: [RFC V6 4/8] PM / devfreq: Add new track_remote flag for governors Date: Thu, 7 May 2026 11:52:33 +0530 Message-Id: <20260507062237.78051-5-sibi.sankar@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260507062237.78051-1-sibi.sankar@oss.qualcomm.com> References: <20260507062237.78051-1-sibi.sankar@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=EoPiaycA c=1 sm=1 tr=0 ts=69fc2fd6 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=LlpFjwiIyvKxJCA_QE0A:9 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-ORIG-GUID: mYEO9fUoG_DUwCXBWFVZ2FhIXZqE4URD X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA3MDA2MCBTYWx0ZWRfX9ShttVyRf/6X GoU3mMRVa/pntKqZ8qYOiNbVCl11m/5CGzn3pPrC2Bz3t/SgJSt/n1i9JDvBW3ttcuRVH5hTM0v xMb/SK8bQl6Mp/ptQNAg58a+QhUTkJP0tXG7/w5JkxtDIwmsM2c4PM3EH8Ry0HW8jcBjz0hEbmZ 1VgutSgC7JWrZoCMq12SLcoKzQYfwjbDGSRZ1P9JnrJuvHlGPym5yNJWtKUCPFb646CiUP40lr1 B4/R8nM2Fqzuo9WBmtlSUbdEGmRwz/346qR+beDLMuWw0ePON3l5eYnJNy9emwsXKL351w+OH5l f4IuE/Y+8gkvIK+qoVcHGbQPSKysLMeU9cR9r7v/8YJ0Iwjh4AQVD7WkYQewuz4JNbqw9S+hhDp 9OXIkPZPqWg8hfPA/2B7ACpJ+uTdfjkFEDG8G8qp278HUxzklTS//X+N2H+MomBTR02ER8q7Ufl Y8+ng0uWtUZinLILZAQ== X-Proofpoint-GUID: mYEO9fUoG_DUwCXBWFVZ2FhIXZqE4URD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-06_02,2026-05-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605070060 Content-Type: text/plain; charset="utf-8" Add a new track_remote flag for devfreq governors as a pre-curor to adding the devfreq governors that is responsible for tracking frequency changes on remote devices. This new governor flag provides for a way track the remote device's frequency and keep the trans_stat data updated and skip the frequency update sequency for the device. Signed-off-by: Sibi Sankar --- drivers/devfreq/devfreq.c | 5 +++++ include/linux/devfreq-governor.h | 1 + 2 files changed, 6 insertions(+) diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c index 85e937e321e8..e0272078912b 100644 --- a/drivers/devfreq/devfreq.c +++ b/drivers/devfreq/devfreq.c @@ -348,6 +348,10 @@ static int devfreq_set_target(struct devfreq *devfreq,= unsigned long new_freq, unsigned long cur_freq; int err =3D 0; =20 + /* Frequency already updated, update trans-stat info */ + if (IS_SUPPORTED_FLAG(devfreq->governor->flags, TRACK_REMOTE)) + goto update_status; + if (devfreq->profile->get_cur_freq) devfreq->profile->get_cur_freq(devfreq->dev.parent, &cur_freq); else @@ -375,6 +379,7 @@ static int devfreq_set_target(struct devfreq *devfreq, = unsigned long new_freq, freqs.new =3D new_freq; devfreq_notify_transition(devfreq, &freqs, DEVFREQ_POSTCHANGE); =20 +update_status: if (devfreq_update_status(devfreq, new_freq)) dev_warn(&devfreq->dev, "Couldn't update frequency transition information.\n"); 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83965945101sm7346557b3a.13.2026.05.06.23.23.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2026 23:23:22 -0700 (PDT) From: Sibi Sankar To: cristian.marussi@arm.com, sudeep.holla@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, myungjoo.ham@samsung.com, konradybcio@kernel.org, andersson@kernel.org Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, arm-scmi@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, dmitry.baryshkov@oss.qualcomm.com, jonathanh@nvidia.com, thierry.reding@kernel.org, digetx@gmail.com, conor+dt@kernel.org, krzk+dt@kernel.org, robh@kernel.org Subject: [RFC V6 5/8] PM / devfreq: Add a governor for tracking remote device frequencies Date: Thu, 7 May 2026 11:52:34 +0530 Message-Id: <20260507062237.78051-6-sibi.sankar@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260507062237.78051-1-sibi.sankar@oss.qualcomm.com> References: <20260507062237.78051-1-sibi.sankar@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=Wv4b99fv c=1 sm=1 tr=0 ts=69fc2fdc cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=4aD_1Snzd4jiIFQuHjIA:9 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-ORIG-GUID: wDjiCj16yVNW2qxe6lDhvYiKwAIvSGvY X-Proofpoint-GUID: wDjiCj16yVNW2qxe6lDhvYiKwAIvSGvY X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA3MDA2MCBTYWx0ZWRfX66Q59z79Ec6p coGHKVIotKXwGDL9TDws1Iip7GNAfV+ZH3CeTfPNkYngauyVpG5rbgF3STTmK7v/TTQ2KUENczH aCbGu8SCmeVOC5+cqmsAkawhPTBDVrM9ZRRohyb9/6XTd7gIPPHX8Kom4WG8y91wd5187zLIeWG Ty2DJbdHk/HDqiyy/qDYbjaERwUDylvPRorq60UrGoJmPuWtYAdATKNBqj9rqaguR6FQIHlyJrM E4zErDtTODZBV1MWSjmOKbilhbaLw76++b0AyhgZ84AVMZzJvxSi5hqnmNt7cYiHnOAaW7dXs0x 2oz1oPLlZzBtKVZStxZxXMxjfonWAcwalU5gxqaJ6lIiR3dPt811y7AWzWoRJaHPQpz2H7wAwlo W5SJ95RHry0M0AjvXqGQziYT9k7QHPPVZlrGhko4dMJpGudNQoM4dZ5Vv0UVE1pPoT+GsAJ99Ty abgo38VcYq9enpDNBgA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-06_02,2026-05-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 impostorscore=0 spamscore=0 phishscore=0 priorityscore=1501 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605070060 Content-Type: text/plain; charset="utf-8" On SoCs, where the governor and the mechanism to control the frequency for devices like caches is hosted on the System Control Processor (SCP), there exists a need track the frequency changes in a reliable way and provide ways to tweaking parameters on the remote governor. To address this introduce the new remote devfreq governor that provides for a way to track the frequency changes on remote devices. It uses the newly introduced target_freq attribute flag and track_remote flag to achieve this. Signed-off-by: Sibi Sankar --- drivers/devfreq/Kconfig | 8 ++++ drivers/devfreq/Makefile | 1 + drivers/devfreq/governor_remote.c | 80 +++++++++++++++++++++++++++++++ include/linux/devfreq.h | 1 + 4 files changed, 90 insertions(+) create mode 100644 drivers/devfreq/governor_remote.c diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig index c999c4a1e567..2caa87554914 100644 --- a/drivers/devfreq/Kconfig +++ b/drivers/devfreq/Kconfig @@ -56,6 +56,14 @@ config DEVFREQ_GOV_POWERSAVE the DEVFREQ framework returns the lowest frequency available at any time. =20 +config DEVFREQ_GOV_REMOTE + tristate "Remote" + help + A simple governor to track the frequency of devices whose + dvfs control lies outside the kernel. This governor acts + as an observer and provides for ways to track frequency and + set/get information related to the remote dvfs device. + config DEVFREQ_GOV_USERSPACE tristate "Userspace" help diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile index 404179d79a9d..cde57c8cda76 100644 --- a/drivers/devfreq/Makefile +++ b/drivers/devfreq/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_PM_DEVFREQ_EVENT) +=3D devfreq-event.o obj-$(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND) +=3D governor_simpleondemand.o obj-$(CONFIG_DEVFREQ_GOV_PERFORMANCE) +=3D governor_performance.o obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE) +=3D governor_powersave.o +obj-$(CONFIG_DEVFREQ_GOV_REMOTE) +=3D governor_remote.o obj-$(CONFIG_DEVFREQ_GOV_USERSPACE) +=3D governor_userspace.o obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) +=3D governor_passive.o =20 diff --git a/drivers/devfreq/governor_remote.c b/drivers/devfreq/governor_r= emote.c new file mode 100644 index 000000000000..6bff3cdaf1e5 --- /dev/null +++ b/drivers/devfreq/governor_remote.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include + +static int devfreq_remote_track_func(struct devfreq *devfreq, unsigned lon= g *freq) +{ + unsigned long cur_freq =3D 0; + + if (devfreq->profile->get_cur_freq) + devfreq->profile->get_cur_freq(devfreq->dev.parent, &cur_freq); + + *freq =3D cur_freq; + + return 0; +} + +static int devfreq_remote_track_handler(struct devfreq *devfreq, unsigned = int event, void *data) +{ + switch (event) { + case DEVFREQ_GOV_START: + devfreq_monitor_start(devfreq); + break; + + case DEVFREQ_GOV_STOP: + devfreq_monitor_stop(devfreq); + break; + + case DEVFREQ_GOV_UPDATE_INTERVAL: + devfreq_update_interval(devfreq, (unsigned int *)data); + break; + + case DEVFREQ_GOV_SUSPEND: + devfreq_monitor_suspend(devfreq); + break; + + case DEVFREQ_GOV_RESUME: + devfreq_monitor_resume(devfreq); + break; + + default: + break; + } + + return 0; +} + +static struct devfreq_governor devfreq_remote_track =3D { + .name =3D DEVFREQ_GOV_REMOTE, + .attrs =3D DEVFREQ_GOV_ATTR_POLLING_INTERVAL + | DEVFREQ_GOV_ATTR_TIMER, + .flags =3D DEVFREQ_GOV_FLAG_IMMUTABLE + | DEVFREQ_GOV_FLAG_TRACK_REMOTE, + .get_target_freq =3D devfreq_remote_track_func, + .event_handler =3D devfreq_remote_track_handler, +}; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83965945101sm7346557b3a.13.2026.05.06.23.23.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2026 23:23:30 -0700 (PDT) From: Sibi Sankar To: cristian.marussi@arm.com, sudeep.holla@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, myungjoo.ham@samsung.com, konradybcio@kernel.org, andersson@kernel.org Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, arm-scmi@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, dmitry.baryshkov@oss.qualcomm.com, jonathanh@nvidia.com, thierry.reding@kernel.org, digetx@gmail.com, conor+dt@kernel.org, krzk+dt@kernel.org, robh@kernel.org, Shivnandan Kumar , Ramakrishna Gottimukkula , Amir Vajid Subject: [RFC V6 6/8] PM / devfreq: Introduce the QCOM SCMI Memlat devfreq device Date: Thu, 7 May 2026 11:52:35 +0530 Message-Id: <20260507062237.78051-7-sibi.sankar@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260507062237.78051-1-sibi.sankar@oss.qualcomm.com> References: <20260507062237.78051-1-sibi.sankar@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=P6IKQCAu c=1 sm=1 tr=0 ts=69fc2fe7 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=iu2ft60PGK6uEemCoLAA:9 a=zc0IvFSfCIW2DFIPzwfm:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: 0nOi4Tp5CKPzT0pMGhllbG9TsGfQJfdu X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA3MDA2MCBTYWx0ZWRfXwQoEHZ7UHl4L tnGX6WpE4cwXot77umIF7+qDQTAkWs0DqcN8JMWtd56RPkl19SbeMCK0BCuTDqEel8BrC2CG3G3 4nRtC83YoM5Ro51DXkFj5Yw1YNZbqA8CgMrR541fBCFeYQUjTrJhEApq6bsxeohaMPgTxP6tBBw iYk6tJi+VgCrVEyA3Zeaxdk2kQQZku5rlk8Tdowr+JfAFxZGq0zO0CSsQdyjXBKfnLubw4fk7KS yXoXfeWPt6eYRj0LJzhVmLvcC8YlvOwTH2Kfwdfmr3Ykk0qAlLshu32qBbgv2F+d6+YuNwsfXdU lV1ru0qXWbl1Y/Yyuy0z05ptCiJsRnsBOOT5bPfucU+jcMjVHjFS7P0lV9fPhGczKJFMObI35WQ ZGqwrZ4RxjuPfYohLlvbC6Vax6ofEUPDkqa+OSbvwK8GYrMbZr86vfNvT5TGr5fBoA86nmkTsKC UcQRKbTRlS0K+fT7Gvg== X-Proofpoint-GUID: 0nOi4Tp5CKPzT0pMGhllbG9TsGfQJfdu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-06_02,2026-05-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 suspectscore=0 clxscore=1015 bulkscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605070060 Content-Type: text/plain; charset="utf-8" On Qualcomm Glymur and Hamoa SoCs, the memlat governor and the mechanism to control the various caches and ram is hosted on the CPU Control Processor (CPUCP) and the method to tweak and start the governor is exposed through the QCOM SCMI Generic Extension Protocol. Introduce the devfreq scmi client driver that uses the memlat algorithm string hosted on QCOM SCMI Generic Extension Protocol to detect memory latency workloads and control frequency/level of the various memory buses (DDR/LLCC/DDR_QOS). The DDR/LLCC/DDR_QOS are modelled as devfreq devices, with the governor set to remote devfreq governor. This serves as a way to get a basic insight into the device operation through trans_stat and provides for ways to further tweak the parameters of the remote governor. Co-developed-by: Shivnandan Kumar Signed-off-by: Shivnandan Kumar Co-developed-by: Ramakrishna Gottimukkula Signed-off-by: Ramakrishna Gottimukkula Co-developed-by: Amir Vajid Signed-off-by: Amir Vajid Signed-off-by: Sibi Sankar --- drivers/devfreq/Kconfig | 13 + drivers/devfreq/Makefile | 1 + drivers/devfreq/scmi-qcom-memlat-cfg.h | 473 +++++++++++++++++ drivers/devfreq/scmi-qcom-memlat-devfreq.c | 582 +++++++++++++++++++++ 4 files changed, 1069 insertions(+) create mode 100644 drivers/devfreq/scmi-qcom-memlat-cfg.h create mode 100644 drivers/devfreq/scmi-qcom-memlat-devfreq.c diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig index 2caa87554914..98b5a50d3189 100644 --- a/drivers/devfreq/Kconfig +++ b/drivers/devfreq/Kconfig @@ -169,6 +169,19 @@ config ARM_SUN8I_A33_MBUS_DEVFREQ This adds the DEVFREQ driver for the MBUS controller in some Allwinner sun8i (A33 through H3) and sun50i (A64 and H5) SoCs. =20 +config SCMI_QCOM_MEMLAT_DEVFREQ + tristate "Qualcomm Technologies Inc. SCMI client driver" + depends on QCOM_SCMI_GENERIC_EXT || COMPILE_TEST + select DEVFREQ_GOV_REMOTE + help + This driver uses the MEMLAT (memory latency) algorithm string + hosted on QCOM SCMI Vendor Protocol to detect memory latency + workloads and control frequency/level of the various memory + buses (DDR/LLCC/DDR_QOS). + + This driver defines/documents the parameter IDs used while configuring + the memory buses. + source "drivers/devfreq/event/Kconfig" =20 endif # PM_DEVFREQ diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile index cde57c8cda76..b11f94e2f485 100644 --- a/drivers/devfreq/Makefile +++ b/drivers/devfreq/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) +=3D mtk-cci-devfr= eq.o obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) +=3D rk3399_dmc.o obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) +=3D sun8i-a33-mbus.o obj-$(CONFIG_ARM_TEGRA_DEVFREQ) +=3D tegra30-devfreq.o +obj-$(CONFIG_SCMI_QCOM_MEMLAT_DEVFREQ) +=3D scmi-qcom-memlat-devfreq.o =20 # DEVFREQ Event Drivers obj-$(CONFIG_PM_DEVFREQ_EVENT) +=3D event/ diff --git a/drivers/devfreq/scmi-qcom-memlat-cfg.h b/drivers/devfreq/scmi-= qcom-memlat-cfg.h new file mode 100644 index 000000000000..e56899489db4 --- /dev/null +++ b/drivers/devfreq/scmi-qcom-memlat-cfg.h @@ -0,0 +1,473 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DRIVERS_DEVFREQ_SCMI_QCOM_MEMLAT_CONFIG_H__ +#define __DRIVERS_DEVFREQ_SCMI_QCOM_MEMLAT_CONFIG_H__ + +/* + * Memlat Effective Frequency Calculation Method + * CPUCP_EFFECTIVE_FREQ_METHOD_0 - Uses CPU Cycles and CONST Cycles to cal= culate + * CPUCP_EFFECTIVE_FREQ_METHOD_1 - Uses CPU Cycles and time period + */ +#define CPUCP_EFFECTIVE_FREQ_CALC_METHOD_0 0 +#define CPUCP_EFFECTIVE_FREQ_CALC_METHOD_1 1 + +#define EV_CPU_CYCLES 0 +#define EV_CNT_CYCLES 1 +#define EV_INST_RETIRED 2 +#define EV_STALL_BACKEND_MEM 3 +#define EV_L2_D_RFILL 5 +#define INVALID_IDX 0xff + +#define MEMLAT_ALGO_STR 0x4D454D4C4154 /* MEMLAT */ + +struct scmi_qcom_map_table { + unsigned int cpu_freq; + unsigned int mem_freq; +}; + +struct scmi_qcom_opp_data { + unsigned long freq; + unsigned int level; +}; + +struct scmi_qcom_memory_range { + unsigned int min_freq; + unsigned int max_freq; +}; + +struct scmi_qcom_monitor_cfg { + const struct scmi_qcom_map_table *table; + const char *name; + u32 be_stall_floor; + u32 cpu_mask; + u32 ipm_ceil; + int table_len; +}; + +struct scmi_qcom_memory_cfg { + const struct scmi_qcom_monitor_cfg *monitor_cfg; + const struct scmi_qcom_opp_data *mem_table; + struct scmi_qcom_memory_range memory_range; + const char *name; + u32 memory_type; + int monitor_cnt; + int num_opps; +}; + +struct scmi_qcom_memlat_cfg_data { + const struct scmi_qcom_memory_cfg *memory_cfg; + u32 cpucp_freq_method; + u32 cpucp_sample_ms; + int memory_cnt; +}; + +static const struct scmi_qcom_opp_data glymur_llcc_table[] =3D { + { .freq =3D 315000000 }, + { .freq =3D 479000000 }, + { .freq =3D 545000000 }, + { .freq =3D 725000000 }, + { .freq =3D 840000000 }, + { .freq =3D 959000000 }, + { .freq =3D 1090000000 }, + { .freq =3D 1211000000 }, +}; + +static const struct scmi_qcom_opp_data hamoa_llcc_table[] =3D { + { .freq =3D 300000000 }, + { .freq =3D 466000000 }, + { .freq =3D 600000000 }, + { .freq =3D 806000000 }, + { .freq =3D 933000000 }, + { .freq =3D 1066000000 }, +}; + +static const struct scmi_qcom_opp_data glymur_ddr_table[] =3D { + { .freq =3D 200000000 }, + { .freq =3D 547000000 }, + { .freq =3D 1353000000 }, + { .freq =3D 1555000000 }, + { .freq =3D 1708000000 }, + { .freq =3D 2092000000 }, + { .freq =3D 2736000000 }, + { .freq =3D 3187000000 }, + { .freq =3D 3686000000 }, + { .freq =3D 4224000000 }, + { .freq =3D 4761000000 }, +}; + +static const struct scmi_qcom_opp_data hamoa_ddr_table[] =3D { + { .freq =3D 200000000 }, + { .freq =3D 547000000 }, + { .freq =3D 768000000 }, + { .freq =3D 1555000000 }, + { .freq =3D 1708000000 }, + { .freq =3D 2092000000 }, + { .freq =3D 2736000000 }, + { .freq =3D 3187000000 }, + { .freq =3D 3686000000 }, + { .freq =3D 4224000000 }, +}; + +static const struct scmi_qcom_opp_data glymur_ddr_qos_table[] =3D { + { .freq =3D 1, .level =3D 0 }, + { .freq =3D 100, .level =3D 1 }, +}; + +static const struct scmi_qcom_memory_cfg glymur_memory_cfg[] =3D { + { + .memory_type =3D 0, + .name =3D "ddr", + .mem_table =3D glymur_ddr_table, + .num_opps =3D ARRAY_SIZE(glymur_ddr_table), + .monitor_cnt =3D 4, + .memory_range =3D { .min_freq =3D 547000, .max_freq =3D 4761000}, + .monitor_cfg =3D (const struct scmi_qcom_monitor_cfg[]) { + { + .name =3D "mon_0", + .cpu_mask =3D 0x3f, + .ipm_ceil =3D 60000000, + .be_stall_floor =3D 1, + .table_len =3D 8, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 960, .mem_freq =3D 547000 }, + { .cpu_freq =3D 1133, .mem_freq =3D 1353000 }, + { .cpu_freq =3D 1594, .mem_freq =3D 1555000 }, + { .cpu_freq =3D 1920, .mem_freq =3D 1708000 }, + { .cpu_freq =3D 2228, .mem_freq =3D 2736000 }, + { .cpu_freq =3D 2362, .mem_freq =3D 3187000 }, + { .cpu_freq =3D 2650, .mem_freq =3D 3686000 }, + { .cpu_freq =3D 2938, .mem_freq =3D 4761000 }, + } + }, + { + .name =3D "mon_1", + .cpu_mask =3D 0xfc0, + .ipm_ceil =3D 60000000, + .be_stall_floor =3D 1, + .table_len =3D 8, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 356, .mem_freq =3D 547000 }, + { .cpu_freq =3D 1018, .mem_freq =3D 1353000 }, + { .cpu_freq =3D 1536, .mem_freq =3D 1555000 }, + { .cpu_freq =3D 1748, .mem_freq =3D 1708800 }, + { .cpu_freq =3D 2324, .mem_freq =3D 2736000 }, + { .cpu_freq =3D 2496, .mem_freq =3D 3187000 }, + { .cpu_freq =3D 2900, .mem_freq =3D 3686000 }, + { .cpu_freq =3D 3514, .mem_freq =3D 4761000 }, + } + }, + { + .name =3D "mon_2", + .cpu_mask =3D 0x3f000, + .ipm_ceil =3D 60000000, + .be_stall_floor =3D 1, + .table_len =3D 8, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 356, .mem_freq =3D 547000 }, + { .cpu_freq =3D 1018, .mem_freq =3D 1353000 }, + { .cpu_freq =3D 1536, .mem_freq =3D 1555000 }, + { .cpu_freq =3D 1748, .mem_freq =3D 1708800 }, + { .cpu_freq =3D 2324, .mem_freq =3D 2736000 }, + { .cpu_freq =3D 2496, .mem_freq =3D 3187000 }, + { .cpu_freq =3D 2900, .mem_freq =3D 3686000 }, + { .cpu_freq =3D 3514, .mem_freq =3D 4761000 }, + } + }, + { + .name =3D "mon_3", + .cpu_mask =3D 0x3ffff, + .table_len =3D 4, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 2823, .mem_freq =3D 547000 }, + { .cpu_freq =3D 3034, .mem_freq =3D 1555000 }, + { .cpu_freq =3D 3226, .mem_freq =3D 1708000 }, + { .cpu_freq =3D 5012, .mem_freq =3D 2092000 }, + } + }, + }, + }, + { + .memory_type =3D 1, + .name =3D "llcc", + .mem_table =3D glymur_llcc_table, + .num_opps =3D ARRAY_SIZE(glymur_llcc_table), + .monitor_cnt =3D 3, + .memory_range =3D { .min_freq =3D 315000, .max_freq =3D 1211000}, + .monitor_cfg =3D (const struct scmi_qcom_monitor_cfg[]) { + { + .name =3D "mon_0", + .cpu_mask =3D 0x3f, + .ipm_ceil =3D 60000000, + .be_stall_floor =3D 1, + .table_len =3D 7, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 960, .mem_freq =3D 315000 }, + { .cpu_freq =3D 1113, .mem_freq =3D 479000 }, + { .cpu_freq =3D 1594, .mem_freq =3D 545000 }, + { .cpu_freq =3D 1920, .mem_freq =3D 725000 }, + { .cpu_freq =3D 2362, .mem_freq =3D 840000 }, + { .cpu_freq =3D 2650, .mem_freq =3D 959000 }, + { .cpu_freq =3D 2938, .mem_freq =3D 1211000 }, + } + }, + { + .name =3D "mon_1", + .cpu_mask =3D 0xfc0, + .ipm_ceil =3D 60000000, + .be_stall_floor =3D 1, + .table_len =3D 7, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 356, .mem_freq =3D 315000 }, + { .cpu_freq =3D 1018, .mem_freq =3D 479000 }, + { .cpu_freq =3D 1536, .mem_freq =3D 545000 }, + { .cpu_freq =3D 1748, .mem_freq =3D 725000 }, + { .cpu_freq =3D 2496, .mem_freq =3D 840000 }, + { .cpu_freq =3D 2900, .mem_freq =3D 959000 }, + { .cpu_freq =3D 3514, .mem_freq =3D 1211000 }, + } + }, + { + .name =3D "mon_2", + .cpu_mask =3D 0x3f000, + .ipm_ceil =3D 60000000, + .be_stall_floor =3D 1, + .table_len =3D 7, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 356, .mem_freq =3D 315000 }, + { .cpu_freq =3D 1018, .mem_freq =3D 479000 }, + { .cpu_freq =3D 1536, .mem_freq =3D 545000 }, + { .cpu_freq =3D 1748, .mem_freq =3D 725000 }, + { .cpu_freq =3D 2496, .mem_freq =3D 840000 }, + { .cpu_freq =3D 2900, .mem_freq =3D 959000 }, + { .cpu_freq =3D 3514, .mem_freq =3D 1211000 }, + } + }, + }, + }, + { + .memory_type =3D 2, + .name =3D "ddr-qos", + .monitor_cnt =3D 3, + .mem_table =3D glymur_ddr_qos_table, + .num_opps =3D ARRAY_SIZE(glymur_ddr_qos_table), + .memory_range =3D { .min_freq =3D 0, .max_freq =3D 1}, + .monitor_cfg =3D (const struct scmi_qcom_monitor_cfg[]) { + { + .name =3D "mon_0", + .cpu_mask =3D 0x3f, + .ipm_ceil =3D 80000000, + .be_stall_floor =3D 1, + .table_len =3D 2, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 2362, .mem_freq =3D 0 }, + { .cpu_freq =3D 2938, .mem_freq =3D 1 }, + } + }, + { + .name =3D "mon_1", + .cpu_mask =3D 0xfc0, + .ipm_ceil =3D 80000000, + .be_stall_floor =3D 1, + .table_len =3D 2, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 2496, .mem_freq =3D 0 }, + { .cpu_freq =3D 3514, .mem_freq =3D 1 }, + } + }, + { + .name =3D "mon_2", + .cpu_mask =3D 0x3f000, + .ipm_ceil =3D 80000000, + .be_stall_floor =3D 1, + .table_len =3D 2, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 2496, .mem_freq =3D 0 }, + { .cpu_freq =3D 3514, .mem_freq =3D 1 }, + } + }, + }, + }, +}; + +static const struct scmi_qcom_memory_cfg hamoa_memory_cfg[] =3D { + { + .memory_type =3D 0, + .name =3D "ddr", + .mem_table =3D hamoa_ddr_table, + .num_opps =3D ARRAY_SIZE(hamoa_ddr_table), + .monitor_cnt =3D 4, + .memory_range =3D { .min_freq =3D 200000, .max_freq =3D 4224000}, + .monitor_cfg =3D (const struct scmi_qcom_monitor_cfg[]) { + { + .name =3D "mon_0", + .cpu_mask =3D 0xf, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 6, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 999, .mem_freq =3D 547000 }, + { .cpu_freq =3D 1440, .mem_freq =3D 768000 }, + { .cpu_freq =3D 1671, .mem_freq =3D 1555000 }, + { .cpu_freq =3D 2189, .mem_freq =3D 2092000 }, + { .cpu_freq =3D 2516, .mem_freq =3D 3187000 }, + { .cpu_freq =3D 3860, .mem_freq =3D 4224000 }, + } + }, + { + .name =3D "mon_1", + .cpu_mask =3D 0xf0, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 6, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 999, .mem_freq =3D 547000 }, + { .cpu_freq =3D 1440, .mem_freq =3D 768000 }, + { .cpu_freq =3D 1671, .mem_freq =3D 1555000 }, + { .cpu_freq =3D 2189, .mem_freq =3D 2092000 }, + { .cpu_freq =3D 2516, .mem_freq =3D 3187000 }, + { .cpu_freq =3D 3860, .mem_freq =3D 4224000 }, + } + }, + { + .name =3D "mon_2", + .cpu_mask =3D 0xf00, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 6, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 999, .mem_freq =3D 547000 }, + { .cpu_freq =3D 1440, .mem_freq =3D 768000 }, + { .cpu_freq =3D 1671, .mem_freq =3D 1555000 }, + { .cpu_freq =3D 2189, .mem_freq =3D 2092000 }, + { .cpu_freq =3D 2516, .mem_freq =3D 3187000 }, + { .cpu_freq =3D 3860, .mem_freq =3D 4224000 }, + } + }, + { + .name =3D "mon_3", + .cpu_mask =3D 0xfff, + .table_len =3D 4, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 1440, .mem_freq =3D 547000 }, + { .cpu_freq =3D 2189, .mem_freq =3D 768000 }, + { .cpu_freq =3D 2516, .mem_freq =3D 1555000 }, + { .cpu_freq =3D 3860, .mem_freq =3D 2092000 }, + } + }, + }, + }, + { + .memory_type =3D 1, + .name =3D "llcc", + .mem_table =3D hamoa_llcc_table, + .num_opps =3D ARRAY_SIZE(hamoa_llcc_table), + .monitor_cnt =3D 3, + .memory_range =3D { .min_freq =3D 300000, .max_freq =3D 1067000}, + .monitor_cfg =3D (const struct scmi_qcom_monitor_cfg[]) { + { + .name =3D "mon_0", + .cpu_mask =3D 0xf, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 6, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 999, .mem_freq =3D 300000 }, + { .cpu_freq =3D 1440, .mem_freq =3D 466000 }, + { .cpu_freq =3D 1671, .mem_freq =3D 600000 }, + { .cpu_freq =3D 2189, .mem_freq =3D 806000 }, + { .cpu_freq =3D 2516, .mem_freq =3D 933000 }, + { .cpu_freq =3D 3860, .mem_freq =3D 1066000 }, + } + }, + { + .name =3D "mon_1", + .cpu_mask =3D 0xf0, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 6, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 999, .mem_freq =3D 300000 }, + { .cpu_freq =3D 1440, .mem_freq =3D 466000 }, + { .cpu_freq =3D 1671, .mem_freq =3D 600000 }, + { .cpu_freq =3D 2189, .mem_freq =3D 806000 }, + { .cpu_freq =3D 2516, .mem_freq =3D 933000 }, + { .cpu_freq =3D 3860, .mem_freq =3D 1066000 }, + } + }, + { + .name =3D "mon_2", + .cpu_mask =3D 0xf00, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 6, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 999, .mem_freq =3D 300000 }, + { .cpu_freq =3D 1440, .mem_freq =3D 466000 }, + { .cpu_freq =3D 1671, .mem_freq =3D 600000 }, + { .cpu_freq =3D 2189, .mem_freq =3D 806000 }, + { .cpu_freq =3D 2516, .mem_freq =3D 933000 }, + { .cpu_freq =3D 3860, .mem_freq =3D 1066000 }, + } + }, + }, + }, + { + .memory_type =3D 2, + .name =3D "ddr-qos", + .monitor_cnt =3D 3, + .mem_table =3D glymur_ddr_qos_table, + .num_opps =3D ARRAY_SIZE(glymur_ddr_qos_table), + .memory_range =3D { .min_freq =3D 0, .max_freq =3D 1}, + .monitor_cfg =3D (const struct scmi_qcom_monitor_cfg[]) { + { + .name =3D "mon_0", + .cpu_mask =3D 0xf, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 2, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 2189, .mem_freq =3D 0 }, + { .cpu_freq =3D 3860, .mem_freq =3D 1 }, + } + }, + { + .name =3D "mon_1", + .cpu_mask =3D 0xf0, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 2, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 2189, .mem_freq =3D 0 }, + { .cpu_freq =3D 3860, .mem_freq =3D 1 }, + } + }, + { + .name =3D "mon_2", + .cpu_mask =3D 0xf00, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 2, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 2189, .mem_freq =3D 0 }, + { .cpu_freq =3D 3860, .mem_freq =3D 1 }, + } + }, + }, + }, +}; + +static const struct scmi_qcom_memlat_cfg_data glymur_memlat_data =3D { + .memory_cfg =3D glymur_memory_cfg, + .cpucp_freq_method =3D CPUCP_EFFECTIVE_FREQ_CALC_METHOD_1, + .cpucp_sample_ms =3D 4, + .memory_cnt =3D ARRAY_SIZE(glymur_memory_cfg), +}; + +static const struct scmi_qcom_memlat_cfg_data hamoa_memlat_data =3D { + .memory_cfg =3D hamoa_memory_cfg, + .cpucp_freq_method =3D CPUCP_EFFECTIVE_FREQ_CALC_METHOD_1, + .cpucp_sample_ms =3D 4, + .memory_cnt =3D ARRAY_SIZE(hamoa_memory_cfg), +}; + +#endif diff --git a/drivers/devfreq/scmi-qcom-memlat-devfreq.c b/drivers/devfreq/s= cmi-qcom-memlat-devfreq.c new file mode 100644 index 000000000000..c75bfb16bb2b --- /dev/null +++ b/drivers/devfreq/scmi-qcom-memlat-devfreq.c @@ -0,0 +1,582 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_MEMORY_TYPES 4 +#define MAX_MONITOR_CNT 5 +#define MAX_NAME_LEN 20 +#define MAX_MAP_ENTRIES 10 + +#include "scmi-qcom-memlat-cfg.h" + +/** + * enum scmi_memlat_protocol_cmd - parameter_ids supported by the "MEMLAT"= algo_str hosted + * by the Qualcomm Generic Vendor Protocol= on the SCMI controller. + * + * MEMLAT (Memory Latency) monitors the counters to detect memory latency = bound workloads + * and scales the frequency/levels of the memory buses accordingly. + * + * @MEMLAT_SET_MEM_GROUP: initializes the frequency/level scaling function= s for the memory bus. + * @MEMLAT_SET_MONITOR: configures the monitor to work on a specific memor= y bus. + * @MEMLAT_SET_COMMON_EV_MAP: set up common counters used to monitor the c= pu frequency. + * @MEMLAT_SET_GRP_EV_MAP: set up any specific counters used to monitor th= e memory bus. + * @MEMLAT_IPM_CEIL: set the IPM (Instruction Per Misses) ceiling per moni= tor. + * @MEMLAT_SAMPLE_MS: set the sampling period for all the monitors. + * @MEMLAT_MON_FREQ_MAP: setup the cpufreq to memfreq map. + * @MEMLAT_SET_MIN_FREQ: set the max frequency of the memory bus. + * @MEMLAT_SET_MAX_FREQ: set the min frequency of the memory bus. + * @MEMLAT_START_TIMER: start all the monitors with the requested sampling= period. + * @MEMLAT_STOP_TIMER: stop all the running monitors. + * @MEMLAT_SET_EFFECTIVE_FREQ_METHOD: set the method used to determine cpu= frequency. + */ +enum scmi_memlat_protocol_cmd { + MEMLAT_SET_MEM_GROUP =3D 16, + MEMLAT_SET_MONITOR, + MEMLAT_SET_COMMON_EV_MAP, + MEMLAT_SET_GRP_EV_MAP, + MEMLAT_IPM_CEIL =3D 23, + MEMLAT_BE_STALL_FLOOR =3D 25, + MEMLAT_SAMPLE_MS =3D 31, + MEMLAT_MON_FREQ_MAP, + MEMLAT_SET_MIN_FREQ, + MEMLAT_SET_MAX_FREQ, + MEMLAT_GET_CUR_FREQ, + MEMLAT_START_TIMER =3D 36, + MEMLAT_STOP_TIMER, + MEMLAT_SET_EFFECTIVE_FREQ_METHOD =3D 39, +}; + +struct cpucp_map_table { + u16 v1; + u16 v2; +}; + +struct map_param_msg { + u32 hw_type; + u32 mon_idx; + u32 nr_rows; + struct cpucp_map_table tbl[MAX_MAP_ENTRIES]; +} __packed; + +struct node_msg { + u32 cpumask; + u32 hw_type; + u32 mon_type; + u32 mon_idx; + char mon_name[MAX_NAME_LEN]; +}; + +struct scalar_param_msg { + u32 hw_type; + u32 mon_idx; + u32 val; +}; + +enum common_ev_idx { + INST_IDX, + CYC_IDX, + CONST_CYC_IDX, + FE_STALL_IDX, + BE_STALL_IDX, + NUM_COMMON_EVS +}; + +enum grp_ev_idx { + MISS_IDX, + WB_IDX, + ACC_IDX, + NUM_GRP_EVS +}; + +struct ev_map_msg { + u32 num_evs; + u32 hw_type; + u32 cid[NUM_COMMON_EVS]; +}; + +struct scmi_qcom_memlat_map { + unsigned int cpufreq_mhz; + unsigned int memfreq_khz; +}; + +struct scmi_qcom_monitor_info { + struct scmi_qcom_memlat_map *freq_map; + char name[MAX_NAME_LEN]; + u32 mon_idx; + u32 mon_type; + u32 ipm_ceil; + u32 be_stall_floor; + u32 mask; + u32 freq_map_len; +}; + +struct scmi_qcom_memory_info { + struct scmi_qcom_monitor_info *monitor[MAX_MONITOR_CNT]; + u32 hw_type; + int monitor_cnt; + u32 min_freq; + u32 max_freq; + struct devfreq_dev_profile profile; + struct devfreq *devfreq; + struct platform_device *pdev; + struct scmi_protocol_handle *ph; + const struct qcom_generic_ext_ops *ops; +}; + +struct scmi_qcom_memlat_info { + struct scmi_protocol_handle *ph; + const struct qcom_generic_ext_ops *ops; + struct scmi_qcom_memory_info *memory[MAX_MEMORY_TYPES]; + u32 cpucp_freq_method; + u32 cpucp_sample_ms; + int memory_cnt; +}; + +static int configure_cpucp_common_events(struct scmi_qcom_memlat_info *inf= o) +{ + const struct qcom_generic_ext_ops *ops =3D info->ops; + u8 ev_map[NUM_COMMON_EVS]; + struct ev_map_msg msg; + + memset(ev_map, 0xFF, NUM_COMMON_EVS); + + msg.num_evs =3D NUM_COMMON_EVS; + msg.cid[INST_IDX] =3D EV_INST_RETIRED; + msg.cid[CYC_IDX] =3D EV_CPU_CYCLES; + msg.cid[CONST_CYC_IDX] =3D EV_CNT_CYCLES; + msg.cid[FE_STALL_IDX] =3D INVALID_IDX; + msg.cid[BE_STALL_IDX] =3D EV_STALL_BACKEND_MEM; + + return ops->set_param(info->ph, &msg, sizeof(msg), MEMLAT_ALGO_STR, + MEMLAT_SET_COMMON_EV_MAP); +} + +static int configure_cpucp_grp(struct device *dev, struct scmi_qcom_memlat= _info *info, + int memory_index) +{ + struct scmi_qcom_memory_info *memory =3D info->memory[memory_index]; + const struct qcom_generic_ext_ops *ops =3D info->ops; + struct ev_map_msg ev_msg; + u8 ev_map[NUM_GRP_EVS]; + struct node_msg msg; + int ret; + + msg.cpumask =3D 0; + msg.hw_type =3D memory->hw_type; + msg.mon_type =3D 0; + msg.mon_idx =3D 0; + ret =3D ops->set_param(info->ph, &msg, sizeof(msg), MEMLAT_ALGO_STR, MEML= AT_SET_MEM_GROUP); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to configure mem type %d\n", + memory->hw_type); + + memset(ev_map, 0xFF, NUM_GRP_EVS); + ev_msg.num_evs =3D NUM_GRP_EVS; + ev_msg.hw_type =3D memory->hw_type; + ev_msg.cid[MISS_IDX] =3D EV_L2_D_RFILL; + ev_msg.cid[WB_IDX] =3D INVALID_IDX; + ev_msg.cid[ACC_IDX] =3D INVALID_IDX; + ret =3D ops->set_param(info->ph, &ev_msg, sizeof(ev_msg), MEMLAT_ALGO_STR, + MEMLAT_SET_GRP_EV_MAP); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to configure event map for mem ty= pe %d\n", + memory->hw_type); + + return ret; +} + +static int configure_cpucp_mon(struct device *dev, struct scmi_qcom_memlat= _info *info, + int memory_index, int monitor_index) +{ + const struct qcom_generic_ext_ops *ops =3D info->ops; + struct scmi_qcom_memory_info *memory =3D info->memory[memory_index]; + struct scmi_qcom_monitor_info *monitor =3D memory->monitor[monitor_index]; + struct scalar_param_msg scalar_msg; + struct map_param_msg map_msg; + struct node_msg msg; + int ret; + int i; + + msg.cpumask =3D monitor->mask; + msg.hw_type =3D memory->hw_type; + msg.mon_type =3D monitor->mon_type; + msg.mon_idx =3D monitor->mon_idx; + strscpy(msg.mon_name, monitor->name, sizeof(msg.mon_name)); + ret =3D ops->set_param(info->ph, &msg, sizeof(msg), MEMLAT_ALGO_STR, MEML= AT_SET_MONITOR); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to configure monitor %s\n", + monitor->name); + + scalar_msg.hw_type =3D memory->hw_type; + scalar_msg.mon_idx =3D monitor->mon_idx; + scalar_msg.val =3D monitor->ipm_ceil; + ret =3D ops->set_param(info->ph, &scalar_msg, sizeof(scalar_msg), MEMLAT_= ALGO_STR, + MEMLAT_IPM_CEIL); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to set ipm ceil for %s\n", + monitor->name); + + scalar_msg.hw_type =3D memory->hw_type; + scalar_msg.mon_idx =3D monitor->mon_idx; + scalar_msg.val =3D monitor->be_stall_floor; + ret =3D ops->set_param(info->ph, &scalar_msg, sizeof(scalar_msg), MEMLAT_= ALGO_STR, + MEMLAT_BE_STALL_FLOOR); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to set ipm ceil for %s\n", monito= r->name); + + map_msg.hw_type =3D memory->hw_type; + map_msg.mon_idx =3D monitor->mon_idx; + map_msg.nr_rows =3D monitor->freq_map_len; + for (i =3D 0; i < monitor->freq_map_len; i++) { + map_msg.tbl[i].v1 =3D monitor->freq_map[i].cpufreq_mhz; + + if (monitor->freq_map[i].memfreq_khz > 1) + map_msg.tbl[i].v2 =3D monitor->freq_map[i].memfreq_khz / 1000; + else + map_msg.tbl[i].v2 =3D monitor->freq_map[i].memfreq_khz; + } + ret =3D ops->set_param(info->ph, &map_msg, sizeof(map_msg), MEMLAT_ALGO_S= TR, + MEMLAT_MON_FREQ_MAP); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to configure freq_map for %s\n", + monitor->name); + + scalar_msg.hw_type =3D memory->hw_type; + scalar_msg.mon_idx =3D monitor->mon_idx; + scalar_msg.val =3D memory->min_freq; + ret =3D ops->set_param(info->ph, &scalar_msg, sizeof(scalar_msg), MEMLAT_= ALGO_STR, + MEMLAT_SET_MIN_FREQ); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to set min_freq for %s\n", + monitor->name); + + scalar_msg.hw_type =3D memory->hw_type; + scalar_msg.mon_idx =3D monitor->mon_idx; + scalar_msg.val =3D memory->max_freq; + ret =3D ops->set_param(info->ph, &scalar_msg, sizeof(scalar_msg), MEMLAT_= ALGO_STR, + MEMLAT_SET_MAX_FREQ); + if (ret < 0) + dev_err_probe(dev, ret, "failed to set max_freq for %s\n", monitor->name= ); + + return ret; +} + +static int scmi_qcom_devfreq_get_cur_freq(struct device *dev, unsigned lon= g *freq) +{ + struct scmi_qcom_memory_info *memory =3D dev_get_drvdata(dev); + const struct qcom_generic_ext_ops *ops; + struct scalar_param_msg scalar_msg; + int ret; + + ops =3D memory->ops; + + scalar_msg.hw_type =3D memory->hw_type; + scalar_msg.mon_idx =3D 0; + u32 cur_freq; + + ret =3D ops->get_param(memory->ph, &scalar_msg, sizeof(scalar_msg), MEMLA= T_ALGO_STR, + MEMLAT_GET_CUR_FREQ, sizeof(cur_freq)); + if (ret < 0) { + pr_err("failed to get mon current frequency\n"); + return ret; + } + + memcpy(&cur_freq, (void *)&scalar_msg, sizeof(cur_freq)); + + if (memory->hw_type =3D=3D 2) + *freq =3D le32_to_cpu(cur_freq) ? 100 : 1; + else + *freq =3D le32_to_cpu(cur_freq) * 1000UL; + + return 0; +} + +static int scmi_qcom_memlat_configure_events(struct scmi_device *sdev, + struct scmi_qcom_memlat_info *info) +{ + const struct qcom_generic_ext_ops *ops =3D info->ops; + struct scmi_protocol_handle *ph =3D info->ph; + int i, j, ret; + + /* Configure common events ids */ + ret =3D configure_cpucp_common_events(info); + if (ret < 0) + return dev_err_probe(&sdev->dev, ret, "failed to configure common events= \n"); + + for (i =3D 0; i < info->memory_cnt; i++) { + /* Configure per group parameters */ + ret =3D configure_cpucp_grp(&sdev->dev, info, i); + if (ret < 0) + return ret; + + for (j =3D 0; j < info->memory[i]->monitor_cnt; j++) { + /* Configure per monitor parameters */ + ret =3D configure_cpucp_mon(&sdev->dev, info, i, j); + if (ret < 0) + return ret; + } + } + + /* Set loop sampling time */ + ret =3D ops->set_param(ph, &info->cpucp_sample_ms, sizeof(info->cpucp_sam= ple_ms), + MEMLAT_ALGO_STR, MEMLAT_SAMPLE_MS); + if (ret < 0) + return dev_err_probe(&sdev->dev, ret, "failed to set sample_ms\n"); + + /* Set the effective cpu frequency calculation method */ + ret =3D ops->set_param(ph, &info->cpucp_freq_method, sizeof(info->cpucp_f= req_method), + MEMLAT_ALGO_STR, MEMLAT_SET_EFFECTIVE_FREQ_METHOD); + if (ret < 0) + return dev_err_probe(&sdev->dev, ret, + "failed to set effective frequency calc method\n"); + + /* Start sampling and voting timer */ + ret =3D ops->start_activity(ph, NULL, 0, MEMLAT_ALGO_STR, MEMLAT_START_TI= MER); + if (ret < 0) + dev_err_probe(&sdev->dev, ret, "failed to start memory group timer\n"); + + for (i =3D 0; i < info->memory_cnt; i++) { + struct scmi_qcom_memory_info *memory =3D info->memory[i]; + struct platform_device *pdev =3D memory->pdev; + struct devfreq_dev_profile *profile =3D &memory->profile; + + profile->polling_ms =3D info->cpucp_sample_ms; + profile->get_cur_freq =3D scmi_qcom_devfreq_get_cur_freq; + profile->initial_freq =3D memory->min_freq > 1 ? + (memory->min_freq * 1000UL) : memory->min_freq; + + memory->ops =3D info->ops; + memory->ph =3D info->ph; + + platform_set_drvdata(pdev, memory); + + memory->devfreq =3D devm_devfreq_add_device(&pdev->dev, profile, + DEVFREQ_GOV_REMOTE, NULL); + if (IS_ERR(memory->devfreq)) { + dev_err(&sdev->dev, "failed to add devfreq device\n"); + /* Start sampling and voting timer */ + ret =3D ops->start_activity(ph, NULL, 0, MEMLAT_ALGO_STR, MEMLAT_STOP_T= IMER); + if (ret < 0) + dev_err_probe(&sdev->dev, ret, + "failed to stop memory group timer\n"); + return -EINVAL; + } + } + + return 0; +} + +static struct scmi_qcom_memlat_map *scmi_qcom_parse_memlat_map(struct devi= ce *dev, + const struct scmi_qcom_monitor_cfg *mon_cfg) +{ + struct scmi_qcom_memlat_map *map_table; + const struct scmi_qcom_map_table *table; + + map_table =3D devm_kzalloc(dev, MAX_MAP_ENTRIES * sizeof(struct scmi_qcom= _memlat_map), + GFP_KERNEL); + if (!map_table) + return ERR_PTR(-ENOMEM); + + for (int i =3D 0; i < mon_cfg->table_len; i++) { + table =3D &mon_cfg->table[i]; + + map_table[i].cpufreq_mhz =3D table->cpu_freq; + map_table[i].memfreq_khz =3D table->mem_freq; + } + + return map_table; +} + +static const struct of_device_id scmi_qcom_memlat_configs[] __maybe_unused= =3D { + { .compatible =3D "qcom,glymur", .data =3D &glymur_memlat_data}, + { .compatible =3D "qcom,mahua", .data =3D &glymur_memlat_data}, + { .compatible =3D "qcom,x1e80100", .data =3D &hamoa_memlat_data}, + { .compatible =3D "qcom,x1p42100", .data =3D &hamoa_memlat_data}, + { } +}; + +static int scmi_qcom_memlat_parse_cfg(struct scmi_device *sdev, struct scm= i_qcom_memlat_info *info) +{ + const struct scmi_qcom_memlat_cfg_data *cfg_data; + struct scmi_qcom_monitor_info *monitor; + struct scmi_qcom_memory_info *memory; + int ret, i, j; + + cfg_data =3D of_machine_get_match_data(scmi_qcom_memlat_configs); + if (!cfg_data) { + return dev_err_probe(&sdev->dev, PTR_ERR(cfg_data), + "Couldn't find config data for this platform\n"); + } + + for (i =3D 0; i < cfg_data->memory_cnt; i++) { + const struct scmi_qcom_memory_cfg *memory_cfg =3D &cfg_data->memory_cfg[= i]; + struct platform_device_info pdevinfo =3D { 0 }; + + pdevinfo.parent =3D &sdev->dev; + pdevinfo.name =3D memory_cfg->name; + pdevinfo.id =3D PLATFORM_DEVID_NONE; + + memory =3D devm_kzalloc(&sdev->dev, sizeof(*memory), GFP_KERNEL); + if (!memory) { + ret =3D -ENOMEM; + goto out; + } + + memory->ops =3D info->ops; + memory->ph =3D info->ph; + memory->hw_type =3D memory_cfg->memory_type; + memory->monitor_cnt =3D memory_cfg->monitor_cnt; + memory->min_freq =3D memory_cfg->memory_range.min_freq; + memory->max_freq =3D memory_cfg->memory_range.max_freq; + + memory->pdev =3D platform_device_register_full(&pdevinfo); + if (IS_ERR(memory->pdev)) { + dev_err_probe(&sdev->dev, PTR_ERR(memory->pdev), + "failed to register platform device\n"); + ret =3D PTR_ERR(memory->pdev); + goto out; + } + + info->memory[i] =3D memory; + + for (j =3D 0; j < memory_cfg->num_opps; j++) { + const struct scmi_qcom_opp_data *table =3D &memory_cfg->mem_table[j]; + struct platform_device *pdev =3D memory->pdev; + struct dev_pm_opp_data data; + + data.freq =3D table->freq; + data.level =3D table->level; + + ret =3D dev_pm_opp_add_dynamic(&pdev->dev, &data); + if (ret) { + dev_err_probe(&sdev->dev, ret, "failed to add OPP\n"); + dev_pm_opp_remove_all_dynamic(&pdev->dev); + goto out; + } + } + + for (j =3D 0; j < memory_cfg->monitor_cnt; j++) { + const struct scmi_qcom_monitor_cfg *monitor_cfg =3D &memory_cfg->monito= r_cfg[j]; + + monitor =3D devm_kzalloc(&sdev->dev, sizeof(*monitor), GFP_KERNEL); + if (!monitor) + return -ENOMEM; + + monitor->ipm_ceil =3D monitor_cfg->ipm_ceil; + monitor->mon_type =3D monitor->ipm_ceil ? 0 : 1; + monitor->be_stall_floor =3D monitor_cfg->be_stall_floor; + monitor->mask =3D monitor_cfg->cpu_mask; + monitor->freq_map_len =3D monitor_cfg->table_len; + + monitor->freq_map =3D scmi_qcom_parse_memlat_map(&sdev->dev, monitor_cf= g); + if (IS_ERR(monitor->freq_map)) { + dev_err_probe(&sdev->dev, PTR_ERR(monitor->freq_map), + "failed to populate cpufreq-memfreq map\n"); + ret =3D -EINVAL; + goto out; + } + + strscpy(monitor->name, monitor_cfg->name, sizeof(monitor->name)); + monitor->mon_idx =3D j; + memory->monitor[j] =3D monitor; + } + } + + info->cpucp_freq_method =3D cfg_data->cpucp_freq_method; + info->cpucp_sample_ms =3D cfg_data->cpucp_sample_ms; + info->memory_cnt =3D cfg_data->memory_cnt; + + return 0; + +out: + for (i =3D 0; i < cfg_data->memory_cnt; i++) { + if (IS_ERR_OR_NULL(info->memory[i])) + break; + + memory =3D info->memory[i]; + if (!IS_ERR(memory->pdev)) + platform_device_unregister(memory->pdev); + } + + return ret; +} + +static int scmi_qcom_devfreq_memlat_probe(struct scmi_device *sdev) +{ + const struct scmi_handle *handle =3D sdev->handle; + const struct qcom_generic_ext_ops *ops; + struct scmi_qcom_memlat_info *info; + struct scmi_protocol_handle *ph; + int ret; + + if (!handle) + return -ENODEV; + + info =3D devm_kzalloc(&sdev->dev, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + ops =3D handle->devm_protocol_get(sdev, SCMI_PROTOCOL_QCOM_GENERIC, &ph); + if (IS_ERR(ops)) + return PTR_ERR(ops); + + info->ops =3D ops; + info->ph =3D ph; + + ret =3D scmi_qcom_memlat_parse_cfg(sdev, info); + if (ret) + return ret; + + ret =3D scmi_qcom_memlat_configure_events(sdev, info); + if (ret) + return ret; + + dev_set_drvdata(&sdev->dev, info); + + return ret; +} + +static void scmi_qcom_devfreq_memlat_remove(struct scmi_device *sdev) +{ + struct scmi_qcom_memlat_info *info =3D dev_get_drvdata(&sdev->dev); + + for (int i =3D 0; i < info->memory_cnt; i++) { + struct scmi_qcom_memory_info *memory =3D info->memory[i]; + + if (!IS_ERR(memory->pdev)) + platform_device_unregister(memory->pdev); + } +} + +static const struct scmi_device_id scmi_id_table[] =3D { + { SCMI_PROTOCOL_QCOM_GENERIC, "qcom-generic-ext" }, + { }, +}; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83965945101sm7346557b3a.13.2026.05.06.23.23.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2026 23:23:36 -0700 (PDT) From: Sibi Sankar To: cristian.marussi@arm.com, sudeep.holla@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, myungjoo.ham@samsung.com, konradybcio@kernel.org, andersson@kernel.org Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, arm-scmi@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, dmitry.baryshkov@oss.qualcomm.com, jonathanh@nvidia.com, thierry.reding@kernel.org, digetx@gmail.com, conor+dt@kernel.org, krzk+dt@kernel.org, robh@kernel.org Subject: [RFC V6 7/8] arm64: dts: qcom: glymur: Enable LLCC/DDR/DDR_QOS dvfs Date: Thu, 7 May 2026 11:52:36 +0530 Message-Id: <20260507062237.78051-8-sibi.sankar@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260507062237.78051-1-sibi.sankar@oss.qualcomm.com> References: <20260507062237.78051-1-sibi.sankar@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: U8e_D__4m1ckv380bfdDGymhB0ExKNXG X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA3MDA2MCBTYWx0ZWRfX7PmPI0mG+OLW pPffDHewP8EJVMSRQ8MjD95einzyFgMb61QLxXclCO73K/Ru5SxPjunq1/ZSa9J6z4WtnFqDL4P QbTBrWZa7/cogRWrgRk9uwdCpSjF3eFJo7JKiK3anCpTnLFFN/4+vv0W/RuKxpDBsQKnyIJNfSe aSD1R8aUbZW5vNqpwk4p89Uy4E42JFfrSxnp/nIE6ubWSaqPw4Sp8GKl5EhHP0qxmA1BRLt4nU1 5DbQ4Fih3mRzaC5jpiQR15rU5Jn02Zig5MToVBf+cNN9Gy8c/dT7OIvXFgrgMhh/qEdRMQ5D/+o 8xqZvQ3j50vX0IFVil8CinNpXqDrlUmr5GTV6Zb+X5VpoSnjgldT2LS/AFKzZPHcPeZKddxcaQr 0TCoB1zC6LG7RYBxbuKURvIDfZzmziyFYc8+iy1aOUP7D1ogBT5wDXLaF5m7eWFCEdKBzAglcef GhWnEckDhpxP3Z66U5A== X-Proofpoint-GUID: U8e_D__4m1ckv380bfdDGymhB0ExKNXG X-Authority-Analysis: v=2.4 cv=X8Zi7mTe c=1 sm=1 tr=0 ts=69fc2fea cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=GY6npCAvCrdgt1im_sIA:9 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-06_02,2026-05-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 spamscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605070060 Content-Type: text/plain; charset="utf-8" On Qualcomm Glymur SoCs, the memlat governor and the mechanism to control the LLCC and DDR/DDR_QOS is hosted on the CPU Control Processor (CPUCP). Enable the nodes required to get QCOM SCMI Generic Extension protocol to probe on Glymur and Mahua SoCs. Signed-off-by: Sibi Sankar --- arch/arm64/boot/dts/qcom/glymur.dtsi | 42 ++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qco= m/glymur.dtsi index f23cf81ddb77..6409350ad9d7 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -349,6 +349,21 @@ scm: scm { &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; }; =20 + cpucp_scmi { + compatible =3D "arm,scmi"; + mboxes =3D <&cpucp_mbox 0>, <&cpucp_mbox 2>; + + mbox-names =3D "tx", "rx"; + shmem =3D <&cpucp_scp_lpri0>, <&cpucp_scp_lpri1>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_vendor: protocol@80 { + reg =3D <0x80>; + }; + }; + scmi { compatible =3D "arm,scmi"; mboxes =3D <&pdp0_mbox 0>, <&pdp0_mbox 1>; @@ -5675,6 +5690,13 @@ pdp0_mbox: mailbox@17610000 { #mbox-cells =3D <1>; }; =20 + cpucp_mbox: mailbox@17620000 { + compatible =3D "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; + reg =3D <0 0x17620000 0 0x8000>, <0 0x18830000 0 0x8000>; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83965945101sm7346557b3a.13.2026.05.06.23.23.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2026 23:23:42 -0700 (PDT) From: Sibi Sankar To: cristian.marussi@arm.com, sudeep.holla@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, myungjoo.ham@samsung.com, konradybcio@kernel.org, andersson@kernel.org Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, arm-scmi@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, dmitry.baryshkov@oss.qualcomm.com, jonathanh@nvidia.com, thierry.reding@kernel.org, digetx@gmail.com, conor+dt@kernel.org, krzk+dt@kernel.org, robh@kernel.org Subject: [RFC V6 8/8] arm64: dts: qcom: hamoa: Enable LLCC/DDR/DDR_QOS dvfs Date: Thu, 7 May 2026 11:52:37 +0530 Message-Id: <20260507062237.78051-9-sibi.sankar@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260507062237.78051-1-sibi.sankar@oss.qualcomm.com> References: <20260507062237.78051-1-sibi.sankar@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA3MDA2MCBTYWx0ZWRfX54SJ666u5fcA eM/dFwLJjXmcOF90uAHbE1ly4uRyvxgGpo7kXtpybca4jIPpk1X2rE+0Vrle4maAi6iKd6qy+Tt kAspnW5MURbCSRLJe5BC9Jk6SmUR2QUJuLKTwN/UtgGahYQ6mziEzum/rhSZVoA2GxJHEnghjyj IV/dXEABu7l7zC9OaEyNSfjHDhmk9WPaO7XkXLIoaFNuQMcRXXxLrXGTyJSMbXD8mi+Xwqg7Tyg KmHLxhsR66+PRzwYxPZcNOlrdQIw3AWHBl/2wYoQD0RzuHPN34m87+mkTzMmVe119ocGP7oVl+f vQMA7vqYq8Lg8Kmea4P5xvNkFwNpwB2yGzOKFg3sgUR3IUWma/yELzzOy3p+ut2Z5fWSm9AKy7H 0s3hEz91eGXjfsTUO6vAJwIOhFKJJZIay/GglZhx7GJ50beqUSpuTYd8B1ZixMGI05uGsVqz+VO fvVHPa+Vrrh+mxs8lxA== X-Proofpoint-ORIG-GUID: vtAeCYUkbkHbNzRGKEASWfaRYHElJX1X X-Authority-Analysis: v=2.4 cv=SuagLvO0 c=1 sm=1 tr=0 ts=69fc2ff0 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=gKi3Cb3mJvt5RuhTHbAA:9 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-GUID: vtAeCYUkbkHbNzRGKEASWfaRYHElJX1X X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-06_02,2026-05-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 adultscore=0 phishscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605070060 Content-Type: text/plain; charset="utf-8" On Qualcomm Hamoa SoCs, the memlat governor and the mechanism to control the LLCC and DDR/DDR_QOS is hosted on the CPU Control Processor (CPUCP). Enable the nodes required to get QCOM SCMI Generic Extension protocol to probe on Hamoa and Purwa SoCs. Signed-off-by: Sibi Sankar --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom= /hamoa.dtsi index 051dee076416..a2d5c9db984d 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -338,6 +338,10 @@ scmi_dvfs: protocol@13 { reg =3D <0x13>; #power-domain-cells =3D <1>; }; + + scmi_vendor: protocol@80 { + reg =3D <0x80>; + }; }; }; =20 --=20 2.34.1