From nobody Sat Jun 13 12:06:18 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FC853246EB for ; Thu, 7 May 2026 16:46:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172420; cv=none; b=d0bvLotRgf7w8hgDYH2HSnzpOsuAua+MS2a4LGRdOr0e9dAduVa+Ad+veb+U5YvIlHZhES47GjRlZ5ki/pDccTjfDiuYQBz25YG301RPrJtq4lKb/XbCrVFMJ6TgmG3VTiKW6b3IXmlKYOkKZlqz/Mi+3u+3vG8oM49CCWzIsxE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172420; c=relaxed/simple; bh=wTTB6e/8ePxI86D4Nfy1cUgRHfcwns176A2TR63+Vjg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gIJ+hGBOPy857JPJcC+oUmXhr7/E4r+/FOktUfHhbir59CkhiAN/sjprHDnSdrodmTwEEfqioV5nP32wk8b75saFBYH8P6bU+lhpZvoDNnUQiRfff0PEj/yeTb23cO7Ys1Q1ySnHlCQQEAnuVtDUNpgWFjqmQ+HO5wkYUbub/ic= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=aDS/QXCu; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="aDS/QXCu" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 3275B4E42C1B; Thu, 7 May 2026 16:46:58 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 07205605CF; Thu, 7 May 2026 16:46:58 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id F2F26108194E2; Thu, 7 May 2026 18:46:55 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1778172417; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=leC2dd2KClzTPcQ+8AI037xoM94Wj2JcMmNh8kB3Pi8=; b=aDS/QXCu/GSwSaA2Dqjk5EkDRxAYQd488pFZleTrwWX6rv3zBwQOox1q5Om1x2wlWW2T1/ 0sAFqPY/PYVww+9JXATjxui8iniivuxJSyA0VxgNpbiEgEQ6VUnA1Q4Yje0dcMjgLtxtF7 PzsAzqHTSsZT9oJmb2cfsNuv6ZVy6+FKZif0MHuV3joLxohIq/i06LfAqHQ+VCEKz1HBvK uxtysc5i4E68haDBXHJCPjrr9ad8grX/4Va3kVpDgdYktghJbZgPziTCIfer9WEtm5SXr3 zLHM2Gl0AY3p37Rl6K6FKoblZn3ixgj8qlwAXHHLtaAgjrOYLkejQU5NfVZ/eg== From: Miquel Raynal Date: Thu, 07 May 2026 18:46:42 +0200 Subject: [PATCH v5 01/28] mtd: spi-nor: Drop duplicate Kconfig dependency Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-1-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 I do not think the MTD dependency is needed twice. This is likely a duplicate coming from a former rebase when the spi-nor core got cleaned up a while ago. Remove the extra line. Fixes: b35b9a10362d ("mtd: spi-nor: Move m25p80 code in spi-nor.c") Signed-off-by: Miquel Raynal Reviewed-by: Michael Walle --- drivers/mtd/spi-nor/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig index 24cd25de2b8b..fd05a24d64a9 100644 --- a/drivers/mtd/spi-nor/Kconfig +++ b/drivers/mtd/spi-nor/Kconfig @@ -1,7 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only menuconfig MTD_SPI_NOR tristate "SPI NOR device support" - depends on MTD depends on MTD && SPI_MASTER select SPI_MEM help --=20 2.53.0 From nobody Sat Jun 13 12:06:18 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 310F93E7150 for ; Thu, 7 May 2026 16:47:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172422; cv=none; b=cOaFhPmb3PEEjAwpVFcbD0BqmHpWgQa13HyDA/qB1qyHnnY9ok058y9UTkdbPsJvPo17oYr80kLb06qmBoWTiblodt6Hw5iNjOT7PzqNH4XpyU3kjdcdoPDZyeJexaJ3JnqMppDMgP76BF9d2ZmQMuxAX4ogtnHC++EIvdUsxWw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172422; c=relaxed/simple; bh=FUqMuwPe/VeYULAiVeahm1trZi1oXESB2z3mCxIRzWc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dV090FhIv0eFzvp+5IaUP6dV6PCLhGHh9sySUgVsM/E7+w3d3+MWhZpyKs8L7pC52MQIjDVaXeJlyU9DYWyUCRtTQVWNYkvaIGjxO3rbxiVTzE+7mVRdHanoSkZNJiBiAILgyAzpfpGXtZoaq+xuESuhIPDBEbrWH91MUfe4zNU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=LyRU2v1w; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="LyRU2v1w" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id DDF6D4E42C33; Thu, 7 May 2026 16:46:59 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id AB3A4605CF; Thu, 7 May 2026 16:46:59 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 97513108194E4; Thu, 7 May 2026 18:46:57 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1778172418; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=p/VrR2zWyEuP7FnbthxkSprPO27GGH7TRyCzje2SKqM=; b=LyRU2v1weD668CqE79SrASuJpy0VoVm3w+qVm3NiuaeV4+qF+8/nYGO1cRFgKKXtiuny6G onEYe6OPKMewhx3Mh/6l3sKWcmAWltnkB7JHG5rJvBzvtmFU/KzWCo/tTu21kqDuVuYn8P Jv1Xo1xxyF0XBWRpiatxs2SmRafrg4rDLpeAdmYXQ/psdjnR/MholvQx7NkDMv06sscWPB p5Vx16aqfQ2IJWT49y3APTBHaEg+jykoQsi9SZCkxK+MhQzrHtmAskCwm4sJoRHVY11tbo KrfI7vWRap2sKT+B32RsvCERS/SeqGLcP27yNzcwxjqgW/7CgmiqzMjczWylsg== From: Miquel Raynal Date: Thu, 07 May 2026 18:46:43 +0200 Subject: [PATCH v5 02/28] mtd: spi-nor: debugfs: Fix the flags list Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-2-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 As mentioned above the spi_nor_option_flags enumeration in core.h, this list should be kept in sync with the one in the core. Add the missing flag. Fixes: 6a42bc97ccda ("mtd: spi-nor: core: Allow specifying the byte order i= n Octal DTR mode") Reviewed-by: Michael Walle Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/debugfs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c index fa6956144d2e..d700e0b27182 100644 --- a/drivers/mtd/spi-nor/debugfs.c +++ b/drivers/mtd/spi-nor/debugfs.c @@ -28,6 +28,7 @@ static const char *const snor_f_names[] =3D { SNOR_F_NAME(RWW), SNOR_F_NAME(ECC), SNOR_F_NAME(NO_WP), + SNOR_F_NAME(SWAP16), }; #undef SNOR_F_NAME =20 --=20 2.53.0 From nobody Sat Jun 13 12:06:18 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA7144508F7 for ; Thu, 7 May 2026 16:47:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172424; cv=none; b=toc6qYxCKAhojF7rhWW0pr+7PqHEWNwfqj/LSDlyRyQJy/3qcllX/eSMvazIOetDLavhmisl1DRESObsoB4gvC8v+DqoMrWdCCpP1eyUw+D+NJT5jVw/McXA+O6CcHpqrA0l3sXc9W0NEWMMzNFruWoL2IzuSNZYDMf/p9gPT1E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172424; c=relaxed/simple; bh=TFb7Rh2PuE/3ceANqlCf3EuJxNoo8eZQMz7YT/aYL5w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CKjy8Ry/n5oUrI4h6e6qWgyMzOEx1mKc5kFQ5m+eVqkvuG+PUkJ7hgld0JcMpPWNYaWVZd5XsgPAHUVumPVTyIFI3k6Vwc1hPIjIxUXfX4ULL4bDfj3BFygyYnliWDUW9fvLviigg7nKx3k+rbuMhuDfSLOWhKD2dBAs4FFU2Ug= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=dcXqUxO2; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="dcXqUxO2" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 23D17C5DC65; Thu, 7 May 2026 16:47:49 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 59213605CF; Thu, 7 May 2026 16:47:01 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 4514F108194A8; Thu, 7 May 2026 18:46:59 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1778172420; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=r/I8HpmdlgiZEDA4JzntxIQZil5h8OVsqG1FV3N20+g=; b=dcXqUxO2tgoi2qQeatUweuEc3whB+18tPx9IUiJ/OnXR7WUd12k/11SZ2tHzoW6Waq9lqo qn/+d6PfFZnHekXaAqy2nl2SC+9Snr6iOHT0EV1Hoho+L1i0OndrLaf136lD6y22VB+AGM N9+m2za0qwGZSgAFAx3Et6nYfMLZ1dm9g0cDFqOjLYqVOciCCg8WIt1wWBucVyCQTfA3Ct ymk7iysyd6aHVle/0N+5Z7zRdUsMW0iCF+dnqzWr5bs/CD5qJQnJyvhhi9bJbfNMXf00L/ VNpOvJKPHtIkiCV46EeBds4b/iSHkJ42kO8uZX++PfGbOcwWaUY9JXz55aHQaA== From: Miquel Raynal Date: Thu, 07 May 2026 18:46:44 +0200 Subject: [PATCH v5 03/28] mtd: spi-nor: Make sure the QE bit is kept enabled if useful Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-3-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Not all chips implement the 4BAIT table which typically indicates the program capability, while many of them do implement the relevant SFDP parts indicating the read capabilities. In such a situation, programs can happen in single mode (1-1-1) and reads in quad mode (1-1-4 or 1-4-4). For the reads to work in such condition, the QE bit must be set. In case we later use the spi_nor_write_16bit_sr_and_check() helper with a chip with such configuration, the QE bit would get incorrectly cleared. Make sure this doesn't happen by keeping the QE bit under a simpler condition: - the quad enable hook is there (no change) - and at least one of the two protocols is based on quad I/O cycles Signed-off-by: Miquel Raynal Reviewed-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 5dd0b3cb5250..394c27de02d6 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -869,8 +869,8 @@ static int spi_nor_write_16bit_sr_and_check(struct spi_= nor *nor, u8 sr1) ret =3D spi_nor_read_cr(nor, &sr_cr[1]); if (ret) return ret; - } else if (spi_nor_get_protocol_width(nor->read_proto) =3D=3D 4 && - spi_nor_get_protocol_width(nor->write_proto) =3D=3D 4 && + } else if ((spi_nor_get_protocol_width(nor->read_proto) =3D=3D 4 || + spi_nor_get_protocol_width(nor->write_proto) =3D=3D 4) && nor->params->quad_enable) { /* * If the Status Register 2 Read command (35h) is not --=20 2.53.0 From nobody Sat Jun 13 12:06:18 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D0B74534B3 for ; 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bh=NSOpkSMxKgBxZoYTHJtqcGhzPwXJVGPGp0SnQOK5CB4=; b=0SIAJHPbcJ1GYls1XM8xG65+FxjW9VqkCQ5LuF1J4j6gEPR9F64t6/ZHNyXCr09XzftiV7 8+9oItBJakoWSP2Jxhb/f6nN/d0Fs4hJlxIay3StGgHJMIUaAQu25z4ZYFzn2eKLaZBE6F 09dMwyrmLJMiXJ7fhG7MlJjWTQEMJL3UckiZreCwgOfOW7E8//ywp+OoNayj8odZxqBhle CCPFLyE4EdaLCxBvTy75qkkmmRFy7Hebsw30Gf6n0OfwOPIpwq0YbZWkqwEB7FHewUZ6mK 8ckZxrr8VV4a/nZxZjjsCrWnvukBcn05wUz63+a4urc14jL9hjKoEMwN/pMsQw== From: Miquel Raynal Date: Thu, 07 May 2026 18:46:45 +0200 Subject: [PATCH v5 04/28] mtd: spi-nor: swp: Improve locking user experience Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-4-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal , stable@kernel.org X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 In the case of the first block being locked (or the few first blocks), if the user want to fully unlock the device it has two possibilities: - either it asks to unlock the entire device, and this works; - or it asks to unlock just the block(s) that are currently locked, which fails. It fails because the conditions "can_be_top" and "can_be_bottom" are true. Indeed, in this case, we unlock everything, so the TB bit does not matter. However in the current implementation, use_top would be true (as this is the favourite option) and lock_len, which in practice should be reduced down to 0, is set to "nor->params->size - (ofs + len)" which is a positive number. This is wrong. An easy way is to simply add an extra condition. In the unlock() path, if we can achieve the same result from both sides, it means we unlock everything and lock_len must simply be 0. A comment is added to clarify that logic. Fixes: 3dd8012a8eeb ("mtd: spi-nor: add TB (Top/Bottom) protect support") Cc: stable@kernel.org Signed-off-by: Miquel Raynal Reviewed-by: Michael Walle --- drivers/mtd/spi-nor/swp.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index e67a81dbb6bf..d5f4bf555cfc 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -282,8 +282,15 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff= _t ofs, u64 len) /* Prefer top, if both are valid */ use_top =3D can_be_top; =20 - /* lock_len: length of region that should remain locked */ - if (use_top) + /* + * lock_len: length of region that should remain locked. + * + * When can_be_top and can_be_bottom booleans are true, both adjacent + * regions are unlocked, thus the entire flash can be unlocked. + */ + if (can_be_top && can_be_bottom) + lock_len =3D 0; + else if (use_top) lock_len =3D nor->params->size - (ofs + len); else lock_len =3D ofs; --=20 2.53.0 From nobody Sat Jun 13 12:06:18 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D56244611E1; Thu, 7 May 2026 16:47:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172427; cv=none; b=VZrNwTPUckD6nmBr0MNzyOMuAC+bglTc1Xo+YPNdU8JXqgu6Vi4+Bexh8/D0CzA/3S1IhGSltPsIOJk6sOkxt0wa9I+7Ws+C3kmlCM6zJu6urOmEnsipzQT04l3hgJOuYiJUYF2mXm1ecQT5Ee67utRwjAHjQX3yHoR3PemF4Pg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172427; c=relaxed/simple; bh=yZMj00763w8r8wUBQCaUh5FU4u4u6hQXAxOsrUapcsc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rX6iXSw2CyKAw4tekNVOME6u7uVGYmPQc5cAxGonCxvatoJAYJXUwkkaYBmU5JO6BA0z9AJ6H8rmmskzHiok9BcEusfmMWGG/QArdxGHr+aQqV0A0mDn6XAnSw7FCwsAkrzJYKd6dIVArj7UocnNgAmEczieSxsuSHjuoWxXW1Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=z7JxekzV; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="z7JxekzV" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 93335C5DC60; Thu, 7 May 2026 16:47:52 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id C9736605CF; Thu, 7 May 2026 16:47:04 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id B2C13108194E4; Thu, 7 May 2026 18:47:02 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1778172424; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=qqYr/KNjLLcJYcEfDklSWHxXQ8BxYrzb3yZHrjztITk=; b=z7JxekzVYYgvMD6dwC4xpwKWui7d/me0mDpO95yr/WyHq4RKZJWsDdQiVlyLV7UIA349K2 G/ICWObZvpMyYv6BvNdwPq+/qExbD0xsmv/BMt95jqr97YCrPDwi19Tm3zbsn1MFzUY2Wo WcNeMfdGHLiKakZCGfa+RwiGaL2BaqSA68V+K/Ui6TuzMxp0rIyjC0xjtAW0i6oFefE0Y+ n8Ocz3RaljqQlTdhoC7TRC6JywVPpiMnjVwtUn8uhMWMGd8J1HIUDbdMBo0inRHaQwLI6z qcUGL9s3od7owSMExnEi24ZRmXPeehcd7RXGxzQH2TiFHGl27OlORZ63NTPCjg== From: Miquel Raynal Date: Thu, 07 May 2026 18:46:46 +0200 Subject: [PATCH v5 05/28] mtd: spi-nor: Improve opcodes documentation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-5-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 There are two status registers, named 1 and 2. The current wording is misleading as "1" may refer to the status register ID as well as the number of bytes required (which, in this case can be 1 or 2). Clarify the comments by aligning them on the same pattern: "{read,write} status {1,2} register" Reviewed-by: Michael Walle Signed-off-by: Miquel Raynal --- include/linux/mtd/spi-nor.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index cdcfe0fd2e7d..90a0cf583512 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -21,8 +21,8 @@ /* Flash opcodes. */ #define SPINOR_OP_WRDI 0x04 /* Write disable */ #define SPINOR_OP_WREN 0x06 /* Write enable */ -#define SPINOR_OP_RDSR 0x05 /* Read status register */ -#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ +#define SPINOR_OP_RDSR 0x05 /* Read status register 1 */ +#define SPINOR_OP_WRSR 0x01 /* Write status register 1 */ #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */ #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */ #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */ --=20 2.53.0 From nobody Sat Jun 13 12:06:18 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07487426690; Thu, 7 May 2026 16:47:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172429; cv=none; b=TUkLejFn9NfWTed7NQEYH3k38Z3Cc8jR5o5IQNFKN9yCoDmPBgeriri8kEMC7qZ5Qj7PLx8srsyPDWBiSE3IOBVzwfouegtGKeggPHagD+VsE8W8DqMVNjzC6dReZtaXoZJ9QM52cKVBU73aBIMhDK52jUKOs18RuMF90avuGr8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172429; c=relaxed/simple; bh=9MefzCIV+tnB/FnzOtLFwFa7sENOrT3OAIQ9rTsmCUI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZPPKwJ91sXPP2sFurk3ZZEwYzgLnHZAI46sLrlQgM28mWp8/TH8Yx/In/PLyy5vfb7luObX4lKV4zuCUMZnDiEZvzG8FSf7bGIyaPEubppVSTDDf8Tix+5XpaM2WU3vQgeNgd1fJOqrPwmS660veeNewxYuoFi2WU2tAvbqlUjU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=ZvwtV/gA; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="ZvwtV/gA" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id BD7344E42C37; Thu, 7 May 2026 16:47:06 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 8BDAE605CF; Thu, 7 May 2026 16:47:06 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 58951108194A8; Thu, 7 May 2026 18:47:04 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1778172425; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=UWpfRE4WtdnRITw0PIgGXyjweTZSRtj+l56eZxMc4k0=; b=ZvwtV/gAyKOO9LkZR9GeLul4tw0EAqwgNH94yUnPwc1J+E9xChzLZIT0DkWGP6jvU6GUVB 0RbfBlXcCRoqFSCK2RPahEqcZAURRm7BEu5wCxA+onY9/AVDUwb8ZICZXGepCg3vZyTYfz XDGtbeL1Kzu5JJGz0r0lK0Z7O1qqa6pTb82JHgUny4sYKYxhZwzsRLvzb4Lz6SIGMVaxTS TnunTO1genAcfHbJvN9f+4NfJzU5n6dxe6iFhS1At0JdIkvxVI8vctAoDSXPbEPVZvXSgm 3Fhro9sFLUr5GlJvN1YnJ8T1pgvNse+dngO1wY+Gks+NcAlPQ0+BQKAWsBDUSQ== From: Miquel Raynal Date: Thu, 07 May 2026 18:46:47 +0200 Subject: [PATCH v5 06/28] mtd: spi-nor: debugfs: Align variable access with the rest of the file Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-6-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The "params" variable is used everywhere else, align this particular line of the file to use "params" directly rather than the "nor" pointer. Reviewed-by: Michael Walle Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/debugfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c index d700e0b27182..69830ad43990 100644 --- a/drivers/mtd/spi-nor/debugfs.c +++ b/drivers/mtd/spi-nor/debugfs.c @@ -139,7 +139,7 @@ static int spi_nor_params_show(struct seq_file *s, void= *data) =20 if (!(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { string_get_size(params->size, 1, STRING_UNITS_2, buf, sizeof(buf)); - seq_printf(s, " %02x (%s)\n", nor->params->die_erase_opcode, buf); + seq_printf(s, " %02x (%s)\n", params->die_erase_opcode, buf); } =20 seq_puts(s, "\nsector map\n"); --=20 2.53.0 From nobody Sat Jun 13 12:06:18 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A3F044D01F; Thu, 7 May 2026 16:47:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172430; cv=none; b=j7ySdFzYITFDt0fbTZf9+JyJioxgX2WK88USQOUDljyeO/q0UpOgNA6m1ydbHIRK8XQYvgQ9SB2rCae+i98mLR95zrMXlnnlWFjaTyieK5HN1c8ZZTAq31psqqUXvauNVIh3Sv5gDMklBoffPVg2kfW2FjITgtWZ52qZ921LTK0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172430; c=relaxed/simple; bh=AJ5kgwcORFft8X7fGFxg332WWjDtcyKWpTMRFzOEUgE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GUMXdUM3qR1je8eIwke6AKMkI7VjI4ulTuEoEk42Jl1RsBLi9cFgRvjz39Bv5qUoVCeSOyFP29/1+a9ecYt5J+tUCo8ZQV2pWzcvbyazts2hD4K8rUqurBogOYHar6y/Fv6nkMDFP+1vPbwRsUJJiQa70klzgSYV3VhgyO9ywKM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=jZOMbxa1; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="jZOMbxa1" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 485494E42C33; Thu, 7 May 2026 16:47:08 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 1C970605CF; Thu, 7 May 2026 16:47:08 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 28A5D108194E2; Thu, 7 May 2026 18:47:06 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1778172427; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=380DMxOtkVf4S8j1lpaF5rnIUMKJfHDNDSHsb4bomqI=; b=jZOMbxa1u8EpHor/OaMpOtoS4ck+q56bAJc6QdT3wvqxVBB5E3wxslMFb4HA4BhRsOp+ct 7Qzva9KLTTFGVCvP0NusFmBfxPBhuXkY901MJ7LJgnDvf0K2OxhI/oON14kvDfkhy1JDss P7FuFh9FlNxlcYw2dpQZV4ocB7MIwZL727OjBRVi++vKnAhX9Kr0LMRMJ4bCiAsOGlPFuP Icq3ru76HZQb9SsPW0BW5gGFXyPKwnZkJalKtopQhOs3/dAA5MbJ+evq8Cbr6zaGFPH9ql edGg3h4MKbEITN1wFmP0FyLoD+QWE5S2XbITlKMe46QgN2nJ5ywwbvEacENLAg== From: Miquel Raynal Date: Thu, 07 May 2026 18:46:48 +0200 Subject: [PATCH v5 07/28] mtd: spi-nor: debugfs: Enhance output Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-7-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Align the number of dashes to the bigger column width (the title in this case) to make the output more pleasant and aligned with what is done in the "params" file output. Reviewed-by: Michael Walle Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/debugfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c index 69830ad43990..d0191eb9f879 100644 --- a/drivers/mtd/spi-nor/debugfs.c +++ b/drivers/mtd/spi-nor/debugfs.c @@ -144,7 +144,7 @@ static int spi_nor_params_show(struct seq_file *s, void= *data) =20 seq_puts(s, "\nsector map\n"); seq_puts(s, " region (in hex) | erase mask | overlaid\n"); - seq_puts(s, " ------------------+------------+----------\n"); + seq_puts(s, " ------------------+------------+---------\n"); for (i =3D 0; i < erase_map->n_regions; i++) { u64 start =3D region[i].offset; u64 end =3D start + region[i].size - 1; --=20 2.53.0 From nobody Sat Jun 13 12:06:18 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0EFCB472767 for ; Thu, 7 May 2026 16:47:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172432; cv=none; b=ASTqtrb+/SKvyNsco9OsNzQ8Mm2rTeCxnY1WY006CRR8q3MO4esu6NquxCA0/fDtDQjlHIji74jmvToA7XKSuZ4ZTLNGAyzlmmAZ9W/My/xKfoEEwgpPNk+4EJ9u3F8Sntv88Rr7dX2zTgY6Lob34a+B4wY8XP0oLFDQ786mYI4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172432; c=relaxed/simple; bh=cgD61f3kJ0Ok5o1W55uyE1PnBczkMq8cG3xlLRmKt2Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CcnOUM0aXjNIXmzdPIsVbsVjVbPvd3UzBPt6kh39RbV4U508naRpYYecWV9tBYAqSr9RBwY52dwn3GOoKJHV0BjATN46YrgyTKSKQLaurF0lEn0BbVoeeO/sqx/yY8MS1p4eeMgkQQtE4Vjj2r1n5kxpvZDWoeUgZ7K6WMF9J9E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=RYLmPhfh; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="RYLmPhfh" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 9B9F2C5DC63; Thu, 7 May 2026 16:47:57 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id D1645605CF; Thu, 7 May 2026 16:47:09 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A1E61108194E4; Thu, 7 May 2026 18:47:07 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1778172429; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=DW149RMGV1/vK6x3sFt0RygGY7FkmmkXRKSFTd7Ff0M=; b=RYLmPhfh3SJ3G9X1Ki2MPVUIx7P+vpnqqgc+rqVzTt+N6K5Galn1WlAH+X3veVvSxJy63j Faxykj9QRUYAZD7MQa/qtwM5v+zsVsCHZpnAwRJFHdwWTHyWmF6IZr/9JqVv/bt1l7UKAg g4Bwyrys16IcUYpYmlRjLuUXRETcZCONlEDcegO2LpWClALgtb7aJEphPzefI1S+bY1RRX FtTmPwFKOdtWewvD24vWCGH1uW12qYzIDXBL6uakXGGM5uiUkCDlt9PzpRMIrdR4OkB6Nd 6xJ0RXpl/CH249ybB0elNdcO0jF7UtvJ/NOoti1OlmS2ksjdKh/71TXjyONxCw== From: Miquel Raynal Date: Thu, 07 May 2026 18:46:49 +0200 Subject: [PATCH v5 08/28] mtd: spi-nor: swp: Explain the MEMLOCK ioctl implementation behaviour Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-8-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add more details about how these requests are actually handled in the SPI NOR core. Their behaviour was not entirely clear to me at first, and explaining them in plain English sounds the way to go. Reviewed-by: Michael Walle Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/core.h | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index e838c40a2589..22f21497c720 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -279,9 +279,14 @@ struct spi_nor_erase_map { =20 /** * struct spi_nor_locking_ops - SPI NOR locking methods - * @lock: lock a region of the SPI NOR. - * @unlock: unlock a region of the SPI NOR. - * @is_locked: check if a region of the SPI NOR is completely locked + * @lock: lock a region of the SPI NOR, never locks more than what is + * requested, ie. may lock less. + * @unlock: unlock a region of the SPI NOR, never unlocks more than what is + * requested, ie. may unlock less. + * @is_locked: check if a region of the SPI NOR is completely locked, retu= rns + * false otherwise. This feeback may be misleading because users + * may get an "unlocked" status even though a subpart of the region + * is effectively locked. */ struct spi_nor_locking_ops { int (*lock)(struct spi_nor *nor, loff_t ofs, u64 len); --=20 2.53.0 From nobody Sat Jun 13 12:06:18 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE3B3472774 for ; Thu, 7 May 2026 16:47:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172434; cv=none; b=T3oxO5h72ZV6y/tXoXi03/G1Yi6+ivlDU4giAQu4sKTj8rfLcNgL+rKBDt0p2EHp+k4nBIk5H+LgmmHtfGc/LpRIXfzL8yhl3l8ykl60VmPHT8/kM6iT18cPg9AuoFUcNijKM7ioe0Rtb5sLD4o7f82C33jcCJKnOXkSGD9ryag= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172434; c=relaxed/simple; bh=0NhpwtjvcZHlnaL3JDUzc3McoMBysNY2GxrJ+BRuGDU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jMBeGL3jRE1vxZ0fgCbVXV5sGMPxCSfgPQfHoLhanabzRn7Kz9V4P+r8giGb3LN4xGa/9BBl6MxIk+faZAxh7h3TVOrdUlnzvevoG2PrKlgltViXRkD8csj1bXRv4LAMaVQnHbMeBVI2Qqgr8mkoU0xCNiUXqAo4TTOVK6aJ9Kc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=BmLRTV0p; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="BmLRTV0p" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id A08804E42C36; Thu, 7 May 2026 16:47:11 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 6D97A605CF; Thu, 7 May 2026 16:47:11 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 62741108194ED; Thu, 7 May 2026 18:47:09 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1778172430; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=6W7hkrB9Ol3hQ/s59VqFJffbxfuvvEc6vOXwL3BRK50=; b=BmLRTV0pLipkHmb3bAqNlGRONFDUq3P/AtiGgoZiUmkisF/dKXWbKZQRsolzdUGUMTptS/ Al7/kqDY/9aJxAoYgZHdsL4Dyd+MokLwaKZYi2cHGr/QZFlmqbSsYupjlbD0hoHz7CkIJZ n383qbc9b3U5kPetYChj4wdHiNOHgtmP3xXCrKjMyW1RzGddYYboMVXBeZLMl97y/itBmi DmYNrhjA+9w+9/8jaLazRFSLRUF6Pl8EVD+fP9WGROHRWkE6QIo5vkG/RXjKlZHUh6zsXP U7b+W9XGXX+scPxNorTWnlx8WUMoGwyHd+1otvbAOZG3Id7j0r1B6jV/0iYAUw== From: Miquel Raynal Date: Thu, 07 May 2026 18:46:50 +0200 Subject: [PATCH v5 09/28] mtd: spi-nor: swp: Clarify a comment Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-9-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The comment states that some power of two sizes are not supported. This is very device dependent (based on the size), so modulate a bit the sentence to make it more accurate. Reviewed-by: Michael Walle Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/swp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index d5f4bf555cfc..f221d6361b57 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -305,7 +305,7 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_= t ofs, u64 len) if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3) val =3D (val & ~SR_BP3) | SR_BP3_BIT6; =20 - /* Some power-of-two sizes are not supported */ + /* Some power-of-two sizes may not be supported */ if (val & ~mask) return -EINVAL; } --=20 2.53.0 From nobody Sat Jun 13 12:06:18 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D90E477982; Thu, 7 May 2026 16:47:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172435; cv=none; b=AFYcBINvu3AsvcltzEqgCv2hPfmUfhEdrvDDbnaa4um79G8VK/o/hikjPa86pH4wMoMYv6XK9pB+KSS11HqNoQwQ4e2QvI6g1HD76vYWi08vCmbqYLw+fdau4dxcIMtXPYJLxErYGyb5skXFMaftVmdpLQ3JTf9QL21uhU6r30M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172435; c=relaxed/simple; bh=O5SRCNJUPxhW0MAcXxjxsdLU2CeqC+uTSU68swKcgmU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Alj5imMPnonGpMLJREWDDQvo6QxAev1aC3RJdBIAqdrXG4a2JkAQPaLxY/kIQIBSD/S9HE86bHRU4Nyxgl7xKx2FKopueQSXpmLIRUkAkfZ+P9s69Xs9Wo0axvjel4Ln0GV3y0Agkt5SBVy+lB6I8Vu1dqIvz8W+/frYtdP/KfQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=rJBQZV/b; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="rJBQZV/b" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 17ECC1A3561; Thu, 7 May 2026 16:47:13 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id E0C90605CF; Thu, 7 May 2026 16:47:12 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id DC6A2108194E2; Thu, 7 May 2026 18:47:10 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1778172432; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=v0jG7SSL0hvSmqOXyehgxCQdSJBYzJtwCSoWUhoR7Js=; b=rJBQZV/bj5fxvZta/B2RzonlSLWRNUJGUQIh0GzXKEa/FUXGjbOLboW//AYOntuGoQkZtp CqqV/Ht+Ea/Up2Q47NS4zKchIbQ6ihSYBEDlI4kI7Mm6O784qwoSg5t3YiEbq42Cu4MXud RDlL78MDmqtzX/VM8jMqsB8neiwyfyx9/s/CQAs5M7kr9QaDv28Wz6FDYYWVmrhh0oFI7B awSWbdOiJPTWpvZK9fkqhVGaSCaDRSikM6VtXRi0CPA7VTJTq3/6+duCErdtFRO5vbFwi1 1QYoId5I2UVZejXHsedrmEw6f76+9rrtY59UGPX3vUGaehFvDt+VqLOLwSReew== From: Miquel Raynal Date: Thu, 07 May 2026 18:46:51 +0200 Subject: [PATCH v5 10/28] mtd: spi-nor: swp: Use a pointer for SR instead of a single byte Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-10-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 At this stage, the Status Register is most often seen as a single byte. This is subject to change when we will need to read the CMP bit which is located in the Control Register (kind of secondary status register). Both will need to be carried. Change a few prototypes to carry a u8 pointer. This way it also makes it very clear where we access the first register, and where we will access the second. There is no functional change. Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/swp.c | 48 ++++++++++++++++++++++++-------------------= ---- 1 file changed, 25 insertions(+), 23 deletions(-) diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index f221d6361b57..61830f18a147 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -55,13 +55,13 @@ static u64 spi_nor_get_min_prot_length_sr(struct spi_no= r *nor) return sector_size; } =20 -static void spi_nor_get_locked_range_sr(struct spi_nor *nor, u8 sr, loff_t= *ofs, +static void spi_nor_get_locked_range_sr(struct spi_nor *nor, const u8 *sr,= loff_t *ofs, u64 *len) { u64 min_prot_len; u8 mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); - u8 bp, val =3D sr & mask; + u8 bp, val =3D sr[0] & mask; =20 if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3_BIT6) val =3D (val & ~SR_BP3_BIT6) | SR_BP3; @@ -81,7 +81,7 @@ static void spi_nor_get_locked_range_sr(struct spi_nor *n= or, u8 sr, loff_t *ofs, if (*len > nor->params->size) *len =3D nor->params->size; =20 - if (nor->flags & SNOR_F_HAS_SR_TB && sr & tb_mask) + if (nor->flags & SNOR_F_HAS_SR_TB && sr[0] & tb_mask) *ofs =3D 0; else *ofs =3D nor->params->size - *len; @@ -92,7 +92,7 @@ static void spi_nor_get_locked_range_sr(struct spi_nor *n= or, u8 sr, loff_t *ofs, * (if @locked is false); false otherwise. */ static bool spi_nor_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, - u64 len, u8 sr, bool locked) + u64 len, const u8 *sr, bool locked) { loff_t lock_offs, lock_offs_max, offs_max; u64 lock_len; @@ -113,13 +113,13 @@ static bool spi_nor_check_lock_status_sr(struct spi_n= or *nor, loff_t ofs, return (ofs >=3D lock_offs_max) || (offs_max <=3D lock_offs); } =20 -static bool spi_nor_is_locked_sr(struct spi_nor *nor, loff_t ofs, u64 len,= u8 sr) +static bool spi_nor_is_locked_sr(struct spi_nor *nor, loff_t ofs, u64 len,= const u8 *sr) { return spi_nor_check_lock_status_sr(nor, ofs, len, sr, true); } =20 static bool spi_nor_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, u64 le= n, - u8 sr) + const u8 *sr) { return spi_nor_check_lock_status_sr(nor, ofs, len, sr, false); } @@ -160,7 +160,8 @@ static bool spi_nor_is_unlocked_sr(struct spi_nor *nor,= loff_t ofs, u64 len, static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len) { u64 min_prot_len; - int ret, status_old, status_new; + int ret; + u8 status_old[1] =3D {}, status_new[1] =3D {}; u8 mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); u8 pow, val; @@ -172,7 +173,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, u64 len) if (ret) return ret; =20 - status_old =3D nor->bouncebuf[0]; + status_old[0] =3D nor->bouncebuf[0]; =20 /* If nothing in our range is unlocked, we don't need to do anything */ if (spi_nor_is_locked_sr(nor, ofs, len, status_old)) @@ -217,7 +218,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, u64 len) return -EINVAL; } =20 - status_new =3D (status_old & ~mask & ~tb_mask) | val; + status_new[0] =3D (status_old[0] & ~mask & ~tb_mask) | val; =20 /* * Disallow further writes if WP# pin is neither left floating nor @@ -225,20 +226,20 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_= t ofs, u64 len) * WP# pin hard strapped to GND can be a valid use case. */ if (!(nor->flags & SNOR_F_NO_WP)) - status_new |=3D SR_SRWD; + status_new[0] |=3D SR_SRWD; =20 if (!use_top) - status_new |=3D tb_mask; + status_new[0] |=3D tb_mask; =20 /* Don't bother if they're the same */ - if (status_new =3D=3D status_old) + if (status_new[0] =3D=3D status_old[0]) return 0; =20 /* Only modify protection if it will not unlock other areas */ - if ((status_new & mask) < (status_old & mask)) + if ((status_new[0] & mask) < (status_old[0] & mask)) return -EINVAL; =20 - return spi_nor_write_sr_and_check(nor, status_new); + return spi_nor_write_sr_and_check(nor, status_new[0]); } =20 /* @@ -249,7 +250,8 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, u64 len) static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, u64 len) { u64 min_prot_len; - int ret, status_old, status_new; + int ret; + u8 status_old[1], status_new[1]; u8 mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); u8 pow, val; @@ -261,7 +263,7 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_= t ofs, u64 len) if (ret) return ret; =20 - status_old =3D nor->bouncebuf[0]; + status_old[0] =3D nor->bouncebuf[0]; =20 /* If nothing in our range is locked, we don't need to do anything */ if (spi_nor_is_unlocked_sr(nor, ofs, len, status_old)) @@ -310,24 +312,24 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, lof= f_t ofs, u64 len) return -EINVAL; } =20 - status_new =3D (status_old & ~mask & ~tb_mask) | val; + status_new[0] =3D (status_old[0] & ~mask & ~tb_mask) | val; =20 /* Don't protect status register if we're fully unlocked */ if (lock_len =3D=3D 0) - status_new &=3D ~SR_SRWD; + status_new[0] &=3D ~SR_SRWD; =20 if (!use_top) - status_new |=3D tb_mask; + status_new[0] |=3D tb_mask; =20 /* Don't bother if they're the same */ - if (status_new =3D=3D status_old) + if (status_new[0] =3D=3D status_old[0]) return 0; =20 /* Only modify protection if it will not lock other areas */ - if ((status_new & mask) > (status_old & mask)) + if ((status_new[0] & mask) > (status_old[0] & mask)) return -EINVAL; =20 - return spi_nor_write_sr_and_check(nor, status_new); + return spi_nor_write_sr_and_check(nor, status_new[0]); } =20 /* @@ -345,7 +347,7 @@ static int spi_nor_sr_is_locked(struct spi_nor *nor, lo= ff_t ofs, u64 len) if (ret) return ret; =20 - return spi_nor_is_locked_sr(nor, ofs, len, nor->bouncebuf[0]); + return spi_nor_is_locked_sr(nor, ofs, len, nor->bouncebuf); } =20 static const struct spi_nor_locking_ops spi_nor_sr_locking_ops =3D { --=20 2.53.0 From nobody Sat Jun 13 12:06:18 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26FBE477E48 for ; Thu, 7 May 2026 16:47:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172437; cv=none; b=rFQ6yh9e8GW+xiaUAXaA6kMmxX1vtO5GIhheWazpk6UGfV/mI0dyH7yCHkgJFa8pO0jXzHU0HTBmOuennrry3nQVc54RSnyK4BVRE387uUlx5f50/+KyKBrDpN+oyGuDq5IVFB00rfNk6B03ww2mio5KEIF5Hvj0Sv02p8iu+Mo= ARC-Message-Signature: i=1; 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Thu, 7 May 2026 16:47:14 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id B8C65605CF; Thu, 7 May 2026 16:47:14 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 7520B108194E4; Thu, 7 May 2026 18:47:12 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1778172433; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=Yw9hmixhwT8/j9bxY/JagAZmyHzXLOzuskrON7hIT9Q=; b=OKYAvzhVhRqDlJIBxpXhtK8vPUdWZYU8YNRT9OwEK5/Z77dJM0HAxkOGQxus1rLb3JEzni jj/bmUmRX8B3r1uwbZdolQHdgGZq2icTmEHB5JjB50zv9gFe/SXfhUVUcS7wKMeaJ5TgwC IkfIzuuJ/bwaTaw1kqdNpx/gEcOCRYD6qwAI2OadHdH6TwWnJHZjTav6wHLfUxo4LUHsKl 2pU49oPUCy9EUhEYIYALI9zLx6PdygAeK8JMsqgLMq8axnR+eElj2yFnoufv1A+Yz6KiX6 ICS6msPhtfH6yN/Az5LImFIXM/nfeD9OkDdq4I9ERqdMNI8v8emLfyeOKf8TIg== From: Miquel Raynal Date: Thu, 07 May 2026 18:46:52 +0200 Subject: [PATCH v5 11/28] mtd: spi-nor: swp: Create a helper that writes SR, CR and checks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-11-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 There are many helpers already to either read and/or write SR and/or CR, as well as sometimes check the returned values. In order to be able to switch from a 1 byte status register to a 2 bytes status register while keeping the same level of verification, let's introduce a new helper that writes them both (atomically) and then reads them back (separated) to compare the values. In case 2 bytes registers are not supported, we still have the usual fallback available in the helper being exported to the rest of the core. Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/core.c | 65 ++++++++++++++++++++++++++++++++++++++++++= ++++ drivers/mtd/spi-nor/core.h | 1 + 2 files changed, 66 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 394c27de02d6..2799c21d0b67 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -976,6 +976,54 @@ int spi_nor_write_16bit_cr_and_check(struct spi_nor *n= or, u8 cr) return 0; } =20 +/** + * spi_nor_write_16bit_sr_cr_and_check() - Write the Status Register 1 and= the + * Configuration Register in one shot. Ensure that the bytes written in bo= th + * registers match the received value. + * @nor: pointer to a 'struct spi_nor'. + * @regs: two-byte array with values to be written to the status and + * configuration registers. + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_write_16bit_sr_cr_and_check(struct spi_nor *nor, const = u8 *regs) +{ + u8 written_regs[2]; + int ret; + + written_regs[0] =3D regs[0]; + written_regs[1] =3D regs[1]; + nor->bouncebuf[0] =3D regs[0]; + nor->bouncebuf[1] =3D regs[1]; + + ret =3D spi_nor_write_sr(nor, nor->bouncebuf, 2); + if (ret) + return ret; + + ret =3D spi_nor_read_sr(nor, &nor->bouncebuf[0]); + if (ret) + return ret; + + if (written_regs[0] !=3D nor->bouncebuf[0]) { + dev_dbg(nor->dev, "SR: Read back test failed\n"); + return -EIO; + } + + if (nor->flags & SNOR_F_NO_READ_CR) + return 0; + + ret =3D spi_nor_read_cr(nor, &nor->bouncebuf[1]); + if (ret) + return ret; + + if (written_regs[1] !=3D nor->bouncebuf[1]) { + dev_dbg(nor->dev, "CR: read back test failed\n"); + return -EIO; + } + + return 0; +} + /** * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure t= hat * the byte written match the received value without affecting other bits = in the @@ -993,6 +1041,23 @@ int spi_nor_write_sr_and_check(struct spi_nor *nor, u= 8 sr1) return spi_nor_write_sr1_and_check(nor, sr1); } =20 +/** + * spi_nor_write_sr_cr_and_check() - Write the Status Register 1 and ensur= e that + * the byte written match the received value. Same for the Control Registe= r if + * available. + * @nor: pointer to a 'struct spi_nor'. + * @regs: byte array to be written to the registers. + * + * Return: 0 on success, -errno otherwise. + */ +int spi_nor_write_sr_cr_and_check(struct spi_nor *nor, const u8 *regs) +{ + if (nor->flags & SNOR_F_HAS_16BIT_SR) + return spi_nor_write_16bit_sr_cr_and_check(nor, regs); + + return spi_nor_write_sr1_and_check(nor, regs[0]); +} + /** * spi_nor_write_sr2() - Write the Status Register 2 using the * SPINOR_OP_WRSR2 (3eh) command. diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 22f21497c720..7f92586b326b 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -637,6 +637,7 @@ int spi_nor_read_cr(struct spi_nor *nor, u8 *cr); int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len); int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1); int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr); +int spi_nor_write_sr_cr_and_check(struct spi_nor *nor, const u8 *regs); =20 ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, u8 *buf); --=20 2.53.0 From nobody Sat Jun 13 12:06:18 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97F2E478E28 for ; Thu, 7 May 2026 16:47:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172439; cv=none; b=c1M0Jykx9pvF4x+fGOG5qJq531q77GI2us9DLPRGSm5wq8D/9R0IAF3ks6AU5sJjXKuHbqXvUJTSlPMYYrXyyqzwD6A9SxRuNwkH4NJlAUams5tTVQiFVWGBLQ39RFLUJviZf27Ai8zDYXoXT3oYC6zlqCp5Zk4ELOYmvPAOgMQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172439; c=relaxed/simple; bh=IRr2/FMxLUtn/FDMCNr6VEcQeIPQJsh19lECUzC//FA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pfNlE99/tDrB7SLCeNX+WCuMUVgSVhcJMaO1mE18ib2psAM0gcjuDY52XulVbYz/aRC4RkcBMigi8WdrrNWHoVNeClnDFe2R8GYfDHPT/HZuaQ0pxNojSySr9TQc3cDAUT58iJNcyl6NxYUxRDOSkeN5UKnSDmRs3J8s6z/6Srw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=hKymR5SV; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="hKymR5SV" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 3D177C5DC60; Thu, 7 May 2026 16:48:04 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 72768605CF; Thu, 7 May 2026 16:47:16 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 39E4C10819513; Thu, 7 May 2026 18:47:14 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1778172435; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=NoH4HRrM2eWPyq6RNqrTnTx6vDNfocXvV7cA6QRFQ4g=; b=hKymR5SVLnssd9iGPfTQfEoTi3NIofTCKQHWdKV/IINyuFMYiwUZsiKpSEU0vt47ycARWq cq8Tx8BEYX1/LNe4V5otuN1r/hcULR/5NMeG3Q+6XdSgtJUDKR66k+Xd9iCoMEbNJKieCd F/MIeYHDfQd4g/T7sTr+Ta35/jzeaacbNeRz16F3c8AFzu25h57QDUgDWFSVmdeJ5hTsZi Di19W/of9fsq3qsOHPMj8Mc3lrlpJbV8i1H6868MsCUGwz32TZkWt9vXqMAk6nKhINTY3U QieBtoWztJOs8VcNH+P2L4mdgwGUDZiLImTT1NoeBYC4qERHyY21Ak/5vnxf6w== From: Miquel Raynal Date: Thu, 07 May 2026 18:46:53 +0200 Subject: [PATCH v5 12/28] mtd: spi-nor: swp: Rename a mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-12-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 "mask" is not very descriptive when we already manipulate two masks, and soon will manipulate three. Rename it "bp_mask" to align with the existing "tb_mask" and soon "cmp_mask". Signed-off-by: Miquel Raynal Reviewed-by: Tudor Ambarus --- drivers/mtd/spi-nor/swp.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index 61830f18a147..07269e09370a 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -59,9 +59,9 @@ static void spi_nor_get_locked_range_sr(struct spi_nor *n= or, const u8 *sr, loff_ u64 *len) { u64 min_prot_len; - u8 mask =3D spi_nor_get_sr_bp_mask(nor); + u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); - u8 bp, val =3D sr[0] & mask; + u8 bp, val =3D sr[0] & bp_mask; =20 if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3_BIT6) val =3D (val & ~SR_BP3_BIT6) | SR_BP3; @@ -162,7 +162,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, u64 len) u64 min_prot_len; int ret; u8 status_old[1] =3D {}, status_new[1] =3D {}; - u8 mask =3D spi_nor_get_sr_bp_mask(nor); + u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); u8 pow, val; loff_t lock_len; @@ -201,7 +201,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, u64 len) lock_len =3D ofs + len; =20 if (lock_len =3D=3D nor->params->size) { - val =3D mask; + val =3D bp_mask; } else { min_prot_len =3D spi_nor_get_min_prot_length_sr(nor); pow =3D ilog2(lock_len) - ilog2(min_prot_len) + 1; @@ -210,15 +210,15 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_= t ofs, u64 len) if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3) val =3D (val & ~SR_BP3) | SR_BP3_BIT6; =20 - if (val & ~mask) + if (val & ~bp_mask) return -EINVAL; =20 /* Don't "lock" with no region! */ - if (!(val & mask)) + if (!(val & bp_mask)) return -EINVAL; } =20 - status_new[0] =3D (status_old[0] & ~mask & ~tb_mask) | val; + status_new[0] =3D (status_old[0] & ~bp_mask & ~tb_mask) | val; =20 /* * Disallow further writes if WP# pin is neither left floating nor @@ -236,7 +236,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, u64 len) return 0; =20 /* Only modify protection if it will not unlock other areas */ - if ((status_new[0] & mask) < (status_old[0] & mask)) + if ((status_new[0] & bp_mask) < (status_old[0] & bp_mask)) return -EINVAL; =20 return spi_nor_write_sr_and_check(nor, status_new[0]); @@ -252,7 +252,7 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_= t ofs, u64 len) u64 min_prot_len; int ret; u8 status_old[1], status_new[1]; - u8 mask =3D spi_nor_get_sr_bp_mask(nor); + u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); u8 pow, val; loff_t lock_len; @@ -308,11 +308,11 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, lof= f_t ofs, u64 len) val =3D (val & ~SR_BP3) | SR_BP3_BIT6; =20 /* Some power-of-two sizes may not be supported */ - if (val & ~mask) + if (val & ~bp_mask) return -EINVAL; } =20 - status_new[0] =3D (status_old[0] & ~mask & ~tb_mask) | val; + status_new[0] =3D (status_old[0] & ~bp_mask & ~tb_mask) | val; =20 /* Don't protect status register if we're fully unlocked */ if (lock_len =3D=3D 0) @@ -326,7 +326,7 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_= t ofs, u64 len) return 0; =20 /* Only modify protection if it will not lock other areas */ - if ((status_new[0] & mask) > (status_old[0] & mask)) + if ((status_new[0] & bp_mask) > (status_old[0] & bp_mask)) return -EINVAL; =20 return spi_nor_write_sr_and_check(nor, status_new[0]); --=20 2.53.0 From nobody Sat Jun 13 12:06:18 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2D3247AF63; Thu, 7 May 2026 16:47:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172440; cv=none; b=bWFGV4fO7mKO47nWlmVkQijdvnTlwwT7JuqF14nkzO7fwX2JVImjWmaVlJsaNqZBChzqXGj//gxFrJPDrGR52RS8lzuzqHWYJpRw2wLZQtKJWHidxUFMtqpJNKsco0TNjPZM7tvAtUdyNYeawwKON2ZLvuByUvEt29/95y4SJls= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-13-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Ease the future reuse of the tb (Top/Bottom) boolean by creating an intermediate variable. Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/swp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index 07269e09370a..540cd221c455 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -62,6 +62,7 @@ static void spi_nor_get_locked_range_sr(struct spi_nor *n= or, const u8 *sr, loff_ u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); u8 bp, val =3D sr[0] & bp_mask; + bool tb =3D (nor->flags & SNOR_F_HAS_SR_TB) ? sr[0] & tb_mask : 0; =20 if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3_BIT6) val =3D (val & ~SR_BP3_BIT6) | SR_BP3; @@ -81,7 +82,7 @@ static void spi_nor_get_locked_range_sr(struct spi_nor *n= or, const u8 *sr, loff_ if (*len > nor->params->size) *len =3D nor->params->size; =20 - if (nor->flags & SNOR_F_HAS_SR_TB && sr[0] & tb_mask) + if (tb) *ofs =3D 0; else *ofs =3D nor->params->size - *len; --=20 2.53.0 From nobody Sat Jun 13 12:06:18 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D58747B43E for ; Thu, 7 May 2026 16:47:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172442; cv=none; b=hJhSVGZrWxNERsqx4SKZGAkf1baGy/i6K10QRV+6Ac0Jx0je32V/oZdih8hnGqLQh0BQeE3VWS0rIY6BDsLCrtBrtI5pOHTiqCI7OhCJN8YPCtuBv/hcoa7z+j7Ldi6qk6o1NY52hsFZYVsdxrorqFoi2tS1FNQU5OcZ87lv6Bs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172442; c=relaxed/simple; bh=JNuaJJ7tGfBMwvMKNN9PBY2xBsXeRGKUq2MB59QV0E0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Zb5QLp3JMuVQYg8dBlqtEMvH5l+GdKqcA/MZgmnP6tHpVXX8yB/iIoZ473qbRIsKN71HkLuRn1VT5zKduzfAtSUhC9HClFd5uI56+VfptmU1lKtwJxg618wL5krAhMVyKWR6cfDuoHmu1F4C7m2KVrPdvDGyDMF5XKMkKV64zjo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=j1mzdCVI; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="j1mzdCVI" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id D7AC51A355C; Thu, 7 May 2026 16:47:19 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id A561A605CF; Thu, 7 May 2026 16:47:19 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 7CE59108194E2; Thu, 7 May 2026 18:47:17 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1778172438; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=e6BDzr2gXG0gqoEqMqjyiWr31fY70QwF9TnwzmX2hIs=; b=j1mzdCVI4s5RarreRyOOUty0J8r8yU/f4AbT84lL2BAVrf0iazgNyB7GecQ2mQHRI5++0k jTT5rmcO0tRXCv4xULxaDW+J1Cv5yKbLjNWJ4ggyMEiDR5DcvjjoXs6bXvbgvB83sjdQbc z3FyBYTZ6fXy+k/nUcOA9wNjYq1YTf0K+Z8tyWsEFfi6vqkpXGFZebC8cyYXFi37S8l+6T +IL6eSad8p6KXDS4zaeHl92Buthfp+s5cSIIucbrTUgZ4mjeycFBt5qAVa/DnyyafrA5fQ MsmFIKZNk5sR9JP5aYhv+a1ACBc1Pt0P9iTnRVx4cSEkKRpPQaeSeMfaNjL22A== From: Miquel Raynal Date: Thu, 07 May 2026 18:46:55 +0200 Subject: [PATCH v5 14/28] mtd: spi-nor: swp: Create helpers for building the SR register Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-14-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The status register contains 3 or 4 BP (Block Protect) bits, 0 or 1 TB (Top/Bottom) bit, soon 0 or 1 CMP (Complement) bit. The last BP bit and the TB bit locations change between vendors. The whole logic of buildling the content of the status register based on some input conditions is used two times and soon will be used 4 times. Create dedicated helpers for these steps. Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/swp.c | 83 +++++++++++++++++++++++++++++--------------= ---- 1 file changed, 51 insertions(+), 32 deletions(-) diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index 540cd221c455..8aa0fe297188 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -125,6 +125,43 @@ static bool spi_nor_is_unlocked_sr(struct spi_nor *nor= , loff_t ofs, u64 len, return spi_nor_check_lock_status_sr(nor, ofs, len, sr, false); } =20 +static int spi_nor_sr_set_bp_mask(struct spi_nor *nor, u8 *sr, u8 pow) +{ + u8 mask =3D spi_nor_get_sr_bp_mask(nor); + u8 val =3D pow << SR_BP_SHIFT; + + if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3) + val =3D (val & ~SR_BP3) | SR_BP3_BIT6; + + if (val & ~mask) + return -EINVAL; + + sr[0] =3D val; + + return 0; +} + +static int spi_nor_build_sr(struct spi_nor *nor, const u8 *old_sr, u8 *new= _sr, + u8 pow, bool use_top) +{ + u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); + u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); + int ret; + + new_sr[0] =3D old_sr[0] & ~bp_mask & ~tb_mask; + + /* Build BP field */ + ret =3D spi_nor_sr_set_bp_mask(nor, &new_sr[0], pow); + if (ret) + return ret; + + /* Build TB field */ + if (!use_top) + new_sr[0] |=3D tb_mask; + + return 0; +} + /* * Lock a region of the flash. Compatible with ST Micro and similar flash. * Supports the block protection bits BP{0,1,2}/BP{0,1,2,3} in the status @@ -164,11 +201,10 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_= t ofs, u64 len) int ret; u8 status_old[1] =3D {}, status_new[1] =3D {}; u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); - u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); - u8 pow, val; loff_t lock_len; bool can_be_top =3D true, can_be_bottom =3D nor->flags & SNOR_F_HAS_SR_TB; bool use_top; + u8 pow; =20 ret =3D spi_nor_read_sr(nor, nor->bouncebuf); if (ret) @@ -202,24 +238,19 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_= t ofs, u64 len) lock_len =3D ofs + len; =20 if (lock_len =3D=3D nor->params->size) { - val =3D bp_mask; + pow =3D (nor->flags & SNOR_F_HAS_4BIT_BP) ? GENMASK(3, 0) : GENMASK(2, 0= ); } else { min_prot_len =3D spi_nor_get_min_prot_length_sr(nor); pow =3D ilog2(lock_len) - ilog2(min_prot_len) + 1; - val =3D pow << SR_BP_SHIFT; - - if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3) - val =3D (val & ~SR_BP3) | SR_BP3_BIT6; - - if (val & ~bp_mask) - return -EINVAL; - - /* Don't "lock" with no region! */ - if (!(val & bp_mask)) - return -EINVAL; } =20 - status_new[0] =3D (status_old[0] & ~bp_mask & ~tb_mask) | val; + ret =3D spi_nor_build_sr(nor, status_old, status_new, pow, use_top); + if (ret) + return ret; + + /* Don't "lock" with no region! */ + if (!(status_new[0] & bp_mask)) + return -EINVAL; =20 /* * Disallow further writes if WP# pin is neither left floating nor @@ -229,9 +260,6 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, u64 len) if (!(nor->flags & SNOR_F_NO_WP)) status_new[0] |=3D SR_SRWD; =20 - if (!use_top) - status_new[0] |=3D tb_mask; - /* Don't bother if they're the same */ if (status_new[0] =3D=3D status_old[0]) return 0; @@ -254,11 +282,10 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, lof= f_t ofs, u64 len) int ret; u8 status_old[1], status_new[1]; u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); - u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); - u8 pow, val; loff_t lock_len; bool can_be_top =3D true, can_be_bottom =3D nor->flags & SNOR_F_HAS_SR_TB; bool use_top; + u8 pow; =20 ret =3D spi_nor_read_sr(nor, nor->bouncebuf); if (ret) @@ -299,29 +326,21 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, lof= f_t ofs, u64 len) lock_len =3D ofs; =20 if (lock_len =3D=3D 0) { - val =3D 0; /* fully unlocked */ + pow =3D 0; /* fully unlocked */ } else { min_prot_len =3D spi_nor_get_min_prot_length_sr(nor); pow =3D ilog2(lock_len) - ilog2(min_prot_len) + 1; - val =3D pow << SR_BP_SHIFT; =20 - if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3) - val =3D (val & ~SR_BP3) | SR_BP3_BIT6; - - /* Some power-of-two sizes may not be supported */ - if (val & ~bp_mask) - return -EINVAL; } =20 - status_new[0] =3D (status_old[0] & ~bp_mask & ~tb_mask) | val; + ret =3D spi_nor_build_sr(nor, status_old, status_new, pow, use_top); + if (ret) + return ret; =20 /* Don't protect status register if we're fully unlocked */ if (lock_len =3D=3D 0) status_new[0] &=3D ~SR_SRWD; =20 - if (!use_top) - status_new[0] |=3D tb_mask; - /* Don't bother if they're the same */ if (status_new[0] =3D=3D status_old[0]) return 0; --=20 2.53.0 From nobody Sat Jun 13 12:06:18 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8BC547CC7F for ; Thu, 7 May 2026 16:47:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172444; cv=none; b=FnPwSpIMDiqEiNR/gbut0UCv0L6Muz1z8pIrdCq0T8XfCwk2PJz0BfKsjdYn0Fk2MaLgqCZLdljBPVGHOW+fQXOrn3x/j/nUkvyRqSYwt2fy7EFJtb9/GZo/YxxXgJFbddkdUf8EdkhT/Wgc+DsPXINnLZl1yq3G8YD7BSJDGuE= ARC-Message-Signature: i=1; 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Thu, 7 May 2026 16:47:21 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 580C2605CF; Thu, 7 May 2026 16:47:21 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 282C6108194E4; Thu, 7 May 2026 18:47:19 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1778172440; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=+w5oU3Gj7K2BYmqNI/4B+f1lhjNH9tKHYf4hS6Tqu1k=; b=SvwCLcRlUH1nlj9wQodxPJxJUNp+urJTHFfLxGnaZPrbD7Z5+YlD5xfKQPmR8ZBBMSCXpy xaci73OYYFThwgZ8KKZeaff3GnxFi6e3LNCJgs+EakNmXu51LnPlf57xtFX8NCdy//BYQG F97AD9IXUyEno2u6+b1HVCDuSDo4zrXAu6jPgp4MLuD1J23arho2tLpXhruzdqVv/iu+yg Ap7ZpAp90fNFbW0y5jmou+6haz9yrt/Yyq7DxIDMHnSny97Nk8teSO2EpwuqLNB7bAG7wL pFPh7xfaxalpFE0I3G53J7WK/EzAOO3/N7TM5TOLTyaCcTngwIurF7ed+EX1mA== From: Miquel Raynal Date: Thu, 07 May 2026 18:46:56 +0200 Subject: [PATCH v5 15/28] mtd: spi-nor: swp: Simplify checking the locked/unlocked range Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-15-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 In both the locking/unlocking steps, at the end we verify whether we do not lock/unlock more than requested (in which case an error must be returned). While being possible to do that with very simple mask comparisons, it does not scale when adding extra locking features such as the CMP possibility. In order to make these checks slightly easier to read and more future proof, use existing helpers to read the (future) status register, extract the covered range, and compare it with very usual algebric comparisons. Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/swp.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index 8aa0fe297188..a45627380363 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -200,7 +200,8 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, u64 len) u64 min_prot_len; int ret; u8 status_old[1] =3D {}, status_new[1] =3D {}; - u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); + loff_t ofs_old, ofs_new; + u64 len_old, len_new; loff_t lock_len; bool can_be_top =3D true, can_be_bottom =3D nor->flags & SNOR_F_HAS_SR_TB; bool use_top; @@ -248,10 +249,6 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t= ofs, u64 len) if (ret) return ret; =20 - /* Don't "lock" with no region! */ - if (!(status_new[0] & bp_mask)) - return -EINVAL; - /* * Disallow further writes if WP# pin is neither left floating nor * wrongly tied to GND (that includes internal pull-downs). @@ -264,8 +261,16 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t= ofs, u64 len) if (status_new[0] =3D=3D status_old[0]) return 0; =20 + spi_nor_get_locked_range_sr(nor, status_old, &ofs_old, &len_old); + spi_nor_get_locked_range_sr(nor, status_new, &ofs_new, &len_new); + + /* Don't "lock" with no region! */ + if (!len_new) + return -EINVAL; + /* Only modify protection if it will not unlock other areas */ - if ((status_new[0] & bp_mask) < (status_old[0] & bp_mask)) + if (len_old && + (ofs_old < ofs_new || (ofs_new + len_new) < (ofs_old + len_old))) return -EINVAL; =20 return spi_nor_write_sr_and_check(nor, status_new[0]); @@ -281,7 +286,8 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_= t ofs, u64 len) u64 min_prot_len; int ret; u8 status_old[1], status_new[1]; - u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); + loff_t ofs_old, ofs_new; + u64 len_old, len_new; loff_t lock_len; bool can_be_top =3D true, can_be_bottom =3D nor->flags & SNOR_F_HAS_SR_TB; bool use_top; @@ -346,7 +352,10 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff= _t ofs, u64 len) return 0; =20 /* Only modify protection if it will not lock other areas */ - if ((status_new[0] & bp_mask) > (status_old[0] & bp_mask)) + spi_nor_get_locked_range_sr(nor, status_old, &ofs_old, &len_old); + spi_nor_get_locked_range_sr(nor, status_new, &ofs_new, &len_new); + if (len_old && len_new && + (ofs_new < ofs_old || (ofs_old + len_old) < (ofs_new + len_new))) return -EINVAL; =20 return spi_nor_write_sr_and_check(nor, status_new[0]); --=20 2.53.0 From nobody Sat Jun 13 12:06:18 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29FB847D949; Thu, 7 May 2026 16:47:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172446; cv=none; b=tZ52kkE+iTCDQeA8JWq5nFaJiJiQa0gIT06+vgEZfJ5OI+fsdKpVyKOj7Rd6O01kKzCypoqVrH/c/LtCPRP9TwCagzgdIP7fC21/w3OYHHHba/lrGr2a5iTa+ZPQL6vnN/5Sq2tDP0FnERy+EuXQmu1gzgExRN0Cu923FFuovfY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Thu, 7 May 2026 16:47:24 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id D224A605CF; Thu, 7 May 2026 16:47:23 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id C142410819513; Thu, 7 May 2026 18:47:20 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1778172442; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=VwHLR/6FdLe2ctHkVMRBIz8NPLwLgjKVBhP9hMYrXR0=; b=zy6DB3nV6oAE3PJCl5cdzL8PtXv0m6T95+5EHUpdg5IS9ykrueUm4idF9usvfxTrowWle8 gMasWrMLSBzjqiiaeZ+AVNuDNRN/ZcymD61CT/nB5vfoGz4U4LiHpo92dCCo5C+Wa7jJ3n srCjDBfu0mAPNAg1ej/JelEkB9Ij+X8iWB7LdSUYh6mhOqF/uIIhv4DiG67UiiG1ZhCl2a 7SKTXGTiY0GIO7JCma03J/aeqIHrnwoVV305N5TPc/J7KcYbJ2Uce5mT88aw4YIeoHPnlq /8dhAYTtU2hlQ7HCI459GD2eu3kkbbRkR8njGXUCWomUHFwruo8+AqUNAS2q5Q== From: Miquel Raynal Date: Thu, 07 May 2026 18:46:57 +0200 Subject: [PATCH v5 16/28] mtd: spi-nor: swp: Cosmetic changes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-16-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 As a final preparation step for the introduction of CMP support, make a few more cosmetic changes to simplify the reading of the diff when adding the CMP feature. In particular, define "min_prot_len" earlier as it will be reused and move the definition of the "ret" variable at the end of the stack just because it looks better. Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/swp.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index a45627380363..c22cb094b66a 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -197,14 +197,14 @@ static int spi_nor_build_sr(struct spi_nor *nor, cons= t u8 *old_sr, u8 *new_sr, */ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len) { - u64 min_prot_len; - int ret; + u64 min_prot_len =3D spi_nor_get_min_prot_length_sr(nor); u8 status_old[1] =3D {}, status_new[1] =3D {}; loff_t ofs_old, ofs_new; u64 len_old, len_new; loff_t lock_len; bool can_be_top =3D true, can_be_bottom =3D nor->flags & SNOR_F_HAS_SR_TB; bool use_top; + int ret; u8 pow; =20 ret =3D spi_nor_read_sr(nor, nor->bouncebuf); @@ -238,12 +238,10 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_= t ofs, u64 len) else lock_len =3D ofs + len; =20 - if (lock_len =3D=3D nor->params->size) { + if (lock_len =3D=3D nor->params->size) pow =3D (nor->flags & SNOR_F_HAS_4BIT_BP) ? GENMASK(3, 0) : GENMASK(2, 0= ); - } else { - min_prot_len =3D spi_nor_get_min_prot_length_sr(nor); + else pow =3D ilog2(lock_len) - ilog2(min_prot_len) + 1; - } =20 ret =3D spi_nor_build_sr(nor, status_old, status_new, pow, use_top); if (ret) @@ -283,7 +281,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t = ofs, u64 len) */ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, u64 len) { - u64 min_prot_len; + u64 min_prot_len =3D spi_nor_get_min_prot_length_sr(nor); int ret; u8 status_old[1], status_new[1]; loff_t ofs_old, ofs_new; @@ -331,14 +329,11 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, lof= f_t ofs, u64 len) else lock_len =3D ofs; =20 - if (lock_len =3D=3D 0) { + if (lock_len =3D=3D 0) pow =3D 0; /* fully unlocked */ - } else { - min_prot_len =3D spi_nor_get_min_prot_length_sr(nor); + else pow =3D ilog2(lock_len) - ilog2(min_prot_len) + 1; =20 - } - ret =3D spi_nor_build_sr(nor, status_old, status_new, pow, use_top); if (ret) return ret; --=20 2.53.0 From nobody Sat Jun 13 12:06:18 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B6B047DD4F for ; Thu, 7 May 2026 16:47:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172449; cv=none; b=asVpAmRZ2RgTgYWZXS70uE1usPM0ZsZ051IciJrCyJGucFf31htHqKjDXcwXMxoguP3w6Ncj20pLTNmhRcza9wNXS+Otzj7DITEFxnNOIqWV/R8jJPMb9HoNRksf0GYd2Y9z91aeppky1zmYOfOx2QJ/HSOaRk1KTNbDNEuyJ6Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172449; c=relaxed/simple; bh=yH07+fBn20Kkp1HYcxpf1Uw9bviLyQufE/Pe1z7auTA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EYWT0E3hl4cz/QtgS2sZ6bkq3lFDBDOgrRUIF92mxCGWoGR2UfyTwPYb8Fr0597n7V7LkD1qp/amOs2rLU/WHxRmpPb7VxwlKkQcdRoFQcKyUH0GIBZ96vOfpnqliAbQS8ZU4+QbzwvXwmvGUGyJEMEwfta2oSme5I9VhFdZsA4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=VLTOP8FN; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="VLTOP8FN" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 4D8EEC5DC64; Thu, 7 May 2026 16:48:14 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 830E0605CF; Thu, 7 May 2026 16:47:26 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 580A3108194E4; Thu, 7 May 2026 18:47:23 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1778172444; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=tyk4eiCefGG1PtqLnRTT3btja7/h8QBKgIFeSq5ePuk=; b=VLTOP8FNVo6lLMxRzSz8X0EcPKhzT0LxEj/GsssLOcevgWVrekxFgzMUbT1BBwQ35aG4CZ KaLk2Tc/KPaXYtWmALW4xAreUbbUjKLAEt2n9jllWR1xIZsx+pk84frweRHTcQeEfbjsNu RI/aWUTEFQp9ZXNUMrB3llQXOOPs89QlkJ6btlHmwMs6I0tqG0aLncWEX7w1rJr/4WwPhG OOveUcL+MrQjK334bJnDpAILMxEjT8BgFIrL1VdG3Go+fltDp4fnPDrYmvCWwhynj4Ocho MbtdYhG2CuWRbjIobdQc+ytn3LMKGjH/oVjXihHt2M9DgdCw8VAT8eTtRp/hCw== From: Miquel Raynal Date: Thu, 07 May 2026 18:46:58 +0200 Subject: [PATCH v5 17/28] mtd: spi-nor: Create a local SR cache Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-17-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 In order to be able to generate debugfs output without having to actually reach the flash, create a SPI NOR local cache of the status registers. What matters in our case are all the bits related to sector locking. As such, in order to make it clear that this cache is not intended to be used anywhere else, we zero the irrelevant bits. The cache is initialized once during the early init, and then maintained every time the write protection scheme is updated. Suggested-by: Michael Walle Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/core.c | 6 +++++- drivers/mtd/spi-nor/core.h | 1 + drivers/mtd/spi-nor/swp.c | 35 +++++++++++++++++++++++++++++++++-- include/linux/mtd/spi-nor.h | 2 ++ 4 files changed, 41 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 2799c21d0b67..cdca0fd881a3 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -3328,8 +3328,12 @@ static int spi_nor_init(struct spi_nor *nor) */ if (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE) || (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE) && - nor->flags & SNOR_F_SWP_IS_VOLATILE)) + nor->flags & SNOR_F_SWP_IS_VOLATILE)) { spi_nor_try_unlock_all(nor); + } else { + /* In the other cases, make sure the debugfs SR cache is up to date */ + spi_nor_cache_sr_lock_bits(nor, NULL); + } =20 if (nor->addr_nbytes =3D=3D 4 && nor->read_proto !=3D SNOR_PROTO_8_8_8_DTR && diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 7f92586b326b..16bf6190e55a 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -679,6 +679,7 @@ int spi_nor_post_bfpt_fixups(struct spi_nor *nor, =20 void spi_nor_init_default_locking_ops(struct spi_nor *nor); void spi_nor_try_unlock_all(struct spi_nor *nor); +void spi_nor_cache_sr_lock_bits(struct spi_nor *nor, u8 *sr); void spi_nor_set_mtd_locking_ops(struct spi_nor *nor); void spi_nor_set_mtd_otp_ops(struct spi_nor *nor); =20 diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index c22cb094b66a..2455f1f6fdf1 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -162,6 +162,25 @@ static int spi_nor_build_sr(struct spi_nor *nor, const= u8 *old_sr, u8 *new_sr, return 0; } =20 +/* + * Keep a local cache containing all lock-related bits for debugfs use onl= y. + * This way, debugfs never needs to access the flash directly. + */ +void spi_nor_cache_sr_lock_bits(struct spi_nor *nor, u8 *sr) +{ + u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); + u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); + + if (!sr) { + if (spi_nor_read_sr(nor, nor->bouncebuf)) + return; + + sr =3D nor->bouncebuf; + } + + nor->dfs_sr_cache[0] =3D sr[0] & (bp_mask | tb_mask | SR_SRWD); +} + /* * Lock a region of the flash. Compatible with ST Micro and similar flash. * Supports the block protection bits BP{0,1,2}/BP{0,1,2,3} in the status @@ -271,7 +290,13 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t= ofs, u64 len) (ofs_old < ofs_new || (ofs_new + len_new) < (ofs_old + len_old))) return -EINVAL; =20 - return spi_nor_write_sr_and_check(nor, status_new[0]); + ret =3D spi_nor_write_sr_and_check(nor, status_new[0]); + if (ret) + return ret; + + spi_nor_cache_sr_lock_bits(nor, status_new); + + return 0; } =20 /* @@ -353,7 +378,13 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff= _t ofs, u64 len) (ofs_new < ofs_old || (ofs_old + len_old) < (ofs_new + len_new))) return -EINVAL; =20 - return spi_nor_write_sr_and_check(nor, status_new[0]); + ret =3D spi_nor_write_sr_and_check(nor, status_new[0]); + if (ret) + return ret; + + spi_nor_cache_sr_lock_bits(nor, status_new); + + return 0; } =20 /* diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 90a0cf583512..9ad77f9e76c2 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -371,6 +371,7 @@ struct spi_nor_flash_parameter; * @reg_proto: the SPI protocol for read_reg/write_reg/erase operations * @sfdp: the SFDP data of the flash * @debugfs_root: pointer to the debugfs directory + * @dfs_sr_cache: Status Register cached value for debugfs use only * @controller_ops: SPI NOR controller driver specific operations. * @params: [FLASH-SPECIFIC] SPI NOR flash parameters and settings. * The structure includes legacy flash parameters and @@ -409,6 +410,7 @@ struct spi_nor { enum spi_nor_cmd_ext cmd_ext_type; struct sfdp *sfdp; struct dentry *debugfs_root; + u8 dfs_sr_cache[2]; =20 const struct spi_nor_controller_ops *controller_ops; =20 --=20 2.53.0 From nobody Sat Jun 13 12:06:18 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FBDD4657CE for ; Thu, 7 May 2026 16:47:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="UMsCaVDw" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id ECBF3C5DC60; Thu, 7 May 2026 16:48:15 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 2E160605CF; Thu, 7 May 2026 16:47:28 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id F1F5C108194A8; Thu, 7 May 2026 18:47:25 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1778172447; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=kNbglLjC+bOzY9rOWqf4+Q3lE3O2aed0iVJ3L4VP1Nw=; b=UMsCaVDwMQtN/DaDZ2MFaW+tI2Cy2g/Cb8FDlSTFu133pu3b81u+6tV17yLWqlv4Iiqbxe appmFwE1NtCZXHQnSAtZ9BTKIHg/BHLvCmLVhnHV67whqK3lCzha+KnuZ1kFZauSdcBjE8 vDtaWbT/PBqreK/81cS1OcsiVBVySSeKHp+CKnbtuzQHCGph/nSy9Wa3LYAWogVTk41NBN nKkh9GXgwpEKAnW8nGF40A8fv8Q9wDkmzrFIEmfCi9IxYJ820vQoS0/HlGJ2M1WuevDVBx Bqy3aAca89WHdKZov7yD/zb83XfD9OYqVPUx14wEIOY4TuJP+cZkEJI+KrHf9g== From: Miquel Raynal Date: Thu, 07 May 2026 18:46:59 +0200 Subject: [PATCH v5 18/28] mtd: spi-nor: debugfs: Add locking support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-18-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The ioctl output may be counter intuitive in some cases. Asking for a "locked status" over a region that is only partially locked will return "unlocked" whereas in practice maybe the biggest part is actually locked. Knowing what is the real software locking state through debugfs would be very convenient for development/debugging purposes, hence this proposal for adding an extra block at the end of the file: a "locked sectors" array which lists every section, if it is locked or not, showing both the address ranges and the sizes in numbers of "lock sectors" (which on small density devices is typically different than erase blocks). Here is an example of output, what is after the "sector map" is new. $ cat /sys/kernel/debug/spi-nor/spi0.0/params name (null) id ef a0 20 00 00 00 size 64.0 MiB write size 1 page size 256 address nbytes 4 flags HAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | HAS_16BIT_SR | HAS_S= R_TB_BIT6 | HAS_4BIT_BP | SOFT_RESET | NO_WP opcodes read 0xec dummy cycles 6 erase 0xdc program 0x34 8D extension none protocols read 1S-4S-4S write 1S-1S-4S register 1S-1S-1S erase commands 21 (4.00 KiB) [1] dc (64.0 KiB) [3] c7 (64.0 MiB) sector map region (in hex) | erase mask | overlaid ------------------+------------+--------- 00000000-03ffffff | [ 3] | no locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-03ffffff | unlocked | 1024 Signed-off-by: Miquel Raynal --- Here are below more examples of output with various situations. The full output of the "params" content has been manually removed to only show what has been added and how it behaves. $ flash_lock -l /dev/mtd0 0x3f00000 16 $ cat /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-03efffff | unlocked | 1008 03f00000-03ffffff | locked | 16 $ $ flash_lock -u /dev/mtd0 0x3f00000 8 $ cat /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-03f7ffff | unlocked | 1016 03f80000-03ffffff | locked | 8 $ $ flash_lock -u /dev/mtd0 $ cat /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-03ffffff | unlocked | 1024 $ $ flash_lock -l /dev/mtd0 $ cat /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-03ffffff | locked | 1024 $ $ flash_lock -u /dev/mtd0 0x20000 1022 $ cat /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-0001ffff | locked | 2 00020000-03ffffff | unlocked | 1022 --- drivers/mtd/spi-nor/core.h | 8 ++++++++ drivers/mtd/spi-nor/debugfs.c | 27 +++++++++++++++++++++++++++ drivers/mtd/spi-nor/swp.c | 13 +++++++++---- 3 files changed, 44 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 16bf6190e55a..552e734c7107 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -287,6 +287,9 @@ struct spi_nor_erase_map { * false otherwise. This feeback may be misleading because users * may get an "unlocked" status even though a subpart of the region * is effectively locked. + * + * If in doubt during development, check-out the debugfs output which trie= s to + * be more user friendly. */ struct spi_nor_locking_ops { int (*lock)(struct spi_nor *nor, loff_t ofs, u64 len); @@ -678,6 +681,7 @@ int spi_nor_post_bfpt_fixups(struct spi_nor *nor, const struct sfdp_bfpt *bfpt); =20 void spi_nor_init_default_locking_ops(struct spi_nor *nor); +bool spi_nor_has_default_locking_ops(struct spi_nor *nor); void spi_nor_try_unlock_all(struct spi_nor *nor); void spi_nor_cache_sr_lock_bits(struct spi_nor *nor, u8 *sr); void spi_nor_set_mtd_locking_ops(struct spi_nor *nor); @@ -712,6 +716,10 @@ static inline bool spi_nor_needs_sfdp(const struct spi= _nor *nor) return !nor->info->size; } =20 +u64 spi_nor_get_min_prot_length_sr(struct spi_nor *nor); +void spi_nor_get_locked_range_sr(struct spi_nor *nor, const u8 *sr, loff_t= *ofs, u64 *len); +bool spi_nor_is_locked_sr(struct spi_nor *nor, loff_t ofs, u64 len, const = u8 *sr); + #ifdef CONFIG_DEBUG_FS void spi_nor_debugfs_register(struct spi_nor *nor); void spi_nor_debugfs_shutdown(void); diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c index d0191eb9f879..36ec35d6b2dc 100644 --- a/drivers/mtd/spi-nor/debugfs.c +++ b/drivers/mtd/spi-nor/debugfs.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 =20 #include +#include #include #include #include @@ -77,10 +78,12 @@ static void spi_nor_print_flags(struct seq_file *s, uns= igned long flags, static int spi_nor_params_show(struct seq_file *s, void *data) { struct spi_nor *nor =3D s->private; + unsigned int min_prot_len =3D spi_nor_get_min_prot_length_sr(nor); struct spi_nor_flash_parameter *params =3D nor->params; struct spi_nor_erase_map *erase_map =3D ¶ms->erase_map; struct spi_nor_erase_region *region =3D erase_map->regions; const struct flash_info *info =3D nor->info; + loff_t lock_start, lock_length; char buf[16], *str; unsigned int i; =20 @@ -159,6 +162,30 @@ static int spi_nor_params_show(struct seq_file *s, voi= d *data) region[i].overlaid ? "yes" : "no"); } =20 + if (!spi_nor_has_default_locking_ops(nor)) + return 0; + + seq_puts(s, "\nlocked sectors\n"); + seq_puts(s, " region (in hex) | status | #sectors\n"); + seq_puts(s, " ------------------+----------+---------\n"); + + spi_nor_get_locked_range_sr(nor, nor->dfs_sr_cache, &lock_start, &lock_le= ngth); + if (!lock_length || lock_length =3D=3D params->size) { + seq_printf(s, " %08llx-%08llx | %s | %llu\n", 0ULL, params->size - 1, + lock_length ? " locked" : "unlocked", + div_u64(params->size, min_prot_len)); + } else if (!lock_start) { + seq_printf(s, " %08llx-%08llx | %s | %llu\n", 0ULL, lock_length - 1, + " locked", div_u64(lock_length, min_prot_len)); + seq_printf(s, " %08llx-%08llx | %s | %llu\n", lock_length, params->size = - 1, + "unlocked", div_u64(params->size - lock_length, min_prot_len)); + } else { + seq_printf(s, " %08llx-%08llx | %s | %llu\n", 0ULL, lock_start - 1, + "unlocked", div_u64(lock_start, min_prot_len)); + seq_printf(s, " %08llx-%08llx | %s | %llu\n", lock_start, params->size -= 1, + " locked", div_u64(lock_length, min_prot_len)); + } + return 0; } DEFINE_SHOW_ATTRIBUTE(spi_nor_params); diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index 2455f1f6fdf1..5d6c3afa36e3 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -34,7 +34,7 @@ static u8 spi_nor_get_sr_tb_mask(struct spi_nor *nor) return 0; } =20 -static u64 spi_nor_get_min_prot_length_sr(struct spi_nor *nor) +u64 spi_nor_get_min_prot_length_sr(struct spi_nor *nor) { unsigned int bp_slots, bp_slots_needed; /* @@ -55,8 +55,8 @@ static u64 spi_nor_get_min_prot_length_sr(struct spi_nor = *nor) return sector_size; } =20 -static void spi_nor_get_locked_range_sr(struct spi_nor *nor, const u8 *sr,= loff_t *ofs, - u64 *len) +void spi_nor_get_locked_range_sr(struct spi_nor *nor, const u8 *sr, loff_t= *ofs, + u64 *len) { u64 min_prot_len; u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); @@ -114,7 +114,7 @@ static bool spi_nor_check_lock_status_sr(struct spi_nor= *nor, loff_t ofs, return (ofs >=3D lock_offs_max) || (offs_max <=3D lock_offs); } =20 -static bool spi_nor_is_locked_sr(struct spi_nor *nor, loff_t ofs, u64 len,= const u8 *sr) +bool spi_nor_is_locked_sr(struct spi_nor *nor, loff_t ofs, u64 len, const = u8 *sr) { return spi_nor_check_lock_status_sr(nor, ofs, len, sr, true); } @@ -416,6 +416,11 @@ void spi_nor_init_default_locking_ops(struct spi_nor *= nor) nor->params->locking_ops =3D &spi_nor_sr_locking_ops; } =20 +bool spi_nor_has_default_locking_ops(struct spi_nor *nor) +{ + return nor->params->locking_ops =3D=3D &spi_nor_sr_locking_ops; +} + static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, u64 len) { struct spi_nor *nor =3D mtd_to_spi_nor(mtd); --=20 2.53.0 From nobody Sat Jun 13 12:06:18 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9394D4657E7; Thu, 7 May 2026 16:47:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172453; cv=none; b=MVAKB6mMBKtaKdUVhB70X1OS+bV5aUTix1XvpLyJdsugwGpMqJv8odvRlqr9QZdhFvb9LoB4NV5MaivaLJS48qJQZP074De8sa3OFN9kQORBuzRgIgeHJoV0+JULwDVinP0/VEvH4sSBTGWZHIgp7nNF4c0KyzXVRyEwZYloeuY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172453; c=relaxed/simple; bh=e2cq/undjZq/vC72DJtcYS3u50cGNet/laObIOtB7LI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Thu, 7 May 2026 16:47:30 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A91E9108194E2; Thu, 7 May 2026 18:47:27 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1778172449; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=iwGbTupe2Sv2/8khMKd3KFO4mUilPJw1cS8ysgUxELs=; b=Pc9jQclBEMOBF8wSMbUXqJ55l5XJxfEockbAPu9x8qZTshD1DUeIZtJzNjzr/lxyJEQ2dg R0otcm5rS4+K0GGS6HKBmnOWgM52V07kzidzySRu5FuzHYecVXZPZ3hu5iQQhkRhTf1ULx A3lnBXzEuQp4qU2KswjeBUXmYyS1kZ+00vUjkGuhV71qUltsEIAFp2pivENlHq49fHsi0u acrN75MUOrzVhp62hwMZZRUInFdVeMx9H8DO1J9/oZn7aQQt0PvuzHffsl34BwSztuVokF qXBIBecSIwVyjQEPdjxoD2LSEziyTnpikMja/EA3YbP5fvHSDn3pXVd5XG3aiA== From: Miquel Raynal Date: Thu, 07 May 2026 18:47:00 +0200 Subject: [PATCH v5 19/28] mtd: spi-nor: debugfs: Add a locked sectors map Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-19-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 In order to get a very clear view of the sectors being locked, besides the `params` output giving the ranges, we may want to see a proper map of the sectors and for each of them, their status. Depending on the use case, this map may be easier to parse by humans and gives a more acurate feeling of the situation. At least myself, for the few locking-related developments I recently went through, I found it very useful to get a clearer mental model of what was locked/unlocked. Here is an example of output: $ cat /sys/kernel/debug/spi-nor/spi0.0/locked-sectors-map Locked sectors map (x: locked, .: unlocked, unit: 64kiB) 0x00000000 (# 0): ................ ................ ................ ..= .............. 0x00400000 (# 64): ................ ................ ................ ..= .............. 0x00800000 (# 128): ................ ................ ................ ..= .............. 0x00c00000 (# 192): ................ ................ ................ ..= .............. 0x01000000 (# 256): ................ ................ ................ ..= .............. 0x01400000 (# 320): ................ ................ ................ ..= .............. 0x01800000 (# 384): ................ ................ ................ ..= .............. 0x01c00000 (# 448): ................ ................ ................ ..= .............. 0x02000000 (# 512): ................ ................ ................ ..= .............. 0x02400000 (# 576): ................ ................ ................ ..= .............. 0x02800000 (# 640): ................ ................ ................ ..= .............. 0x02c00000 (# 704): ................ ................ ................ ..= .............. 0x03000000 (# 768): ................ ................ ................ ..= .............. 0x03400000 (# 832): ................ ................ ................ ..= .............. 0x03800000 (# 896): ................ ................ ................ ..= .............. 0x03c00000 (# 960): ................ ................ ................ ..= ............xx The output is wrapped at 64 sectors, spaces every 16 sectors are improving the readability, every line starts by the first sector offset (hex) and number (decimal). Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/debugfs.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c index 36ec35d6b2dc..a07e879bfa25 100644 --- a/drivers/mtd/spi-nor/debugfs.c +++ b/drivers/mtd/spi-nor/debugfs.c @@ -190,6 +190,40 @@ static int spi_nor_params_show(struct seq_file *s, voi= d *data) } DEFINE_SHOW_ATTRIBUTE(spi_nor_params); =20 +static int spi_nor_locked_sectors_map_show(struct seq_file *s, void *data) +{ + struct spi_nor *nor =3D s->private; + struct spi_nor_flash_parameter *params =3D nor->params; + unsigned int min_prot_len =3D spi_nor_get_min_prot_length_sr(nor); + unsigned int offset =3D 0, sector =3D 0; + bool locked; + int i; + + seq_printf(s, "Locked sectors map (x: locked, .: unlocked, unit: %dkiB)\n= ", + min_prot_len / 1024); + while (offset < params->size) { + seq_printf(s, " 0x%08x (#%5d): ", offset, sector); + for (i =3D 0; i < 64 && offset < params->size; i++) { + locked =3D spi_nor_is_locked_sr(nor, offset, min_prot_len, + nor->dfs_sr_cache); + if (locked) + seq_puts(s, "x"); + else + seq_puts(s, "."); + + if (((i + 1) % 16) =3D=3D 0) + seq_puts(s, " "); + + offset +=3D min_prot_len; + sector++; + } + seq_puts(s, "\n"); + } + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(spi_nor_locked_sectors_map); + static void spi_nor_print_read_cmd(struct seq_file *s, u32 cap, struct spi_nor_read_command *cmd) { @@ -275,6 +309,8 @@ void spi_nor_debugfs_register(struct spi_nor *nor) debugfs_create_file("params", 0444, d, nor, &spi_nor_params_fops); debugfs_create_file("capabilities", 0444, d, nor, &spi_nor_capabilities_fops); + if (spi_nor_has_default_locking_ops(nor)) + debugfs_create_file("locked-sectors-map", 0444, d, nor, &spi_nor_locked_= sectors_map_fops); } =20 void spi_nor_debugfs_shutdown(void) --=20 2.53.0 From nobody Sat Jun 13 12:06:18 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0964447DFBD; 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bh=vA9icDvy306xR1K0kstfOr9lQ8ml0UsecMyKCH6123E=; b=sSJSM5CIVUqsQmJyHSjIkwVY1iX+Hb6ixlo1qEYgw1Fax9vw+DsYRjbXKgvvWouhm7iviY APYKq+AFbFz0FaGLsV7wqkZh1daxWLmwCE59yquiGgxGFKIjHWlDziu+LnJqE6QwXi7tr0 Imc0fMQug8rXb90fs5DehToANzrc6kR/tILsM9tMkhmNH6nSpTGsZU/2qSThVOyfV+sP1I ntOPEVN3ngcxcfYmA5o5UTU495r7UCqDtqmzTtwMpPYn04mI2n1baRT/P80pocvFHPUTWQ hbfWWGOb+dY4NwnuSY7MMF/9dL1jX86TbV2lpHO+nRcPY2ajx7c4jSuRVUmjPA== From: Miquel Raynal Date: Thu, 07 May 2026 18:47:01 +0200 Subject: [PATCH v5 20/28] mtd: spi-nor: Add steps for testing locking support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-20-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 As recently raised on the mailing list, it may be useful to propose a list of steps to go through in order to proove the devices have been described correctly, especially since all the block protection information is not stored in any kind of table and is instead filled manually by developpers. Use the debugfs output to ease the comparison between expectations and reality. Signed-off-by: Miquel Raynal --- Documentation/driver-api/mtd/spi-nor.rst | 132 +++++++++++++++++++++++++++= ++++ 1 file changed, 132 insertions(+) diff --git a/Documentation/driver-api/mtd/spi-nor.rst b/Documentation/drive= r-api/mtd/spi-nor.rst index 148fa4288760..b42de32c6eba 100644 --- a/Documentation/driver-api/mtd/spi-nor.rst +++ b/Documentation/driver-api/mtd/spi-nor.rst @@ -203,3 +203,135 @@ section, after the ``---`` marker. mtd.writesize =3D 1 mtd.oobsize =3D 0 regions =3D 0 + +5) If your flash supports locking, please go through the following test + procedure to make sure it correctly behaves. The below example + expects the typical situation where eraseblocks and lock sectors have + the same size. In case you enabled MTD_SPI_NOR_USE_4K_SECTORS, you + must adapt `bs` accordingly. + + Warning: These tests may hard lock your device! Make sure: + - The device is not hard locked already (#WP strapped to low and + SR_SRWD bit set) + - If you have a WPn pin, you may want to set `no-wp` in your DT for + the time of the test, to only make use of software protection. + Otherwise, clearing the locking state depends on the WPn + signal and if it is tied to low, the flash will be permanently + locked. + + Test full chip locking and make sure expectations, the MEMISLOCKED + ioctl output, the debugfs output and experimental results are all + aligned:: + + root@1:~# alias show_sectors=3D'grep -A4 "locked sectors" /sys/kernel/= debug/spi-nor/spi0.0/params' + root@1:~# flash_lock -u /dev/mtd0 + root@1:~# flash_lock -i /dev/mtd0 + Device: /dev/mtd0 + Start: 0 + Len: 0x4000000 + Lock status: unlocked + Return code: 0 + root@1:~# mtd_debug erase /dev/mtd0 0 2097152 + Erased 2097152 bytes from address 0x00000000 in flash + root@1:~# mtd_debug write /dev/mtd0 0 2097152 spi_test + Copied 2097152 bytes from spi_test to address 0x00000000 in flash + root@1:~# mtd_debug read /dev/mtd0 0 2097152 spi_read + Copied 2097152 bytes from address 0x00000000 in flash to spi_read + root@1:~# sha256sum spi* + c444216a6ba2a4a66cccd60a0dd062bce4b865dd52b200ef5e21838c4b899ac8 spi_= read + c444216a6ba2a4a66cccd60a0dd062bce4b865dd52b200ef5e21838c4b899ac8 spi_= test + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #sectors + ------------------+----------+--------- + 00000000-03ffffff | unlocked | 1024 + + root@1:~# flash_lock -l /dev/mtd0 + root@1:~# flash_lock -i /dev/mtd0 + Device: /dev/mtd0 + Start: 0 + Len: 0x4000000 + Lock status: locked + Return code: 1 + root@1:~# mtd_debug erase /dev/mtd0 0 2097152 + Erased 2097152 bytes from address 0x00000000 in flash + root@1:~# mtd_debug read /dev/mtd0 0 2097152 spi_read + Copied 2097152 bytes from address 0x00000000 in flash to spi_read + root@1:~# sha256sum spi* + c444216a6ba2a4a66cccd60a0dd062bce4b865dd52b200ef5e21838c4b899ac8 spi_= read + c444216a6ba2a4a66cccd60a0dd062bce4b865dd52b200ef5e21838c4b899ac8 spi_= test + root@1:~# dd if=3D/dev/urandom of=3D./spi_test2 bs=3D1M count=3D2 + 2+0 records in + 2+0 records out + root@1:~# mtd_debug write /dev/mtd0 0 2097152 spi_test2 + Copied 2097152 bytes from spi_test to address 0x00000000 in flash + root@1:~# mtd_debug read /dev/mtd0 0 2097152 spi_read2 + Copied 2097152 bytes from address 0x00000000 in flash to spi_read + root@1:~# sha256sum spi* + c444216a6ba2a4a66cccd60a0dd062bce4b865dd52b200ef5e21838c4b899ac8 spi_= read + c444216a6ba2a4a66cccd60a0dd062bce4b865dd52b200ef5e21838c4b899ac8 spi_= read2 + c444216a6ba2a4a66cccd60a0dd062bce4b865dd52b200ef5e21838c4b899ac8 spi_= test + bea9334df51c620440f86751cba0799214a016329f1736f9456d40cf40efdc88 spi_= test2 + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #sectors + ------------------+----------+--------- + 00000000-03ffffff | locked | 1024 + root@1:~# flash_lock -u /dev/mtd0 + + Once we trust the debugfs output we can use it to test various + situations. Check top locking/unlocking (end of the device):: + + root@1:~# size=3D$(cat /sys/class/mtd/mtd0/size) + root@1:~# bs=3D$(cat /sys/class/mtd/mtd0/erasesize) + root@1:~# nsectors=3D$(grep unlocked /sys/kernel/debug/spi-nor/spi0.0/= params | sed -e 's/.*unlocked | //') + root@1:~# ss=3D$(($size / $nsectors)) + root@1:~# bps=3D$(($ss / $bs)) + + root@1:~# flash_lock -u /dev/mtd0 + root@1:~# flash_lock -l /dev/mtd0 $(($size - (2 * $ss))) $((2 * $bps))= # last two + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #sectors + ------------------+----------+--------- + 00000000-03fdffff | unlocked | 1022 + 03fe0000-03ffffff | locked | 2 + root@1:~# flash_lock -u /dev/mtd0 $(($size - (2 * $ss))) $((1 * $bps))= # last one + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #sectors + ------------------+----------+--------- + 00000000-03feffff | unlocked | 1023 + 03ff0000-03ffffff | locked | 1 + + If the flash features 4 block protection bits (BP), we can protect + more than 4MB (typically 128 64kiB-blocks or more), with a finer + grain than locking the entire device:: + + root@1:~# flash_lock -u /dev/mtd0 + root@1:~# flash_lock -l /dev/mtd0 $(($size - (2**7 * $ss))) $((2**7 * = $bps)) + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #sectors + ------------------+----------+--------- + 00000000-037fffff | unlocked | 896 + 03800000-03ffffff | locked | 128 + + If the flash features a Top/Bottom (TB) bit, we can protect the + beginning of the flash:: + + root@1:~# flash_lock -u /dev/mtd0 + root@1:~# flash_lock -l /dev/mtd0 0 $((2 * $bps)) # first two + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #sectors + ------------------+----------+--------- + 00000000-0001ffff | locked | 2 + 00020000-03ffffff | unlocked | 1022 + root@1:~# flash_lock -u /dev/mtd0 $ss $((1 * $bps)) # first one + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #sectors + ------------------+----------+--------- + 00000000-0000ffff | locked | 1 + 00010000-03ffffff | unlocked | 1023 --=20 2.53.0 From nobody Sat Jun 13 12:06:18 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37FBB480332 for ; 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bh=P4ZwINiCfyqTY0eabFbt9ESk/GrmREYHsC/9v2XI8MY=; b=rf3W7sLYqdX/1lNmowPU3eM5DJAnTaDEyQUTwujKK1SM1n9sRpFUXSUGNPJhNaqt7t6jdy 1JXiLbkFhaRraUctUZOwBQGzHppbShfw4ORyMtqCh2cH3p3Vokm1kOUIEyrT6L57ypvPZD nlwKBaLpxkvNQCR55h+Rs2/L4bbFLyJXUtsUDp8F6f61Mt3z94+p023hq9nnWmexoGaMcc pRaDSFIH71OhZXL45+IiOfcoG3bbBrRSKpCR6nJLZYBtvgRxSS2aTit5xlVBQnIi7IkUC4 sn5rLIyvhpNZ2EyAwgKuvwRr/RC9OPLJN3vBU8tPH4+PCYU6+9NxCcIqKx4T5Q== From: Miquel Raynal Date: Thu, 07 May 2026 18:47:02 +0200 Subject: [PATCH v5 21/28] mtd: spi-nor: swp: Add support for the complement feature Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-21-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The current locking implementation allows to select a power of two number of blocks, which is going to be the protected amount, as well as telling whether this is the data at the top (end of the device) or the bottom (beginning of the device). This means at most we can cover half of the device or the entire device, but nothing in between. The complement feature allows a much finer grain of configuration, by allowing to invert what is considered locked and unlocked. Add support for this feature. The only known position for the CMP bit is bit 6 of the configuration register. The locking and unlocking logics are kept unchanged if the CMP bit is unavailable. Otherwise, once the regular logic has been applied, we check if we already found an optimal configuration. If not, we try with the CMP bit set. If the coverage is closer to the request, we use it. Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/core.c | 3 + drivers/mtd/spi-nor/core.h | 4 + drivers/mtd/spi-nor/debugfs.c | 1 + drivers/mtd/spi-nor/swp.c | 202 +++++++++++++++++++++++++++++++++++---= ---- include/linux/mtd/spi-nor.h | 1 + 5 files changed, 179 insertions(+), 32 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index cdca0fd881a3..e78f709d3f5a 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2974,6 +2974,9 @@ static void spi_nor_init_flags(struct spi_nor *nor) nor->flags |=3D SNOR_F_HAS_SR_BP3_BIT6; } =20 + if (flags & SPI_NOR_HAS_CMP) + nor->flags |=3D SNOR_F_HAS_SR2_CMP_BIT6; + if (flags & SPI_NOR_RWW && nor->params->n_banks > 1 && !nor->controller_ops) nor->flags |=3D SNOR_F_RWW; diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 552e734c7107..3ec36103ebab 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -141,6 +141,7 @@ enum spi_nor_option_flags { SNOR_F_ECC =3D BIT(15), SNOR_F_NO_WP =3D BIT(16), SNOR_F_SWAP16 =3D BIT(17), + SNOR_F_HAS_SR2_CMP_BIT6 =3D BIT(18), }; =20 struct spi_nor_read_command { @@ -491,6 +492,8 @@ struct spi_nor_id { * SPI_NOR_NO_ERASE: no erase command needed. * SPI_NOR_QUAD_PP: flash supports Quad Input Page Program. * SPI_NOR_RWW: flash supports reads while write. + * SPI_NOR_HAS_CMP: flash SR2 has complement (CMP) protect bit. = Must + * be used with SPI_NOR_HAS_LOCK. * * @no_sfdp_flags: flags that indicate support that can be discovered via= SFDP. * Used when SFDP tables are not defined in the flash. Th= ese @@ -539,6 +542,7 @@ struct flash_info { #define SPI_NOR_NO_ERASE BIT(6) #define SPI_NOR_QUAD_PP BIT(8) #define SPI_NOR_RWW BIT(9) +#define SPI_NOR_HAS_CMP BIT(10) =20 u8 no_sfdp_flags; #define SPI_NOR_SKIP_SFDP BIT(0) diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c index a07e879bfa25..635ed1cfb3fa 100644 --- a/drivers/mtd/spi-nor/debugfs.c +++ b/drivers/mtd/spi-nor/debugfs.c @@ -30,6 +30,7 @@ static const char *const snor_f_names[] =3D { SNOR_F_NAME(ECC), SNOR_F_NAME(NO_WP), SNOR_F_NAME(SWAP16), + SNOR_F_NAME(HAS_SR2_CMP_BIT6), }; #undef SNOR_F_NAME =20 diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index 5d6c3afa36e3..6b301d04ff23 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -34,6 +34,15 @@ static u8 spi_nor_get_sr_tb_mask(struct spi_nor *nor) return 0; } =20 +static u8 spi_nor_get_sr_cmp_mask(struct spi_nor *nor) +{ + if (!(nor->flags & SNOR_F_NO_READ_CR) && + nor->flags & SNOR_F_HAS_SR2_CMP_BIT6) + return SR2_CMP_BIT6; + else + return 0; +} + u64 spi_nor_get_min_prot_length_sr(struct spi_nor *nor) { unsigned int bp_slots, bp_slots_needed; @@ -61,8 +70,10 @@ void spi_nor_get_locked_range_sr(struct spi_nor *nor, co= nst u8 *sr, loff_t *ofs, u64 min_prot_len; u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); + u8 cmp_mask =3D spi_nor_get_sr_cmp_mask(nor); u8 bp, val =3D sr[0] & bp_mask; bool tb =3D (nor->flags & SNOR_F_HAS_SR_TB) ? sr[0] & tb_mask : 0; + bool cmp =3D sr[1] & cmp_mask; =20 if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3_BIT6) val =3D (val & ~SR_BP3_BIT6) | SR_BP3; @@ -70,22 +81,37 @@ void spi_nor_get_locked_range_sr(struct spi_nor *nor, c= onst u8 *sr, loff_t *ofs, bp =3D val >> SR_BP_SHIFT; =20 if (!bp) { - /* No protection */ - *ofs =3D 0; - *len =3D 0; - return; + if (!cmp) { + /* No protection */ + *ofs =3D 0; + *len =3D 0; + return; + } else { + /* Full protection */ + *ofs =3D 0; + *len =3D nor->params->size; + } } =20 min_prot_len =3D spi_nor_get_min_prot_length_sr(nor); *len =3D min_prot_len << (bp - 1); - if (*len > nor->params->size) *len =3D nor->params->size; =20 - if (tb) - *ofs =3D 0; - else - *ofs =3D nor->params->size - *len; + if (cmp) + *len =3D nor->params->size - *len; + + if (!cmp) { + if (tb) + *ofs =3D 0; + else + *ofs =3D nor->params->size - *len; + } else { + if (tb) + *ofs =3D nor->params->size - *len; + else + *ofs =3D 0; + } } =20 /* @@ -142,13 +168,15 @@ static int spi_nor_sr_set_bp_mask(struct spi_nor *nor= , u8 *sr, u8 pow) } =20 static int spi_nor_build_sr(struct spi_nor *nor, const u8 *old_sr, u8 *new= _sr, - u8 pow, bool use_top) + u8 pow, bool use_top, bool cmp) { u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); + u8 cmp_mask =3D spi_nor_get_sr_cmp_mask(nor); int ret; =20 new_sr[0] =3D old_sr[0] & ~bp_mask & ~tb_mask; + new_sr[1] =3D old_sr[1] & ~cmp_mask; =20 /* Build BP field */ ret =3D spi_nor_sr_set_bp_mask(nor, &new_sr[0], pow); @@ -156,9 +184,13 @@ static int spi_nor_build_sr(struct spi_nor *nor, const= u8 *old_sr, u8 *new_sr, return ret; =20 /* Build TB field */ - if (!use_top) + if ((!cmp && !use_top) || (cmp && use_top)) new_sr[0] |=3D tb_mask; =20 + /* Build CMP field */ + if (cmp) + new_sr[1] |=3D cmp_mask; + return 0; } =20 @@ -170,15 +202,22 @@ void spi_nor_cache_sr_lock_bits(struct spi_nor *nor, = u8 *sr) { u8 bp_mask =3D spi_nor_get_sr_bp_mask(nor); u8 tb_mask =3D spi_nor_get_sr_tb_mask(nor); + u8 cmp_mask =3D spi_nor_get_sr_cmp_mask(nor); =20 if (!sr) { if (spi_nor_read_sr(nor, nor->bouncebuf)) return; =20 + if (!(nor->flags & SNOR_F_NO_READ_CR)) { + if (spi_nor_read_cr(nor, nor->bouncebuf + 1)) + return; + } + sr =3D nor->bouncebuf; } =20 nor->dfs_sr_cache[0] =3D sr[0] & (bp_mask | tb_mask | SR_SRWD); + nor->dfs_sr_cache[1] =3D sr[1] & cmp_mask; } =20 /* @@ -187,10 +226,11 @@ void spi_nor_cache_sr_lock_bits(struct spi_nor *nor, = u8 *sr) * register * (SR). Does not support these features found in newer SR bitfields: * - SEC: sector/block protect - only handle SEC=3D0 (block protect) - * - CMP: complement protect - only support CMP=3D0 (range is not comple= mented) * * Support for the following is provided conditionally for some flash: * - TB: top/bottom protect + * - CMP: complement protect (BP and TP describe the unlocked part, while + * the reminder is locked) * * Sample table portion for 8MB flash (Winbond w25q64fw): * @@ -217,11 +257,13 @@ void spi_nor_cache_sr_lock_bits(struct spi_nor *nor, = u8 *sr) static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len) { u64 min_prot_len =3D spi_nor_get_min_prot_length_sr(nor); - u8 status_old[1] =3D {}, status_new[1] =3D {}; - loff_t ofs_old, ofs_new; - u64 len_old, len_new; + u8 status_old[2] =3D {}, status_new[2] =3D {}, status_new_cmp[2] =3D {}; + u8 *best_status_new =3D status_new; + loff_t ofs_old, ofs_new, ofs_new_cmp; + u64 len_old, len_new, len_new_cmp; loff_t lock_len; - bool can_be_top =3D true, can_be_bottom =3D nor->flags & SNOR_F_HAS_SR_TB; + bool can_be_top =3D true, can_be_bottom =3D nor->flags & SNOR_F_HAS_SR_TB, + can_be_cmp =3D spi_nor_get_sr_cmp_mask(nor); bool use_top; int ret; u8 pow; @@ -232,6 +274,14 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t= ofs, u64 len) =20 status_old[0] =3D nor->bouncebuf[0]; =20 + if (!(nor->flags & SNOR_F_NO_READ_CR)) { + ret =3D spi_nor_read_cr(nor, nor->bouncebuf + 1); + if (ret) + return ret; + + status_old[1] =3D nor->bouncebuf[1]; + } + /* If nothing in our range is unlocked, we don't need to do anything */ if (spi_nor_is_locked_sr(nor, ofs, len, status_old)) return 0; @@ -262,24 +312,56 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_= t ofs, u64 len) else pow =3D ilog2(lock_len) - ilog2(min_prot_len) + 1; =20 - ret =3D spi_nor_build_sr(nor, status_old, status_new, pow, use_top); + ret =3D spi_nor_build_sr(nor, status_old, status_new, pow, use_top, false= ); if (ret) return ret; =20 + /* + * In case the region asked is not fully met, maybe we can try with the + * complement feature + */ + spi_nor_get_locked_range_sr(nor, status_new, &ofs_new, &len_new); + if (can_be_cmp && len_new !=3D lock_len) { + pow =3D ilog2(nor->params->size - lock_len) - ilog2(min_prot_len) + 1; + ret =3D spi_nor_build_sr(nor, status_old, status_new_cmp, pow, use_top, = true); + if (ret) + return ret; + + /* + * ilog2() "floors" the result, which means in some cases we may have to + * manually reduce the scope when the complement feature is used. + * The uAPI is to never lock more than what is requested, but less is ac= cepted. + * Make sure we are not covering a too wide range, reduce it otherwise. + */ + spi_nor_get_locked_range_sr(nor, status_new_cmp, &ofs_new_cmp, &len_new_= cmp); + if (len_new_cmp > lock_len) { + pow++; + ret =3D spi_nor_build_sr(nor, status_old, status_new_cmp, pow, use_top,= true); + if (ret) + return ret; + } + + /* Pick the CMP configuration if we cover a closer range */ + spi_nor_get_locked_range_sr(nor, status_new, &ofs_new, &len_new); + spi_nor_get_locked_range_sr(nor, status_new_cmp, &ofs_new_cmp, &len_new_= cmp); + if (len_new_cmp > len_new) + best_status_new =3D status_new_cmp; + } + /* * Disallow further writes if WP# pin is neither left floating nor * wrongly tied to GND (that includes internal pull-downs). * WP# pin hard strapped to GND can be a valid use case. */ if (!(nor->flags & SNOR_F_NO_WP)) - status_new[0] |=3D SR_SRWD; + best_status_new[0] |=3D SR_SRWD; =20 /* Don't bother if they're the same */ - if (status_new[0] =3D=3D status_old[0]) + if (best_status_new[0] =3D=3D status_old[0] && best_status_new[1] =3D=3D = status_old[1]) return 0; =20 spi_nor_get_locked_range_sr(nor, status_old, &ofs_old, &len_old); - spi_nor_get_locked_range_sr(nor, status_new, &ofs_new, &len_new); + spi_nor_get_locked_range_sr(nor, best_status_new, &ofs_new, &len_new); =20 /* Don't "lock" with no region! */ if (!len_new) @@ -290,11 +372,14 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_= t ofs, u64 len) (ofs_old < ofs_new || (ofs_new + len_new) < (ofs_old + len_old))) return -EINVAL; =20 - ret =3D spi_nor_write_sr_and_check(nor, status_new[0]); + if (nor->flags & SNOR_F_NO_READ_CR) + ret =3D spi_nor_write_sr_and_check(nor, best_status_new[0]); + else + ret =3D spi_nor_write_sr_cr_and_check(nor, best_status_new); if (ret) return ret; =20 - spi_nor_cache_sr_lock_bits(nor, status_new); + spi_nor_cache_sr_lock_bits(nor, best_status_new); =20 return 0; } @@ -308,11 +393,13 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, lof= f_t ofs, u64 len) { u64 min_prot_len =3D spi_nor_get_min_prot_length_sr(nor); int ret; - u8 status_old[1], status_new[1]; - loff_t ofs_old, ofs_new; - u64 len_old, len_new; + u8 status_old[2], status_new[2], status_new_cmp[2]; + u8 *best_status_new =3D status_new; + loff_t ofs_old, ofs_new, ofs_new_cmp; + u64 len_old, len_new, len_new_cmp; loff_t lock_len; - bool can_be_top =3D true, can_be_bottom =3D nor->flags & SNOR_F_HAS_SR_TB; + bool can_be_top =3D true, can_be_bottom =3D nor->flags & SNOR_F_HAS_SR_TB, + can_be_cmp =3D spi_nor_get_sr_cmp_mask(nor); bool use_top; u8 pow; =20 @@ -322,6 +409,14 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff= _t ofs, u64 len) =20 status_old[0] =3D nor->bouncebuf[0]; =20 + if (!(nor->flags & SNOR_F_NO_READ_CR)) { + ret =3D spi_nor_read_cr(nor, nor->bouncebuf + 1); + if (ret) + return ret; + + status_old[1] =3D nor->bouncebuf[1]; + } + /* If nothing in our range is locked, we don't need to do anything */ if (spi_nor_is_unlocked_sr(nor, ofs, len, status_old)) return 0; @@ -359,30 +454,65 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, lof= f_t ofs, u64 len) else pow =3D ilog2(lock_len) - ilog2(min_prot_len) + 1; =20 - ret =3D spi_nor_build_sr(nor, status_old, status_new, pow, use_top); + ret =3D spi_nor_build_sr(nor, status_old, status_new, pow, use_top, false= ); if (ret) return ret; =20 + /* + * In case the region asked is not fully met, maybe we can try with the + * complement feature + */ + spi_nor_get_locked_range_sr(nor, status_new, &ofs_new, &len_new); + if (can_be_cmp && len_new !=3D lock_len) { + pow =3D ilog2(nor->params->size - lock_len) - ilog2(min_prot_len) + 1; + ret =3D spi_nor_build_sr(nor, status_old, status_new_cmp, pow, use_top, = true); + if (ret) + return ret; + + /* + * ilog2() "floors" the result, which means in some cases we may have to + * manually reduce the scope when the complement feature is used. + * The uAPI is to never unlock more than what is requested, but less is = accepted. + * Make sure we are not covering a too small range, increase it otherwis= e. + */ + spi_nor_get_locked_range_sr(nor, status_new_cmp, &ofs_new_cmp, &len_new_= cmp); + if (len_new_cmp < lock_len) { + pow--; + ret =3D spi_nor_build_sr(nor, status_old, status_new_cmp, pow, use_top,= true); + if (ret) + return ret; + } + + /* Pick the CMP configuration if we cover a closer range */ + spi_nor_get_locked_range_sr(nor, status_new, &ofs_new, &len_new); + spi_nor_get_locked_range_sr(nor, status_new_cmp, &ofs_new_cmp, &len_new_= cmp); + if (len_new_cmp > len_new) + best_status_new =3D status_new_cmp; + } + /* Don't protect status register if we're fully unlocked */ if (lock_len =3D=3D 0) - status_new[0] &=3D ~SR_SRWD; + best_status_new[0] &=3D ~SR_SRWD; =20 /* Don't bother if they're the same */ - if (status_new[0] =3D=3D status_old[0]) + if (best_status_new[0] =3D=3D status_old[0] && best_status_new[1] =3D=3D = status_old[1]) return 0; =20 /* Only modify protection if it will not lock other areas */ spi_nor_get_locked_range_sr(nor, status_old, &ofs_old, &len_old); - spi_nor_get_locked_range_sr(nor, status_new, &ofs_new, &len_new); + spi_nor_get_locked_range_sr(nor, best_status_new, &ofs_new, &len_new); if (len_old && len_new && (ofs_new < ofs_old || (ofs_old + len_old) < (ofs_new + len_new))) return -EINVAL; =20 - ret =3D spi_nor_write_sr_and_check(nor, status_new[0]); + if (nor->flags & SNOR_F_NO_READ_CR) + ret =3D spi_nor_write_sr_and_check(nor, best_status_new[0]); + else + ret =3D spi_nor_write_sr_cr_and_check(nor, best_status_new); if (ret) return ret; =20 - spi_nor_cache_sr_lock_bits(nor, status_new); + spi_nor_cache_sr_lock_bits(nor, best_status_new); =20 return 0; } @@ -402,6 +532,14 @@ static int spi_nor_sr_is_locked(struct spi_nor *nor, l= off_t ofs, u64 len) if (ret) return ret; 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b=V79yClZ0ondZxWahZNR19BLo5lhNx3GWoRvbgMVf/jShRbtdrsRPvYz08hI6AxCxdwZL8k xDAoSKO7TIC3LMrVA6I1NyRXRKKRVLYVm/nS+RT0S0n+n1kqQ+x5qWNe9Fh1B93PGWldmR /CrAVfZTMWi0K2S+XrDdC3cOloI+exKo6uHuBdqPWD2o2ogyewJnBqalQ1qr5Nj7bLqvtF RZUHyuyrQVBEIt5k8Yssc95AiHFA0UbN+v8qHXDw/GmSAwrVyKe2wz0W5I24kg7hV/HRv5 wT7I+7GqSkvww4OtQZj1F9rnEaYiOudQafbykExnPYbQ6ZxczcZKqpvK66AYKg== From: Miquel Raynal Date: Thu, 07 May 2026 18:47:03 +0200 Subject: [PATCH v5 22/28] mtd: spi-nor: Add steps for testing locking with CMP Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-22-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Extend the test coverage by giving guidelines to verify the CMP bit acts according to our expectations. Signed-off-by: Miquel Raynal --- The instructions listed in this file target people adding support for new chips, however here are below extra steps that I also ran with the same W25H512NWxxAM chip. They are here to prove core correctness. $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 0 1008 $ show_sectors software locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-03efffff | locked | 1008 03f00000-03ffffff | unlocked | 16 $ flash_lock -l /dev/mtd0 0 1009 $ show_sectors # should not change software locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-03efffff | locked | 1008 03f00000-03ffffff | unlocked | 16 $ flash_lock -l /dev/mtd0 0 1015 $ show_sectors # should not change software locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-03efffff | locked | 1008 03f00000-03ffffff | unlocked | 16 $ flash_lock -l /dev/mtd0 0 1016 $ show_sectors # should cover more software locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-03f7ffff | locked | 1016 03f80000-03ffffff | unlocked | 8 $ flash_lock -u /dev/mtd0 $((1015 * $bs)) 1 $ show_sectors # should not change software locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-03f7ffff | locked | 1016 03f80000-03ffffff | unlocked | 8 $ flash_lock -u /dev/mtd0 $((1009 * $bs)) 7 $ show_sectors # should not change software locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-03f7ffff | locked | 1016 03f80000-03ffffff | unlocked | 8 $ flash_lock -u /dev/mtd0 $((1008 * $bs)) 8 $ show_sectors # range should reduce down to initial value software locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-03efffff | locked | 1008 03f00000-03ffffff | unlocked | 16 [Similar situations, on the other side of the device] $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 $((16 * $bs)) 1008 $ show_sectors software locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-000fffff | unlocked | 16 00100000-03ffffff | locked | 1008 $ flash_lock -l /dev/mtd0 $((15 * $bs)) 1009 $ show_sectors # should not change software locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-000fffff | unlocked | 16 00100000-03ffffff | locked | 1008 $ flash_lock -l /dev/mtd0 $((9 * $bs)) 1015 $ show_sectors # should not change software locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-000fffff | unlocked | 16 00100000-03ffffff | locked | 1008 $ flash_lock -l /dev/mtd0 $((8 * $bs)) 1016 $ show_sectors # should cover more software locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-0007ffff | unlocked | 8 00080000-03ffffff | locked | 1016 $ flash_lock -u /dev/mtd0 $((8 * $bs)) 1 $ show_sectors # should not change software locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-0007ffff | unlocked | 8 00080000-03ffffff | locked | 1016 $ flash_lock -u /dev/mtd0 $((8 * $bs)) 7 $ show_sectors # should not change software locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-0007ffff | unlocked | 8 00080000-03ffffff | locked | 1016 $ flash_lock -u /dev/mtd0 $((8 * $bs)) 8 $ show_sectors # range should reduce down to initial value software locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-000fffff | unlocked | 16 00100000-03ffffff | locked | 1008 --- Documentation/driver-api/mtd/spi-nor.rst | 37 ++++++++++++++++++++++++++++= ++++ 1 file changed, 37 insertions(+) diff --git a/Documentation/driver-api/mtd/spi-nor.rst b/Documentation/drive= r-api/mtd/spi-nor.rst index b42de32c6eba..896cff9c7675 100644 --- a/Documentation/driver-api/mtd/spi-nor.rst +++ b/Documentation/driver-api/mtd/spi-nor.rst @@ -335,3 +335,40 @@ section, after the ``---`` marker. ------------------+----------+--------- 00000000-0000ffff | locked | 1 00010000-03ffffff | unlocked | 1023 + + If the flash features a Complement (CMP) bit, we can protect with + more granularity above half of the capacity. Let's lock all but one + block, then unlock one more block:: + + root@1:~# all_but_one=3D$((($size / $bs) - ($ss / $bs))) + + root@1:~# flash_lock -u /dev/mtd0 + root@1:~# flash_lock -l /dev/mtd0 $ss $all_but_one # all but the first + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #sectors + ------------------+----------+--------- + 00000000-0000ffff | unlocked | 1 + 00010000-03ffffff | locked | 1023 + root@1:~# flash_lock -u /dev/mtd0 $ss $(($ss / $bs)) # all but the two= first + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #sectors + ------------------+----------+--------- + 00000000-0001ffff | unlocked | 2 + 00020000-03ffffff | locked | 1022 + root@1:~# flash_lock -u /dev/mtd0 + root@1:~# flash_lock -l /dev/mtd0 0 $all_but_one # same from the other= side + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #sectors + ------------------+----------+--------- + 00000000-03feffff | locked | 1023 + 03ff0000-03ffffff | unlocked | 1 + root@1:~# flash_lock -u /dev/mtd0 $(($size - (2 * $ss))) $(($ss / $bs)= ) # all but two + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #sectors + ------------------+----------+--------- + 00000000-03fdffff | locked | 1022 + 03fe0000-03ffffff | unlocked | 2 --=20 2.53.0 From nobody Sat Jun 13 12:06:18 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4E23480DEE; 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bh=BoCPB/pz5WLAgqByx+8hBN7GKNEFydMpDcPo2Prr5BA=; b=hU+zfN2ufovGkh8JdGM8ch5PVIf2EKeX4cBtgQDWnF2mSB6Ns1nO3TCXeHRhoY4ZRnDoyY 9+zoqZufq8Gb6hyyYULJzn6npkA7tEY60D3lwZBllzgk13ghB4KOlA0uu8tvqdhqPQah4e J/KMDe0giyNDEnnErgHHbZMixfOgRfTcpXEZunhIPKBYcCdHOMy3pS8gdO7yXLDmALdQpv Hw0XS3BzOPGiQGaceR0QPGledUGIJxuEGpY3gT5FPNUZsK+fC2vUcp7Gj4hcFK1kOdNe94 zmzCArmDMgk6C0R0rSpYadtAs87RD7SnY3jT+7QkJJ8q7KNqlEAa5evxeA0ItA== From: Miquel Raynal Date: Thu, 07 May 2026 18:47:04 +0200 Subject: [PATCH v5 23/28] mtd: spi-nor: winbond: Add W25H512NWxxAM CMP locking support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-23-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 This chip has support for the locking complement (CMP) feature. Add the relevant bit to enable it. Signed-off-by: Miquel Raynal --- Test run following the freshly written documentation: $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 $bs $all_but_one # all but the first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0000ffff | unlocked | 1 00010000-03ffffff | locked | 1023 $ flash_lock -u /dev/mtd0 $bs 1 # all but the two first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0001ffff | unlocked | 2 00020000-03ffffff | locked | 1022 $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 0 $all_but_one # same from the other side $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-03feffff | locked | 1023 03ff0000-03ffffff | unlocked | 1 $ flash_lock -u /dev/mtd0 $(($size - (2 * $bs))) 1 # all but two $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-03fdffff | locked | 1022 03fe0000-03ffffff | unlocked | 2 --- drivers/mtd/spi-nor/winbond.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index eaa547d36aad..ef73c855cedb 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -360,7 +360,8 @@ static const struct flash_info winbond_nor_parts[] =3D { }, { /* W25H512NWxxAM */ .id =3D SNOR_ID(0xef, 0xa0, 0x20), - .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_= NOR_4BIT_BP, + .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | + SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP, }, { /* W25H01NWxxAM */ .id =3D SNOR_ID(0xef, 0xa0, 0x21), --=20 2.53.0 From nobody Sat Jun 13 12:06:18 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AEB348123A; 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bh=iRDyQtvFOEnF1iYl8F9VQ/3msDYew8pxy5X8p5VmpqA=; b=O8axOUlENVkHbq1q4NxFyS9xYvRxPfXkFYlsGkSwGeGKCAcxfW0FheDLDBGAAZ4TA8oY5S o2UqHhbjbSZFxB8gs4ZD0mTZRzNLX7vXCE2++pHd4bMgJUNxBWIkgH0KvxA5w5LG/k6UVU +a85KpGVIRwtfAXL6Xul7suPmUf/0cOWNRjxOVOR2RKRM6OLeM8enatqPDrf9Ro1W6rXL3 GkMaLL/+rCEPi0FIWckdSiN+JaD+In40QVyayReVCfHcnBIvfi5ZNNqQewIbEQWz26bNvX AZ0vN3u4io4W7ADlc6/p8CDwb9owyc9TtHlK+g9QdtMZdKervGBJY/qp2POO5w== From: Miquel Raynal Date: Thu, 07 May 2026 18:47:05 +0200 Subject: [PATCH v5 24/28] mtd: spi-nor: winbond: Add W25H01NWxxAM CMP locking support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-24-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 This chip has support for the locking complement (CMP) feature. Add the relevant bit to enable it. Signed-off-by: Miquel Raynal --- Test run with W25H01NWxxAM: $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 $bs $all_but_one # all but the first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0000ffff | unlocked | 1 00010000-07ffffff | locked | 2047 $ flash_lock -u /dev/mtd0 $bs 1 # all but the two first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0001ffff | unlocked | 2 00020000-07ffffff | locked | 2046 $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 0 $all_but_one # same from the other side $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-07feffff | locked | 2047 07ff0000-07ffffff | unlocked | 1 $ flash_lock -u /dev/mtd0 $(($size - (2 * $bs))) 1 # all but two $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-07fdffff | locked | 2046 07fe0000-07ffffff | unlocked | 2 --- drivers/mtd/spi-nor/winbond.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index ef73c855cedb..7628fa7fb64f 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -365,7 +365,8 @@ static const struct flash_info winbond_nor_parts[] =3D { }, { /* W25H01NWxxAM */ .id =3D SNOR_ID(0xef, 0xa0, 0x21), - .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_= NOR_4BIT_BP, + .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | + SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP, }, { /* W25H02NWxxAM */ .id =3D SNOR_ID(0xef, 0xa0, 0x22), --=20 2.53.0 From nobody Sat Jun 13 12:06:18 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C565A481A92; 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bh=edSYQazxhakuu8k26vId3X0/S/a6bSHMtg1O+5hvsoM=; b=vKwYPBrS4YjVoVEO4GxXcjYXKV+h72br8aWoMtv0FhCJ5KuSeBmfu3DIDU4ECsReg6P0ca EfguaW25dJKf3N5wm4kQ3tCe6HS4cg1fUNfZfXBOvTxqU70TOC5Oh6z+PtrhlIoBhmPiDD hdBgu664mNRAffAJHuC26Q5IOImFvrftq9xCYsK4d/hMlENhGT+3e6QBCqyKkEs5zICihR THTxfOZIrdeFRZg4g7lchfeulBO6+SFiq8+UA6TtQDcoar3BIjrQOrgLU4wNdZmfxFHWBu ihb7sENefFdmMfUuEw8a6WyHMzZSeTzNF7zg9KfZzYu+En1sxhmtpDiAFb3bow== From: Miquel Raynal Date: Thu, 07 May 2026 18:47:06 +0200 Subject: [PATCH v5 25/28] mtd: spi-nor: winbond: Add W25H02NWxxAM CMP locking support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-25-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 This chip has support for the locking complement (CMP) feature. Add the relevant bit to enable it. Unfortunately, this chip also comes with an incorrect BFPT table, indicating the Control Register cannot be read back. This is wrong, reading back the register works and has no (observed) side effect. The datasheet clearly indicates supporting the 35h command and all bits from the CR are marked readable. QE and CMP bits are inside, and can be properly read back. Add a fixup for this, otherwise it would defeat the use of the CMP feature. Signed-off-by: Miquel Raynal --- Test run with W25H02NWxxAM: $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 $bs $all_but_one # all but the first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0000ffff | unlocked | 1 00010000-0fffffff | locked | 4095 $ flash_lock -u /dev/mtd0 $bs 1 # all but the two first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0001ffff | unlocked | 2 00020000-0fffffff | locked | 4094 $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 0 $all_but_one # same from the other side $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0ffeffff | locked | 4095 0fff0000-0fffffff | unlocked | 1 $ flash_lock -u /dev/mtd0 $(($size - (2 * $bs))) 1 # all but two $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0ffdffff | locked | 4094 0ffe0000-0fffffff | unlocked | 2 --- drivers/mtd/spi-nor/winbond.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index 7628fa7fb64f..2c48d6c4a0aa 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -73,6 +73,26 @@ static const struct spi_nor_fixups w25q256_fixups =3D { .post_bfpt =3D w25q256_post_bfpt_fixups, }; =20 +static int +winbond_rdcr_post_bfpt_fixup(struct spi_nor *nor, + const struct sfdp_parameter_header *bfpt_header, + const struct sfdp_bfpt *bfpt) +{ + /* + * W25H02NW, unlike its W25H512NW nor W25H01NW cousins, improperly sets + * the QE BFPT configuration bits, indicating a non readable CR. This is + * both incorrect and impractical, as the chip features a CMP bit for its + * locking scheme that lays in the Control Register, and needs to be read. + */ + nor->flags &=3D ~SNOR_F_NO_READ_CR; + + return 0; +} + +static const struct spi_nor_fixups winbond_rdcr_fixup =3D { + .post_bfpt =3D winbond_rdcr_post_bfpt_fixup, +}; + /** * winbond_nor_select_die() - Set active die. * @nor: pointer to 'struct spi_nor'. @@ -370,7 +390,9 @@ static const struct flash_info winbond_nor_parts[] =3D { }, { /* W25H02NWxxAM */ .id =3D SNOR_ID(0xef, 0xa0, 0x22), - .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_= NOR_4BIT_BP, + .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | + SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP, + .fixups =3D &winbond_rdcr_fixup, }, }; =20 --=20 2.53.0 From nobody Sat Jun 13 12:06:18 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2605546AF1A for ; Thu, 7 May 2026 16:47:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172465; cv=none; b=QH4uQ3kvxUShczgSdLRBz/3f4k9YjZD7QxYhdOXypotdoasB6t/Sxa0DuoN3QXSd8OHi8Lb3TuucroFkvWGlfcioPQwqGYF/pLL0SpsLNIOfVAXHhlx2obyu89v0RS1vfTItIL0F8UTHagTKplTbvh6ENCphz138M1M6rAkEd/M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778172465; c=relaxed/simple; bh=s2upg+yyQ25JI+MtuBTR9uKA1XB4c767Rq9LyzEa1so=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RL2mnqHAVDz1sWwstvxUGpGJ8V9w8JYwYZYpjAYhCman/hMZ01rQ8JVSamFOGDaJ2f8tKcVnO/2mlQ5PQ7/tFfLfNARrWALKPs4TZft+I/1S38YiS/ZgUfBFihMeOvAhaC4Uk9yNbsILn2MI4vTUQjOcecXmARVnnZT9YD899qk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=xRpHxfvC; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="xRpHxfvC" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 05F7E4E42C34; Thu, 7 May 2026 16:47:43 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id CF3EA605CF; Thu, 7 May 2026 16:47:42 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id B0FBB108194E2; Thu, 7 May 2026 18:47:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1778172462; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=m694PdkvWCEJbXS1IgRNRXhpvKEaYvzV1RsJuJcqUY0=; b=xRpHxfvCM8p5NHDJ18DnXbiKrovCnE6ssfpQ/nthHKtlceWg7MSWwKiZ3udmnYi8lUgtkX DL4uxLFhBQH2QFvIsMiI1bjE+1fKnZXdFJUfIn/Dz6aVCznU97/QZ9HzsI9PaSEUa2aFf0 9/k+TaDLjJd+Atd1eWi9iqqv5FaPooCczaA1LsSznpRF9fNdIFokHiSP3Gkq6kmPqa8FOW xJPP7vWyeuBIY4/E2ZV2yoWh1IuK5QTpssPrt8CHGgsQzAeMYxZPRKaHy/jD/QKd3Xv1zm eo1vFnmHmECifWCGm/A0drtPvMR6xblmyDpShEjS/pg90Lxks0yCH9eOEPoVQA== From: Miquel Raynal Date: Thu, 07 May 2026 18:47:07 +0200 Subject: [PATCH v5 26/28] mtd: spi-nor: winbond: Add W25H01NWxxIQ CMP locking support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-26-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 This chip has support for the locking complement (CMP) feature. Add the relevant bit to enable it. Unfortunately, this chip also comes with an incorrect BFPT table, indicating the Control Register cannot be read back. This is wrong, reading back the register works and has no (observed) side effect. The datasheet clearly indicates supporting the 35h command and all bits from the CR are marked readable. QE and CMP bits are inside, and can be properly read back. Add a fixup for this, otherwise it would defeat the use of the CMP feature. Signed-off-by: Miquel Raynal --- Test run with W25H01NWxxIQ: $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 $bs $all_but_one # all but the first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0000ffff | unlocked | 1 00010000-07ffffff | locked | 2047 $ flash_lock -u /dev/mtd0 $bs 1 # all but the two first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0001ffff | unlocked | 2 00020000-07ffffff | locked | 2046 $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 0 $all_but_one # same from the other side $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-07feffff | locked | 2047 07ff0000-07ffffff | unlocked | 1 $ flash_lock -u /dev/mtd0 $(($size - (2 * $bs))) 1 # alll but two $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-07fdffff | locked | 2046 07fe0000-07ffffff | unlocked | 2 --- drivers/mtd/spi-nor/winbond.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index 2c48d6c4a0aa..3eca7baa4d5a 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -368,7 +368,9 @@ static const struct flash_info winbond_nor_parts[] =3D { }, { /* W25Q01NWxxIQ */ .id =3D SNOR_ID(0xef, 0x60, 0x21), - .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_= NOR_4BIT_BP, + .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | + SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP, + .fixups =3D &winbond_rdcr_fixup, }, { /* W25Q01NWxxIM */ .id =3D SNOR_ID(0xef, 0x80, 0x21), --=20 2.53.0 From nobody Sat Jun 13 12:06:18 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CBA5481FC7 for ; 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bh=BzudXirteyCIpUHAn2PSh0cnsxh8jvQrz2NfKL2yz8c=; b=rqFqbMZwEdCfqW2o+ClqRVtVQmm3OWeDk4XGcfZWRMAtYbEE8GhsmkPsLaWG2euWrP3Npx cc79bemYuxskGmxsiAVu4GM3/9mn0UUQ0xCV5O2VesnE8q3JbsoIkrAmEWibujGmiBlJ6Z 4mJflq7+xthqOTZl8jf8rq/8lc+EnU2GfAv3e5ZKIKDx6xlKc9nX1v7FU+1HOJWRW1U7ls KKnxj5glOix0lsJeGXUWwbO8Y0fNG8dyAlPD/l8h8HzONNc6Cpw2tDHBBJJR5pi9jVIuNT ZD8M9BN5q5twd020YHoLMKlskOHacilHRLW8EvD75N7GPFxgKPYDH13CGDITlQ== From: Miquel Raynal Date: Thu, 07 May 2026 18:47:08 +0200 Subject: [PATCH v5 27/28] mtd: spi-nor: winbond: Add W25Q01NWxxIM CMP locking support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-27-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 This chip has support for the locking complement (CMP) feature. Add the relevant bit to enable it. Signed-off-by: Miquel Raynal --- Test run with W25Q01NWxxIM: $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 $bs $all_but_one # all but the first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0000ffff | unlocked | 1 00010000-0fffffff | locked | 4095 $ flash_lock -u /dev/mtd0 $bs 1 # all but the two first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0001ffff | unlocked | 2 00020000-0fffffff | locked | 4094 $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 0 $all_but_one # same from the other side $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0ffeffff | locked | 4095 0fff0000-0fffffff | unlocked | 1 $ flash_lock -u /dev/mtd0 $(($size - (2 * $bs))) 1 # all but two $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0ffdffff | locked | 4094 0ffe0000-0fffffff | unlocked | 2 --- drivers/mtd/spi-nor/winbond.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index 3eca7baa4d5a..3a3b7f2f1659 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -374,7 +374,8 @@ static const struct flash_info winbond_nor_parts[] =3D { }, { /* W25Q01NWxxIM */ .id =3D SNOR_ID(0xef, 0x80, 0x21), - .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_= NOR_4BIT_BP, + .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | + SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP, }, { /* W25Q02NWxxIM */ .id =3D SNOR_ID(0xef, 0x80, 0x22), --=20 2.53.0 From nobody Sat Jun 13 12:06:18 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5AB79481FB0; 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bh=tZrjKlrSTIx0EpT8S91i2zZxREgNAGIUjyhXtv54w/g=; b=mYvXZdy8urt7OjdZ5yUP+KbpFc+fDEFrhM0yjtEhBT19fVKAnPtcI2Ni6A2QaIN1+GXEhn wy9gzxJ1MqCzQQtqERtht7A/B6yBofBfP8BDn1cohGMkQqcq1LCPF+gsWmVRO4RlbtMrXn 80JuZZBSncYuwUpmJykMVxiaC6/U6WrNxevVZfEfoE4y/SLi9wdUQpG+oWJeoFdS57xEZH IP4IOGM2xEuURMMEG/nRKWgsLC9OY4uxxVnOBu1BpA2Zte/4gSTUMe2A2eO0LxB6eUE288 bJCFUf8uTUZz0eydFl9s+37noV7rmMeaVJLEah6t0QcCsW2R8bY0j1D4lN68yw== From: Miquel Raynal Date: Thu, 07 May 2026 18:47:09 +0200 Subject: [PATCH v5 28/28] mtd: spi-nor: winbond: Add W25Q02NWxxIM CMP locking support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-28-93453e1a9597@bootlin.com> References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> In-Reply-To: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Tudor Ambarus , Shuah Khan Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 This chip has support for the locking complement (CMP) feature. Add the relevant bit to enable it. Unfortunately, this chip also comes with an incorrect BFPT table, indicating the Control Register cannot be read back. This is wrong, reading back the register works and has no (observed) side effect. The datasheet clearly indicates supporting the 35h command and all bits from the CR are marked readable. QE and CMP bits are inside, and can be properly read back. Add a fixup for this, otherwise it would defeat the use of the CMP feature. Signed-off-by: Miquel Raynal --- Test run with W25Q02NWxxIM: $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 $bs $all_but_one # all but the first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0000ffff | unlocked | 1 00010000-0fffffff | locked | 4095 $ flash_lock -u /dev/mtd0 $bs 1 # all but the two first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0001ffff | unlocked | 2 00020000-0fffffff | locked | 4094 $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 0 $all_but_one # same from the other side $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0ffeffff | locked | 4095 0fff0000-0fffffff | unlocked | 1 $ flash_lock -u /dev/mtd0 $(($size - (2 * $bs))) 1 # all but two $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0ffdffff | locked | 4094 0ffe0000-0fffffff | unlocked | 2 --- drivers/mtd/spi-nor/winbond.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index 3a3b7f2f1659..8ebdbcec0b3f 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -379,7 +379,9 @@ static const struct flash_info winbond_nor_parts[] =3D { }, { /* W25Q02NWxxIM */ .id =3D SNOR_ID(0xef, 0x80, 0x22), - .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_= NOR_4BIT_BP, + .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | + SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP, + .fixups =3D &winbond_rdcr_fixup, }, { /* W25H512NWxxAM */ .id =3D SNOR_ID(0xef, 0xa0, 0x20), --=20 2.53.0