From nobody Sat Jun 13 12:37:02 2026 Received: from smtpbgbr2.qq.com (smtpbgbr2.qq.com [54.207.22.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C781D3FBED0; Thu, 7 May 2026 14:25:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.207.22.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778163954; cv=none; b=W5cQ0CTen3WkMbEgxbteamzm5Jp8Do9dret0+FTLbmhAEHXfs7Cl4mULIm09z5YX4cdZjxU+ByN7pEucMRir3h8/fYqsCKYlw4elT+HyBN2GLM4qaEml8jdWmYTKIIOG/ctPj2yN4lozdgzGydHOI7Q79NzV5SfyRgCYvSRcIuE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778163954; c=relaxed/simple; bh=KdzwVU8IK1gqq04CutOwP5DDVNNDmSbJ+IC5PGAGMVs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CMGEV89wD96hfjrVhXUmJzgLCjmriVKbUg6dxsHrdJ75A+uwms/gKmQMY55pJIBfCaQ1Y2gTKo9LUcGGoHz/dWifwcQv6NLfpAiBGWVXuHizjLcW+ZOeGEldwZY3gIfSHo8wcSPFivQfMd0zaFLKp8OfpfZdljpWLfivETaXxKk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=radxa.com; spf=pass smtp.mailfrom=radxa.com; arc=none smtp.client-ip=54.207.22.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=radxa.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=radxa.com X-QQ-mid: esmtpgz12t1778163921t64ba066d X-QQ-Originating-IP: T6wJUoRNjvM1mvNJs5gWMX633YucnQkbgVDKCEcdsWE= Received: from [192.168.30.32] ( [116.234.74.217]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 07 May 2026 22:25:20 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 10160670334267879407 EX-QQ-RecipientCnt: 11 From: Xilin Wu Date: Thu, 07 May 2026 22:25:12 +0800 Subject: [PATCH 1/3] dt-bindings: interconnect: qcom,sc8280xp-rpmh: Add reg and clocks for QoS Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-sc8280xp-qos-v1-1-15135858cd98@radxa.com> References: <20260507-sc8280xp-qos-v1-0-15135858cd98@radxa.com> In-Reply-To: <20260507-sc8280xp-qos-v1-0-15135858cd98@radxa.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Xilin Wu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4130; i=sophon@radxa.com; h=from:subject:message-id; bh=KdzwVU8IK1gqq04CutOwP5DDVNNDmSbJ+IC5PGAGMVs=; b=owGbwMvMwCVmdFg0fe08Iz/G02pJDJl/Fpy1lWQV8mo6kirlr9NmFfZZuUlij9qjBVxJ37IYv yt9tDDsKGVhEONikBVTZFGIZ5jLXpl77alYqR7MHFYmkCEMXJwCMJGzZQx/xXmNG/a/yT+QyTvR JDf6kf8hRds5e/dnG6/+VZo1Z1H2Y0aGfdIn37z7YxJ/N8Ngf9bu1aKiCyT/XgxT2hGYlZ0anLK bHwA= X-Developer-Key: i=sophon@radxa.com; a=openpgp; fpr=205F009D07796DD6E516752E32C31567AD9E324E X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:radxa.com:qybglogicsvrsz:qybglogicsvrsz3b-0 X-QQ-XMAILINFO: NvWYEgjCCjcV+k+EafPwdwn55cC+XFjol/ttsc/ooOD78p6RivE/rBbk LwPsN33h8gb9KQBH6LYR405JOyZerMerGAi/Bf+XkKbpLJC4Gc0f8dKqZtU49gGLkCL7TjL bC6HO1go+rXpPxMNfT6l0ZffzbynHbTn8Vt9q2R0ZH3KxblVdn7+Cv/SteNGfe2ORmAgxa2 DljJNF6dpqZbNyDkKGB3yxvKZcE2qjbk+G7fvTNYTazYHfMvLMVArBfEcfIUGe5wf9qAy9c clxpOEvu6qDixQvCkqSLeC3EECYNKcfIkmTiuFqgxx2DzgkSkShPl1Up6910Rm8DRq4gaRV vcH83M/xGHz3STMhPZnTBSO1AapLN4ctevVPPlcST4j1oXButtkNl+88crGjqWqddjY9c/Q cIMsXY8j/uoh4F9Fc4sFQwXCPGhJ6GMyPqTN7kpdj2hVrd0+Km/lIgucv3eJw92tQemTqz3 8MjOG4VITx48oI2TThRovXhqP+OkspvKTESGX3b9aed2qL3YS07D9eTGIZeq9W9/6vc/jAb xexWZTDM3UkwpQf+9CnmRrJQtLNIFLWnxXLHJsUWd9buDelJXLTL2PLRwAGjwZ0u2CaHzZK A1kP5vM/pG1XXsqsag1WCNzWagDIrdVrMnXXRKPrxSaL3B127ytrkBtB2g5N7Ax2KapO8D7 W3GTqlDhnz6OoNcvxCGfRgnM742zcgd7eAPPZvfxbR67dKdu6OzHZwI3DVXhejaNIrWY21t iLHaAm3EZtXwTzMA+JrPGaJW9OIu1lnVJi4wVOOKNVfuofJkl7fDPemvY09Lcywv9fTn75o zN+53jteZsnHhz3hsz7SvhftYurB1ffC9T6SVOAqP2QMF8MaBbcoksbg+IrkT4jLidVtZB3 2/x9mPzWGuy2G/150x1kfGo9vVDR1ucv+tUJOHwn5/DJX2ORirHzlKw395lrloFrdxz3eWz 7gVEnw7aMAxQhOsOgirxSuaTw4frKCuWI6kHZhAvZ0OxrynaGeMq4ECjUDd7j0wuPcqBplf YlbW51AOKtKbFkgP5w5NAq4VQeAtzoef9qbiyDQDyWU3Hegfu8pn9yxqjCm/E= X-QQ-XMRINFO: NS+P29fieYNwqS3WCnRCOn9D1NpZuCnCRA== X-QQ-RECHKSPAM: 0 Add the register range and clock properties needed for programming NoC QoS configuration on SC8280XP. Require a register range for the real NoC providers, require QoS clocks for aggre1_noc and aggre2_noc, and keep the virtual clk_virt and mc_virt providers without MMIO resources or clocks. Signed-off-by: Xilin Wu Reviewed-by: Krzysztof Kozlowski --- .../bindings/interconnect/qcom,sc8280xp-rpmh.yaml | 99 ++++++++++++++++++= +++- 1 file changed, 98 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sc8280xp-r= pmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sc8280xp-rpm= h.yaml index 2a5a7594bafd..cd327a3bf3b9 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,sc8280xp-rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,sc8280xp-rpmh.yaml @@ -32,18 +32,115 @@ properties: - qcom,sc8280xp-nspb-noc - qcom,sc8280xp-system-noc =20 + reg: + maxItems: 1 + + clocks: + minItems: 7 + maxItems: 8 + required: - compatible =20 allOf: - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-clk-virt + - qcom,sc8280xp-mc-virt + then: + properties: + reg: false + clocks: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre USB3 PRIM AXI clock + - description: aggre USB3 SEC AXI clock + - description: aggre USB3 MP AXI clock + - description: aggre USB4 AXI clock + - description: aggre USB4 1 AXI clock + - description: aggre USB NOC SOUTH AXI clock + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-aggre2-noc + then: + properties: + clocks: + items: + - description: aggre NOC PCIE0 tunnel AXI clock + - description: aggre NOC PCIE1 tunnel AXI clock + - description: aggre NOC PCIE 4 AXI clock + - description: aggre NOC PCIE SOUTH SF AXI clock + - description: aggre UFS CARD AXI clock + - description: DDRSS GPU AXI clock + - description: DDRSS PCIE SF TBU clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-aggre1-noc + - qcom,sc8280xp-aggre2-noc + then: + required: + - clocks + else: + properties: + clocks: false =20 unevaluatedProperties: false =20 examples: - | - interconnect-0 { + #include + #include + + interconnect { + compatible =3D "qcom,sc8280xp-clk-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + interconnect@9100000 { + compatible =3D "qcom,sc8280xp-gem-noc"; + reg =3D <0x9100000 0xb8400>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + interconnect@16c0000 { compatible =3D "qcom,sc8280xp-aggre1-noc"; + reg =3D <0x16c0000 0x3af80>; #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_1_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; }; --=20 2.54.0 From nobody Sat Jun 13 12:37:02 2026 Received: from smtpbg150.qq.com (smtpbg150.qq.com [18.132.163.193]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA3E23F20E3; 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dmarc=pass (p=none dis=none) header.from=radxa.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=radxa.com X-QQ-mid: esmtpgz12t1778163924t72b03f88 X-QQ-Originating-IP: d3FR6BTPFfIkyHEhGuflvGaoRQPgM4SifelKYrAD++E= Received: from [192.168.30.32] ( [116.234.74.217]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 07 May 2026 22:25:23 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 7931842178826442287 EX-QQ-RecipientCnt: 11 From: Xilin Wu Date: Thu, 07 May 2026 22:25:13 +0800 Subject: [PATCH 2/3] interconnect: qcom: sc8280xp: Enable QoS configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-sc8280xp-qos-v1-2-15135858cd98@radxa.com> References: <20260507-sc8280xp-qos-v1-0-15135858cd98@radxa.com> In-Reply-To: <20260507-sc8280xp-qos-v1-0-15135858cd98@radxa.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Xilin Wu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; 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Add the QoS box data for the SC8280XP providers, add regmap configurations for the real NoCs, and mark only aggre1_noc and aggre2_noc as requiring clocks for QoS register access. Signed-off-by: Xilin Wu Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/interconnect/qcom/sc8280xp.c | 356 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 356 insertions(+) diff --git a/drivers/interconnect/qcom/sc8280xp.c b/drivers/interconnect/qc= om/sc8280xp.c index ed2161da37bf..333e0aa6b953 100644 --- a/drivers/interconnect/qcom/sc8280xp.c +++ b/drivers/interconnect/qcom/sc8280xp.c @@ -216,6 +216,11 @@ static struct qcom_icc_node qhm_qspi =3D { .name =3D "qhm_qspi", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x5000 }, + .prio =3D 2, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -224,6 +229,11 @@ static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x6000 }, + .prio =3D 2, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -232,6 +242,11 @@ static struct qcom_icc_node qhm_qup2 =3D { .name =3D "qhm_qup2", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xc000 }, + .prio =3D 2, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -248,6 +263,12 @@ static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x8000 }, + .prio =3D 2, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -256,6 +277,11 @@ static struct qcom_icc_node xm_emac_1 =3D { .name =3D "xm_emac_1", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xd000 }, + .prio =3D 2, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -264,6 +290,11 @@ static struct qcom_icc_node xm_sdc4 =3D { .name =3D "xm_sdc4", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x7000 }, + .prio =3D 2, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -272,6 +303,11 @@ static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x9000 }, + .prio =3D 2, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -280,6 +316,11 @@ static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb000 }, + .prio =3D 2, + }, .num_links =3D 1, .link_nodes =3D { &qns_aggre_usb_snoc }, }; @@ -288,6 +329,11 @@ static struct qcom_icc_node xm_usb3_1 =3D { .name =3D "xm_usb3_1", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa000 }, + .prio =3D 2, + }, .num_links =3D 1, .link_nodes =3D { &qns_aggre_usb_snoc }, }; @@ -296,6 +342,11 @@ static struct qcom_icc_node xm_usb3_mp =3D { .name =3D "xm_usb3_mp", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xe000 }, + .prio =3D 2, + }, .num_links =3D 1, .link_nodes =3D { &qns_aggre_usb_snoc }, }; @@ -304,6 +355,11 @@ static struct qcom_icc_node xm_usb4_host0 =3D { .name =3D "xm_usb4_host0", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xf000 }, + .prio =3D 2, + }, .num_links =3D 1, .link_nodes =3D { &qns_aggre_usb_snoc }, }; @@ -312,6 +368,11 @@ static struct qcom_icc_node xm_usb4_host1 =3D { .name =3D "xm_usb4_host1", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x10000 }, + .prio =3D 2, + }, .num_links =3D 1, .link_nodes =3D { &qns_aggre_usb_snoc }, }; @@ -320,6 +381,11 @@ static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa000 }, + .prio =3D 2, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -328,6 +394,11 @@ static struct qcom_icc_node qhm_qup0 =3D { .name =3D "qhm_qup0", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb000 }, + .prio =3D 2, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -344,6 +415,12 @@ static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xe000 }, + .prio =3D 2, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -368,6 +445,11 @@ static struct qcom_icc_node xm_emac_0 =3D { .name =3D "xm_emac_0", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x11000 }, + .prio =3D 2, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -376,6 +458,11 @@ static struct qcom_icc_node xm_pcie3_0 =3D { .name =3D "xm_pcie3_0", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x12000 }, + .prio =3D 2, + }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_gem_noc }, }; @@ -384,6 +471,11 @@ static struct qcom_icc_node xm_pcie3_1 =3D { .name =3D "xm_pcie3_1", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xf000 }, + .prio =3D 2, + }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_gem_noc }, }; @@ -392,6 +484,11 @@ static struct qcom_icc_node xm_pcie3_2a =3D { .name =3D "xm_pcie3_2a", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x13000 }, + .prio =3D 2, + }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_gem_noc }, }; @@ -400,6 +497,11 @@ static struct qcom_icc_node xm_pcie3_2b =3D { .name =3D "xm_pcie3_2b", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x14000 }, + .prio =3D 2, + }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_gem_noc }, }; @@ -408,6 +510,11 @@ static struct qcom_icc_node xm_pcie3_3a =3D { .name =3D "xm_pcie3_3a", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x15000 }, + .prio =3D 2, + }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_gem_noc }, }; @@ -416,6 +523,11 @@ static struct qcom_icc_node xm_pcie3_3b =3D { .name =3D "xm_pcie3_3b", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x16000 }, + .prio =3D 2, + }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_gem_noc }, }; @@ -424,6 +536,11 @@ static struct qcom_icc_node xm_pcie3_4 =3D { .name =3D "xm_pcie3_4", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x10000 }, + .prio =3D 2, + }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_gem_noc }, }; @@ -432,6 +549,11 @@ static struct qcom_icc_node xm_qdss_etr =3D { .name =3D "xm_qdss_etr", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x7000 }, + .prio =3D 2, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -440,6 +562,11 @@ static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x8000 }, + .prio =3D 2, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -448,6 +575,11 @@ static struct qcom_icc_node xm_ufs_card =3D { .name =3D "xm_ufs_card", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x9000 }, + .prio =3D 2, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -587,6 +719,11 @@ static struct qcom_icc_node alm_gpu_tcu =3D { .name =3D "alm_gpu_tcu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa0000 }, + .prio =3D 1, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, @@ -596,6 +733,11 @@ static struct qcom_icc_node alm_pcie_tcu =3D { .name =3D "alm_pcie_tcu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa1000 }, + .prio =3D 3, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, @@ -605,6 +747,11 @@ static struct qcom_icc_node alm_sys_tcu =3D { .name =3D "alm_sys_tcu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa2000 }, + .prio =3D 6, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, @@ -624,6 +771,11 @@ static struct qcom_icc_node qnm_cmpnoc0 =3D { .name =3D "qnm_cmpnoc0", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x1b000, 0x66000 }, + .urg_fwd =3D 1, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, @@ -633,6 +785,11 @@ static struct qcom_icc_node qnm_cmpnoc1 =3D { .name =3D "qnm_cmpnoc1", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x24000, 0x6f000 }, + .urg_fwd =3D 1, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, @@ -652,6 +809,11 @@ static struct qcom_icc_node qnm_gpu =3D { .name =3D "qnm_gpu", .channels =3D 4, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 4, + .port_offsets =3D { 0x1c000, 0x1d000, 0x67000, 0x68000 }, + .urg_fwd =3D 1, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, @@ -661,6 +823,11 @@ static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x1e000, 0x69000 }, + .urg_fwd =3D 1, + }, .num_links =3D 2, .link_nodes =3D { &qns_llcc, &qns_pcie }, @@ -670,6 +837,11 @@ static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x1f000, 0x6a000 }, + .urg_fwd =3D 1, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, @@ -679,6 +851,12 @@ static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa3000 }, + .prio =3D 2, + .urg_fwd =3D 1, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, @@ -688,6 +866,11 @@ static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa4000 }, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_llcc }, }; @@ -696,6 +879,11 @@ static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa5000 }, + .urg_fwd =3D 1, + }, .num_links =3D 3, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, @@ -738,6 +926,11 @@ static struct qcom_icc_node qnm_camnoc_hf =3D { .name =3D "qnm_camnoc_hf", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x10000, 0x10180 }, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_hf }, }; @@ -746,6 +939,11 @@ static struct qcom_icc_node qnm_mdp0_0 =3D { .name =3D "qnm_mdp0_0", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x16000 }, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_hf }, }; @@ -754,6 +952,11 @@ static struct qcom_icc_node qnm_mdp0_1 =3D { .name =3D "qnm_mdp0_1", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x16080 }, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_hf }, }; @@ -762,6 +965,11 @@ static struct qcom_icc_node qnm_mdp1_0 =3D { .name =3D "qnm_mdp1_0", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xf000 }, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_hf }, }; @@ -770,6 +978,11 @@ static struct qcom_icc_node qnm_mdp1_1 =3D { .name =3D "qnm_mdp1_1", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xf800 }, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_hf }, }; @@ -786,6 +999,11 @@ static struct qcom_icc_node qnm_rot_0 =3D { .name =3D "qnm_rot_0", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x17000 }, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -794,6 +1012,11 @@ static struct qcom_icc_node qnm_rot_1 =3D { .name =3D "qnm_rot_1", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xe000 }, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -802,6 +1025,11 @@ static struct qcom_icc_node qnm_video0 =3D { .name =3D "qnm_video0", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x14000 }, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -810,6 +1038,11 @@ static struct qcom_icc_node qnm_video1 =3D { .name =3D "qnm_video1", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x14080 }, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -818,6 +1051,11 @@ static struct qcom_icc_node qnm_video_cvp =3D { .name =3D "qnm_video_cvp", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x15000 }, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -826,6 +1064,11 @@ static struct qcom_icc_node qxm_camnoc_icp =3D { .name =3D "qxm_camnoc_icp", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x11000 }, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -834,6 +1077,11 @@ static struct qcom_icc_node qxm_camnoc_sf =3D { .name =3D "qxm_camnoc_sf", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x12000 }, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -900,6 +1148,11 @@ static struct qcom_icc_node qnm_lpass_noc =3D { .name =3D "qnm_lpass_noc", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xe000 }, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_gemnoc_sf }, }; @@ -916,6 +1169,12 @@ static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x10000 }, + .prio =3D 2, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_gemnoc_gc }, }; @@ -924,6 +1183,11 @@ static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x12000 }, + .prio =3D 2, + }, .num_links =3D 1, .link_nodes =3D { &qns_gemnoc_gc }, }; @@ -1997,11 +2261,21 @@ static struct qcom_icc_node * const aggre1_noc_node= s[] =3D { [SLAVE_SERVICE_A1NOC] =3D &srvc_aggre1_noc, }; =20 +static const struct regmap_config sc8280xp_aggre1_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x3af80, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sc8280xp_aggre1_noc =3D { + .config =3D &sc8280xp_aggre1_noc_regmap_config, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, .num_bcms =3D ARRAY_SIZE(aggre1_noc_bcms), + .qos_requires_clocks =3D true, }; =20 static struct qcom_icc_bcm * const aggre2_noc_bcms[] =3D { @@ -2033,11 +2307,21 @@ static struct qcom_icc_node * const aggre2_noc_node= s[] =3D { [SLAVE_SERVICE_A2NOC] =3D &srvc_aggre2_noc, }; =20 +static const struct regmap_config sc8280xp_aggre2_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x3af80, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sc8280xp_aggre2_noc =3D { + .config =3D &sc8280xp_aggre2_noc_regmap_config, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, .num_bcms =3D ARRAY_SIZE(aggre2_noc_bcms), + .qos_requires_clocks =3D true, }; =20 static struct qcom_icc_bcm * const clk_virt_bcms[] =3D { @@ -2159,7 +2443,16 @@ static struct qcom_icc_node * const config_noc_nodes= [] =3D { [SLAVE_TCU] =3D &xs_sys_tcu_cfg, }; =20 +static const struct regmap_config sc8280xp_config_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x2c000, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sc8280xp_config_noc =3D { + .config =3D &sc8280xp_config_noc_regmap_config, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -2175,7 +2468,16 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { [SLAVE_GEM_NOC_CFG] =3D &qns_gemnoc, }; =20 +static const struct regmap_config sc8280xp_dc_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x5080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sc8280xp_dc_noc =3D { + .config =3D &sc8280xp_dc_noc_regmap_config, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), .bcms =3D dc_noc_bcms, @@ -2209,7 +2511,16 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { [SLAVE_SERVICE_GEM_NOC] =3D &srvc_sys_gemnoc, }; =20 +static const struct regmap_config sc8280xp_gem_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xb8400, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sc8280xp_gem_noc =3D { + .config =3D &sc8280xp_gem_noc_regmap_config, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -2232,7 +2543,16 @@ static struct qcom_icc_node * const lpass_ag_noc_nod= es[] =3D { [SLAVE_SERVICE_LPASS_AG_NOC] =3D &srvc_niu_lpass_agnoc, }; =20 +static const struct regmap_config sc8280xp_lpass_ag_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xf080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sc8280xp_lpass_ag_noc =3D { + .config =3D &sc8280xp_lpass_ag_noc_regmap_config, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), .bcms =3D lpass_ag_noc_bcms, @@ -2280,7 +2600,16 @@ static struct qcom_icc_node * const mmss_noc_nodes[]= =3D { [SLAVE_SERVICE_MNOC] =3D &srvc_mnoc, }; =20 +static const struct regmap_config sc8280xp_mmss_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1fa80, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sc8280xp_mmss_noc =3D { + .config =3D &sc8280xp_mmss_noc_regmap_config, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -2300,7 +2629,16 @@ static struct qcom_icc_node * const nspa_noc_nodes[]= =3D { [SLAVE_SERVICE_NSP_NOC] =3D &service_nsp_noc, }; =20 +static const struct regmap_config sc8280xp_nspa_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x10000, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sc8280xp_nspa_noc =3D { + .config =3D &sc8280xp_nspa_noc_regmap_config, .nodes =3D nspa_noc_nodes, .num_nodes =3D ARRAY_SIZE(nspa_noc_nodes), .bcms =3D nspa_noc_bcms, @@ -2320,7 +2658,16 @@ static struct qcom_icc_node * const nspb_noc_nodes[]= =3D { [SLAVE_SERVICE_NSPB_NOC] =3D &service_nspb_noc, }; =20 +static const struct regmap_config sc8280xp_nspb_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x10000, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sc8280xp_nspb_noc =3D { + .config =3D &sc8280xp_nspb_noc_regmap_config, .nodes =3D nspb_noc_nodes, .num_nodes =3D ARRAY_SIZE(nspb_noc_nodes), .bcms =3D nspb_noc_bcms, @@ -2349,7 +2696,16 @@ static struct qcom_icc_node * const system_noc_main_= nodes[] =3D { [SLAVE_SERVICE_SNOC] =3D &srvc_snoc, }; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-sc8280xp-qos-v1-3-15135858cd98@radxa.com> References: <20260507-sc8280xp-qos-v1-0-15135858cd98@radxa.com> In-Reply-To: <20260507-sc8280xp-qos-v1-0-15135858cd98@radxa.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Xilin Wu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6485; i=sophon@radxa.com; h=from:subject:message-id; bh=s1q8Z2zLk379tlyeuEzoNaf2j3FUEhXmKv5Jezkio8k=; b=owGbwMvMwCVmdFg0fe08Iz/G02pJDJl/Fpw9mCc9Oyk0sXTFFobP0hNKWSPaTMI38X80V77xP zJu1WfHjlIWBjEuBlkxRRaFeIa57JW5156KlerBzGFlAhnCwMUpABNpXM3w35Gh4foRLqV7L3x3 9emV99+1F9Hbnpqj5fv/Zx7johnvuBgZJmdxG20u03Litv0mFed6dcrVMIecoM2/FR/2CP6Yqyr LDwA= X-Developer-Key: i=sophon@radxa.com; a=openpgp; fpr=205F009D07796DD6E516752E32C31567AD9E324E X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:radxa.com:qybglogicsvrsz:qybglogicsvrsz3b-0 X-QQ-XMAILINFO: MLY6kX+APjAQ3XvEyTG3A63TZMprpixo0rLkwGVpgV89wUgZlq80gsoY trJji5sKrFe9T+X1v4Td+aWT40V/Jo7SplzX0Rg78P4eQICRlMEH6pc44zqqzah7lV9bS6P M38gjS2l0s9iKQSiW4wQNoFfF/RB9F0UlrrFvCszLpYUQqZjZ2tS6k/MnVokeSbp0b6BYVc dz6l2kSWUBfSV44CmWOdlsHenM67fTHjpCm8JCPJU5beswC0CcOOg3ZsLhmRos2r4CpCKlH XZHs9iOET5lcogIZ4JjwIqKDooUudiSWUdPv39+u8LjJm6OTKSN+v4N80c0SkfxkRKo1GPs 5l3vqNxPpQE5Ako6nZqn8cuGAc7w49E9duNcSlM3rmMT9HxcikO1+IPZDcVk4H1XkINFuCU H3q4PyNTAKqqCyJCrDH7StZMjK6uaSriL9Ml0DSUvnGQqELAgYBsKEC68UtyTuKzqB75ZHC C7BCmT2uLHrrT1/Jrdy5QSgrOP9+EQytpryW2Y7RjnoJA4f9Ulae5PcOLd70s6C9+owd2AA NHU8W/48LBrlDI5BjIgt6FVrXo4rYW8xhC+5RfksE+P2+rkEgvgXfX/BdgXwhoTNn5Qma+3 QTfYVZqMRJTwP5/t8fVJnXLCV7EgF/MlePmoSJxWyfE47/FOrREzKFzf1VdCSRFWOlRj/ZC eHkX+xrOImIAseSz1v5zigad43JfgMBkjgO8Tgk6w0xeOaH8zHO4KCCrKo0S3AruM2p8d0F /xsS7BYkcP1Zmx8oOkdrlVVn5Sv+R5opWDy5U1HxutGlPrY/FvF3TFa0fDh55yVrK3fQwpI em0YS7PJZMV1ymTTRlz13b7FpfA+tDd4zc96EuU2U4lV2Egw+Ntln3f+00tBB6uPOSeaOoP MTjmi11hxg78jfkrgSaNsHx1WDSz1tDZUFfFHYPV5VJALy+nfpkhzADd9LzOR0pz5zBoR1g LrXKDVzpTdjZsiwqWQpW3gMghQnGnwv4aTzF1JzYlTc5NRam7blmabRAMLjxlC0OE5TlC9t /MC+OH6qwlJ8qES3YfpJD2E/PW845zg3BsWjDKflwKZlHZPyelgVmrwAusmTYwRZrXj1Xk3 qTF0c0WOmFh X-QQ-XMRINFO: OWPUhxQsoeAVwkVaQIEGSKwwgKCxK/fD5g== X-QQ-RECHKSPAM: 0 Add register ranges for the SC8280XP interconnect providers so the driver can program the NoC QoS registers. Move the real NoC providers under soc@0, keep clk_virt and mc_virt as virtual top-level providers, and add the clocks required for QoS programming on aggre1_noc and aggre2_noc. Signed-off-by: Xilin Wu Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 157 ++++++++++++++++++++---------= ---- 1 file changed, 97 insertions(+), 60 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 761f229e8f47..8e64db07a9e9 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -314,78 +314,18 @@ scm: scm { }; }; =20 - aggre1_noc: interconnect-aggre1-noc { - compatible =3D "qcom,sc8280xp-aggre1-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - aggre2_noc: interconnect-aggre2-noc { - compatible =3D "qcom,sc8280xp-aggre2-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - clk_virt: interconnect-clk-virt { compatible =3D "qcom,sc8280xp-clk-virt"; #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 - config_noc: interconnect-config-noc { - compatible =3D "qcom,sc8280xp-config-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - dc_noc: interconnect-dc-noc { - compatible =3D "qcom,sc8280xp-dc-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - gem_noc: interconnect-gem-noc { - compatible =3D "qcom,sc8280xp-gem-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - lpass_noc: interconnect-lpass-ag-noc { - compatible =3D "qcom,sc8280xp-lpass-ag-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - mc_virt: interconnect-mc-virt { compatible =3D "qcom,sc8280xp-mc-virt"; #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 - mmss_noc: interconnect-mmss-noc { - compatible =3D "qcom,sc8280xp-mmss-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - nspa_noc: interconnect-nspa-noc { - compatible =3D "qcom,sc8280xp-nspa-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - nspb_noc: interconnect-nspb-noc { - compatible =3D "qcom,sc8280xp-nspb-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - system_noc: interconnect-system-noc { - compatible =3D "qcom,sc8280xp-system-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - memory@80000000 { device_type =3D "memory"; /* We expect the bootloader to fill in the size */ @@ -2152,6 +2092,63 @@ rng: rng@10d3000 { clock-names =3D "core"; }; =20 + config_noc: interconnect@1500000 { + compatible =3D "qcom,sc8280xp-config-noc"; + reg =3D <0 0x01500000 0 0x2c000>; + + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + compatible =3D "qcom,sc8280xp-system-noc"; + reg =3D <0 0x01680000 0 0x1a400>; + + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16c0000 { + compatible =3D "qcom,sc8280xp-aggre1-noc"; + reg =3D <0 0x016c0000 0 0x3af80>; + + clocks =3D <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_1_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; + + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible =3D "qcom,sc8280xp-aggre2-noc"; + reg =3D <0 0x01700000 0 0x3af80>; + + clocks =3D <&gcc GCC_AGGRE_NOC_PCIE0_TUNNEL_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE1_TUNNEL_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; + + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + compatible =3D "qcom,sc8280xp-mmss-noc"; + reg =3D <0 0x01740000 0 0x1fa80>; + + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + pcie4: pcie@1c00000 { device_type =3D "pci"; compatible =3D "qcom,pcie-sc8280xp"; @@ -3352,6 +3349,14 @@ lpasscc: clock-controller@33e0000 { #reset-cells =3D <1>; }; =20 + lpass_noc: interconnect@3c40000 { + compatible =3D "qcom,sc8280xp-lpass-ag-noc"; + reg =3D <0 0x03c40000 0 0xf080>; + + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + gpu: gpu@3d00000 { compatible =3D "qcom,adreno-690.0", "qcom,adreno"; =20 @@ -3927,6 +3932,22 @@ opp-6 { }; }; =20 + dc_noc: interconnect@90e0000 { + compatible =3D "qcom,sc8280xp-dc-noc"; + reg =3D <0 0x090e0000 0 0x5080>; + + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + gem_noc: interconnect@9100000 { + compatible =3D "qcom,sc8280xp-gem-noc"; + reg =3D <0 0x09100000 0 0xb8400>; + + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + system-cache-controller@9200000 { compatible =3D "qcom,sc8280xp-llcc"; reg =3D <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, @@ -5977,6 +5998,14 @@ cpufreq_hw: cpufreq@18591000 { #clock-cells =3D <1>; }; =20 + nspa_noc: interconnect@1b0c0000 { + compatible =3D "qcom,sc8280xp-nspa-noc"; + reg =3D <0 0x1b0c0000 0 0x10000>; + + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + remoteproc_nsp0: remoteproc@1b300000 { compatible =3D "qcom,sc8280xp-nsp0-pas"; reg =3D <0 0x1b300000 0 0x10000>; @@ -6112,6 +6141,14 @@ compute-cb@14 { }; }; =20 + nspb_noc: interconnect@210c0000 { + compatible =3D "qcom,sc8280xp-nspb-noc"; + reg =3D <0 0x210c0000 0 0x10000>; + + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + remoteproc_nsp1: remoteproc@21300000 { compatible =3D "qcom,sc8280xp-nsp1-pas"; reg =3D <0 0x21300000 0 0x10000>; --=20 2.54.0