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[79.50.55.97]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48e53891d62sm209994895e9.1.2026.05.07.08.43.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 May 2026 08:43:54 -0700 (PDT) From: Anna Maniscalco Date: Thu, 07 May 2026 17:43:15 +0200 Subject: [PATCH v3] iommu: arm-smmu-qcom: Ensure smmu is powered up in set_ttbr0_cfg Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260507-qcom_smmu_pmfix-v3-1-af8cd05831a2@gmail.com> X-B4-Tracking: v=1; b=H4sIAAAAAAAC/3WNzQrCMBAGX6XkbCTZ9Ec9+R4iZdOubcA0NdGgl L67aS8K4nE+dmYnFsgbCuyQTcxTNMG4IYHaZKzpceiImzYxAwGlACn4rXG2DtY+6tFezJMDEra gMScQLFmjpzSvxdM5cW/C3fnX+iDKZf3fipJLXu10JXOFjSjUsbNortt0xpZWhI+voPj1Ifkaq 3KPJbZC07c/z/Mb6SbGKO4AAAA= X-Change-ID: 20260210-qcom_smmu_pmfix-2aead2ba4e20 To: Rob Clark , Will Deacon , Robin Murphy , Joerg Roedel Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Anna Maniscalco , Rob Clark X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1778168633; l=2650; i=anna.maniscalco2000@gmail.com; s=20240815; h=from:subject:message-id; bh=JvTfGtQt/QzZHDNLS/mKUWRZZK3nInAjvOmIg4zwlgw=; b=78r+QvfiiQHi317bGaK1Vp3B2bi2od5HUfeBqAj9XVv3eh8gwkCyaKS+hC7krNXwwLSK/Ustd uBpdiT/GZqBDZ8rCiOrpauIwtCS2Vf4qswB9VZB1iXJHovt55TZVPwy X-Developer-Key: i=anna.maniscalco2000@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= arm_smmu_write_context_bank() assumes it is being called with RPM active, but it turns out that is not guaranteed in the path from qcom_adreno_smmu_set_ttbr0_cfg(), so it's possible for the register writes to get lost when configuring the context bank while the GPU is idle, leading to page faults later. Add the RPM calls here to make sure the SMMU is active before we touch it. Signed-off-by: Anna Maniscalco Reviewed-by: Rob Clark Reviewed-by: Robin Murphy --- Changes in v3: - Changed commit message to be more self-contained as suggested. - Collected RBs - Link to v2: https://lore.kernel.org/r/20260325-qcom_smmu_pmfix-v2-1-ba769= a6ad0be@gmail.com Changes in v2: - Simplify patch by acquiring device just around the call that needs it - Link to v1: https://lore.kernel.org/r/20260210-qcom_smmu_pmfix-v1-1-78b71= 43ac053@gmail.com To: Rob Clark To: Will Deacon To: Robin Murphy To: Joerg Roedel Cc: iommu@lists.linux.dev Cc: linux-arm-msm@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.c index 573085349df3..cab7d110aaf5 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -231,6 +231,7 @@ static int qcom_adreno_smmu_set_ttbr0_cfg(const void *c= ookie, struct io_pgtable *pgtable =3D io_pgtable_ops_to_pgtable(smmu_domain->pgt= bl_ops); struct arm_smmu_cfg *cfg =3D &smmu_domain->cfg; struct arm_smmu_cb *cb =3D &smmu_domain->smmu->cbs[cfg->cbndx]; + int ret; =20 /* The domain must have split pagetables already enabled */ if (cb->tcr[0] & ARM_SMMU_TCR_EPD1) @@ -260,8 +261,16 @@ static int qcom_adreno_smmu_set_ttbr0_cfg(const void *= cookie, cb->ttbr[0] |=3D FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); } =20 + ret =3D pm_runtime_resume_and_get(smmu_domain->smmu->dev); + if (ret < 0) { + dev_err(smmu_domain->smmu->dev, "failed to get runtime PM: %d\n", ret); + return -ENODEV; + } + arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx); =20 + pm_runtime_put_autosuspend(smmu_domain->smmu->dev); + return 0; } =20 --- base-commit: 50c4a49f7292b33b454ea1a16c4f77d6965405dc change-id: 20260210-qcom_smmu_pmfix-2aead2ba4e20 Best regards, -- =20 Anna Maniscalco