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Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kathiravan Thirumoorthy --- .../bindings/clock/qcom,ipq9650-gcc.yaml | 68 +++++++ include/dt-bindings/clock/qcom,ipq9650-gcc.h | 172 +++++++++++++++++ include/dt-bindings/reset/qcom,ipq9650-gcc.h | 215 +++++++++++++++++= ++++ 3 files changed, 455 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9650-gcc.yaml = b/Documentation/devicetree/bindings/clock/qcom,ipq9650-gcc.yaml new file mode 100644 index 000000000000..f33105217a06 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9650-gcc.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq9650-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on IPQ9650 + +maintainers: + - Bjorn Andersson + - Kathiravan Thirumoorthy + +description: | + Qualcomm global clock control module provides the clocks, resets and pow= er + domains on IPQ9650 + + See also: + include/dt-bindings/clock/qcom,ipq9650-gcc.h + include/dt-bindings/reset/qcom,ipq9650-gcc.h + +properties: + compatible: + const: qcom,ipq9650-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE30 PHY0 pipe clock source + - description: PCIE30 PHY1 pipe clock source + - description: PCIE30 PHY2 pipe clock source + - description: PCIE30 PHY3 pipe clock source + - description: PCIE30 PHY4 pipe clock source + - description: USB PCIE wrapper pipe clock source + - description: NSS common clock source + + '#power-domain-cells': false + + '#interconnect-cells': + const: 1 + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + clock-controller@1800000 { + compatible =3D "qcom,ipq9650-gcc"; + reg =3D <0x01800000 0x40000>; + clocks =3D <&xo_board_clk>, + <&sleep_clk>, + <&pcie30_phy0_pipe_clk>, + <&pcie30_phy1_pipe_clk>, + <&pcie30_phy2_pipe_clk>, + <&pcie30_phy3_pipe_clk>, + <&pcie30_phy4_pipe_clk>, + <&usb3phy_0_cc_pipe_clk>, + <&nss_cmn_clk>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,ipq9650-gcc.h b/include/dt-bind= ings/clock/qcom,ipq9650-gcc.h new file mode 100644 index 000000000000..afd17c00d96e --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq9650-gcc.h @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ9650_H +#define _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ9650_H + +#define GCC_ADSS_PWM_CLK 0 +#define GCC_ADSS_PWM_CLK_SRC 1 +#define GCC_ANOC_PCIE0_1LANE_M_CLK 2 +#define GCC_ANOC_PCIE0_1LANE_S_CLK 3 +#define GCC_ANOC_PCIE1_2LANE_M_CLK 4 +#define GCC_ANOC_PCIE1_2LANE_S_CLK 5 +#define GCC_ANOC_PCIE2_2LANE_M_CLK 6 +#define GCC_ANOC_PCIE2_2LANE_S_CLK 7 +#define GCC_ANOC_PCIE3_2LANE_M_CLK 8 +#define GCC_ANOC_PCIE3_2LANE_S_CLK 9 +#define GCC_ANOC_PCIE4_1LANE_M_CLK 10 +#define GCC_ANOC_PCIE4_1LANE_S_CLK 11 +#define GCC_CMN_12GPLL_AHB_CLK 12 +#define GCC_CMN_12GPLL_APU_CLK 13 +#define GCC_CMN_12GPLL_SYS_CLK 14 +#define GCC_CMN_LDO_CLK 15 +#define GCC_MDIO_AHB_CLK 16 +#define GCC_NSSCC_CLK 17 +#define GCC_NSSCFG_CLK 18 +#define GCC_NSSNOC_ATB_CLK 19 +#define GCC_NSSNOC_MEMNOC_1_CLK 20 +#define GCC_NSSNOC_MEMNOC_BFDCD_CLK_SRC 21 +#define GCC_NSSNOC_MEMNOC_CLK 22 +#define GCC_NSSNOC_MEMNOC_DIV_CLK_SRC 23 +#define GCC_NSSNOC_NSSCC_CLK 24 +#define GCC_NSSNOC_PCNOC_1_CLK 25 +#define GCC_NSSNOC_QOSGEN_REF_CLK 26 +#define GCC_NSSNOC_SNOC_1_CLK 27 +#define GCC_NSSNOC_SNOC_CLK 28 +#define GCC_NSSNOC_TIMEOUT_REF_CLK 29 +#define GCC_NSSNOC_XO_DCD_CLK 30 +#define GCC_NSS_TS_CLK 31 +#define GCC_NSS_TS_CLK_SRC 32 +#define GCC_PCIE0_AHB_CLK 33 +#define GCC_PCIE0_AUX_CLK 34 +#define GCC_PCIE0_AXI_M_CLK 35 +#define GCC_PCIE0_AXI_M_CLK_SRC 36 +#define GCC_PCIE0_AXI_S_BRIDGE_CLK 37 +#define GCC_PCIE0_AXI_S_CLK 38 +#define GCC_PCIE0_AXI_S_CLK_SRC 39 +#define GCC_PCIE0_PIPE_CLK 40 +#define GCC_PCIE0_PIPE_CLK_SRC 41 +#define GCC_PCIE0_RCHNG_CLK 42 +#define GCC_PCIE0_RCHNG_CLK_SRC 43 +#define GCC_PCIE1_AHB_CLK 44 +#define GCC_PCIE1_AUX_CLK 45 +#define GCC_PCIE1_AXI_M_CLK 46 +#define GCC_PCIE1_AXI_M_CLK_SRC 47 +#define GCC_PCIE1_AXI_S_BRIDGE_CLK 48 +#define GCC_PCIE1_AXI_S_CLK 49 +#define GCC_PCIE1_AXI_S_CLK_SRC 50 +#define GCC_PCIE1_PIPE_CLK 51 +#define GCC_PCIE1_PIPE_CLK_SRC 52 +#define GCC_PCIE1_RCHNG_CLK 53 +#define GCC_PCIE1_RCHNG_CLK_SRC 54 +#define GCC_PCIE2_AHB_CLK 55 +#define GCC_PCIE2_AUX_CLK 56 +#define GCC_PCIE2_AXI_M_CLK 57 +#define GCC_PCIE2_AXI_M_CLK_SRC 58 +#define GCC_PCIE2_AXI_S_BRIDGE_CLK 59 +#define GCC_PCIE2_AXI_S_CLK 60 +#define GCC_PCIE2_AXI_S_CLK_SRC 61 +#define GCC_PCIE2_PIPE_CLK 62 +#define GCC_PCIE2_PIPE_CLK_SRC 63 +#define GCC_PCIE2_RCHNG_CLK 64 +#define GCC_PCIE2_RCHNG_CLK_SRC 65 +#define GCC_PCIE3_AHB_CLK 66 +#define GCC_PCIE3_AUX_CLK 67 +#define GCC_PCIE3_AXI_M_CLK 68 +#define GCC_PCIE3_AXI_M_CLK_SRC 69 +#define GCC_PCIE3_AXI_S_BRIDGE_CLK 70 +#define GCC_PCIE3_AXI_S_CLK 71 +#define GCC_PCIE3_AXI_S_CLK_SRC 72 +#define GCC_PCIE3_PIPE_CLK 73 +#define GCC_PCIE3_PIPE_CLK_SRC 74 +#define GCC_PCIE3_RCHNG_CLK 75 +#define GCC_PCIE3_RCHNG_CLK_SRC 76 +#define GCC_PCIE4_AHB_CLK 77 +#define GCC_PCIE4_AUX_CLK 78 +#define GCC_PCIE4_AXI_M_CLK 79 +#define GCC_PCIE4_AXI_M_CLK_SRC 80 +#define GCC_PCIE4_AXI_S_BRIDGE_CLK 81 +#define GCC_PCIE4_AXI_S_CLK 82 +#define GCC_PCIE4_AXI_S_CLK_SRC 83 +#define GCC_PCIE4_PIPE_CLK 84 +#define GCC_PCIE4_PIPE_CLK_SRC 85 +#define GCC_PCIE4_RCHNG_CLK 86 +#define GCC_PCIE4_RCHNG_CLK_SRC 87 +#define GCC_PCIE_AUX_CLK_SRC 88 +#define GCC_PCNOC_BFDCD_CLK_SRC 89 +#define GCC_QDSS_AT_CLK 90 +#define GCC_QDSS_AT_CLK_SRC 91 +#define GCC_QDSS_DAP_CLK 92 +#define GCC_QDSS_TSCTR_CLK_SRC 93 +#define GCC_QPIC_AHB_CLK 94 +#define GCC_QPIC_CLK 95 +#define GCC_QPIC_CLK_SRC 96 +#define GCC_QPIC_IO_MACRO_CLK 97 +#define GCC_QPIC_IO_MACRO_CLK_SRC 98 +#define GCC_QPIC_SLEEP_CLK 99 +#define GCC_QUPV3_2X_CORE_CLK 100 +#define GCC_QUPV3_2X_CORE_CLK_SRC 101 +#define GCC_QUPV3_AHB_MST_CLK 102 +#define GCC_QUPV3_AHB_SLV_CLK 103 +#define GCC_QUPV3_CORE_CLK 104 +#define GCC_QUPV3_SLEEP_CLK 105 +#define GCC_QUPV3_WRAP_SE0_CLK 106 +#define GCC_QUPV3_WRAP_SE0_CLK_SRC 107 +#define GCC_QUPV3_WRAP_SE1_CLK 108 +#define GCC_QUPV3_WRAP_SE1_CLK_SRC 109 +#define GCC_QUPV3_WRAP_SE2_CLK 110 +#define GCC_QUPV3_WRAP_SE2_CLK_SRC 111 +#define GCC_QUPV3_WRAP_SE3_CLK 112 +#define GCC_QUPV3_WRAP_SE3_CLK_SRC 113 +#define GCC_QUPV3_WRAP_SE4_CLK 114 +#define GCC_QUPV3_WRAP_SE4_CLK_SRC 115 +#define GCC_QUPV3_WRAP_SE5_CLK 116 +#define GCC_QUPV3_WRAP_SE5_CLK_SRC 117 +#define GCC_QUPV3_WRAP_SE6_CLK 118 +#define GCC_QUPV3_WRAP_SE6_CLK_SRC 119 +#define GCC_QUPV3_WRAP_SE7_CLK 120 +#define GCC_QUPV3_WRAP_SE7_CLK_SRC 121 +#define GCC_SDCC1_AHB_CLK 122 +#define GCC_SDCC1_APPS_CLK 123 +#define GCC_SDCC1_APPS_CLK_SRC 124 +#define GCC_SDCC1_ICE_CORE_CLK 125 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 126 +#define GCC_SLEEP_CLK_SRC 127 +#define GCC_SNOC_USB_CLK 128 +#define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 129 +#define GCC_TLMM_AHB_CLK 130 +#define GCC_TLMM_CLK 131 +#define GCC_UNIPHY0_AHB_CLK 132 +#define GCC_UNIPHY0_SYS_CLK 133 +#define GCC_UNIPHY1_AHB_CLK 134 +#define GCC_UNIPHY1_SYS_CLK 135 +#define GCC_UNIPHY2_AHB_CLK 136 +#define GCC_UNIPHY2_SYS_CLK 137 +#define GCC_UNIPHY_SYS_CLK_SRC 138 +#define GCC_USB0_AUX_CLK 139 +#define GCC_USB0_AUX_CLK_SRC 140 +#define GCC_USB0_EUD_AT_CLK 141 +#define GCC_USB0_MASTER_CLK 142 +#define GCC_USB0_MASTER_CLK_SRC 143 +#define GCC_USB0_MOCK_UTMI_CLK 144 +#define GCC_USB0_MOCK_UTMI_CLK_SRC 145 +#define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 146 +#define GCC_USB0_PHY_CFG_AHB_CLK 147 +#define GCC_USB0_PIPE_CLK 148 +#define GCC_USB0_PIPE_CLK_SRC 149 +#define GCC_USB0_SLEEP_CLK 150 +#define GCC_USB1_MASTER_CLK 151 +#define GCC_USB1_MOCK_UTMI_CLK 152 +#define GCC_USB1_MOCK_UTMI_CLK_SRC 153 +#define GCC_USB1_MOCK_UTMI_DIV_CLK_SRC 154 +#define GCC_USB1_PHY_CFG_AHB_CLK 155 +#define GCC_USB1_SLEEP_CLK 156 +#define GCC_XO_CLK_SRC 157 +#define GPLL0 158 +#define GPLL0_MAIN 159 +#define GPLL2 160 +#define GPLL2_OUT_MAIN 161 +#define GPLL4 162 +#endif diff --git a/include/dt-bindings/reset/qcom,ipq9650-gcc.h b/include/dt-bind= ings/reset/qcom,ipq9650-gcc.h new file mode 100644 index 000000000000..a2cbb114addd --- /dev/null +++ b/include/dt-bindings/reset/qcom,ipq9650-gcc.h @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_RESET_IPQ_GCC_IPQ9650_H +#define _DT_BINDINGS_RESET_IPQ_GCC_IPQ9650_H + +#define GCC_ADSS_BCR 0 +#define GCC_ADSS_PWM_CLK_ARES 1 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 2 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES 3 +#define GCC_APSS_AHB_CLK_ARES 4 +#define GCC_APSS_ATB_CLK_ARES 5 +#define GCC_APSS_AXI_CLK_ARES 6 +#define GCC_APSS_TS_CLK_ARES 7 +#define GCC_BOOT_ROM_AHB_CLK_ARES 8 +#define GCC_BOOT_ROM_BCR 9 +#define GCC_CMN_12GPLL_AHB_CLK_ARES 10 +#define GCC_CMN_12GPLL_APU_CLK_ARES 11 +#define GCC_CMN_12GPLL_SYS_CLK_ARES 12 +#define GCC_CMN_BLK_BCR 13 +#define GCC_CMN_LDO_CLK_ARES 14 +#define GCC_CPUSS_TRIG_CLK_ARES 15 +#define GCC_GP1_CLK_ARES 16 +#define GCC_GP2_CLK_ARES 17 +#define GCC_GP3_CLK_ARES 18 +#define GCC_MDIO_AHB_CLK_ARES 19 +#define GCC_MDIO_BCR 20 +#define GCC_NSSCC_CLK_ARES 21 +#define GCC_NSSCFG_CLK_ARES 22 +#define GCC_NSSNOC_ATB_CLK_ARES 23 +#define GCC_NSSNOC_MEMNOC_1_CLK_ARES 24 +#define GCC_NSSNOC_MEMNOC_CLK_ARES 25 +#define GCC_NSSNOC_NSSCC_CLK_ARES 26 +#define GCC_NSSNOC_PCNOC_1_CLK_ARES 27 +#define GCC_NSSNOC_QOSGEN_REF_CLK_ARES 28 +#define GCC_NSSNOC_SNOC_1_CLK_ARES 29 +#define GCC_NSSNOC_SNOC_CLK_ARES 30 +#define GCC_NSSNOC_TIMEOUT_REF_CLK_ARES 31 +#define GCC_NSSNOC_XO_DCD_CLK_ARES 32 +#define GCC_NSS_BCR 33 +#define GCC_NSS_TS_CLK_ARES 34 +#define GCC_PCIE0PHY_PHY_BCR 35 +#define GCC_PCIE0_AHB_CLK_ARES 36 +#define GCC_PCIE0_AHB_RESET 37 +#define GCC_PCIE0_AUX_CLK_ARES 38 +#define GCC_PCIE0_AUX_RESET 39 +#define GCC_PCIE0_AXI_M_CLK_ARES 40 +#define GCC_PCIE0_AXI_M_RESET 41 +#define GCC_PCIE0_AXI_M_STICKY_RESET 42 +#define GCC_PCIE0_AXI_S_BRIDGE_CLK_ARES 43 +#define GCC_PCIE0_AXI_S_CLK_ARES 44 +#define GCC_PCIE0_AXI_S_RESET 45 +#define GCC_PCIE0_AXI_S_STICKY_RESET 46 +#define GCC_PCIE0_BCR 47 +#define GCC_PCIE0_CORE_STICKY_RESET 48 +#define GCC_PCIE0_LINK_DOWN_BCR 49 +#define GCC_PCIE0_PHY_BCR 50 +#define GCC_PCIE0_PIPE_CLK_ARES 51 +#define GCC_PCIE0_PIPE_RESET 52 +#define GCC_PCIE1PHY_PHY_BCR 53 +#define GCC_PCIE1_AHB_CLK_ARES 54 +#define GCC_PCIE1_AHB_RESET 55 +#define GCC_PCIE1_AUX_CLK_ARES 56 +#define GCC_PCIE1_AUX_RESET 57 +#define GCC_PCIE1_AXI_M_CLK_ARES 58 +#define GCC_PCIE1_AXI_M_RESET 59 +#define GCC_PCIE1_AXI_M_STICKY_RESET 60 +#define GCC_PCIE1_AXI_S_BRIDGE_CLK_ARES 61 +#define GCC_PCIE1_AXI_S_CLK_ARES 62 +#define GCC_PCIE1_AXI_S_RESET 63 +#define GCC_PCIE1_AXI_S_STICKY_RESET 64 +#define GCC_PCIE1_BCR 65 +#define GCC_PCIE1_CORE_STICKY_RESET 66 +#define GCC_PCIE1_LINK_DOWN_BCR 67 +#define GCC_PCIE1_PHY_BCR 68 +#define GCC_PCIE1_PIPE_CLK_ARES 69 +#define GCC_PCIE1_PIPE_RESET 70 +#define GCC_PCIE2PHY_PHY_BCR 71 +#define GCC_PCIE2_AHB_CLK_ARES 72 +#define GCC_PCIE2_AHB_RESET 73 +#define GCC_PCIE2_AUX_CLK_ARES 74 +#define GCC_PCIE2_AUX_RESET 75 +#define GCC_PCIE2_AXI_M_CLK_ARES 76 +#define GCC_PCIE2_AXI_M_RESET 77 +#define GCC_PCIE2_AXI_M_STICKY_RESET 78 +#define GCC_PCIE2_AXI_S_BRIDGE_CLK_ARES 79 +#define GCC_PCIE2_AXI_S_CLK_ARES 80 +#define GCC_PCIE2_AXI_S_RESET 81 +#define GCC_PCIE2_AXI_S_STICKY_RESET 82 +#define GCC_PCIE2_BCR 83 +#define GCC_PCIE2_CORE_STICKY_RESET 84 +#define GCC_PCIE2_LINK_DOWN_BCR 85 +#define GCC_PCIE2_PHY_BCR 86 +#define GCC_PCIE2_PIPE_CLK_ARES 87 +#define GCC_PCIE2_PIPE_RESET 88 +#define GCC_PCIE3PHY_PHY_BCR 89 +#define GCC_PCIE3_AHB_CLK_ARES 90 +#define GCC_PCIE3_AHB_RESET 91 +#define GCC_PCIE3_AUX_CLK_ARES 92 +#define GCC_PCIE3_AUX_RESET 93 +#define GCC_PCIE3_AXI_M_CLK_ARES 94 +#define GCC_PCIE3_AXI_M_RESET 95 +#define GCC_PCIE3_AXI_M_STICKY_RESET 96 +#define GCC_PCIE3_AXI_S_BRIDGE_CLK_ARES 97 +#define GCC_PCIE3_AXI_S_CLK_ARES 98 +#define GCC_PCIE3_AXI_S_RESET 99 +#define GCC_PCIE3_AXI_S_STICKY_RESET 100 +#define GCC_PCIE3_BCR 101 +#define GCC_PCIE3_CORE_STICKY_RESET 102 +#define GCC_PCIE3_LINK_DOWN_BCR 103 +#define GCC_PCIE3_PHY_BCR 104 +#define GCC_PCIE3_PIPE_CLK_ARES 105 +#define GCC_PCIE3_PIPE_RESET 106 +#define GCC_PCIE4PHY_PHY_BCR 107 +#define GCC_PCIE4_AHB_CLK_ARES 108 +#define GCC_PCIE4_AHB_RESET 109 +#define GCC_PCIE4_AUX_CLK_ARES 110 +#define GCC_PCIE4_AUX_RESET 111 +#define GCC_PCIE4_AXI_M_CLK_ARES 112 +#define GCC_PCIE4_AXI_M_RESET 113 +#define GCC_PCIE4_AXI_M_STICKY_RESET 114 +#define GCC_PCIE4_AXI_S_BRIDGE_CLK_ARES 115 +#define GCC_PCIE4_AXI_S_CLK_ARES 116 +#define GCC_PCIE4_AXI_S_RESET 117 +#define GCC_PCIE4_AXI_S_STICKY_RESET 118 +#define GCC_PCIE4_BCR 119 +#define GCC_PCIE4_CORE_STICKY_RESET 120 +#define GCC_PCIE4_LINK_DOWN_BCR 121 +#define GCC_PCIE4_PHY_BCR 122 +#define GCC_PCIE4_PIPE_CLK_ARES 123 +#define GCC_PCIE4_PIPE_RESET 124 +#define GCC_QDSS_APB2JTAG_CLK_ARES 125 +#define GCC_QDSS_AT_CLK_ARES 126 +#define GCC_QDSS_BCR 127 +#define GCC_QDSS_CFG_AHB_CLK_ARES 128 +#define GCC_QDSS_DAP_AHB_CLK_ARES 129 +#define GCC_QDSS_DAP_CLK_ARES 130 +#define GCC_QDSS_ETR_USB_CLK_ARES 131 +#define GCC_QDSS_EUD_AT_CLK_ARES 132 +#define GCC_QDSS_STM_CLK_ARES 133 +#define GCC_QDSS_TRACECLKIN_CLK_ARES 134 +#define GCC_QDSS_TSCTR_DIV16_CLK_ARES 135 +#define GCC_QDSS_TSCTR_DIV2_CLK_ARES 136 +#define GCC_QDSS_TSCTR_DIV3_CLK_ARES 137 +#define GCC_QDSS_TSCTR_DIV4_CLK_ARES 138 +#define GCC_QDSS_TSCTR_DIV8_CLK_ARES 139 +#define GCC_QDSS_TS_CLK_ARES 140 +#define GCC_QPIC_AHB_CLK_ARES 141 +#define GCC_QPIC_BCR 142 +#define GCC_QPIC_CLK_ARES 143 +#define GCC_QPIC_IO_MACRO_CLK_ARES 144 +#define GCC_QPIC_SLEEP_CLK_ARES 145 +#define GCC_QUPV3_2X_CORE_CLK_ARES 146 +#define GCC_QUPV3_AHB_MST_CLK_ARES 147 +#define GCC_QUPV3_AHB_SLV_CLK_ARES 148 +#define GCC_QUPV3_BCR 149 +#define GCC_QUPV3_CORE_CLK_ARES 150 +#define GCC_QUPV3_WRAP_SE0_BCR 151 +#define GCC_QUPV3_WRAP_SE0_CLK_ARES 152 +#define GCC_QUPV3_WRAP_SE1_BCR 153 +#define GCC_QUPV3_WRAP_SE1_CLK_ARES 154 +#define GCC_QUPV3_WRAP_SE2_BCR 155 +#define GCC_QUPV3_WRAP_SE2_CLK_ARES 156 +#define GCC_QUPV3_WRAP_SE3_BCR 157 +#define GCC_QUPV3_WRAP_SE3_CLK_ARES 158 +#define GCC_QUPV3_WRAP_SE4_BCR 159 +#define GCC_QUPV3_WRAP_SE4_CLK_ARES 160 +#define GCC_QUPV3_WRAP_SE5_BCR 161 +#define GCC_QUPV3_WRAP_SE5_CLK_ARES 162 +#define GCC_QUPV3_WRAP_SE6_BCR 163 +#define GCC_QUPV3_WRAP_SE6_CLK_ARES 164 +#define GCC_QUPV3_WRAP_SE7_BCR 165 +#define GCC_QUPV3_WRAP_SE7_CLK_ARES 166 +#define GCC_QUSB2_0_PHY_BCR 167 +#define GCC_QUSB2_1_PHY_BCR 168 +#define GCC_SDCC1_APPS_CLK_ARES 169 +#define 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Signed-off-by: Kathiravan Thirumoorthy --- drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-ipq9650.c | 3445 ++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 3456 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index df21ef5ffd68..9573e88d1f25 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -434,6 +434,16 @@ config IPQ_GCC_9574 i2c, USB, SD/eMMC, etc. Select this for the root clock of ipq9574. =20 +config IPQ_GCC_9650 + tristate "IPQ9650 Global Clock Controller" + depends on ARM64 || COMPILE_TEST + default ARCH_QCOM + help + Support for global clock controller on ipq9650 devices. + Say Y if you want to use peripheral devices such as UART, SPI, + i2c, USB, SD/eMMC, etc. Select this for the root clock + of ipq9650. + config IPQ_NSSCC_5424 tristate "IPQ5424 NSS Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 89d07c35e4d9..ca04117371cf 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -57,6 +57,7 @@ obj-$(CONFIG_IPQ_GCC_6018) +=3D gcc-ipq6018.o obj-$(CONFIG_IPQ_GCC_806X) +=3D gcc-ipq806x.o obj-$(CONFIG_IPQ_GCC_8074) +=3D gcc-ipq8074.o obj-$(CONFIG_IPQ_GCC_9574) +=3D gcc-ipq9574.o +obj-$(CONFIG_IPQ_GCC_9650) +=3D gcc-ipq9650.o obj-$(CONFIG_IPQ_NSSCC_5424) +=3D nsscc-ipq5424.o obj-$(CONFIG_IPQ_NSSCC_9574) +=3D nsscc-ipq9574.o obj-$(CONFIG_IPQ_LCC_806X) +=3D lcc-ipq806x.o diff --git a/drivers/clk/qcom/gcc-ipq9650.c b/drivers/clk/qcom/gcc-ipq9650.c new file mode 100644 index 000000000000..c556c2bbfd96 --- /dev/null +++ b/drivers/clk/qcom/gcc-ipq9650.c @@ -0,0 +1,3445 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include + +#include +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "reset.h" + +enum { + DT_XO, + DT_SLEEP_CLK, + DT_PCIE30_PHY0_PIPE_CLK, + DT_PCIE30_PHY1_PIPE_CLK, + DT_PCIE30_PHY2_PIPE_CLK, + DT_PCIE30_PHY3_PIPE_CLK, + DT_PCIE30_PHY4_PIPE_CLK, + DT_USB3_PHY0_CC_PIPE_CLK, + DT_NSS_CMN_CLK, +}; + +enum { + P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_ODD, + P_GPLL2_OUT_AUX, + P_GPLL2_OUT_MAIN, + P_GPLL4_OUT_MAIN, + P_GPLL4_OUT_ODD, + P_NSS_CMN_CLK, + P_SLEEP_CLK, + P_XO, +}; + +static const struct clk_parent_data gcc_parent_data_xo =3D { .index =3D DT= _XO }; + +static struct clk_alpha_pll gpll0_main =3D { + .offset =3D 0x20000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr =3D { + .enable_reg =3D 0xb000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll0_main", + .parent_data =3D &gcc_parent_data_xo, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ops, + }, + }, +}; + +static struct clk_fixed_factor gpll0_div2 =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll0_div2", + .parent_hws =3D (const struct clk_hw *[]) { + &gpll0_main.clkr.hw + }, + .num_parents =3D 1, + .ops =3D &clk_fixed_factor_ops, + }, +}; + +static struct clk_alpha_pll_postdiv gpll0 =3D { + .offset =3D 0x20000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll0", + .parent_hws =3D (const struct clk_hw *[]) { + &gpll0_main.clkr.hw }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_ro_ops, + }, +}; + +static struct clk_alpha_pll gpll2 =3D { + .offset =3D 0x21000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], + .clkr =3D { + .enable_reg =3D 0xb000, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll2", + .parent_data =3D &gcc_parent_data_xo, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_zonda_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpll2_out_main[] =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpll2_out_main =3D { + .offset =3D 0x21000, + .post_div_shift =3D 8, + .post_div_table =3D post_div_table_gpll2_out_main, + .num_post_div =3D ARRAY_SIZE(post_div_table_gpll2_out_main), + .width =3D 2, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll2_out_main", + .parent_hws =3D (const struct clk_hw*[]) { + &gpll2.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_zonda_ops, + }, +}; + +static struct clk_alpha_pll gpll4 =3D { + .offset =3D 0x22000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr =3D { + .enable_reg =3D 0xb000, + .enable_mask =3D BIT(2), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll4", + .parent_data =3D &gcc_parent_data_xo, + .num_parents =3D 1, + /* + * There are no consumers for this GPLL in kernel yet, + * (will be added soon), so the clock framework + * disables this source. But some of the clocks + * initialized by boot loaders uses this source. So we + * need to keep this clock ON. Add the + * CLK_IGNORE_UNUSED flag so the clock will not be + * disabled. Once the consumer in kernel is added, we + * can get rid of this flag. + */ + .flags =3D CLK_IS_CRITICAL, + .ops =3D &clk_alpha_pll_fixed_lucid_ops, + }, + }, +}; + +static const struct parent_map gcc_parent_map_xo[] =3D { + { P_XO, 0 }, +}; + +static const struct parent_map gcc_parent_map_0[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, +}; + +static const struct clk_parent_data gcc_parent_data_0[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0_div2.hw }, +}; + +static const struct parent_map gcc_parent_map_1[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL4_OUT_MAIN, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_1[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll4.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_2[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data gcc_parent_data_2[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_3[] =3D { + { P_XO, 0 }, +}; + +static const struct clk_parent_data gcc_parent_data_3[] =3D { + { .index =3D DT_XO }, +}; + +static const struct parent_map gcc_parent_map_4[] =3D { + { P_XO, 0 }, + { P_GPLL4_OUT_MAIN, 1 }, + { P_GPLL0_OUT_ODD, 2 }, + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, +}; + +static const struct clk_parent_data gcc_parent_data_4[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll4.clkr.hw }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0_div2.hw }, +}; + +static const struct parent_map gcc_parent_map_5[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL2_OUT_AUX, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_5[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll2.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_6[] =3D { + { P_XO, 0 }, + { P_GPLL4_OUT_ODD, 1 }, + { P_GPLL0_OUT_MAIN, 3 }, + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, +}; + +static const struct clk_parent_data gcc_parent_data_6[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll4.clkr.hw }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0_div2.hw }, +}; + +static const struct parent_map gcc_parent_map_7[] =3D { + { P_XO, 0 }, + { P_NSS_CMN_CLK, 1 }, + { P_GPLL0_OUT_ODD, 2 }, + { P_GPLL2_OUT_AUX, 3 }, +}; + +static const struct clk_parent_data gcc_parent_data_7[] =3D { + { .index =3D DT_XO }, + { .index =3D DT_NSS_CMN_CLK }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll2.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_8[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_ODD, 2 }, + { P_SLEEP_CLK, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_8[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_parent_map_9[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL2_OUT_MAIN, 2 }, + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, +}; + +static const struct clk_parent_data gcc_parent_data_9[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll2_out_main.clkr.hw }, + { .hw =3D &gpll0_div2.hw }, +}; + +static const struct parent_map gcc_parent_map_10[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL4_OUT_MAIN, 2 }, + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, +}; + +static const struct clk_parent_data gcc_parent_data_10[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll4.clkr.hw }, + { .hw =3D &gpll0_div2.hw }, +}; + +static const struct parent_map gcc_parent_map_11[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_ODD, 2 }, + { P_SLEEP_CLK, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_11[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_parent_map_12[] =3D { + { P_SLEEP_CLK, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_12[] =3D { + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_parent_map_13[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL4_OUT_MAIN, 2 }, + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 3 }, +}; + +static const struct clk_parent_data gcc_parent_data_13[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll4.clkr.hw }, + { .hw =3D &gpll0_div2.hw }, +}; + +static const struct freq_tbl ftbl_gcc_adss_pwm_clk_src[] =3D { + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_adss_pwm_clk_src =3D { + .cmd_rcgr =3D 0x1c004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_adss_pwm_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_adss_pwm_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_gemnoc_anoc_pcie_clk_src[] =3D { + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_nss_ts_clk_src[] =3D { + F(24000000, P_XO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_xo_clk_src =3D { + .cmd_rcgr =3D 0x34004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_xo, + .freq_tbl =3D ftbl_gcc_nss_ts_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_xo_clk_src", + .parent_data =3D &gcc_parent_data_xo, + .num_parents =3D 1, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_fixed_factor gcc_xo_div4_clk_src =3D { + .mult =3D 1, + .div =3D 4, + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_xo_div4_clk_src", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_xo_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_fixed_factor_ops, + }, +}; + +static struct clk_rcg2 gcc_nss_ts_clk_src =3D { + .cmd_rcgr =3D 0x17088, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_nss_ts_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nss_ts_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_nssnoc_memnoc_bfdcd_clk_src[] =3D { + F(462000000, P_NSS_CMN_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_nssnoc_memnoc_bfdcd_clk_src =3D { + .cmd_rcgr =3D 0x17004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_7, + .freq_tbl =3D ftbl_gcc_nssnoc_memnoc_bfdcd_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_memnoc_bfdcd_clk_src", + .parent_data =3D gcc_parent_data_7, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_7), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_system_noc_bfdcd_clk_src[] =3D { + F(24000000, P_XO, 1, 0, 0), + F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src =3D { + .cmd_rcgr =3D 0x2e004, + .freq_tbl =3D ftbl_gcc_system_noc_bfdcd_clk_src, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_13, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_system_noc_bfdcd_clk_src", + .parent_data =3D gcc_parent_data_13, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_13), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcnoc_bfdcd_clk_src[] =3D { + F(24000000, P_XO, 1, 0, 0), + F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcnoc_bfdcd_clk_src =3D { + .cmd_rcgr =3D 0x31004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcnoc_bfdcd_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcnoc_bfdcd_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + /* + * There are no consumers for this source in kernel yet, + * (will be added soon), so the clock framework + * disables this source. But some of the clocks + * initialized by boot loaders uses this source. So we + * need to keep this clock ON. Add the + * CLK_IGNORE_UNUSED flag so the clock will not be + * disabled. Once the consumer in kernel is added, we + * can get rid of this flag. + */ + .flags =3D CLK_IS_CRITICAL, + .ops =3D &clk_rcg2_ops, + }, +}; +static const struct freq_tbl ftbl_gcc_pcie0_axi_m_clk_src[] =3D { + F(200000000, P_GPLL4_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcie0_axi_m_clk_src =3D { + .cmd_rcgr =3D 0x28018, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie0_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_axi_m_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie0_axi_s_clk_src =3D { + .cmd_rcgr =3D 0x28020, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie0_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_axi_s_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie0_rchng_clk_src =3D { + .cmd_rcgr =3D 0x28028, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_adss_pwm_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_rchng_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie1_axi_m_clk_src[] =3D { + F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcie1_axi_m_clk_src =3D { + .cmd_rcgr =3D 0x29018, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie1_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_axi_m_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie1_axi_s_clk_src =3D { + .cmd_rcgr =3D 0x29020, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie0_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_axi_s_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie1_rchng_clk_src =3D { + .cmd_rcgr =3D 0x29028, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_adss_pwm_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_rchng_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie2_axi_m_clk_src =3D { + .cmd_rcgr =3D 0x2a018, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie1_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie2_axi_m_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie2_axi_s_clk_src =3D { + .cmd_rcgr =3D 0x2a020, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie0_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie2_axi_s_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie2_rchng_clk_src =3D { + .cmd_rcgr =3D 0x2a028, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_adss_pwm_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie2_rchng_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie3_axi_m_clk_src =3D { + .cmd_rcgr =3D 0x2b018, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie1_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie3_axi_m_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie3_axi_s_clk_src =3D { + .cmd_rcgr =3D 0x2b020, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie0_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie3_axi_s_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie3_rchng_clk_src =3D { + .cmd_rcgr =3D 0x2b028, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_adss_pwm_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie3_rchng_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie4_axi_m_clk_src =3D { + .cmd_rcgr =3D 0x25004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie0_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie4_axi_m_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie4_axi_s_clk_src =3D { + .cmd_rcgr =3D 0x2500c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie0_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie4_axi_s_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie4_rchng_clk_src =3D { + .cmd_rcgr =3D 0x25014, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_adss_pwm_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie4_rchng_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie_aux_clk_src[] =3D { + F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4), + { } +}; + +static struct clk_rcg2 gcc_pcie_aux_clk_src =3D { + .cmd_rcgr =3D 0x28004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_8, + .freq_tbl =3D ftbl_gcc_pcie_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_aux_clk_src", + .parent_data =3D gcc_parent_data_8, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_8), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qdss_at_clk_src[] =3D { + F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_qdss_at_clk_src =3D { + .cmd_rcgr =3D 0x2d004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_4, + .freq_tbl =3D ftbl_gcc_qdss_at_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qdss_at_clk_src", + .parent_data =3D gcc_parent_data_4, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_4), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_fixed_factor gcc_eud_at_div_clk_src =3D { + .mult =3D 1, + .div =3D 6, + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_eud_at_div_clk_src", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_qdss_at_clk_src.clkr.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_fixed_factor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qdss_tsctr_clk_src[] =3D { + F(600000000, P_GPLL4_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_qdss_tsctr_clk_src =3D { + .cmd_rcgr =3D 0x2d01c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_4, + .freq_tbl =3D ftbl_gcc_qdss_tsctr_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qdss_tsctr_clk_src", + .parent_data =3D gcc_parent_data_4, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_4), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_fixed_factor gcc_qdss_dap_sync_clk_src =3D { + .mult =3D 1, + .div =3D 4, + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qdss_dap_sync_clk_src", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_qdss_tsctr_clk_src.clkr.hw + }, + .num_parents =3D 1, + .ops =3D &clk_fixed_factor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sleep_clk_src[] =3D { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sleep_clk_src =3D { + .cmd_rcgr =3D 0x3400c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_12, + .freq_tbl =3D ftbl_gcc_sleep_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sleep_clk_src", + .parent_data =3D gcc_parent_data_12, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_12), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qpic_io_macro_clk_src[] =3D { + F(24000000, P_XO, 1, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_qpic_clk_src =3D { + .cmd_rcgr =3D 0x32020, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_5, + .freq_tbl =3D ftbl_gcc_qpic_io_macro_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qpic_clk_src", + .parent_data =3D gcc_parent_data_5, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_5), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_qpic_io_macro_clk_src =3D { + .cmd_rcgr =3D 0x32004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_5, + .freq_tbl =3D ftbl_gcc_qpic_io_macro_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qpic_io_macro_clk_src", + .parent_data =3D gcc_parent_data_5, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_5), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_qupv3_2x_core_clk_src =3D { + .cmd_rcgr =3D 0x100c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_gemnoc_anoc_pcie_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_2x_core_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap_se0_clk_src[] =3D { + F(960000, P_XO, 10, 2, 5), + F(3686636, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 2, 217), + F(4800000, P_XO, 5, 0, 0), + F(7373272, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 4, 217), + F(9600000, P_XO, 2.5, 0, 0), + F(14746544, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 8, 217), + F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5), + F(24000000, P_XO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2), + F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25), + F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20), + F(46400000, P_GPLL0_OUT_MAIN, 2, 29, 250), + F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50), + F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), + F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125), + F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100), + F(58986175, P_GPLL0_OUT_MAIN, 1, 16, 217), + F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40), + F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se0_clk_src =3D { + .cmd_rcgr =3D 0x2018, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se0_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se1_clk_src =3D { + .cmd_rcgr =3D 0x3018, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se1_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se2_clk_src =3D { + .cmd_rcgr =3D 0x3034, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se3_clk_src =3D { + .cmd_rcgr =3D 0x3050, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se3_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap_se4_clk_src[] =3D { + F(960000, P_XO, 10, 2, 5), + F(3686636, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 2, 217), + F(4800000, P_XO, 5, 0, 0), + F(7373272, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 4, 217), + F(9600000, P_XO, 2.5, 0, 0), + F(14746544, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 8, 217), + F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5), + F(24000000, P_XO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2), + F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25), + F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20), + F(46400000, P_GPLL0_OUT_MAIN, 2, 29, 250), + F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50), + F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), + F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125), + F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100), + F(58986175, P_GPLL0_OUT_MAIN, 1, 16, 217), + F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40), + F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se4_clk_src =3D { + .cmd_rcgr =3D 0x306c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se4_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se4_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se5_clk_src =3D { + .cmd_rcgr =3D 0x3090, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se4_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se5_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se6_clk_src =3D { + .cmd_rcgr =3D 0x4004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se6_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se7_clk_src =3D { + .cmd_rcgr =3D 0x4020, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se7_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] =3D { + F(144000, P_XO, 16, 12, 125), + F(400000, P_XO, 12, 1, 5), + F(24000000, P_GPLL2_OUT_MAIN, 12, 1, 2), + F(48000000, P_GPLL2_OUT_MAIN, 12, 0, 0), + F(96000000, P_GPLL2_OUT_MAIN, 6, 0, 0), + F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0), + F(192000000, P_GPLL2_OUT_MAIN, 3, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_apps_clk_src =3D { + .cmd_rcgr =3D 0x33004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_9, + .freq_tbl =3D ftbl_gcc_sdcc1_apps_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_apps_clk_src", + .parent_data =3D gcc_parent_data_9, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_9), + .ops =3D &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] =3D { + F(300000000, P_GPLL4_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src =3D { + .cmd_rcgr =3D 0x33018, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_10, + .freq_tbl =3D ftbl_gcc_sdcc1_ice_core_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_ice_core_clk_src", + .parent_data =3D gcc_parent_data_10, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_10), + .ops =3D &clk_rcg2_floor_ops, + }, +}; + +static struct clk_rcg2 gcc_uniphy_sys_clk_src =3D { + .cmd_rcgr =3D 0x17090, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_nss_ts_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy_sys_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb0_aux_clk_src =3D { + .cmd_rcgr =3D 0x2c018, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_11, + .freq_tbl =3D ftbl_gcc_nss_ts_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_aux_clk_src", + .parent_data =3D gcc_parent_data_11, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_11), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb0_master_clk_src =3D { + .cmd_rcgr =3D 0x2c004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_gemnoc_anoc_pcie_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_master_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb0_mock_utmi_clk_src[] =3D { + F(24000000, P_XO, 1, 0, 0), + F(60000000, P_GPLL4_OUT_ODD, 10, 1, 2), + { } +}; + +static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src =3D { + .cmd_rcgr =3D 0x2c02c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_6, + .freq_tbl =3D ftbl_gcc_usb0_mock_utmi_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_mock_utmi_clk_src", + .parent_data =3D gcc_parent_data_6, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_6), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb1_mock_utmi_clk_src =3D { + .cmd_rcgr =3D 0x3c004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_6, + .freq_tbl =3D ftbl_gcc_usb0_mock_utmi_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb1_mock_utmi_clk_src", + .parent_data =3D gcc_parent_data_6, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_6), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div gcc_nssnoc_memnoc_div_clk_src =3D { + .reg =3D 0x1700c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_memnoc_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_nssnoc_memnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_usb0_mock_utmi_div_clk_src =3D { + .reg =3D 0x2c040, + .shift =3D 0, + .width =3D 2, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_mock_utmi_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb0_mock_utmi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_usb1_mock_utmi_div_clk_src =3D { + .reg =3D 0x3c018, + .shift =3D 0, + .width =3D 2, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb1_mock_utmi_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb1_mock_utmi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gcc_adss_pwm_clk =3D { + .halt_reg =3D 0x1c00c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1c00c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_adss_pwm_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_adss_pwm_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_anoc_pcie0_1lane_m_clk =3D { + .halt_reg =3D 0x2e07c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e07c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_anoc_pcie0_1lane_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie0_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_anoc_pcie0_1lane_s_clk =3D { + .halt_reg =3D 0x2e0cc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e0cc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_anoc_pcie0_1lane_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie0_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_anoc_pcie1_2lane_m_clk =3D { + .halt_reg =3D 0x2e084, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e084, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_anoc_pcie1_2lane_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie1_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_anoc_pcie1_2lane_s_clk =3D { + .halt_reg =3D 0x2e0d0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e0d0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_anoc_pcie1_2lane_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie1_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_anoc_pcie2_2lane_m_clk =3D { + .halt_reg =3D 0x2e080, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e080, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_anoc_pcie2_2lane_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie2_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_anoc_pcie2_2lane_s_clk =3D { + .halt_reg =3D 0x2e0d4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e0d4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_anoc_pcie2_2lane_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie2_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_anoc_pcie3_2lane_m_clk =3D { + .halt_reg =3D 0x2e0bc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e0bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_anoc_pcie3_2lane_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie3_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_anoc_pcie3_2lane_s_clk =3D { + .halt_reg =3D 0x2e0d8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e0d8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_anoc_pcie3_2lane_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie3_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_anoc_pcie4_1lane_m_clk =3D { + .halt_reg =3D 0x2e0c0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e0c0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_anoc_pcie4_1lane_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie4_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_anoc_pcie4_1lane_s_clk =3D { + .halt_reg =3D 0x2e0dc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e0dc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_anoc_pcie4_1lane_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie4_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cmn_12gpll_ahb_clk =3D { + .halt_reg =3D 0x3a004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3a004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cmn_12gpll_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cmn_12gpll_sys_clk =3D { + .halt_reg =3D 0x3a008, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x3a008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cmn_12gpll_sys_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_uniphy_sys_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mdio_ahb_clk =3D { + .halt_reg =3D 0x17040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_mdio_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nss_ts_clk =3D { + .halt_reg =3D 0x17018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x17018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nss_ts_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_nss_ts_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nsscc_clk =3D { + .halt_reg =3D 0x17034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nsscc_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nsscfg_clk =3D { + .halt_reg =3D 0x1702c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1702c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nsscfg_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_atb_clk =3D { + .halt_reg =3D 0x17014, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x17014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_atb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qdss_at_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_memnoc_1_clk =3D { + .halt_reg =3D 0x17084, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17084, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_memnoc_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_nssnoc_memnoc_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_memnoc_clk =3D { + .halt_reg =3D 0x17024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_memnoc_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_nssnoc_memnoc_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_nsscc_clk =3D { + .halt_reg =3D 0x17030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_nsscc_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_pcnoc_1_clk =3D { + .halt_reg =3D 0x17080, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17080, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_pcnoc_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_qosgen_ref_clk =3D { + .halt_reg =3D 0x1701c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1701c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_qosgen_ref_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_xo_div4_clk_src.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_snoc_1_clk =3D { + .halt_reg =3D 0x1707c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1707c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_snoc_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_system_noc_bfdcd_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_snoc_clk =3D { + .halt_reg =3D 0x17028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_snoc_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_system_noc_bfdcd_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_timeout_ref_clk =3D { + .halt_reg =3D 0x17020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_timeout_ref_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_xo_div4_clk_src.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_xo_dcd_clk =3D { + .halt_reg =3D 0x17074, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17074, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_xo_dcd_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_ahb_clk =3D { + .halt_reg =3D 0x28030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_aux_clk =3D { + .halt_reg =3D 0x28070, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28070, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_axi_m_clk =3D { + .halt_reg =3D 0x28038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_axi_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie0_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_axi_s_bridge_clk =3D { + .halt_reg =3D 0x28048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_axi_s_bridge_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie0_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_axi_s_clk =3D { + .halt_reg =3D 0x28040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_axi_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie0_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie0_pipe_clk_src =3D { + .reg =3D 0x28064, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "pcie0_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_PCIE30_PHY0_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_pipe_clk =3D { + .halt_reg =3D 0x28068, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x28068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_pipe_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie0_pipe_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_ahb_clk =3D { + .halt_reg =3D 0x29030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x29030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_aux_clk =3D { + .halt_reg =3D 0x29074, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x29074, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_axi_m_clk =3D { + .halt_reg =3D 0x29038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x29038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_axi_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie1_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_axi_s_bridge_clk =3D { + .halt_reg =3D 0x29048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x29048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_axi_s_bridge_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie1_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_axi_s_clk =3D { + .halt_reg =3D 0x29040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x29040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_axi_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie1_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie1_pipe_clk_src =3D { + .reg =3D 0x29064, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "pcie1_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_PCIE30_PHY1_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_pipe_clk =3D { + .halt_reg =3D 0x29068, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x29068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_pipe_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie1_pipe_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie2_ahb_clk =3D { + .halt_reg =3D 0x2a030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2a030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie2_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie2_aux_clk =3D { + .halt_reg =3D 0x2a078, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2a078, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie2_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie2_axi_m_clk =3D { + .halt_reg =3D 0x2a038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2a038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie2_axi_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie2_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie2_axi_s_bridge_clk =3D { + .halt_reg =3D 0x2a048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2a048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie2_axi_s_bridge_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie2_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie2_axi_s_clk =3D { + .halt_reg =3D 0x2a040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2a040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie2_axi_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie2_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie2_pipe_clk_src =3D { + .reg =3D 0x2a064, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "pcie2_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_PCIE30_PHY2_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie2_pipe_clk =3D { + .halt_reg =3D 0x2a068, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x2a068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie2_pipe_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie2_pipe_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie3_ahb_clk =3D { + .halt_reg =3D 0x2b030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2b030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie3_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie3_aux_clk =3D { + .halt_reg =3D 0x2b07c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2b07c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie3_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie3_axi_m_clk =3D { + .halt_reg =3D 0x2b038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2b038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie3_axi_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie3_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie3_axi_s_bridge_clk =3D { + .halt_reg =3D 0x2b048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2b048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie3_axi_s_bridge_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie3_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie3_axi_s_clk =3D { + .halt_reg =3D 0x2b040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2b040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie3_axi_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie3_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie3_pipe_clk_src =3D { + .reg =3D 0x2b064, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "pcie3_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_PCIE30_PHY3_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie3_pipe_clk =3D { + .halt_reg =3D 0x2b068, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x2b068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie3_pipe_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie3_pipe_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie4_ahb_clk =3D { + .halt_reg =3D 0x2501c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2501c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie4_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie4_aux_clk =3D { + .halt_reg =3D 0x25020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x25020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie4_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie4_axi_m_clk =3D { + .halt_reg =3D 0x25028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x25028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie4_axi_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie4_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie4_axi_s_bridge_clk =3D { + .halt_reg =3D 0x25038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x25038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie4_axi_s_bridge_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie4_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie4_axi_s_clk =3D { + .halt_reg =3D 0x25030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x25030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie4_axi_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie4_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie4_pipe_clk_src =3D { + .reg =3D 0x25058, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "pcie4_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_PCIE30_PHY4_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie4_pipe_clk =3D { + .halt_reg =3D 0x2503c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x2503c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie4_pipe_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie4_pipe_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_rchng_clk =3D { + .halt_reg =3D 0x28028, + .clkr =3D { + .enable_reg =3D 0x28028, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_rchng_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie0_rchng_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_rchng_clk =3D { + .halt_reg =3D 0x29028, + .clkr =3D { + .enable_reg =3D 0x29028, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_rchng_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie1_rchng_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie2_rchng_clk =3D { + .halt_reg =3D 0x2a028, + .clkr =3D { + .enable_reg =3D 0x2a028, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie2_rchng_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie2_rchng_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie3_rchng_clk =3D { + .halt_reg =3D 0x2b028, + .clkr =3D { + .enable_reg =3D 0x2b028, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie3_rchng_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie3_rchng_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie4_rchng_clk =3D { + .halt_reg =3D 0x25014, + .clkr =3D { + .enable_reg =3D 0x25014, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie4_rchng_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie4_rchng_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qdss_at_clk =3D { + .halt_reg =3D 0x2d034, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x2d034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qdss_at_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qdss_at_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qdss_dap_clk =3D { + .halt_reg =3D 0x2d058, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb004, + .enable_mask =3D BIT(2), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qdss_dap_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qdss_dap_sync_clk_src.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qpic_ahb_clk =3D { + .halt_reg =3D 0x32010, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x32010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qpic_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qpic_clk =3D { + .halt_reg =3D 0x32028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x32028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qpic_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qpic_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qpic_io_macro_clk =3D { + .halt_reg =3D 0x3200c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3200c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qpic_io_macro_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qpic_io_macro_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qpic_sleep_clk =3D { + .halt_reg =3D 0x32018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x32018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qpic_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_ahb_mst_clk =3D { + .halt_reg =3D 0x1014, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb004, + .enable_mask =3D BIT(14), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_ahb_mst_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_ahb_slv_clk =3D { + .halt_reg =3D 0x102c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb004, + .enable_mask =3D BIT(4), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_ahb_slv_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se0_clk =3D { + .halt_reg =3D 0x202c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x202c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se1_clk =3D { + .halt_reg =3D 0x302c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x302c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se2_clk =3D { + .halt_reg =3D 0x3048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se3_clk =3D { + .halt_reg =3D 0x3064, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se4_clk =3D { + .halt_reg =3D 0x3080, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3080, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se4_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se5_clk =3D { + .halt_reg =3D 0x30a4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x30a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se5_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se5_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se6_clk =3D { + .halt_reg =3D 0x4018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x4018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se6_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se6_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se7_clk =3D { + .halt_reg =3D 0x4034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x4034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se7_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se7_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ahb_clk =3D { + .halt_reg =3D 0x3303c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3303c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_apps_clk =3D { + .halt_reg =3D 0x3302c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3302c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_apps_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_sdcc1_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ice_core_clk =3D { + .halt_reg =3D 0x33034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x33034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_ice_core_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_sdcc1_ice_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_snoc_usb_clk =3D { + .halt_reg =3D 0x2e0c4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e0c4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_snoc_usb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb0_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy0_ahb_clk =3D { + .halt_reg =3D 0x1704c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1704c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy0_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy0_sys_clk =3D { + .halt_reg =3D 0x17048, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x17048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy0_sys_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_uniphy_sys_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy1_ahb_clk =3D { + .halt_reg =3D 0x1705c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1705c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy1_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy1_sys_clk =3D { + .halt_reg =3D 0x17058, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x17058, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy1_sys_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_uniphy_sys_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy2_ahb_clk =3D { + .halt_reg =3D 0x1706c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1706c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy2_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy2_sys_clk =3D { + .halt_reg =3D 0x17068, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x17068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy2_sys_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_uniphy_sys_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_aux_clk =3D { + .halt_reg =3D 0x2c04c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x2c04c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb0_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_eud_at_clk =3D { + .halt_reg =3D 0x30004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x30004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_eud_at_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_eud_at_div_clk_src.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_master_clk =3D { + .halt_reg =3D 0x2c044, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x2c044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_master_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb0_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_mock_utmi_clk =3D { + .halt_reg =3D 0x2c050, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x2c050, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_mock_utmi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb0_mock_utmi_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_phy_cfg_ahb_clk =3D { + .halt_reg =3D 0x2c05c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x2c05c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_phy_cfg_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src =3D { + .reg =3D 0x2c074, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_USB3_PHY0_CC_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_pipe_clk =3D { + .halt_reg =3D 0x2c054, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x2c054, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_pipe_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_usb0_pipe_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_sleep_clk =3D { + .halt_reg =3D 0x2c058, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x2c058, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_sleep_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_sleep_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb1_master_clk =3D { + .halt_reg =3D 0x3c028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3c028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb1_master_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb1_mock_utmi_clk =3D { + .halt_reg =3D 0x3c024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3c024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb1_mock_utmi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb1_mock_utmi_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb1_phy_cfg_ahb_clk =3D { + .halt_reg =3D 0x3c01c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x3c01c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb1_phy_cfg_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb1_sleep_clk =3D { + .halt_reg =3D 0x3c020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3c020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb1_sleep_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_sleep_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *gcc_ipq9650_clocks[] =3D { + [GCC_ADSS_PWM_CLK] =3D &gcc_adss_pwm_clk.clkr, + [GCC_ADSS_PWM_CLK_SRC] =3D &gcc_adss_pwm_clk_src.clkr, + [GCC_ANOC_PCIE0_1LANE_M_CLK] =3D &gcc_anoc_pcie0_1lane_m_clk.clkr, + [GCC_ANOC_PCIE0_1LANE_S_CLK] =3D &gcc_anoc_pcie0_1lane_s_clk.clkr, + [GCC_ANOC_PCIE1_2LANE_M_CLK] =3D &gcc_anoc_pcie1_2lane_m_clk.clkr, + [GCC_ANOC_PCIE1_2LANE_S_CLK] =3D &gcc_anoc_pcie1_2lane_s_clk.clkr, + [GCC_ANOC_PCIE2_2LANE_M_CLK] =3D &gcc_anoc_pcie2_2lane_m_clk.clkr, + [GCC_ANOC_PCIE2_2LANE_S_CLK] =3D &gcc_anoc_pcie2_2lane_s_clk.clkr, + [GCC_ANOC_PCIE3_2LANE_M_CLK] =3D &gcc_anoc_pcie3_2lane_m_clk.clkr, + [GCC_ANOC_PCIE3_2LANE_S_CLK] =3D &gcc_anoc_pcie3_2lane_s_clk.clkr, + [GCC_ANOC_PCIE4_1LANE_M_CLK] =3D &gcc_anoc_pcie4_1lane_m_clk.clkr, + [GCC_ANOC_PCIE4_1LANE_S_CLK] =3D &gcc_anoc_pcie4_1lane_s_clk.clkr, + [GCC_CMN_12GPLL_AHB_CLK] =3D &gcc_cmn_12gpll_ahb_clk.clkr, + [GCC_CMN_12GPLL_SYS_CLK] =3D &gcc_cmn_12gpll_sys_clk.clkr, + [GCC_MDIO_AHB_CLK] =3D &gcc_mdio_ahb_clk.clkr, + [GCC_NSS_TS_CLK] =3D &gcc_nss_ts_clk.clkr, + [GCC_NSS_TS_CLK_SRC] =3D &gcc_nss_ts_clk_src.clkr, + [GCC_NSSCC_CLK] =3D &gcc_nsscc_clk.clkr, + [GCC_NSSCFG_CLK] =3D &gcc_nsscfg_clk.clkr, + [GCC_NSSNOC_ATB_CLK] =3D &gcc_nssnoc_atb_clk.clkr, + [GCC_NSSNOC_MEMNOC_1_CLK] =3D &gcc_nssnoc_memnoc_1_clk.clkr, + [GCC_NSSNOC_MEMNOC_BFDCD_CLK_SRC] =3D &gcc_nssnoc_memnoc_bfdcd_clk_src.cl= kr, + [GCC_NSSNOC_MEMNOC_CLK] =3D &gcc_nssnoc_memnoc_clk.clkr, + [GCC_NSSNOC_MEMNOC_DIV_CLK_SRC] =3D &gcc_nssnoc_memnoc_div_clk_src.clkr, + [GCC_NSSNOC_NSSCC_CLK] =3D &gcc_nssnoc_nsscc_clk.clkr, + [GCC_NSSNOC_PCNOC_1_CLK] =3D &gcc_nssnoc_pcnoc_1_clk.clkr, + [GCC_NSSNOC_QOSGEN_REF_CLK] =3D &gcc_nssnoc_qosgen_ref_clk.clkr, + [GCC_NSSNOC_SNOC_1_CLK] =3D &gcc_nssnoc_snoc_1_clk.clkr, + [GCC_NSSNOC_SNOC_CLK] =3D &gcc_nssnoc_snoc_clk.clkr, + [GCC_NSSNOC_TIMEOUT_REF_CLK] =3D &gcc_nssnoc_timeout_ref_clk.clkr, + [GCC_NSSNOC_XO_DCD_CLK] =3D &gcc_nssnoc_xo_dcd_clk.clkr, + [GCC_PCIE0_AHB_CLK] =3D &gcc_pcie0_ahb_clk.clkr, + [GCC_PCIE0_AUX_CLK] =3D &gcc_pcie0_aux_clk.clkr, + [GCC_PCIE0_AXI_M_CLK] =3D &gcc_pcie0_axi_m_clk.clkr, + [GCC_PCIE0_AXI_M_CLK_SRC] =3D &gcc_pcie0_axi_m_clk_src.clkr, + [GCC_PCIE0_AXI_S_BRIDGE_CLK] =3D &gcc_pcie0_axi_s_bridge_clk.clkr, + [GCC_PCIE0_AXI_S_CLK] =3D &gcc_pcie0_axi_s_clk.clkr, + [GCC_PCIE0_AXI_S_CLK_SRC] =3D &gcc_pcie0_axi_s_clk_src.clkr, + [GCC_PCIE0_PIPE_CLK] =3D &gcc_pcie0_pipe_clk.clkr, + [GCC_PCIE0_PIPE_CLK_SRC] =3D &gcc_pcie0_pipe_clk_src.clkr, + [GCC_PCIE0_RCHNG_CLK_SRC] =3D &gcc_pcie0_rchng_clk_src.clkr, + [GCC_PCIE0_RCHNG_CLK] =3D &gcc_pcie0_rchng_clk.clkr, + [GCC_PCIE1_AHB_CLK] =3D &gcc_pcie1_ahb_clk.clkr, + [GCC_PCIE1_AUX_CLK] =3D &gcc_pcie1_aux_clk.clkr, + [GCC_PCIE1_AXI_M_CLK] =3D &gcc_pcie1_axi_m_clk.clkr, + [GCC_PCIE1_AXI_M_CLK_SRC] =3D &gcc_pcie1_axi_m_clk_src.clkr, + [GCC_PCIE1_AXI_S_BRIDGE_CLK] =3D &gcc_pcie1_axi_s_bridge_clk.clkr, + [GCC_PCIE1_AXI_S_CLK] =3D &gcc_pcie1_axi_s_clk.clkr, + [GCC_PCIE1_AXI_S_CLK_SRC] =3D &gcc_pcie1_axi_s_clk_src.clkr, + [GCC_PCIE1_PIPE_CLK] =3D &gcc_pcie1_pipe_clk.clkr, + [GCC_PCIE1_PIPE_CLK_SRC] =3D &gcc_pcie1_pipe_clk_src.clkr, + [GCC_PCIE1_RCHNG_CLK_SRC] =3D &gcc_pcie1_rchng_clk_src.clkr, + [GCC_PCIE1_RCHNG_CLK] =3D &gcc_pcie1_rchng_clk.clkr, + [GCC_PCIE2_AHB_CLK] =3D &gcc_pcie2_ahb_clk.clkr, + [GCC_PCIE2_AUX_CLK] =3D &gcc_pcie2_aux_clk.clkr, + [GCC_PCIE2_AXI_M_CLK] =3D &gcc_pcie2_axi_m_clk.clkr, + [GCC_PCIE2_AXI_M_CLK_SRC] =3D &gcc_pcie2_axi_m_clk_src.clkr, + [GCC_PCIE2_AXI_S_BRIDGE_CLK] =3D &gcc_pcie2_axi_s_bridge_clk.clkr, + [GCC_PCIE2_AXI_S_CLK] =3D &gcc_pcie2_axi_s_clk.clkr, + [GCC_PCIE2_AXI_S_CLK_SRC] =3D &gcc_pcie2_axi_s_clk_src.clkr, + [GCC_PCIE2_PIPE_CLK] =3D &gcc_pcie2_pipe_clk.clkr, + [GCC_PCIE2_PIPE_CLK_SRC] =3D &gcc_pcie2_pipe_clk_src.clkr, + [GCC_PCIE2_RCHNG_CLK_SRC] =3D &gcc_pcie2_rchng_clk_src.clkr, + [GCC_PCIE2_RCHNG_CLK] =3D &gcc_pcie2_rchng_clk.clkr, + [GCC_PCIE3_AHB_CLK] =3D &gcc_pcie3_ahb_clk.clkr, + [GCC_PCIE3_AUX_CLK] =3D &gcc_pcie3_aux_clk.clkr, + [GCC_PCIE3_AXI_M_CLK] =3D &gcc_pcie3_axi_m_clk.clkr, + [GCC_PCIE3_AXI_M_CLK_SRC] =3D &gcc_pcie3_axi_m_clk_src.clkr, + [GCC_PCIE3_AXI_S_BRIDGE_CLK] =3D &gcc_pcie3_axi_s_bridge_clk.clkr, + [GCC_PCIE3_AXI_S_CLK] =3D &gcc_pcie3_axi_s_clk.clkr, + [GCC_PCIE3_AXI_S_CLK_SRC] =3D &gcc_pcie3_axi_s_clk_src.clkr, + [GCC_PCIE3_PIPE_CLK] =3D &gcc_pcie3_pipe_clk.clkr, + [GCC_PCIE3_PIPE_CLK_SRC] =3D &gcc_pcie3_pipe_clk_src.clkr, + [GCC_PCIE3_RCHNG_CLK_SRC] =3D &gcc_pcie3_rchng_clk_src.clkr, + [GCC_PCIE3_RCHNG_CLK] =3D &gcc_pcie3_rchng_clk.clkr, + [GCC_PCIE4_AHB_CLK] =3D &gcc_pcie4_ahb_clk.clkr, + [GCC_PCIE4_AUX_CLK] =3D &gcc_pcie4_aux_clk.clkr, + [GCC_PCIE4_AXI_M_CLK] =3D &gcc_pcie4_axi_m_clk.clkr, + [GCC_PCIE4_AXI_M_CLK_SRC] =3D &gcc_pcie4_axi_m_clk_src.clkr, + [GCC_PCIE4_AXI_S_BRIDGE_CLK] =3D &gcc_pcie4_axi_s_bridge_clk.clkr, + [GCC_PCIE4_AXI_S_CLK] =3D &gcc_pcie4_axi_s_clk.clkr, + [GCC_PCIE4_AXI_S_CLK_SRC] =3D &gcc_pcie4_axi_s_clk_src.clkr, + [GCC_PCIE4_PIPE_CLK] =3D &gcc_pcie4_pipe_clk.clkr, + [GCC_PCIE4_PIPE_CLK_SRC] =3D &gcc_pcie4_pipe_clk_src.clkr, + [GCC_PCIE4_RCHNG_CLK_SRC] =3D &gcc_pcie4_rchng_clk_src.clkr, + [GCC_PCIE4_RCHNG_CLK] =3D &gcc_pcie4_rchng_clk.clkr, + [GCC_PCIE_AUX_CLK_SRC] =3D &gcc_pcie_aux_clk_src.clkr, + [GCC_PCNOC_BFDCD_CLK_SRC] =3D &gcc_pcnoc_bfdcd_clk_src.clkr, + [GCC_QDSS_AT_CLK] =3D &gcc_qdss_at_clk.clkr, + [GCC_QDSS_AT_CLK_SRC] =3D &gcc_qdss_at_clk_src.clkr, + [GCC_QDSS_DAP_CLK] =3D &gcc_qdss_dap_clk.clkr, + [GCC_QDSS_TSCTR_CLK_SRC] =3D &gcc_qdss_tsctr_clk_src.clkr, + [GCC_QPIC_AHB_CLK] =3D &gcc_qpic_ahb_clk.clkr, + [GCC_QPIC_CLK] =3D &gcc_qpic_clk.clkr, + [GCC_QPIC_CLK_SRC] =3D &gcc_qpic_clk_src.clkr, + [GCC_QPIC_IO_MACRO_CLK] =3D &gcc_qpic_io_macro_clk.clkr, + [GCC_QPIC_IO_MACRO_CLK_SRC] =3D &gcc_qpic_io_macro_clk_src.clkr, + [GCC_QPIC_SLEEP_CLK] =3D &gcc_qpic_sleep_clk.clkr, + [GCC_QUPV3_2X_CORE_CLK_SRC] =3D &gcc_qupv3_2x_core_clk_src.clkr, + [GCC_QUPV3_AHB_MST_CLK] =3D &gcc_qupv3_ahb_mst_clk.clkr, + [GCC_QUPV3_AHB_SLV_CLK] =3D &gcc_qupv3_ahb_slv_clk.clkr, + [GCC_QUPV3_WRAP_SE0_CLK] =3D &gcc_qupv3_wrap_se0_clk.clkr, + [GCC_QUPV3_WRAP_SE0_CLK_SRC] =3D &gcc_qupv3_wrap_se0_clk_src.clkr, + [GCC_QUPV3_WRAP_SE1_CLK] =3D &gcc_qupv3_wrap_se1_clk.clkr, + [GCC_QUPV3_WRAP_SE1_CLK_SRC] =3D &gcc_qupv3_wrap_se1_clk_src.clkr, + [GCC_QUPV3_WRAP_SE2_CLK] =3D &gcc_qupv3_wrap_se2_clk.clkr, + [GCC_QUPV3_WRAP_SE2_CLK_SRC] =3D &gcc_qupv3_wrap_se2_clk_src.clkr, + [GCC_QUPV3_WRAP_SE3_CLK] =3D &gcc_qupv3_wrap_se3_clk.clkr, + [GCC_QUPV3_WRAP_SE3_CLK_SRC] =3D &gcc_qupv3_wrap_se3_clk_src.clkr, + [GCC_QUPV3_WRAP_SE4_CLK] =3D &gcc_qupv3_wrap_se4_clk.clkr, + [GCC_QUPV3_WRAP_SE4_CLK_SRC] =3D &gcc_qupv3_wrap_se4_clk_src.clkr, + [GCC_QUPV3_WRAP_SE5_CLK] =3D &gcc_qupv3_wrap_se5_clk.clkr, + [GCC_QUPV3_WRAP_SE5_CLK_SRC] =3D &gcc_qupv3_wrap_se5_clk_src.clkr, + [GCC_QUPV3_WRAP_SE6_CLK] =3D &gcc_qupv3_wrap_se6_clk.clkr, + [GCC_QUPV3_WRAP_SE6_CLK_SRC] =3D &gcc_qupv3_wrap_se6_clk_src.clkr, + [GCC_QUPV3_WRAP_SE7_CLK] =3D &gcc_qupv3_wrap_se7_clk.clkr, + [GCC_QUPV3_WRAP_SE7_CLK_SRC] =3D &gcc_qupv3_wrap_se7_clk_src.clkr, + [GCC_SDCC1_AHB_CLK] =3D &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] =3D &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC1_APPS_CLK_SRC] =3D &gcc_sdcc1_apps_clk_src.clkr, + [GCC_SDCC1_ICE_CORE_CLK] =3D &gcc_sdcc1_ice_core_clk.clkr, + [GCC_SDCC1_ICE_CORE_CLK_SRC] =3D &gcc_sdcc1_ice_core_clk_src.clkr, + [GCC_SLEEP_CLK_SRC] =3D &gcc_sleep_clk_src.clkr, + [GCC_SNOC_USB_CLK] =3D &gcc_snoc_usb_clk.clkr, + [GCC_SYSTEM_NOC_BFDCD_CLK_SRC] =3D &gcc_system_noc_bfdcd_clk_src.clkr, + [GCC_UNIPHY0_AHB_CLK] =3D &gcc_uniphy0_ahb_clk.clkr, + [GCC_UNIPHY0_SYS_CLK] =3D &gcc_uniphy0_sys_clk.clkr, + [GCC_UNIPHY1_AHB_CLK] =3D &gcc_uniphy1_ahb_clk.clkr, + [GCC_UNIPHY1_SYS_CLK] =3D &gcc_uniphy1_sys_clk.clkr, + [GCC_UNIPHY2_AHB_CLK] =3D &gcc_uniphy2_ahb_clk.clkr, + [GCC_UNIPHY2_SYS_CLK] =3D &gcc_uniphy2_sys_clk.clkr, + [GCC_UNIPHY_SYS_CLK_SRC] =3D &gcc_uniphy_sys_clk_src.clkr, + [GCC_USB0_AUX_CLK] =3D &gcc_usb0_aux_clk.clkr, + [GCC_USB0_AUX_CLK_SRC] =3D &gcc_usb0_aux_clk_src.clkr, + [GCC_USB0_EUD_AT_CLK] =3D &gcc_usb0_eud_at_clk.clkr, + [GCC_USB0_MASTER_CLK] =3D &gcc_usb0_master_clk.clkr, + [GCC_USB0_MASTER_CLK_SRC] =3D &gcc_usb0_master_clk_src.clkr, + [GCC_USB0_MOCK_UTMI_CLK] =3D &gcc_usb0_mock_utmi_clk.clkr, + [GCC_USB0_MOCK_UTMI_CLK_SRC] =3D &gcc_usb0_mock_utmi_clk_src.clkr, + [GCC_USB0_MOCK_UTMI_DIV_CLK_SRC] =3D &gcc_usb0_mock_utmi_div_clk_src.clkr, + [GCC_USB0_PHY_CFG_AHB_CLK] =3D &gcc_usb0_phy_cfg_ahb_clk.clkr, + [GCC_USB0_PIPE_CLK] =3D &gcc_usb0_pipe_clk.clkr, + [GCC_USB0_PIPE_CLK_SRC] =3D &gcc_usb0_pipe_clk_src.clkr, + [GCC_USB0_SLEEP_CLK] =3D &gcc_usb0_sleep_clk.clkr, + [GCC_USB1_MASTER_CLK] =3D &gcc_usb1_master_clk.clkr, + [GCC_USB1_MOCK_UTMI_CLK] =3D &gcc_usb1_mock_utmi_clk.clkr, + [GCC_USB1_MOCK_UTMI_CLK_SRC] =3D &gcc_usb1_mock_utmi_clk_src.clkr, + [GCC_USB1_MOCK_UTMI_DIV_CLK_SRC] =3D &gcc_usb1_mock_utmi_div_clk_src.clkr, + [GCC_USB1_PHY_CFG_AHB_CLK] =3D &gcc_usb1_phy_cfg_ahb_clk.clkr, + [GCC_USB1_SLEEP_CLK] =3D &gcc_usb1_sleep_clk.clkr, + [GCC_XO_CLK_SRC] =3D &gcc_xo_clk_src.clkr, + [GPLL0_MAIN] =3D &gpll0_main.clkr, + [GPLL0] =3D &gpll0.clkr, + [GPLL2] =3D &gpll2.clkr, + [GPLL2_OUT_MAIN] =3D &gpll2_out_main.clkr, + [GPLL4] =3D &gpll4.clkr, +}; + +static const struct qcom_reset_map gcc_ipq9650_resets[] =3D { + [GCC_ADSS_BCR] =3D { 0x1c000 }, + [GCC_ADSS_PWM_CLK_ARES] =3D { 0x1c00c, 2 }, + [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] =3D { 0x38000 }, + [GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES] =3D { 0x3800c, 2 }, + [GCC_APSS_AHB_CLK_ARES] =3D { 0x24014, 2 }, + [GCC_APSS_ATB_CLK_ARES] =3D { 0x24034, 2 }, + [GCC_APSS_AXI_CLK_ARES] =3D { 0x24018, 2 }, + [GCC_APSS_TS_CLK_ARES] =3D { 0x24030, 2 }, + [GCC_BOOT_ROM_AHB_CLK_ARES] =3D { 0x1302c, 2 }, + [GCC_BOOT_ROM_BCR] =3D { 0x13028 }, + [GCC_CPUSS_TRIG_CLK_ARES] =3D { 0x2401c, 2 }, + [GCC_GP1_CLK_ARES] =3D { 0x8018, 2 }, + [GCC_GP2_CLK_ARES] =3D { 0x8030, 2 }, + [GCC_GP3_CLK_ARES] =3D { 0x8048, 2 }, + [GCC_MDIO_AHB_CLK_ARES] =3D { 0x17040, 2 }, + [GCC_MDIO_BCR] =3D { 0x1703c }, + [GCC_NSS_BCR] =3D { 0x17000 }, + [GCC_NSS_TS_CLK_ARES] =3D { 0x17018, 2 }, + [GCC_NSSCC_CLK_ARES] =3D { 0x17034, 2 }, + [GCC_NSSCFG_CLK_ARES] =3D { 0x1702c, 2 }, + [GCC_NSSNOC_ATB_CLK_ARES] =3D { 0x17014, 2 }, + [GCC_NSSNOC_MEMNOC_1_CLK_ARES] =3D { 0x17084, 2 }, + [GCC_NSSNOC_MEMNOC_CLK_ARES] =3D { 0x17024, 2 }, + [GCC_NSSNOC_NSSCC_CLK_ARES] =3D { 0x17030, 2 }, + [GCC_NSSNOC_PCNOC_1_CLK_ARES] =3D { 0x17080, 2 }, + [GCC_NSSNOC_QOSGEN_REF_CLK_ARES] =3D { 0x1701c, 2 }, + [GCC_NSSNOC_SNOC_1_CLK_ARES] =3D { 0x1707c, 2 }, + [GCC_NSSNOC_SNOC_CLK_ARES] =3D { 0x17028, 2 }, + [GCC_NSSNOC_TIMEOUT_REF_CLK_ARES] =3D { 0x17020, 2 }, + [GCC_NSSNOC_XO_DCD_CLK_ARES] =3D { 0x17074, 2 }, + [GCC_PCIE0_AHB_CLK_ARES] =3D { 0x28030, 2 }, + [GCC_PCIE0_AUX_CLK_ARES] =3D { 0x28070, 2 }, + [GCC_PCIE0_AXI_M_CLK_ARES] =3D { 0x28038, 2 }, + [GCC_PCIE0_AXI_S_BRIDGE_CLK_ARES] =3D { 0x28048, 2 }, + [GCC_PCIE0_AXI_S_CLK_ARES] =3D { 0x28040, 2 }, + [GCC_PCIE0_BCR] =3D { 0x28000 }, + [GCC_PCIE0_LINK_DOWN_BCR] =3D { 0x28054 }, + [GCC_PCIE0_PHY_BCR] =3D { 0x28060 }, + [GCC_PCIE0_PIPE_CLK_ARES] =3D { 0x28068, 2 }, + [GCC_PCIE0PHY_PHY_BCR] =3D { 0x2805c }, + [GCC_PCIE0_PIPE_RESET] =3D { 0x28058, 0 }, + [GCC_PCIE0_CORE_STICKY_RESET] =3D { 0x28058, 1 }, + [GCC_PCIE0_AXI_S_STICKY_RESET] =3D { 0x28058, 2 }, + [GCC_PCIE0_AXI_S_RESET] =3D { 0x28058, 3 }, + [GCC_PCIE0_AXI_M_STICKY_RESET] =3D { 0x28058, 4 }, + [GCC_PCIE0_AXI_M_RESET] =3D { 0x28058, 5 }, + [GCC_PCIE0_AUX_RESET] =3D { 0x28058, 6 }, + [GCC_PCIE0_AHB_RESET] =3D { 0x28058, 7 }, + [GCC_PCIE1_AHB_CLK_ARES] =3D { 0x29030, 2 }, + [GCC_PCIE1_AUX_CLK_ARES] =3D { 0x29074, 2 }, + [GCC_PCIE1_AXI_M_CLK_ARES] =3D { 0x29038, 2 }, + [GCC_PCIE1_AXI_S_BRIDGE_CLK_ARES] =3D { 0x29048, 2 }, + [GCC_PCIE1_AXI_S_CLK_ARES] =3D { 0x29040, 2 }, + [GCC_PCIE1_BCR] =3D { 0x29000 }, + [GCC_PCIE1_LINK_DOWN_BCR] =3D { 0x29054 }, + [GCC_PCIE1_PHY_BCR] =3D { 0x29060 }, + [GCC_PCIE1_PIPE_CLK_ARES] =3D { 0x29068, 2 }, + [GCC_PCIE1PHY_PHY_BCR] =3D { 0x2905c }, + [GCC_PCIE1_PIPE_RESET] =3D { 0x29058, 0 }, + [GCC_PCIE1_CORE_STICKY_RESET] =3D { 0x29058, 1 }, + [GCC_PCIE1_AXI_S_STICKY_RESET] =3D { 0x29058, 2 }, + [GCC_PCIE1_AXI_S_RESET] =3D { 0x29058, 3 }, + [GCC_PCIE1_AXI_M_STICKY_RESET] =3D { 0x29058, 4 }, + [GCC_PCIE1_AXI_M_RESET] =3D { 0x29058, 5 }, + [GCC_PCIE1_AUX_RESET] =3D { 0x29058, 6 }, + [GCC_PCIE1_AHB_RESET] =3D { 0x29058, 7 }, + [GCC_PCIE2_AHB_CLK_ARES] =3D { 0x2a030, 2 }, + [GCC_PCIE2_AUX_CLK_ARES] =3D { 0x2a078, 2 }, + [GCC_PCIE2_AXI_M_CLK_ARES] =3D { 0x2a038, 2 }, + [GCC_PCIE2_AXI_S_BRIDGE_CLK_ARES] =3D { 0x2a048, 2 }, + [GCC_PCIE2_AXI_S_CLK_ARES] =3D { 0x2a040, 2 }, + [GCC_PCIE2_BCR] =3D { 0x2a000 }, + [GCC_PCIE2_LINK_DOWN_BCR] =3D { 0x2a054 }, + [GCC_PCIE2_PHY_BCR] =3D { 0x2a060 }, + [GCC_PCIE2_PIPE_CLK_ARES] =3D { 0x2a068, 2 }, + [GCC_PCIE2PHY_PHY_BCR] =3D { 0x2a05c }, + [GCC_PCIE2_PIPE_RESET] =3D { 0x2a058, 0 }, + [GCC_PCIE2_CORE_STICKY_RESET] =3D { 0x2a058, 1 }, + [GCC_PCIE2_AXI_S_STICKY_RESET] =3D { 0x2a058, 2 }, + [GCC_PCIE2_AXI_S_RESET] =3D { 0x2a058, 3 }, + [GCC_PCIE2_AXI_M_STICKY_RESET] =3D { 0x2a058, 4 }, + [GCC_PCIE2_AXI_M_RESET] =3D { 0x2a058, 5 }, + [GCC_PCIE2_AUX_RESET] =3D { 0x2a058, 6 }, + [GCC_PCIE2_AHB_RESET] =3D { 0x2a058, 7 }, + [GCC_PCIE3_AHB_CLK_ARES] =3D { 0x2b030, 2 }, + [GCC_PCIE3_AUX_CLK_ARES] =3D { 0x2b07c, 2 }, + [GCC_PCIE3_AXI_M_CLK_ARES] =3D { 0x2b038, 2 }, + [GCC_PCIE3_AXI_S_BRIDGE_CLK_ARES] =3D { 0x2b048, 2 }, + [GCC_PCIE3_AXI_S_CLK_ARES] =3D { 0x2b040, 2 }, + [GCC_PCIE3_BCR] =3D { 0x2b000 }, + [GCC_PCIE3_LINK_DOWN_BCR] =3D { 0x2b054 }, + [GCC_PCIE3_PHY_BCR] =3D { 0x2b060 }, + [GCC_PCIE3_PIPE_CLK_ARES] =3D { 0x2b068, 2 }, + [GCC_PCIE3PHY_PHY_BCR] =3D { 0x2b05c }, + [GCC_PCIE3_PIPE_RESET] =3D { 0x2b058, 0 }, + [GCC_PCIE3_CORE_STICKY_RESET] =3D { 0x2b058, 1 }, + [GCC_PCIE3_AXI_S_STICKY_RESET] =3D { 0x2b058, 2 }, + [GCC_PCIE3_AXI_S_RESET] =3D { 0x2b058, 3 }, + [GCC_PCIE3_AXI_M_STICKY_RESET] =3D { 0x2b058, 4 }, + [GCC_PCIE3_AXI_M_RESET] =3D { 0x2b058, 5 }, + [GCC_PCIE3_AUX_RESET] =3D { 0x2b058, 6 }, + [GCC_PCIE3_AHB_RESET] =3D { 0x2b058, 7 }, + [GCC_PCIE4_AHB_CLK_ARES] =3D { 0x2501c, 2 }, + [GCC_PCIE4_AUX_CLK_ARES] =3D { 0x25020, 2 }, + [GCC_PCIE4_AXI_M_CLK_ARES] =3D { 0x25028, 2 }, + [GCC_PCIE4_AXI_S_BRIDGE_CLK_ARES] =3D { 0x25038, 2 }, + [GCC_PCIE4_AXI_S_CLK_ARES] =3D { 0x25030, 2 }, + [GCC_PCIE4_BCR] =3D { 0x25000 }, + [GCC_PCIE4_LINK_DOWN_BCR] =3D { 0x25044 }, + [GCC_PCIE4_PHY_BCR] =3D { 0x2504c }, + [GCC_PCIE4_PIPE_CLK_ARES] =3D { 0x2503c, 2 }, + [GCC_PCIE4_PIPE_RESET] =3D { 0x25054, 0 }, + [GCC_PCIE4_CORE_STICKY_RESET] =3D { 0x25054, 1 }, + [GCC_PCIE4_AXI_S_STICKY_RESET] =3D { 0x25054, 2 }, + [GCC_PCIE4_AXI_S_RESET] =3D { 0x25054, 3 }, + [GCC_PCIE4_AXI_M_STICKY_RESET] =3D { 0x25054, 4 }, + [GCC_PCIE4_AXI_M_RESET] =3D { 0x25054, 5 }, + [GCC_PCIE4_AUX_RESET] =3D { 0x25054, 6 }, + [GCC_PCIE4_AHB_RESET] =3D { 0x25054, 7 }, + [GCC_PCIE4PHY_PHY_BCR] =3D { 0x25048 }, + [GCC_QDSS_APB2JTAG_CLK_ARES] =3D { 0x2d05c, 2 }, + [GCC_QDSS_AT_CLK_ARES] =3D { 0x2d034, 2 }, + [GCC_QDSS_BCR] =3D { 0x2d000 }, + [GCC_QDSS_CFG_AHB_CLK_ARES] =3D { 0x2d068, 2 }, + [GCC_QDSS_DAP_AHB_CLK_ARES] =3D { 0x2d064, 2 }, + [GCC_QDSS_DAP_CLK_ARES] =3D { 0x2d058, 2 }, + [GCC_QDSS_ETR_USB_CLK_ARES] =3D { 0x2d060, 2 }, + [GCC_QDSS_EUD_AT_CLK_ARES] =3D { 0x2d06c, 2 }, + [GCC_QDSS_STM_CLK_ARES] =3D { 0x2d03c, 2 }, + [GCC_QDSS_TRACECLKIN_CLK_ARES] =3D { 0x2d040, 2 }, + [GCC_QDSS_TS_CLK_ARES] =3D { 0x2d078, 2 }, + [GCC_QDSS_TSCTR_DIV16_CLK_ARES] =3D { 0x2d054, 2 }, + [GCC_QDSS_TSCTR_DIV2_CLK_ARES] =3D { 0x2d044, 2 }, + [GCC_QDSS_TSCTR_DIV3_CLK_ARES] =3D { 0x2d048, 2 }, + [GCC_QDSS_TSCTR_DIV4_CLK_ARES] =3D { 0x2d04c, 2 }, + [GCC_QDSS_TSCTR_DIV8_CLK_ARES] =3D { 0x2d050, 2 }, + [GCC_QPIC_AHB_CLK_ARES] =3D { 0x32010, 2 }, + [GCC_QPIC_CLK_ARES] =3D { 0x32028, 2 }, + [GCC_QPIC_BCR] =3D { 0x32000 }, + [GCC_QPIC_IO_MACRO_CLK_ARES] =3D { 0x3200c, 2 }, + [GCC_QPIC_SLEEP_CLK_ARES] =3D { 0x32018, 2 }, + [GCC_QUPV3_2X_CORE_CLK_ARES] =3D { 0x1020, 2 }, + [GCC_QUPV3_AHB_MST_CLK_ARES] =3D { 0x1014, 2 }, + [GCC_QUPV3_AHB_SLV_CLK_ARES] =3D { 0x102c, 2 }, + [GCC_QUPV3_BCR] =3D { 0x1000 }, + [GCC_QUPV3_CORE_CLK_ARES] =3D { 0x1018, 2 }, + [GCC_QUPV3_WRAP_SE0_CLK_ARES] =3D { 0x202c, 2 }, + [GCC_QUPV3_WRAP_SE0_BCR] =3D { 0x2000 }, + [GCC_QUPV3_WRAP_SE1_CLK_ARES] =3D { 0x302c, 2 }, + [GCC_QUPV3_WRAP_SE1_BCR] =3D { 0x3000 }, + [GCC_QUPV3_WRAP_SE2_CLK_ARES] =3D { 0x3048, 2 }, + [GCC_QUPV3_WRAP_SE2_BCR] =3D { 0x3030 }, + [GCC_QUPV3_WRAP_SE3_CLK_ARES] =3D { 0x3064, 2 }, + [GCC_QUPV3_WRAP_SE3_BCR] =3D { 0x304c }, + [GCC_QUPV3_WRAP_SE4_CLK_ARES] =3D { 0x3080, 2 }, + [GCC_QUPV3_WRAP_SE4_BCR] =3D { 0x3068 }, + [GCC_QUPV3_WRAP_SE5_CLK_ARES] =3D { 0x30a4, 2 }, + [GCC_QUPV3_WRAP_SE5_BCR] =3D { 0x308c }, + [GCC_QUPV3_WRAP_SE6_CLK_ARES] =3D { 0x4018, 2 }, + [GCC_QUPV3_WRAP_SE6_BCR] =3D { 0x4000 }, + [GCC_QUPV3_WRAP_SE7_CLK_ARES] =3D { 0x4034, 2 }, + [GCC_QUPV3_WRAP_SE7_BCR] =3D { 0x401c }, + [GCC_QUSB2_0_PHY_BCR] =3D { 0x2c068 }, + [GCC_QUSB2_1_PHY_BCR] =3D { 0x3c030 }, + [GCC_SDCC1_APPS_CLK_ARES] =3D { 0x3302c, 2 }, + [GCC_SDCC1_ICE_CORE_CLK_ARES] =3D { 0x33034, 2 }, + [GCC_SDCC_BCR] =3D { 0x33000 }, + [GCC_TLMM_AHB_CLK_ARES] =3D { 0x3e004, 2 }, + [GCC_TLMM_CLK_ARES] =3D { 0x3e008, 2 }, + [GCC_TLMM_BCR] =3D { 0x3e000 }, + [GCC_UNIPHY0_AHB_CLK_ARES] =3D { 0x1704c, 2 }, + [GCC_UNIPHY0_BCR] =3D { 0x17044 }, + [GCC_UNIPHY0_PMA_BCR] =3D { 0x17098 }, + [GCC_UNIPHY0_SYS_CLK_ARES] =3D { 0x17048, 2 }, + [GCC_UNIPHY1_AHB_CLK_ARES] =3D { 0x1705c, 2 }, + [GCC_UNIPHY1_BCR] =3D { 0x17054 }, + [GCC_UNIPHY1_PMA_BCR] =3D { 0x1709c }, + [GCC_UNIPHY1_SYS_CLK_ARES] =3D { 0x17058, 2 }, + [GCC_UNIPHY2_AHB_CLK_ARES] =3D { 0x1706c, 2 }, + [GCC_UNIPHY2_BCR] =3D { 0x17064 }, + [GCC_UNIPHY2_PMA_BCR] =3D { 0x170a0 }, + [GCC_UNIPHY2_SYS_CLK_ARES] =3D { 0x17068, 2 }, + [GCC_UNIPHY0_XPCS_ARES] =3D { 0x17050, 2 }, + [GCC_UNIPHY1_XLGPCS_ARES] =3D { 0x17060, 1 }, + [GCC_UNIPHY1_XPCS_ARES] =3D { 0x17060, 2 }, + [GCC_UNIPHY2_XLGPCS_ARES] =3D { 0x17070, 1 }, + [GCC_UNIPHY2_XPCS_ARES] =3D { 0x17070, 2 }, + [GCC_USB0_AUX_CLK_ARES] =3D { 0x2c04c, 2 }, + [GCC_USB0_MASTER_CLK_ARES] =3D { 0x2c044, 2 }, + [GCC_USB0_MOCK_UTMI_CLK_ARES] =3D { 0x2c050, 2 }, + [GCC_USB0_PHY_BCR] =3D { 0x2c06c }, + [GCC_USB0_PHY_CFG_AHB_CLK_ARES] =3D { 0x2c05c, 2 }, + [GCC_USB0_PIPE_CLK_ARES] =3D { 0x2c054, 2 }, + [GCC_USB0_SLEEP_CLK_ARES] =3D { 0x2c058, 2 }, + [GCC_USB1_BCR] =3D { 0x3c000 }, + [GCC_USB1_MASTER_CLK_ARES] =3D { 0x3c028, 2 }, + [GCC_USB1_MOCK_UTMI_CLK_ARES] =3D { 0x3c024, 2 }, + [GCC_USB1_PHY_CFG_AHB_CLK_ARES] =3D { 0x3c01c, 2 }, + [GCC_USB1_SLEEP_CLK_ARES] =3D { 0x3c020, 2 }, + [GCC_USB3PHY_0_PHY_BCR] =3D { 0x2c070 }, + [GCC_USB_BCR] =3D { 0x2c000 }, +}; + +static const struct of_device_id gcc_ipq9650_match_table[] =3D { + { .compatible =3D "qcom,ipq9650-gcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_ipq9650_match_table); + +static const struct regmap_config gcc_ipq9650_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x3f024, + .fast_io =3D true, +}; + +static struct clk_hw *gcc_ipq9650_hws[] =3D { + &gpll0_div2.hw, + &gcc_xo_div4_clk_src.hw, + &gcc_qdss_dap_sync_clk_src.hw, + &gcc_eud_at_div_clk_src.hw, +}; + +static const struct qcom_cc_desc gcc_ipq9650_desc =3D { + .config =3D &gcc_ipq9650_regmap_config, + .clks =3D gcc_ipq9650_clocks, + .num_clks =3D ARRAY_SIZE(gcc_ipq9650_clocks), + .resets =3D gcc_ipq9650_resets, + .num_resets =3D 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Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kathiravan Thirumoorthy --- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index b4943123d2e4..5d0855765fdb 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -365,6 +365,11 @@ properties: - qcom,ipq9574-ap-al02-c9 - const: qcom,ipq9574 =20 + - items: + - enum: + - qcom,ipq9650-rdp488 + - const: qcom,ipq9650 + - items: - enum: - qcom,kaanapali-mtp --=20 2.34.1 From nobody Sat Jun 13 11:35:50 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 918E0402B90 for ; Thu, 7 May 2026 17:09:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Kathiravan Thirumoorthy --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq9650-rdp488.dts | 79 ++++++ arch/arm64/boot/dts/qcom/ipq9650.dtsi | 377 ++++++++++++++++++++++++= ++++ 3 files changed, 457 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 4ba8e7306419..dba16311ca2b 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -39,6 +39,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp433.dtb ipq9574-r= dp433-emmc.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp449.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp453.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp454.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9650-rdp488.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D kaanapali-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D kaanapali-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq9650-rdp488.dts b/arch/arm64/boot/= dts/qcom/ipq9650-rdp488.dts new file mode 100644 index 000000000000..6871f3dc4eaf --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9650-rdp488.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "ipq9650.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. IPQ9650 RDP488"; + compatible =3D "qcom,ipq9650-rdp488", "qcom,ipq9650"; + + aliases { + serial0 =3D &uart1; + }; + + chosen { + stdout-path =3D "serial0"; + }; +}; + +&sdhc { + max-frequency =3D <192000000>; + bus-width =3D <4>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + pinctrl-0 =3D <&sdhc_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32000>; +}; + +&tlmm { + qup_uart1_default_state: qup-uart1-default-state { + pins =3D "gpio43", "gpio44"; + function =3D "qup_se6"; + drive-strength =3D <8>; + bias-pull-down; + }; + + sdhc_default_state: sdhc-default-state { + clk-pins { + pins =3D "gpio5"; + function =3D "sdc_clk"; + drive-strength =3D <8>; + bias-disable; + }; + + cmd-pins { + pins =3D "gpio4"; + function =3D "sdc_cmd"; + drive-strength =3D <8>; + bias-pull-up; + }; + + data-pins { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "sdc_data"; + drive-strength =3D <8>; + bias-pull-up; + }; + }; +}; + +&uart1 { + pinctrl-0 =3D <&qup_uart1_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&xo_board { + clock-frequency =3D <24000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq9650.dtsi b/arch/arm64/boot/dts/qc= om/ipq9650.dtsi new file mode 100644 index 000000000000..a1bea8e648cd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9650.dtsi @@ -0,0 +1,377 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&intc>; + + clocks { + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + xo_board: xo-board-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + + l3_0: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-unified; + }; + }; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x100>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_100>; + + l2_100: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x200>; + enable-method =3D "psci"; + + l2_200: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x300>; + enable-method =3D "psci"; + + l2_300: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x400>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_400>; + + l2_400: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + + core4 { + cpu =3D <&cpu4>; + }; + }; + }; + }; + + firmware { + optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + + scm { + compatible =3D "qcom,scm-ipq9650", "qcom,scm"; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0x0 0x80000000 0x0 0x0>; + }; + + pmu-a55 { + compatible =3D "arm,cortex-a55-pmu"; + interrupts =3D ; + }; + + pmu-a78 { + compatible =3D "arm,cortex-a78-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + bootloader@8a100000 { + reg =3D <0x0 0x8a100000 0x0 0x400000>; + no-map; + }; + + smem@8a500000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x8a500000 0x0 0x40000>; + no-map; + + hwlocks =3D <&tcsr_mutex 3>; + }; + + tfa@8a600000 { + reg =3D <0x0 0x8a600000 0x0 0x80000>; + no-map; + }; + + optee@8a680000 { + reg =3D <0x0 0x8a680000 0x0 0x280000>; + no-map; + }; + }; + + soc@0 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-ranges =3D <0 0 0 0 0x10 0>; + ranges =3D <0 0 0 0 0x10 0>; + + tlmm: pinctrl@1000000 { + compatible =3D "qcom,ipq9650-tlmm"; + reg =3D <0x0 0x01000000 0x0 0x300000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 54>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gcc: clock-controller@1800000 { + compatible =3D "qcom,ipq9650-gcc"; + reg =3D <0x0 0x01800000 0x0 0x40000>; + clocks =3D <&xo_board>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + tcsr_mutex: hwlock@1917000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x01917000 0x0 0x57000>; + #hwlock-cells =3D <1>; + }; + + qupv3: geniqup@1ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x01ac0000 0x0 0x2000>; + clocks =3D <&gcc GCC_QUPV3_AHB_MST_CLK>, + <&gcc GCC_QUPV3_AHB_SLV_CLK>; + clock-names =3D "m-ahb", "s-ahb"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + uart1: serial@1a98000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0x0 0x01a98000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP_SE6_CLK>; + clock-names =3D "se"; + interrupts =3D ; + + status =3D "disabled"; + }; + }; + + sdhc: mmc@7804000 { + compatible =3D "qcom,ipq9650-sdhci", "qcom,sdhci-msm-v5"; + reg =3D <0x0 0x07804000 0x0 0x1000>, + <0x0 0x07805000 0x0 0x1000>; + reg-names =3D "hc", + "cqhci"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", + "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; + clock-names =3D "iface", + "core", + "xo"; + non-removable; + + status =3D "disabled"; + }; + + intc: interrupt-controller@f200000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x0f200000 0x0 0x10000>, + <0x0 0x0f240000 0x0 0xa0000>; + #interrupt-cells =3D <0x4>; + interrupt-controller; + #redistributor-regions =3D <1>; + redistributor-stride =3D <0x0 0x20000>; + interrupts =3D ; + mbi-ranges =3D <800 160>; + msi-controller; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity =3D <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity =3D <&cpu4>; + }; + }; + }; + + timer@f420000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0x0f420000 0x0 0x1000>; + ranges =3D <0 0 0 0x10000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + frame@f421000 { + reg =3D <0x0f421000 0x1000>, + <0x0f422000 0x1000>; + interrupts =3D , + ; + frame-number =3D <0>; + }; + + frame@f423000 { + reg =3D <0x0f423000 0x1000>; + interrupts =3D ; + frame-number =3D <1>; + + status =3D "disabled"; + }; + + frame@f425000 { + reg =3D <0x0f425000 0x1000>, + <0x0f426000 0x1000>; + interrupts =3D ; + frame-number =3D <2>; + + status =3D "disabled"; + }; + + frame@f427000 { + reg =3D <0x0f427000 0x1000>; + interrupts =3D ; + frame-number =3D <3>; + + status =3D "disabled"; + }; + + frame@f429000 { + reg =3D <0x0f429000 0x1000>; + interrupts =3D ; + frame-number =3D <4>; + + status =3D "disabled"; + }; + + frame@f42b000 { + reg =3D <0x0f42b000 0x1000>; + interrupts =3D ; + frame-number =3D <5>; + + status =3D "disabled"; + }; + + frame@f42d000 { + reg =3D <0x0f42d000 0x1000>; + interrupts =3D ; + frame-number =3D <6>; + + status =3D "disabled"; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + , + ; + }; +}; --=20 2.34.1