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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexander Duyck , Kees Cook Cc: mike.marciniszyn@gmail.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 1/2] net: pcs: xpcs: Add hooks for xpcs configuration of rsfec Date: Wed, 6 May 2026 15:09:03 -0400 Message-ID: <20260506190904.4029-2-mike.marciniszyn@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260506190904.4029-1-mike.marciniszyn@gmail.com> References: <20260506190904.4029-1-mike.marciniszyn@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "Mike Marciniszyn (Meta)" The DW PCS IP data sheet calls out the need to populate these vendor registers when operating at speeds above 10Gbps. This change enables the correct FEC settings to enable RS-FEC encoding on the link which is the standard used for most links at these higher speeds. Reviewed-by: Alexander Duyck Signed-off-by: Mike Marciniszyn (Meta) --- drivers/net/pcs/pcs-xpcs.c | 82 ++++++++++++++++++++++++++++++++++++++ drivers/net/pcs/pcs-xpcs.h | 6 +++ include/uapi/linux/mdio.h | 3 ++ 3 files changed, 91 insertions(+) diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c index e69fa2f0a0e8..0987621632a7 100644 --- a/drivers/net/pcs/pcs-xpcs.c +++ b/drivers/net/pcs/pcs-xpcs.c @@ -219,6 +219,12 @@ int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg,= u16 val) return mdiodev_c45_write(xpcs->mdiodev, dev, reg, val); } =20 +static int +xpcs_bus_write(struct dw_xpcs *xpcs, int prtad, int dev, u32 reg, u16 val) +{ + return mdiobus_c45_write(xpcs->mdiodev->bus, prtad, dev, reg, val); +} + int xpcs_modify(struct dw_xpcs *xpcs, int dev, u32 reg, u16 mask, u16 set) { return mdiodev_c45_modify(xpcs->mdiodev, dev, reg, mask, set); @@ -1402,6 +1408,78 @@ static int xpcs_read_ids(struct dw_xpcs *xpcs) return 0; } =20 +static int xpcs_get_pma_mmd(struct dw_xpcs *xpcs) +{ + int devs1, b; + + devs1 =3D xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVS1); + if (devs1 < 0) + return devs1; + + /* Locate the PMA closest to the PCS as this should be the one provided + * with the DW IP. This is identified by being the PMA with the + * highest MMD device address. + */ + devs1 &=3D MDIO_DEVS_SEP_PMA1 | MDIO_DEVS_SEP_PMA2 | MDIO_DEVS_SEP_PMA3 | + MDIO_DEVS_SEP_PMA4 | MDIO_DEVS_PMAPMD; + b =3D fls(devs1); + if (b) + return b - 1; + + return -ENODEV; +} + +struct pma_pcs_values { + int lanes; + u16 rsfec_ctrl; +}; + +static int +xpcs_config_rsfec_pma(struct dw_xpcs *xpcs, const struct pma_pcs_values *v) +{ + int ret =3D 0, i, pma_mmd; + + pma_mmd =3D xpcs_get_pma_mmd(xpcs); + if (pma_mmd < 1) + return pma_mmd; + + for (i =3D 0; ret >=3D 0 && i < v->lanes; i++) { + ret =3D xpcs_bus_write(xpcs, i, pma_mmd, MDIO_PMA_RSFEC_CTRL, + v->rsfec_ctrl); + } + return ret; +} + +static int xpcs_25gbaser_pma_config(struct dw_xpcs *xpcs) +{ + const struct pma_pcs_values v =3D { + .rsfec_ctrl =3D 0, + .lanes =3D 1, + }; + + return xpcs_config_rsfec_pma(xpcs, &v); +} + +static int xpcs_50gbaser_pma_config(struct dw_xpcs *xpcs) +{ + const struct pma_pcs_values v =3D { + .rsfec_ctrl =3D DW_VR_RSFEC_CTRL_TC_PAD_ALTER, + .lanes =3D 2, + }; + + return xpcs_config_rsfec_pma(xpcs, &v); +} + +static int xpcs_100gbasep_pma_config(struct dw_xpcs *xpcs) +{ + const struct pma_pcs_values v =3D { + .rsfec_ctrl =3D MDIO_PMA_RSFEC_CTRL_4LANE_PMD, + .lanes =3D 2, + }; + + return xpcs_config_rsfec_pma(xpcs, &v); +} + static const struct dw_xpcs_compat synopsys_xpcs_compat[] =3D { { .interface =3D PHY_INTERFACE_MODE_USXGMII, @@ -1415,6 +1493,7 @@ static const struct dw_xpcs_compat synopsys_xpcs_comp= at[] =3D { .interface =3D PHY_INTERFACE_MODE_25GBASER, .supported =3D xpcs_25gbaser_features, .an_mode =3D DW_AN_C73, + .pma_config =3D xpcs_25gbaser_pma_config, }, { .interface =3D PHY_INTERFACE_MODE_XLGMII, .supported =3D xpcs_xlgmii_features, @@ -1423,14 +1502,17 @@ static const struct dw_xpcs_compat synopsys_xpcs_co= mpat[] =3D { .interface =3D PHY_INTERFACE_MODE_50GBASER, .supported =3D xpcs_50gbaser_features, .an_mode =3D DW_AN_C73, + .pma_config =3D xpcs_50gbaser_pma_config, }, { .interface =3D PHY_INTERFACE_MODE_LAUI, .supported =3D xpcs_50gbaser2_features, .an_mode =3D DW_AN_C73, + .pma_config =3D xpcs_50gbaser_pma_config, }, { .interface =3D PHY_INTERFACE_MODE_100GBASEP, .supported =3D xpcs_100gbasep_features, .an_mode =3D DW_AN_C73, + .pma_config =3D xpcs_100gbasep_pma_config, }, { .interface =3D PHY_INTERFACE_MODE_10GBASER, .supported =3D xpcs_10gbaser_features, diff --git a/drivers/net/pcs/pcs-xpcs.h b/drivers/net/pcs/pcs-xpcs.h index 929fa238445e..187cdec30e70 100644 --- a/drivers/net/pcs/pcs-xpcs.h +++ b/drivers/net/pcs/pcs-xpcs.h @@ -94,6 +94,12 @@ #define DW_VR_MII_DIG_CTRL2_TX_POL_INV BIT(4) #define DW_VR_MII_DIG_CTRL2_RX_POL_INV BIT(0) =20 +/* Clause 133 defines */ +/* RSFEC transcode pad alter + * DW vendor extension in RS-FEC control + */ +#define DW_VR_RSFEC_CTRL_TC_PAD_ALTER BIT(10) + #define DW_XPCS_INFO_DECLARE(_name, _pcs, _pma) \ static const struct dw_xpcs_info _name =3D { .pcs =3D _pcs, .pma =3D _pma= } =20 diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h index b2541c948fc1..5219c877b2cf 100644 --- a/include/uapi/linux/mdio.h +++ b/include/uapi/linux/mdio.h @@ -317,6 +317,9 @@ #define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001 /* FEC ability */ #define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002 /* FEC error indic. ability = */ =20 +/* RSFEC PMA Control register */ +#define MDIO_PMA_RSFEC_CTRL_4LANE_PMD BIT(3) + /* PMA 10GBASE-R Fast Retrain status and control register. */ #define MDIO_PMA_10GBR_FSRT_ENABLE 0x0001 /* Fast retrain enable */ =20 --=20 2.43.0 From nobody Sat May 30 08:45:22 2026 Received: from mail-qk1-f170.google.com (mail-qk1-f170.google.com [209.85.222.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F067F30EF6C for ; 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Wed, 06 May 2026 12:09:08 -0700 (PDT) Received: from PF5YBGDS.localdomain ([163.114.130.1]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-5104090bb03sm157489421cf.10.2026.05.06.12.09.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2026 12:09:08 -0700 (PDT) From: mike.marciniszyn@gmail.com To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexander Duyck , Kees Cook Cc: mike.marciniszyn@gmail.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 2/2] net: pcs: xpcs: Add handling for 4 channel rsfec device Date: Wed, 6 May 2026 15:09:04 -0400 Message-ID: <20260506190904.4029-3-mike.marciniszyn@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260506190904.4029-1-mike.marciniszyn@gmail.com> References: <20260506190904.4029-1-mike.marciniszyn@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "Mike Marciniszyn (Meta)" This patch introduces the configuration of vendor specific registers for alignment encoding, PCS Mode, and VL_INTVL over the one or two instances as required. The DW_PCS IP specification calls out the need to configure both lanes identically when using 2 lane modes such as 50-R2 and 100-R2, so the programming is repeated for each lane. The encoding tables are derived from the IEEE 8023-2022 spec sections 82.2.7 and tables 82-2 and 82-3 for the alignment markers and their insertion. Note that there is a conflict between VRs DW_VR_XS_PCS_DIG_STS and and the DW_PCS_IP DW_VR_MII_PCS_PCS_MODE. The bit mask for DW_VR_XS_PCS_DIG_STS/RX_FIFO_ERR fits within the reserved bits for the DW_PCS IP the DW_VR_MII_PCS_PCS_MODE register so there is no issue. There is also a confict between DW_VR_MII_PCS_VL_INTVL and DW_VR_MII_AN_INTR_STS but an_mode differs, so again there is no issue. Reviewed-by: Alexander Duyck Signed-off-by: Mike Marciniszyn (Meta) --- drivers/net/pcs/pcs-xpcs.c | 90 +++++++++++++++++++++++++++++++++++++- drivers/net/pcs/pcs-xpcs.h | 25 +++++++++++ 2 files changed, 114 insertions(+), 1 deletion(-) diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c index 0987621632a7..c42eacafad91 100644 --- a/drivers/net/pcs/pcs-xpcs.c +++ b/drivers/net/pcs/pcs-xpcs.c @@ -1429,21 +1429,94 @@ static int xpcs_get_pma_mmd(struct dw_xpcs *xpcs) return -ENODEV; } =20 +/* m0 - m2 from Table 82-2/82-3 + * m4 - m6 are skipped since they are inversions of m0 - m2. + * Inverted parity fields (IEEE 82.2.8) bip3 and bip7 are omitted. + */ +struct lane_markers { + u8 m0, m1, m2; +}; + +/* Alignment marker encodings, see table 82-2 in IEEE 802.3-2022 */ +static const struct lane_markers xpcs_100gbaser_markers[] =3D { + {0xc1, 0x68, 0x21}, + {0x9d, 0x71, 0x8e}, + {0x59, 0x4b, 0xe8}, + {0x4d, 0x95, 0x7b}, +}; + +/* Alignment marker encodings, see table 82-3 in IEEE 802.3-2022 + * The content of the 50G markers is identical to 40G values (IEEE 133.2.2= ). + */ +static const struct lane_markers xpcs_50gbaser_markers[] =3D { + {0x90, 0x76, 0x47}, + {0xf0, 0xc4, 0xe6}, + {0xc5, 0x65, 0x9b}, + {0xa2, 0x79, 0x3d}, +}; + struct pma_pcs_values { + const struct lane_markers *vl0_markers; + const struct lane_markers *vl123_markers; int lanes; u16 rsfec_ctrl; + u16 pcs_mode; + u16 vl_intvl; }; =20 +#define XPCS_VL_TO_REG(vl, lh) \ + (((vl) * 2) + DW_VR_MII_PCS_VL0_##lh) + +static int xpcs_write_pcs_prtad(struct dw_xpcs *xpcs, int prtad, int reg, + u16 val) +{ + return xpcs_bus_write(xpcs, prtad, MDIO_MMD_PCS, reg, val); +} + +static int xpcs_config_vl_markers(struct dw_xpcs *xpcs, int vl, int addr, + const struct lane_markers *m) +{ + int ret; + + /* m0, m1, m2 written to _L and _H registers + * + * _L =3D (m1 << 8) | m0 + * _H =3D m2 + */ + ret =3D xpcs_write_pcs_prtad(xpcs, addr, XPCS_VL_TO_REG(vl, L), + ((u16)m->m1 << 8) | m->m0); + if (ret < 0) + return ret; + return xpcs_write_pcs_prtad(xpcs, addr, XPCS_VL_TO_REG(vl, H), m->m2); +} + static int xpcs_config_rsfec_pma(struct dw_xpcs *xpcs, const struct pma_pcs_values *v) { - int ret =3D 0, i, pma_mmd; + int ret =3D 0, i, vl, pma_mmd; =20 pma_mmd =3D xpcs_get_pma_mmd(xpcs); if (pma_mmd < 1) return pma_mmd; =20 for (i =3D 0; ret >=3D 0 && i < v->lanes; i++) { + /* code word markings */ + for (vl =3D 0; ret >=3D 0 && vl < 4; vl++) + ret =3D xpcs_config_vl_markers(xpcs, vl, i, + !vl ? &v->vl0_markers[0] : + &v->vl123_markers[vl - 1]); + if (ret < 0) + break; + /* vendor registers */ + ret =3D xpcs_write_pcs_prtad(xpcs, i, DW_VR_MII_PCS_VL_INTVL, + v->vl_intvl); + if (ret < 0) + break; + ret =3D xpcs_write_pcs_prtad(xpcs, i, DW_VR_MII_PCS_PCS_MODE, + v->pcs_mode); + if (ret < 0) + break; + /* rsfec register */ ret =3D xpcs_bus_write(xpcs, i, pma_mmd, MDIO_PMA_RSFEC_CTRL, v->rsfec_ctrl); } @@ -1455,6 +1528,13 @@ static int xpcs_25gbaser_pma_config(struct dw_xpcs *= xpcs) const struct pma_pcs_values v =3D { .rsfec_ctrl =3D 0, .lanes =3D 1, + /* 25g markers from 100g and 50g tables per 802.3-2022 + * 108.5.2.4 + */ + .vl0_markers =3D &xpcs_100gbaser_markers[0], + .vl123_markers =3D &xpcs_50gbaser_markers[1], + .vl_intvl =3D 20479, + .pcs_mode =3D DW_VR_MII_PCS_MODE_CLAUSE107, }; =20 return xpcs_config_rsfec_pma(xpcs, &v); @@ -1465,6 +1545,10 @@ static int xpcs_50gbaser_pma_config(struct dw_xpcs *= xpcs) const struct pma_pcs_values v =3D { .rsfec_ctrl =3D DW_VR_RSFEC_CTRL_TC_PAD_ALTER, .lanes =3D 2, + .vl0_markers =3D &xpcs_50gbaser_markers[0], + .vl123_markers =3D &xpcs_50gbaser_markers[1], + .pcs_mode =3D 0, + .vl_intvl =3D 20479, }; =20 return xpcs_config_rsfec_pma(xpcs, &v); @@ -1475,6 +1559,10 @@ static int xpcs_100gbasep_pma_config(struct dw_xpcs = *xpcs) const struct pma_pcs_values v =3D { .rsfec_ctrl =3D MDIO_PMA_RSFEC_CTRL_4LANE_PMD, .lanes =3D 2, + .vl0_markers =3D &xpcs_100gbaser_markers[0], + .vl123_markers =3D &xpcs_100gbaser_markers[1], + .pcs_mode =3D DW_VR_MII_PCS_MODE_DISABLE_MLD, + .vl_intvl =3D 16383, }; =20 return xpcs_config_rsfec_pma(xpcs, &v); diff --git a/drivers/net/pcs/pcs-xpcs.h b/drivers/net/pcs/pcs-xpcs.h index 187cdec30e70..8161d75370e6 100644 --- a/drivers/net/pcs/pcs-xpcs.h +++ b/drivers/net/pcs/pcs-xpcs.h @@ -100,6 +100,31 @@ */ #define DW_VR_RSFEC_CTRL_TC_PAD_ALTER BIT(10) =20 +/* Vendor specific 4 channel PCS registers */ + +/* DW_VR_MII_PCS_VL_INTVL and DW_VR_MII_AN_INTR_STS conflict + * but code paths are different + */ +#define DW_VR_MII_PCS_VL_INTVL 0x8002 +/* 0x8008 - 0x800f */ +#define DW_VR_MII_PCS_VL0_L 0x8008 +#define DW_VR_MII_PCS_VL0_H 0x8009 +#define DW_VR_MII_PCS_PCS_MODE 0x8010 + +/* DW_VR_MII_PCS_PCS_MODE bits */ +#define DW_VR_MII_PCS_MODE_HI_BER25 BIT(2) +#define DW_VR_MII_PCS_MODE_DISABLE_MLD BIT(1) +#define DW_VR_MII_PCS_MODE_CLAUSE49 BIT(0) + +/* 25G requires these two bits are set. + * + * The CLAUSE49 bit changes the interface with the MAC + * to 64 bit and the BER25 bit changes the measurement + * interval to 2ms. + */ +#define DW_VR_MII_PCS_MODE_CLAUSE107 \ + (DW_VR_MII_PCS_MODE_HI_BER25 | DW_VR_MII_PCS_MODE_CLAUSE49) + #define DW_XPCS_INFO_DECLARE(_name, _pcs, _pma) \ static const struct dw_xpcs_info _name =3D { .pcs =3D _pcs, .pma =3D _pma= } =20 --=20 2.43.0