From nobody Sat Jun 13 16:24:25 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4358A3ED12D; Wed, 6 May 2026 15:25:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778081123; cv=none; b=eL3Xh6EmtA/kpebIVSG0UPmP38AT2AZWMH6a58IfEWpUaqhyijTkolvmN5UO/fQCaI/2GweL5eejo/nkciSebDqjQscOMSdfrDWe9PKTjyEoZxghYGoyfSGG0RVKEAdjrLVZ3h2lkZA9L+YARgUI0O9v7PC+DBe0ktyfB1ajWFE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778081123; c=relaxed/simple; bh=hY++APyd3XZbnN5q3LQICWZ+d1vEmEnd5lJnusDw0jA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=StugWU9ER4aiZTUEHcJRCshR3d+z2PD5S4dDieoYjkcg6rW2yAGlni4P14EisbAQa0cYueRCY1enC0BGFk7IaOnDj67H1lo9osn/+b1WetzVPQ5uqsUV1VAgv8HD7gpU6XTNmNah97iI/XJ47xzzNcENrjmKN8QhHmSnj4HsiQc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=hllE0yxF; arc=none smtp.client-ip=117.135.210.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="hllE0yxF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=qC WWMFDSN/kOWR8DlFD6me9GCJ5creIxlg4thZxsX2U=; b=hllE0yxFT8/hsbJuSi 2R7v+UgjAVdFGNBZ5Vp9+HdWrR3NGVK2rjNvfG10npkPNWUV1nU7v7Fh406x5nQk YjPykxbwcybUus+apz8TalWSYNz8gDgz/tSxlf/8ZfwLCpzYpGohHZtzV23NGo5F mHgKLs2cp4Krvtp6/Bgu2LBdo= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g0-0 (Coremail) with SMTP id _____wCHAqsXXftpv5CgDg--.43926S3; Wed, 06 May 2026 23:24:10 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, vigneshr@ti.com, jingoohan1@gmail.com, thomas.petazzoni@bootlin.com, pali@kernel.org, ryder.lee@mediatek.com, jianjun.wang@mediatek.com, claudiu.beznea.uj@bp.renesas.com, mpillai@cadence.com Cc: robh@kernel.org, s-vadapalli@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 1/8] PCI: Add pcie_wait_after_link_train() helper Date: Wed, 6 May 2026 23:23:39 +0800 Message-Id: <20260506152346.166056-2-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260506152346.166056-1-18255117159@163.com> References: <20260506152346.166056-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wCHAqsXXftpv5CgDg--.43926S3 X-Coremail-Antispam: 1Uf129KBjvJXoW7Cr15uw48KF43tFWkXr4kXrb_yoW8Xw45pa 93CF10kr48XFy3Xws3Ja43WFyYvan3Kay7GrZ7G347KFy7J3W3tF40g3y3Wrnaqrs5Zr13 Jw15Kw17CF4YkFJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pif-BAUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxBq2Wmn7XRo4wQAA3e Content-Type: text/plain; charset="utf-8" PCIe r6.0, sec 6.6.1 (Conventional Reset) requires that for a Downstream Port supporting Link speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link training completes before sending any Configuration Request. Introduce a static inline helper pcie_wait_after_link_train() that checks the given max_link_speed (2 =3D 5.0 GT/s, 3 =3D 8.0 GT/s, etc.) and calls msleep(100) only when the speed is greater than 5.0 GT/s. The helper uses the existing PCIE_RESET_CONFIG_WAIT_MS macro defined in pci.h. This allows multiple host controller drivers to share the same mandatory delay without duplicating the logic. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/pci.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 4a14f88e543a..a8705a2a2d85 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -60,6 +60,19 @@ struct pcie_tlp_log; */ #define PCIE_RESET_CONFIG_WAIT_MS 100 =20 +/** + * pcie_wait_after_link_train - Wait 100 ms if link speed > 5 GT/s + * @max_link_speed: the maximum link speed (2 =3D 5.0 GT/s, 3 =3D 8.0 GT/s= , ...) + * + * Must be called after Link training completes and before the first + * Configuration Request is sent. + */ +static inline void pcie_wait_after_link_train(int max_link_speed) +{ + if (max_link_speed > 2) + msleep(PCIE_RESET_CONFIG_WAIT_MS); +} + /* Parameters for the waiting for link up routine */ #define PCIE_LINK_WAIT_MAX_RETRIES 10 #define PCIE_LINK_WAIT_SLEEP_MS 90 --=20 2.34.1 From nobody Sat Jun 13 16:24:25 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2EA0647DD75; Wed, 6 May 2026 15:25:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778081122; cv=none; b=JZSOTV4G2kKurWqKsbc9V8Mnz+PMpl9xEaTGnqVd2Va6MpeQc0fCIyFaP43Crph0MOtJrc5FsJgRBuqmJRlOwEYH21b5lOxP9adIjxtvsOGddcPnwi1KNF3P4/wzkTa6Z6uacElnCOeFtmpJv0FEBLT2s5o/OlVIyIjZQ1CWboU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778081122; c=relaxed/simple; bh=EwX5vw8flnwTRgHgywLKXc0U4GS3nY6wv8fQ5S7ddKU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZeRhqJ6yXR0tmVKzuKb3mJBpb5zYlIKoV4ma4JJB1BgBIKKEnU0V+8WdaKbd9cB/Ki2Wc2fKNPmH6rYh2Rn+qckANollMN/cBLBPMbeu46C3NIMK6BoLfIW7sdks0r6JloyRSqYzyVnDKg80IWRpySl/V+4NyZGJmei/t3pK19I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=lgrgDVct; arc=none smtp.client-ip=220.197.31.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="lgrgDVct" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=BN GiJZhgTLPluypgzeJ1aG/d9sbWAAhxnbKSoRw5x1o=; b=lgrgDVctqQNdhZIm1t PcEbxw4/HmqAapBQyeaO8ydZ1v915P9ACRci6PFsg1rsX/KPMVEbYTfocgsylCtR u6Gce0AmIoirQwtAuLx8wuzT5nrymkOjbCKp1BRUrhDHT3oWq3Qb9zfcWFVpoKSQ 75ceAByEc1iuse/J93QGXRVH4= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g0-0 (Coremail) with SMTP id _____wCHAqsXXftpv5CgDg--.43926S4; Wed, 06 May 2026 23:24:11 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, vigneshr@ti.com, jingoohan1@gmail.com, thomas.petazzoni@bootlin.com, pali@kernel.org, ryder.lee@mediatek.com, jianjun.wang@mediatek.com, claudiu.beznea.uj@bp.renesas.com, mpillai@cadence.com Cc: robh@kernel.org, s-vadapalli@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 2/8] PCI: cadence: LGA: Add max_link_speed field and 100 ms delay after link training Date: Wed, 6 May 2026 23:23:40 +0800 Message-Id: <20260506152346.166056-3-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260506152346.166056-1-18255117159@163.com> References: <20260506152346.166056-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wCHAqsXXftpv5CgDg--.43926S4 X-Coremail-Antispam: 1Uf129KBjvJXoW7ZFWfZryUWw43Wr43uw17ZFb_yoW5JFWfpa yDWryfGF1IqrWY9a1kZa4UXryaq3Z8C347tws2k34xWr17CrW5JF42gF1fJFy3KrZrZry7 ZF1DtF9rGr4ayFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0ziM7KxUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxBu2Wmn7XRs43gAA3B Content-Type: text/plain; charset="utf-8" The Cadence LGA (Legacy Architecture IP) PCIe host controller currently lacks the mandatory 100 ms delay after link training completes for speeds > 5.0 GT/s, as required by PCIe r6.0 sec 6.6.1. Add a 'max_link_speed' field to struct cdns_pcie to record the maximum supported link speed (or the currently configured speed). In the common host layer function cdns_pcie_host_start_link(), after the link has been successfully established, call pcie_wait_after_link_train() to insert the required delay if max_link_speed > 2. Glue drivers must set max_link_speed appropriately (e.g., from the device tree property "max-link-speed") to enable the delay. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/cadence/pcie-cadence-host-common.c | 4 ++++ drivers/pci/controller/cadence/pcie-cadence.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.c b/dr= ivers/pci/controller/cadence/pcie-cadence-host-common.c index 2b0211870f02..51376f69d007 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host-common.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c @@ -14,6 +14,7 @@ =20 #include "pcie-cadence.h" #include "pcie-cadence-host-common.h" +#include "../../pci.h" =20 #define LINK_RETRAIN_TIMEOUT HZ =20 @@ -115,6 +116,9 @@ int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc, if (!ret && rc->quirk_retrain_flag) ret =3D cdns_pcie_retrain(pcie, pcie_link_up); =20 + if (!ret) + pcie_wait_after_link_train(pcie->max_link_speed); + return ret; } EXPORT_SYMBOL_GPL(cdns_pcie_host_start_link); diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index 574e9cf4d003..e222b095d2b6 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -86,6 +86,7 @@ struct cdns_plat_pcie_of_data { * @ops: Platform-specific ops to control various inputs from Cadence PCIe * wrapper * @cdns_pcie_reg_offsets: Register bank offsets for different SoC + * @max_link_speed: maximum supported link speed */ struct cdns_pcie { void __iomem *reg_base; @@ -98,6 +99,7 @@ struct cdns_pcie { struct device_link **link; const struct cdns_pcie_ops *ops; const struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets; + int max_link_speed; }; =20 /** --=20 2.34.1 From nobody Sat Jun 13 16:24:25 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B7177481223; Wed, 6 May 2026 15:25:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778081122; cv=none; b=J1XmFVcY3ANwklZZgLHtqunyDOSNtjh2PRQgEuNbFb4x11MKSXQSaqgZRXypopkwxxKv601nBiRple3YQ9Ga5vNZJolHd/8QFk+95O33HizcRYuvSqUHiTrnxEGJPXl012qeXC9aCvrwHQKWDqjU5Gx4F6XyCFN3f5/jpNVxLiA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778081122; c=relaxed/simple; bh=uydKpHM9iyYMDP1LK8ft6FSruCHVzkFjBG6Cab8j0AY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=lQVXlmZ6mYoVunZiLrm7S8CSEF/B6eoTko3j3BxtFjIeVGkkXu9vDPSQXGeXFQ5bqDgK2UcAqWcGv6vQ5tQ0oSDMW4oksLflu/g1P/oW9+dZdKPLK3Y+NRy33ilF1iNFUa55h+9rRm/DQVAhcPUhP038FuGk3NZz1AeRKFHNZzI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=JFRLZgkF; arc=none smtp.client-ip=117.135.210.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="JFRLZgkF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=Ls zCurdEFO+gZG00jUn6BF5va881gN4RYCn+EeYYN5U=; b=JFRLZgkFncbn0mZNVg bgNHubQd2aPL4LijHJB40HyofKtgnKXK/l/zOe/rxEUlfEd81kJOJUgRm0+pP/OV P+jjvmAXcXOFBsV5KwowqixbwwbfdRbSKDDHtyQ2drM4edrLxursidDltRtTZVYg 1b40+r7YCxWL/6hNT6OdZz2S0= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g0-0 (Coremail) with SMTP id _____wCHAqsXXftpv5CgDg--.43926S5; Wed, 06 May 2026 23:24:12 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, vigneshr@ti.com, jingoohan1@gmail.com, thomas.petazzoni@bootlin.com, pali@kernel.org, ryder.lee@mediatek.com, jianjun.wang@mediatek.com, claudiu.beznea.uj@bp.renesas.com, mpillai@cadence.com Cc: robh@kernel.org, s-vadapalli@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 3/8] PCI: cadence: HPA: Add 100 ms delay after link training Date: Wed, 6 May 2026 23:23:41 +0800 Message-Id: <20260506152346.166056-4-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260506152346.166056-1-18255117159@163.com> References: <20260506152346.166056-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wCHAqsXXftpv5CgDg--.43926S5 X-Coremail-Antispam: 1Uf129KBjvJXoW7ZF1xur47GryfZF47ZFy3XFb_yoW8XF18pa yDGF1xCF1xZr4Y9an5A3W3Xr1aqasxA3srt3yv9w1xZF9xCrWDtF4IgF13Xa45KFZFvr17 Xw1DtF9rGr45ZFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07U1SoXUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCwx23W2n7XR0yzQAA3f Content-Type: text/plain; charset="utf-8" The Cadence HPA (High Performance Architecture IP) specific link setup function cdns_pcie_hpa_host_link_setup() waits for the link to come up but does not implement the required 100 ms delay after link training completes for speeds > 5.0 GT/s (PCIe r6.0 sec 6.6.1). Add a call to pcie_wait_after_link_train() immediately after the link is confirmed to be up, using the max_link_speed previously stored in struct cdns_pcie. This ensures compliance with the specification regardless of whether the HPA or LGA path is used. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/cadence/pcie-cadence-host-hpa.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c b/drive= rs/pci/controller/cadence/pcie-cadence-host-hpa.c index 0f540bed58e8..62e939906785 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c @@ -15,6 +15,7 @@ =20 #include "pcie-cadence.h" #include "pcie-cadence-host-common.h" +#include "../../pci.h" =20 static u8 bar_aperture_mask[] =3D { [RP_BAR0] =3D 0x3F, @@ -304,6 +305,8 @@ int cdns_pcie_hpa_host_link_setup(struct cdns_pcie_rc *= rc) ret =3D cdns_pcie_host_wait_for_link(pcie, cdns_pcie_hpa_link_up); if (ret) dev_dbg(dev, "PCIe link never came up\n"); + else + pcie_wait_after_link_train(pcie->max_link_speed); =20 return ret; } --=20 2.34.1 From nobody Sat Jun 13 16:24:25 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8922E47CC80; Wed, 6 May 2026 15:25:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778081122; cv=none; b=EEFSq3OMG4YuZp9BV0mGescbMn6o3Bhr6UBbrr1qyLBESC+ixvjVNqeo0q4X7KtnQiDhaSN1mP8sXlXsKbF2C5pwkT/ZCqzxcyyl4CnsH1ypZZrzc0Y7dAGoY/AGItW/x0BAxwzIWHImZYFg4bubCOxwLDNX+7KkXpU/z+ZE+PM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778081122; c=relaxed/simple; bh=hOvMa018kLpNbaWX7Zza3kl+vca409Z0VW8vMXcwSVs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=G1ZV3NRqc52l6lYYCW4FFG3ch2XJtfr+G4RSP3pw7Nf6A2t3X4BSk1Y3Au+aKf/gIMp/SXUAFil5lhvHIZWFqxaAhYLTxn7BNNRoAiQpFIPN+MnSpNExhMJdgE2yRE2xm3ybymC0c60CPyUuhaEIFPIG0kT/G1SuLlIl5UVqToQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=mMb9kc89; arc=none smtp.client-ip=117.135.210.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="mMb9kc89" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=uE EJQ9fXszYfwRyDtR6o0/pUHqmq54B1aA4O008XVv8=; b=mMb9kc89cru2itfUkh Eh2md/CTuLPUpRJN1UCaVC+R7gJg/05zaFVf6MN375fUdxTcEbLRvm5HGyFiq31g C8tU96NjI4ZuPrcQSVMbckGSM6JiREeQqRoa5JbpvmbpVJG2G04HE0b46cM2H5az 7D+Snzwl538eCInoaS0sk74dM= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g0-0 (Coremail) with SMTP id _____wCHAqsXXftpv5CgDg--.43926S6; Wed, 06 May 2026 23:24:13 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, vigneshr@ti.com, jingoohan1@gmail.com, thomas.petazzoni@bootlin.com, pali@kernel.org, ryder.lee@mediatek.com, jianjun.wang@mediatek.com, claudiu.beznea.uj@bp.renesas.com, mpillai@cadence.com Cc: robh@kernel.org, s-vadapalli@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 4/8] PCI: j721e: Set max_link_speed to enable 100 ms delay after link up Date: Wed, 6 May 2026 23:23:42 +0800 Message-Id: <20260506152346.166056-5-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260506152346.166056-1-18255117159@163.com> References: <20260506152346.166056-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wCHAqsXXftpv5CgDg--.43926S6 X-Coremail-Antispam: 1Uf129KBjvJXoW7uF17Jr4UXrWkZF1xZFy5urg_yoW8Gr1xpa y7GFWxG3WIqFW5uanrZ3W5XFyaqFn8J3y7GrZag3WxZFnxCr93JFyIqFyfJ3yfKF4kAF17 A3Zrt342qr43tF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zEt8ncUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxB63W2n7XR45DgAA3Q Content-Type: text/plain; charset="utf-8" Set cdns_pcie.max_link_speed to the maximum supported link speed (obtained from the device tree property "max-link-speed") in j721e_pcie_set_link_speed(). This activates the post-link delay logic added in cdns_pcie_host_start_link() when the controller supports speeds greater than 5 GT/s. As required by PCIe r6.0 sec 6.6.1, and following the same approach as commit 80dc18a0cba8d ("PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link up"), this ensures a 100 ms delay after link training completes before any Configuration Request is sent. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/cadence/pci-j721e.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/contr= oller/cadence/pci-j721e.c index bfdfe98d5aba..ee85b8e04f5b 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -206,6 +206,7 @@ static int j721e_pcie_set_link_speed(struct j721e_pcie = *pcie, (pcie_get_link_speed(link_speed) =3D=3D PCI_SPEED_UNKNOWN)) link_speed =3D 2; =20 + pcie->cdns_pcie.max_link_speed =3D link_speed; val =3D link_speed - 1; ret =3D regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val); if (ret) --=20 2.34.1 From nobody Sat Jun 13 16:24:25 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20A2A49219C; Wed, 6 May 2026 15:25:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778081125; cv=none; b=Q4ptf/NmqNYFQWUcUst/XwlBpsf7YRT5Vm275ACa8dyw/qoB9OflSZxprGk/Y8/Y0PtvJILTMdwsjEYnK38zNhmoq92KKP52WxO4BNIcTDjFjczBVGDI7O7qZunC70Khu7QbL0Fmx/wK6he/dJk8hWdJOX4KrJSfEN0ea5BGoR4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778081125; c=relaxed/simple; bh=G0FMgyUyO0ZfGOOdQVnL8bDKgkjDFXxYECNke1oaX4g=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=N0dCoQgiMv7iHVih1kzX7eQzaq3bSG/v7xSLIPJTH3XUtQAE7OUX1Yxr80NxjlGOtXixkRt5Ty13dJuDavqkKga/FvRaCXnjm5IXq7bnGjuRobthsGIfTCwlUgjN7ytHFMy8CzlhNYBenzJXsSkBlcOxg5U0h4e3Yxvpik17A7w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=ORxpGjQJ; arc=none smtp.client-ip=117.135.210.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="ORxpGjQJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=8f YT+L8xujiw5+/Qen2DspUJWPjgtV6UMGsDVRY0cUw=; b=ORxpGjQJCvXUb8Tvix QGSzijb+F36amAMRqRzzmnASTnmVEvZHKV9f3uyBrtOUd8BgKDstr1CoimQHhbyt BxulBaoF81LkfW9Ggaf12Uj6s7SohMZq43+mdkMyT7FwQ06bSfaqckw+1nX365Fb lavDSZktYOnJS761Hljeyu6dk= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g0-0 (Coremail) with SMTP id _____wCHAqsXXftpv5CgDg--.43926S7; Wed, 06 May 2026 23:24:14 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, vigneshr@ti.com, jingoohan1@gmail.com, thomas.petazzoni@bootlin.com, pali@kernel.org, ryder.lee@mediatek.com, jianjun.wang@mediatek.com, claudiu.beznea.uj@bp.renesas.com, mpillai@cadence.com Cc: robh@kernel.org, s-vadapalli@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 5/8] PCI: dwc: Use common pcie_wait_after_link_train() helper Date: Wed, 6 May 2026 23:23:43 +0800 Message-Id: <20260506152346.166056-6-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260506152346.166056-1-18255117159@163.com> References: <20260506152346.166056-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wCHAqsXXftpv5CgDg--.43926S7 X-Coremail-Antispam: 1Uf129KBjvJXoW7tw1rAFW7WryDZw4xXw4DCFg_yoW8Grykpa 98JF4FkFy8JF43ua1DC3Z3ury5X3ZxArW7GFZ3Wa4fZa47ArZFqr10q34Sq34xXrsFvr1a qr17tF17GwsrAF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0piI38bUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxB+3W2n7XR85JgAA34 Content-Type: text/plain; charset="utf-8" The DWC driver already implements the 100 ms delay required by PCIe r6.0 sec 6.6.1 by checking pci->max_link_speed and calling msleep(100). Replace the open-coded msleep() with the new common helper pcie_wait_after_link_train() to reduce code duplication and improve maintainability. No functional change intended. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-designware.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index c11cf61b8319..e5808d4b3867 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -799,13 +799,7 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci) return -ETIMEDOUT; } =20 - /* - * As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link - * speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms - * after Link training completes before sending a Configuration Request. - */ - if (pci->max_link_speed > 2) - msleep(PCIE_RESET_CONFIG_WAIT_MS); + pcie_wait_after_link_train(pci->max_link_speed); =20 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); val =3D dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); --=20 2.34.1 From nobody Sat Jun 13 16:24:25 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C5F8305E32; Wed, 6 May 2026 15:25:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778081121; cv=none; b=XY6dGPAiPkICaSVVGPKdl0R6TT4jQO6FP8Wf9KAfXZxBfe6cS53rVh0B0eYvtlHyiiK8OEf8jHDjyjBq+208otv2dfL4lFgkRCu6fR5eQ8W/wLt4fuW7leCD+gXnq/60HsrqLZGCxgHJWngaklfYUQp1SqpHbXTUb5DhRgO2SoI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778081121; c=relaxed/simple; bh=8RSvHgYPL2alwIZrECLHiUWVHieN2Z9SRt7jPvr24Nw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=t/BSZEQuOl1RQoL1V9Bbhgq3KXB3utBDIpn5n/i5BzWmsHquoXQwYSHDkBct9HMQIpkB8oG4GT0e94ncHn7EJV+46Q1PjOCEXd+2IR/LQo9T4uMd1EaN+chkTm1rpjeHRPpWRpbTdf11+yuX+RKYGAvLzRtEv+fBrNuZrxTZbsA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=TPY5+qpw; arc=none smtp.client-ip=117.135.210.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="TPY5+qpw" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=tp 7iBmKEeToHBfnghM1mY5+mcwB0MOqh5PUwFfpbteU=; b=TPY5+qpwXptAnLUh8Q EDOo86MRSINt0ckXXgtI7UP+/Y79denmZwR6kiQUrUN+y6QvMoit0jQOAiqg/95J I83z1sZ9bVyuccU7RPhaZ8qzJUhau+WQ+SwXfdxWuYtlV6IpJ6DDYvtCr+X2sAz3 UJSF6msBQxTZzfHebcedC/n/g= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g0-0 (Coremail) with SMTP id _____wCHAqsXXftpv5CgDg--.43926S8; Wed, 06 May 2026 23:24:15 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, vigneshr@ti.com, jingoohan1@gmail.com, thomas.petazzoni@bootlin.com, pali@kernel.org, ryder.lee@mediatek.com, jianjun.wang@mediatek.com, claudiu.beznea.uj@bp.renesas.com, mpillai@cadence.com Cc: robh@kernel.org, s-vadapalli@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 6/8] PCI: aardvark: Add 100 ms delay after link training Date: Wed, 6 May 2026 23:23:44 +0800 Message-Id: <20260506152346.166056-7-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260506152346.166056-1-18255117159@163.com> References: <20260506152346.166056-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wCHAqsXXftpv5CgDg--.43926S8 X-Coremail-Antispam: 1Uf129KBjvJXoW7Jw48Gr13Zr1UKFW8Ww4fGrg_yoW8Jr4Dpa y3GF97KF1ktr43ua1UAayfWFy3WanI9a47Jrn7Kw13ZF9xWrWUGr1j9393KFnIyw4vvr13 G3W3ta4xCa13Za7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zEubyiUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC7AC4XGn7XSDh8QAA33 Content-Type: text/plain; charset="utf-8" The Aardvark PCIe controller driver waits for the link to come up but does not implement the mandatory 100 ms delay after link training completes for speeds greater than 5.0 GT/s (PCIe r6.0 sec 6.6.1). The driver already maintains a 'link_gen' field that holds the negotiated link speed. Use it together with pcie_wait_after_link_train() to insert the required delay immediately after confirming that the link is up. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/pci-aardvark.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller= /pci-aardvark.c index e34bea1ff0ac..526351c21c49 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -350,8 +350,10 @@ static int advk_pcie_wait_for_link(struct advk_pcie *p= cie) =20 /* check if the link is up or not */ for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { - if (advk_pcie_link_up(pcie)) + if (advk_pcie_link_up(pcie)) { + pcie_wait_after_link_train(pcie->link_gen); return 0; + } =20 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); } --=20 2.34.1 From nobody Sat Jun 13 16:24:25 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50A1D4949E3; Wed, 6 May 2026 15:25:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778081126; cv=none; b=laXSQpY/FnWxfXDbBu4lmamR/BCU/EnmPSj9H7GeBkg2B/62bnnODfbLK+R3UaxhtA7hOWV03zH3+QAnti7rOLi04U3rxTToT4MIL07+DWVPU0Jsi4oBt+zPOYB7l19Vf+hdYkungbF7EmnQQJjAUqLVGbhxG7pbCpuo+cAbrBI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778081126; c=relaxed/simple; bh=mpv3vlGZm+Ok6QVRvcIV33SeSqsLagci5BU4xYX168c=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NCJ8jiLiQsCXueas41Gj82ec4hBYu3uWPBT+7aouRoV2RV/bRZUw8Iy8Zog5eMESMbFP3g0CBQzsd0zTIOx7cRs8G/8s8tlqW81ZZGk87bTD3ywEfxqWyRI+js3TSUWdvVStulItIFIVISpKphnnGkFPJM4VtRWw+NRv7IdThD8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=hDDHTfQz; arc=none smtp.client-ip=117.135.210.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="hDDHTfQz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=sr is0xyiMLfYPD6D/YefkQkhGzEH93jUaJ4nBZ/Loa0=; b=hDDHTfQzz2ffofBWZ6 MMO1lj9A9H/9vDW4NbQFBR/f8Xw7UUFwfkt8GvaLmvh5Hx8u21aeOzXk27XcU+rD huHoO115HRJ9ERdNVq5Db1hOUD9Io3ook8IBV7imAu6TVHzcEbjgNG7e7A/iz6/+ 3fabcJ6BJK/JGoeQ6yLk2bLk0= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g0-0 (Coremail) with SMTP id _____wCHAqsXXftpv5CgDg--.43926S9; Wed, 06 May 2026 23:24:17 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, vigneshr@ti.com, jingoohan1@gmail.com, thomas.petazzoni@bootlin.com, pali@kernel.org, ryder.lee@mediatek.com, jianjun.wang@mediatek.com, claudiu.beznea.uj@bp.renesas.com, mpillai@cadence.com Cc: robh@kernel.org, s-vadapalli@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 7/8] PCI: mediatek-gen3: Add 100 ms delay after link training Date: Wed, 6 May 2026 23:23:45 +0800 Message-Id: <20260506152346.166056-8-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260506152346.166056-1-18255117159@163.com> References: <20260506152346.166056-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wCHAqsXXftpv5CgDg--.43926S9 X-Coremail-Antispam: 1Uf129KBjvdXoW7Jr4kWw4fAw18WF4rJF1kZrb_yoWDArXE9a y8JrWfZay5Cry5CFnayFyrZr9aya47Wr18XayrKFnxZa48ur9Yqr9IvryDXFs5Gw4aqF17 tryqyF18uFyDAjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7xRufOztUUUUU== X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC7AG4XGn7XSHiCgAA3P Content-Type: text/plain; charset="utf-8" The MediaTek Gen3 PCIe host driver lacks the required 100 ms delay after link training completes for speeds > 5.0 GT/s, as specified in PCIe r6.0 sec 6.6.1. The driver already stores max_link_speed (from the device tree). After mtk_pcie_startup_port() successfully brings up the link, call pcie_wait_after_link_train() to comply with the specification. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/pcie-mediatek-gen3.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index b0accd828589..7c5f2ba7157b 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -570,6 +570,8 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *= pcie) goto err_power_down_device; } =20 + pcie_wait_after_link_train(pcie->max_link_speed); + return 0; =20 err_power_down_device: --=20 2.34.1 From nobody Sat Jun 13 16:24:25 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1DE2481A82; Wed, 6 May 2026 15:25:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778081125; cv=none; b=sf1PVkgdrmAHr78u0hlT9/QiqzwDbTS7pBSK7qnF9zoAgkeix02Qh52pv+fDsMe7O+cyqiNOTCsOJQzSa3ZH9+6JKcTvIsVff0mcwZa1J1+slL8K8RQ2PniZvLk4O3mDdJBkurvyH2Xfs0Y6QXfTrsIY+CbBpnWEiEQjkIjZ6Zg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778081125; c=relaxed/simple; bh=GhIUQhK/ACVD4fdxZ164YUvoWXZbPzyuCKLehj/SzdA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DvD0WhqSRoSQWEYqP1CvWcyVvHhVcoXYGQe/FyJ/6btMUVcADnxgAJg3NZNv7ojAKT02poCULUSVmamA+k8tblnPxmHNQsY2Cvk4UmAFZNAibnAyNGe5414mUOitTC08DzabtYo/kWDXOEiBbV4ri68uD6ngbz1650KEwXuVOiQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=joWJy+qj; arc=none smtp.client-ip=220.197.31.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="joWJy+qj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=pD yIM4BKweQBnCpgrNGgNcV7Vbp6Q+A8dmpeii+IQGo=; b=joWJy+qjTJCNktMpzt ZqXslnzQhJb1oT/i6kVzHaxMfME0l3i7P69BPzq7402unsiX/DLgq1c7c5w8Opts FeoNmeCBC/CLmqIJVT+84XHBaEZAvXAOhCVNxaV+0C4teOKBqAIAArIXYq1xkeFU 2WIITz0TSsY1VyPDzjF9cu12o= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g0-4 (Coremail) with SMTP id _____wAXH5wkXftpfKPsDg--.7909S2; Wed, 06 May 2026 23:24:21 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, vigneshr@ti.com, jingoohan1@gmail.com, thomas.petazzoni@bootlin.com, pali@kernel.org, ryder.lee@mediatek.com, jianjun.wang@mediatek.com, claudiu.beznea.uj@bp.renesas.com, mpillai@cadence.com Cc: robh@kernel.org, s-vadapalli@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 8/8] PCI: rzg3s-host: Add 100 ms delay after link training Date: Wed, 6 May 2026 23:23:46 +0800 Message-Id: <20260506152346.166056-9-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260506152346.166056-1-18255117159@163.com> References: <20260506152346.166056-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wAXH5wkXftpfKPsDg--.7909S2 X-Coremail-Antispam: 1Uf129KBjvdXoWrtr1DXw47ZryDZFy8XryfCrg_yoWkurg_u3 9xCFn7Aw4UGr9akF12y34rZryYy342qr10qa10vF13ta4I9r1rXw1fZF4jy3WUWa15JFyv yryqyr109r9rujkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7xRM7KItUUUUU== X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxAW5XWn7XSU5xwAA3x Content-Type: text/plain; charset="utf-8" The Renesas RZ/G3S PCIe host driver currently does not enforce the mandatory 100 ms delay after link training completes for speeds > 5.0 GT/s, required by PCIe r6.0 sec 6.6.1. The driver already has a 'max_link_speed' field (derived from the device tree). Add a call to pcie_wait_after_link_train() in rzg3s_pcie_host_init() after reading the link status, ensuring that the delay is applied before any Configuration Request is sent downstream. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/pcie-rzg3s-host.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/control= ler/pcie-rzg3s-host.c index d86e7516dcc2..6ab59c5464cf 100644 --- a/drivers/pci/controller/pcie-rzg3s-host.c +++ b/drivers/pci/controller/pcie-rzg3s-host.c @@ -1390,6 +1390,8 @@ static int rzg3s_pcie_host_init(struct rzg3s_pcie_hos= t *host) val =3D readl_relaxed(host->axi + RZG3S_PCI_PCSTAT2); dev_info(host->dev, "PCIe link status [0x%x]\n", val); =20 + pcie_wait_after_link_train(host->max_link_speed); + return 0; =20 config_deinit_post: --=20 2.34.1