From nobody Sat Jun 13 16:22:27 2026 Received: from e3i439.smtp2go.com (e3i439.smtp2go.com [158.120.85.183]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08D9C3F7AAA for ; Wed, 6 May 2026 14:19:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=158.120.85.183 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778077199; cv=none; b=T1ESSULZYuoQ1L6HEGe9ZIotAkxZb82rO5WftdqNorFWbva5hUjFQMDwxz05yuVD0gIgcua7mPtU9u3QV068Ch+VkxG6cUTWpirvjW7m97ME8749KD6Br9CM90QEHTbnR9mHIfVkqYtW+YXLP68Ln3bxpN9ymr3l/SwqtLGaFsA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778077199; c=relaxed/simple; bh=YkeQZFtiXgt58B6BhRqS7nupUuzLxE9TvgMLL0bOa+Y=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=lF+Qrcxr/DwMdhXmHX8SzRgVS6/j39FUY+9x7M/qHpyzETXM+ekv10DnZuA1Y931vxfd0+ytZC25z+oc0a6zvw1VA9TNquyPRYNpgjLFGCwoyeFS3QY7dbFFzhwfOY/WNK7DYAOV7KuAGXq/oAxnooWCbJdIYFvm6/RbS5tzSqw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=asem.it; spf=pass smtp.mailfrom=em1174574.asem.it; dkim=pass (2048-bit key) header.d=asem.it header.i=@asem.it header.b=Q3lnCkDk; arc=none smtp.client-ip=158.120.85.183 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=asem.it Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=em1174574.asem.it Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=asem.it header.i=@asem.it header.b="Q3lnCkDk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=asem.it; i=@asem.it; q=dns/txt; s=s1174574; t=1778077188; h=from : subject : to : message-id : date; bh=leK7bUcmkCSB0GIeM0E1DOJ48uqzN9IZWq1tkaVx8g0=; b=Q3lnCkDkTX8bpumTi3j+Cv49GCov01VWWS5I6UNjbGnlbEADIwRINSXvo3WKCyKS0tkhX 92Wh5Cd1QrmRyUqphd2GXJDJrAEajAJawcXA8DDibbm4TGlfXLtn8X4Tn5qxQaqrO4BQUhV S5Web0W4/W3kZ4VpTrCC28pIf4wFAw0ntowC4Q7u/C2zyNmGaUnQB2hsQEUsv7mf6Jmz6AP D5wSnenSf0b+/PtydSFuHk956bPuV+famgX/Enhhbv4fljzmg48KGiIb8F75nNpGdXvudEf N1lioc7Nx5ky9CIM/9EqCMRw0VLtoO271hZkMtUYLV9P82n4dYQipv2kG5yg== Received: from [10.86.249.198] (helo=asas054.asem.intra) by smtpcorp.com with esmtpa (Exim 4.99.1-S2G) (envelope-from ) id 1wKd6G-FnQW0hPybXG-d0Tc; Wed, 06 May 2026 14:19:44 +0000 Received: from asem-ThinkStation-P330.asem.intra ([172.16.23.8]) by asas054.asem.intra with Microsoft SMTPSVC(10.0.14393.4169); Wed, 6 May 2026 16:19:29 +0200 From: Luca Ellero To: Cc: Luca Ellero , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v2] net: phy: dp83867: add MDI-X management Date: Wed, 6 May 2026 16:19:06 +0200 Message-ID: <20260506141918.13136-1-l.ellero@asem.it> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 06 May 2026 14:19:29.0477 (UTC) FILETIME=[59F17750:01DCDD63] X-Report-Abuse: Please forward a copy of this message, including all headers, to Feedback-ID: 1174574m:1174574aXfMg4B:1174574slHq65a5AS X-smtpcorp-track: 9xVgHpLEa7_X.wD1Em3tR2Bnu.051sxQVMzcu Content-Type: text/plain; charset="utf-8" ethtool on this phy device always reports "MDI-X: Unknown" and doesn't support forcing it to on or off. This patch adds support for reading/forcing MDI-X mode from ethtool properly. Signed-off-by: Luca Ellero Reviewed-by: Andrew Lunn --- v2: - add net-next to patch subject (no code modifications) v1: https://lore.kernel.org/netdev/9414fa96-05e1-4d7e-adca-4ccf3b96853b@lun= n.ch/T/#t drivers/net/phy/dp83867.c | 60 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 3fb2293f568f..88255e92b4cd 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -103,6 +103,10 @@ #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12) #define DP83867_PHYCR_SGMII_EN BIT(11) #define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10) +#define DP83867_PHYCR_MDIX_MASK GENMASK(6, 5) +#define DP83867_PHYCR_MDIX_MDI (0x0 << 5) +#define DP83867_PHYCR_MDIX_MDIX (0x1 << 5) +#define DP83867_PHYCR_MDIX_AUTO (0x3 << 5) =20 /* RGMIIDCTL bits */ #define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf @@ -123,6 +127,10 @@ #define DP83867_PHYSTS_100 BIT(14) #define DP83867_PHYSTS_DUPLEX BIT(13) #define DP83867_PHYSTS_LINK BIT(10) +#define DP83867_PHYSTS_MDIX_CD BIT(9) +#define DP83867_PHYSTS_MDIX_AB BIT(8) +#define DP83867_PHYSTS_MDIX_MASK (DP83867_PHYSTS_MDIX_AB | \ + DP83867_PHYSTS_MDIX_CD) =20 /* CFG2 bits */ #define DP83867_DOWNSHIFT_EN (BIT(8) | BIT(9)) @@ -391,6 +399,22 @@ static int dp83867_read_status(struct phy_device *phyd= ev) else phydev->speed =3D SPEED_10; =20 + if (!(status & DP83867_PHYSTS_LINK)) { + phydev->mdix =3D ETH_TP_MDI_INVALID; + } else { + switch (status & DP83867_PHYSTS_MDIX_MASK) { + case 0: + phydev->mdix =3D ETH_TP_MDI; + break; + case DP83867_PHYSTS_MDIX_MASK: + phydev->mdix =3D ETH_TP_MDI_X; + break; + default: + phydev->mdix =3D ETH_TP_MDI_INVALID; + break; + } + } + return 0; } =20 @@ -714,6 +738,8 @@ static int dp83867_config_init(struct phy_device *phyde= v) struct dp83867_private *dp83867 =3D phydev->priv; int ret, val, bs; =20 + phydev->mdix_ctrl =3D ETH_TP_MDI_AUTO; + /* Force speed optimization for the PHY even if it strapped */ ret =3D phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN, DP83867_DOWNSHIFT_EN); @@ -873,6 +899,39 @@ static int dp83867_config_init(struct phy_device *phyd= ev) return 0; } =20 +static int dp83867_config_mdix(struct phy_device *phydev, u8 ctrl) +{ + int val; + + switch (ctrl) { + case ETH_TP_MDI: + val =3D DP83867_PHYCR_MDIX_MDI; + break; + case ETH_TP_MDI_X: + val =3D DP83867_PHYCR_MDIX_MDIX; + break; + case ETH_TP_MDI_AUTO: + val =3D DP83867_PHYCR_MDIX_AUTO; + break; + default: + return -EINVAL; + } + + return phy_modify(phydev, MII_DP83867_PHYCTRL, + DP83867_PHYCR_MDIX_MASK, val); +} + +static int dp83867_config_aneg(struct phy_device *phydev) +{ + int ret; + + ret =3D dp83867_config_mdix(phydev, phydev->mdix_ctrl); + if (ret) + return ret; + + return genphy_config_aneg(phydev); +} + static int dp83867_phy_reset(struct phy_device *phydev) { int err; @@ -1127,6 +1186,7 @@ static struct phy_driver dp83867_driver[] =3D { =20 .probe =3D dp83867_probe, .config_init =3D dp83867_config_init, + .config_aneg =3D dp83867_config_aneg, .soft_reset =3D dp83867_phy_reset, =20 .read_status =3D dp83867_read_status, --=20 2.43.0