From nobody Sat Jun 13 16:22:58 2026 Received: from smtpout.sipearl.com (smtpout.sipearl.com [178.170.11.57]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C14A644B674 for ; Wed, 6 May 2026 12:35:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.170.11.57 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778070953; cv=none; b=LHTyq5IEZ5b+bXZ5MJgFk8pXOnMtHfSAPL1UoQuDP3Nuh2ZBQx9I+5TFZSjQK+XxZTUoIBbP3+9e/feJw1HTMNEiNdQilUB2o6a1mpiLpEiDuK+c+WU/WDrK31MDNBnSX7+6fkgsQHiHIk8Ie0PQJl4U2zpLsRE3aaw2PEA/8sY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778070953; c=relaxed/simple; bh=AbSpQ8VhCcTGSBfM6KX5kJgMIGRkVO7qL3B1g+DHvaw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YLMOmJbmO9iUz0TC5KoU05jmzKkZKoQ6QSOdcBEMhnbUJf6IW43VFxv7U/l1gi/0YHzJXUErEs/AwYtjPPFCT6v5HUznoWrCLv1NjG4WY33m3a9wahtigmaeYIBKhGFhJPJja3JBKHDV/+XQg/t1O5m4MYS3hcTB2TzMHBCOd1g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sipearl.com; spf=pass smtp.mailfrom=sipearl.com; dkim=pass (2048-bit key) header.d=sipearl.com header.i=@sipearl.com header.b=nnYdFHUU; arc=none smtp.client-ip=178.170.11.57 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sipearl.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sipearl.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sipearl.com header.i=@sipearl.com header.b="nnYdFHUU" Received: from smtpout.sipearl.com ([172.31.29.1]) by smtpin.sipearl.com with ESMTPS id 646CZgkO032479-646CZgkQ032479 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 6 May 2026 14:35:42 +0200 Received: from dc2pvlnosz002.pub.int.sipearl.com (172.31.65.18) by dc2pvwexcz001.sipearl.corp (172.31.29.1) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.36; Wed, 6 May 2026 14:35:42 +0200 From: Andrea Tomassetti To: CC: , , , , , Subject: [PATCH v2] mux: gpio-mux: add support for 4:1 2-channels mux Date: Wed, 6 May 2026 14:33:50 +0200 Message-ID: <20260506123350.310564-1-andrea.tomassetti@sipearl.com> X-Mailer: git-send-email 2.51.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dc2pvwexcz002.sipearl.corp (172.31.29.2) To dc2pvwexcz001.sipearl.corp (172.31.29.1) X-FEAS-BEC-Info: WlpIGw0aAQkEARIJHAEHBlJSCRoLAAEeDUhZUEhYSFhIWUhZXkguLT4lWFo8JVpcWFhZW1xcSFpRSAkGDBoNCUYcBwUJGxsNHBwBKBsBGA0JGgRGCwcFSFlIWV9IBAEGHRsfKAMNGgYNBEYHGg9IWEhaSFlZSFlfWkZbWUZaUUZZSFBIWEhYSFtIWEhYSFhIWltIAgcACQZDBAEGCRoHKAMNGgYNBEYHGg9IWEhaUEgEAQYdEEUDDRoGDQQoHg8NGkYDDRoGDQRGBxoPSFhIWV1IGA0MCSgJEA0GHAEJRhsNSFg= X-FEAS-Client-IP: 172.31.29.1 X-FE-Policy-ID: 2:2:2:SYSTEM DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; d=sipearl.com; s=sipearl2024; c=relaxed/relaxed; h=from:to:cc:subject:date:message-id:references:mime-version:content-type; bh=frkSLut7KfxvpVwV9kmS6k+GGiX/oQ/XgoDpHwG3UrI=; b=nnYdFHUUfsJHxs63CYXv0yZ/P+OhPyBOub6bAkEoTBuVwPQfuPway+KqE6hAXy1k8IkXtRVH6hep JdgiDdmai+HJMwdxRzfgNxYX4Ow6oyyl2ZG3djVSWfsWGstoK/XMhX4fNZQXlZHcPNyVwtXOfz6c afwgi4mu7j+V77JoD0/ilpS+W5zZ6Ht/TRPY2ntZR4pf3+K3H+fhTUCCQui2po59is3xHL8OO/cK 6fqQzNLCqsNOP2LgGmeCWb1s4YmjzA8GlSzw7r8SDdhay/FUTtuZ8NRmxNntCSCAvjBURNqZfeBW qEPOHoLvaTFNDW07esD/wfzEnK30Os4MGduMeg== Content-Type: text/plain; charset="utf-8" Some gpio multiplexers, like TMUX1209, offer differential 4:1 or dual 4:1 single-ended channels. No binding changes are needed because the DT binding already supports #mux-control-cells with values 0 and 1. So, similarly to what was already done by the adg792a driver, the gpio-mux driver has to take into account the #mux-control-cells property and allocate as many controllers as advised by it. As an example, in the DTS you can now define: tmux1209: mux-controller { compatible =3D "gpio-mux"; #mux-control-cells =3D <1>; mux-gpios =3D <&gpio_expander 01 GPIO_ACTIVE_HIGH>, <&gpio_expander 02 GPIO_ACTIVE_HIGH>; }; And use it like this: adcmux30: adcmux30 { compatible =3D "io-channel-mux"; io-channels =3D <&adc1 4>; io-channel-names =3D "parent"; #io-channel-cells =3D <1>; mux-controls =3D <&tmux1209 0>; channels =3D "S1A", "S2A", "S3A", "S4A"; }; adcmux31: adcmux31 { compatible =3D "io-channel-mux"; io-channels =3D <&adc1 5>; io-channel-names =3D "parent"; #io-channel-cells =3D <1>; mux-controls =3D <&tmux1209 1>; channels =3D "S1B", "S2B", "S3B", "S4B"; }; Signed-off-by: Andrea Tomassetti Reviewed-by: Linus Walleij --- v2: Address feedback from Linus Walleij - reword commit message by making clear that patching the binding is not needed - make clear from error message that binding only allows 0 or 1 - fix two other locations where `mux` was accessed drivers/mux/gpio.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/mux/gpio.c b/drivers/mux/gpio.c index 4cc3202c58f3..ab3ed5247d2c 100644 --- a/drivers/mux/gpio.c +++ b/drivers/mux/gpio.c @@ -52,12 +52,23 @@ static int mux_gpio_probe(struct platform_device *pdev) int pins; s32 idle_state; int ret; + u32 cells; + int i; pins =3D gpiod_count(dev, "mux"); if (pins < 0) return pins; - mux_chip =3D devm_mux_chip_alloc(dev, 1, sizeof(*mux_gpio)); + ret =3D device_property_read_u32(dev, "#mux-control-cells", &cells); + if (ret < 0) + cells =3D 0; + + if (cells >=3D 2) { + dev_err(dev, "invalid control-cells %u, must be 0 or 1\n", cells); + return -EINVAL; + } + + mux_chip =3D devm_mux_chip_alloc(dev, cells + 1, sizeof(*mux_gpio)); if (IS_ERR(mux_chip)) return PTR_ERR(mux_chip); @@ -69,7 +80,9 @@ static int mux_gpio_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(mux_gpio->gpios), "failed to get gpios\n"); WARN_ON(pins !=3D mux_gpio->gpios->ndescs); - mux_chip->mux->states =3D BIT(pins); + + for (i =3D 0; i < mux_chip->controllers; ++i) + mux_chip->mux[i].states =3D BIT(pins); ret =3D device_property_read_u32(dev, "idle-state", (u32 *)&idle_state); if (ret >=3D 0 && idle_state !=3D MUX_IDLE_AS_IS) { @@ -78,7 +91,8 @@ static int mux_gpio_probe(struct platform_device *pdev) return -EINVAL; } - mux_chip->mux->idle_state =3D idle_state; + for (i =3D 0; i < mux_chip->controllers; ++i) + mux_chip->mux[i].idle_state =3D idle_state; } ret =3D devm_regulator_get_enable_optional(dev, "mux"); @@ -89,8 +103,8 @@ static int mux_gpio_probe(struct platform_device *pdev) if (ret < 0) return ret; - dev_info(dev, "%u-way mux-controller registered\n", - mux_chip->mux->states); + dev_info(dev, "%u-way mux-controller registered, %u controllers\n", + mux_chip->mux->states, mux_chip->controllers); return 0; } base-commit: 74fe02ce122a6103f207d29fafc8b3a53de6abaf -- 2.51.2