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Wed, 06 May 2026 12:33:55 -0700 (PDT) From: =?utf-8?q?Stefan_D=C3=B6singer?= Date: Wed, 06 May 2026 22:33:18 +0300 Subject: [PATCH v8 1/6] dt-bindings: arm: zte: Add D-Link DWR932M board based on zx297520v3 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260506-send-v8-1-f1bdf3243b34@gmail.com> References: <20260506-send-v8-0-f1bdf3243b34@gmail.com> In-Reply-To: <20260506-send-v8-0-f1bdf3243b34@gmail.com> To: Jonathan Corbet , Shuah Khan , Russell King , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , Linus Walleij , Drew Fustini , Greg Kroah-Hartman , Jiri Slaby Cc: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, soc@lists.linux.dev, linux-serial@vger.kernel.org, =?utf-8?q?Stefan_D=C3=B6singer?= , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 This adds a new binding file for ZTE, containing their zx297520v3 SoC and one board (D-Link DWR-932M) based on it. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Stefan D=C3=B6singer --- Changelog: v6: Removed extra boards, I'll add them when submitting their individual DTS files. Rephrase the subject to add "zte" and remove the redundant use of "binding". Moved the devicetree bindings patch ahead of the implementation patches. Moved the MAINTAINERS section from "ZX29" to "ARM/ZTE". --- Documentation/devicetree/bindings/arm/zte.yaml | 26 ++++++++++++++++++++++= ++++ MAINTAINERS | 4 ++++ 2 files changed, 30 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/zte.yaml b/Documentation= /devicetree/bindings/arm/zte.yaml new file mode 100644 index 000000000000..f028d2cec7ab --- /dev/null +++ b/Documentation/devicetree/bindings/arm/zte.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/zte.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ZTE zx platforms + +maintainers: + - Stefan D=C3=B6singer + +description: | + ARM platforms using SoCs designed by ZTE. Currently this supports devices + based on the zx297520v3 SoC which is found in LTE routers. + +properties: + $nodename: + const: "/" + compatible: + oneOf: + - items: + - enum: + - dlink,dwr932m + - const: zte,zx297520v3 + +additionalProperties: true diff --git a/MAINTAINERS b/MAINTAINERS index d1cc0e12fe1f..b768b9da37a4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3772,6 +3772,10 @@ F: drivers/video/fbdev/vt8500lcdfb.* F: drivers/video/fbdev/wm8505fb* F: drivers/video/fbdev/wmt_ge_rops.* =20 +ARM/ZTE ZX29 SOC SUPPORT +M: Stefan D=C3=B6singer +F: Documentation/devicetree/bindings/arm/zte.yaml + ARM/ZYNQ ARCHITECTURE M: Michal Simek L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) --=20 2.53.0 From nobody Mon May 25 16:35:37 2026 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBA8233509B for ; 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Wed, 06 May 2026 12:34:00 -0700 (PDT) Received: from [192.168.0.2] ([197.250.51.29]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-45055960022sm14895673f8f.26.2026.05.06.12.33.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2026 12:34:00 -0700 (PDT) From: =?utf-8?q?Stefan_D=C3=B6singer?= Date: Wed, 06 May 2026 22:33:19 +0300 Subject: [PATCH v8 2/6] ARM: zte: Add zx297520v3 platform support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260506-send-v8-2-f1bdf3243b34@gmail.com> References: <20260506-send-v8-0-f1bdf3243b34@gmail.com> In-Reply-To: <20260506-send-v8-0-f1bdf3243b34@gmail.com> To: Jonathan Corbet , Shuah Khan , Russell King , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , Linus Walleij , Drew Fustini , Greg Kroah-Hartman , Jiri Slaby Cc: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, soc@lists.linux.dev, linux-serial@vger.kernel.org, =?utf-8?q?Stefan_D=C3=B6singer?= , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 This SoC is used in low end LTE-to-WiFi routers, for example some D-Link DWR 932 revisions, ZTE K10, ZLT S10 4G, but also models that are branded and sold by ISPs themselves. They are widespread in Africa, China, Russia and Eastern Europe. This SoC is a relative of the zx296702 and zx296718 that had some upstream support until commit 89d4f98ae90d ("ARM: remove zte zx platform"). My eventual goal is to enable OpenWRT to run on these devices. Reviewed-by: Linus Walleij Reviewed-by: Krzysztof Kozlowski Signed-off-by: Stefan D=C3=B6singer --- Patch changelog: v8: * Select ARM_PSCI_FW (Sashiko). This is an issue make defconfig pointed out in the last patch in this series. The board does not have PSCI firmware as far as I can tell, but the ARM_GIC_V3 option indirectly assumes ARM_PSCI_FW is enabled. * Include in the board file for __initdata (Sashiko), removed other includes copypasted from another platform that aren't needed. Let's see if Sashiko agrees. * Add the SoC documentation to the documentation index (Sashiko) * Add the SoC documentation to MAINTAINERS (Sashiko) * Removed redundant if ARCH_ZTE (Sashiko) * Point towards a sane (USB-Only) U-Boot and modify the example code for booting from NAND to detect already fixed GIC setups. --- Documentation/arch/arm/index.rst | 2 + Documentation/arch/arm/zte/index.rst | 10 ++ Documentation/arch/arm/zte/zx297520v3.rst | 167 ++++++++++++++++++++++++++= ++++ MAINTAINERS | 2 + arch/arm/Kconfig | 2 + arch/arm/Makefile | 1 + arch/arm/mach-zte/Kconfig | 29 ++++++ arch/arm/mach-zte/Makefile | 2 + arch/arm/mach-zte/zx297520v3.c | 16 +++ 9 files changed, 231 insertions(+) diff --git a/Documentation/arch/arm/index.rst b/Documentation/arch/arm/inde= x.rst index afe17db294c4..b15621093f7a 100644 --- a/Documentation/arch/arm/index.rst +++ b/Documentation/arch/arm/index.rst @@ -75,3 +75,5 @@ SoC-specific documents sti/overview =20 vfp/release-notes + + zte/index diff --git a/Documentation/arch/arm/zte/index.rst b/Documentation/arch/arm/= zte/index.rst new file mode 100644 index 000000000000..0ed80b60b746 --- /dev/null +++ b/Documentation/arch/arm/zte/index.rst @@ -0,0 +1,10 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +=3D=3D=3D=3D=3D=3D=3D +ZTE SoC +=3D=3D=3D=3D=3D=3D=3D + +.. toctree:: + :maxdepth: 1 + + zx297520v3 diff --git a/Documentation/arch/arm/zte/zx297520v3.rst b/Documentation/arch= /arm/zte/zx297520v3.rst new file mode 100644 index 000000000000..2122887e391a --- /dev/null +++ b/Documentation/arch/arm/zte/zx297520v3.rst @@ -0,0 +1,167 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Booting Linux on ZTE zx297520v3 SoCs +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +..........................................................................= ..... + +Author: Stefan D=C3=B6singer + +Date : 27 Jan 2026 + +1. Hardware description +--------------------------- +Zx297520v3 SoCs use a 64 bit capable Cortex-A53 CPU and GICv3, although th= ey +run in arm32 mode only. The CPU has support EL3, but no hypervisor (EL2) a= nd +it seems to lack VFP and NEON. + +The SoC is used in a number of cheap LTE to WiFi routers, both battery pow= ered +MiFis and stationary CPEs. In addition to the CPU these devices usually ha= ve +64 MB Ram (although some is shared with the LTE chip), 128 MB NAND flash, = an +SDIO connected RTL8192-type Wifi chip limited to 2.4 ghz operation, USB 2, +and buttons. Devices with as low as 32 MB or as high as 128 MB ram exist, = as +do devices with 8 or 16 MB of NOR flash. + +Some devices, especially the stationary ones, have 100 mbit Ethernet and an +Ethernet switch. + +Usually the devices have LEDs for status indication, although some have SP= I or +I2C connected displays + +Some have an SD card slot. If it exists, it is a better choice for the root +file system because it easily outperforms the built-in NAND. + +The LTE interface runs on a separate DSP called ZSP880. It is probably der= ived +from LSI ZSPs and has an undocumented instruction set. The ZSP communicates +with the main CPU via SRAM and DRAM and a mailbox hardware that can genera= te +IRQs on either ends. + +There is also a Cortex M0 CPU, which is responsible for early HW initializ= ation +and starting the Cortex A53 CPU. It does not have any essential purpose on= ce +U-Boot is started. A SRAM-Based handover protocol exists to run custom cod= e on +this CPU. + +2. Booting via USB +--------------------------- + +The Boot ROM has support for booting custom code via USB. This mode can be +entered by connecting a Boot PIN to GND or by modifying the third byte on = NAND +(set it to anything other than 0x5A aka 'Z'). A free software tool to start +custom U-Boot and kernels can be found here: + +https://github.com/zx297520v3-mainline/zx297520v3-loader + +If USB download mode is entered but no boot commands are sent through USB,= the +device will proceed to boot normally after a few seconds. It is therefore +possible to enable USB boot permanently and still leave the default boot f= iles +in place. + +https://github.com/zx297520v3-mainline/u-boot-mainline + +Contains an U-Boot version that can be used with the USB loader and sets u= p the +CPU and interrupt controller to comply with Linux's booting requirements. + +3. Building for built-in U-Boot +--------------------------- +The devices come with an ancient U-Boot that loads legacy uImages from NAN= D and +boots them without a chance for the user to interrupt. The images are stor= ed in +files ap_cpuap.bin and ap_recovery.bin on a jffs2 partition named imagefs, +usually mtd4. A file named "fotaflag" switches between the two modes. + +In addition to the uImage header, those files have a 384 byte signature he= ader, +which is used for authenticating the images on some devices. Most devices = have +this authentication disabled and it is enough to pad the uImage files with= 384 +zero bytes. + +Builtin U-Boot also poorly sets up the CPU. Read the next section for deta= ils +on this. It has no support for loading DTBs, so CONFIG_ARM_APPENDED_DTB is +needed. + +So to build an image that boots from NAND the following steps are necessar= y: + +1) Patch the assembly code from section 3 into arch/arm/kernel/head.S. +2) make zx29_defconfig +3) make [-j x] +4) cat arch/arm/boot/zImage arch/arm/boot/dts/zte/[device].dtb > kernel+dtb +5) mkimage -A arm -O linux -T kernel -C none -a 0x20008000 -d kernel+dtb u= img +6) dd if=3D/dev/zero bs=3D1 count=3D384 of=3Dap_recovery.bin +7) cat uimg >> ap_recovery.bin +8) Place this file onto imagefs on the device. Delete ap_cpuap.bin if the +free space is not enough. +9) Create the file fotaflag: echo -n FOTA-RECOVERY > fotaflag + +For development, booting ap_recovery.bin is recommended because the normal= boot +mode arms the watchdog before starting the kernel. + +4. CPU and GIC Setup +--------------------------- + +Generally CPU and GICv3 need to be set up according to the requirements sp= elled +out in Documentation/arch/arm64/booting.rst. For zx297520v3 this means: + +1. GICD_CTLR.DS=3D1 to disable GIC security +2. Enable access to ICC_SRE +3. Disable trapping IRQs into monitor mode +4. Configure EL2 and below to run in insecure mode. +5. Configure timer PPIs to active-low. + +The kernel sources provided by ZTE do not boot either (interrupts do not w= ork +at all). They are incomplete in other aspects too, so it is assumed that t= here +is some workaround similar to the one described in this document somewhere= in +the binary blobs. + +The assembly code below is given as an example of how to achieve this: + +``` +#include +#include +#include + +@ Detect sane bootloaders and skip the hack +ldr r3, =3D0xf2000000 +ldr r3, [r3] +ldr r4, =3D(GICD_CTLR_ARE_NS | GICD_CTLR_DS) +cmp r3, r4 +beq skip_zx_hack +@ This allows EL1 to handle ints hat are normally handled by EL2/3. +ldr r3, =3D0xf2000000 +str r4, [r3] + +cps #MON_MODE + +@ Work in non-secure physical address space: SCR_EL3.NS =3D 1. At least th= e UART +@ seems to respond only to non-secure addresses. I have taken insipiration= from +@ Raspberry pi's armstub7.S here. +mov r3, #0x131 @ non-secure, Make F, A bits in CPSR writeable + @ Allow hypervisor call. +mcr p15, 0, r3, c1, c1, 0 + +@ AP_PPI_MODE_REG: Configure timer PPIs (10, 11, 13, 14) to active-low. +ldr r3, =3D0xF22020a8 +ldr r4, =3D0x50 +str r4, [r3] +ldr r3, =3D0xF22020ac +ldr r4, =3D0x14 +str r4, [r3] + +@ Enable EL2 access to ICC_SRE (bit 3, ICC_SRE_EL3.Enable). Enable system = reg +@ access to GICv3 registers (bit 0, ICC_SRE_EL3.SRE) for EL1 and EL3. +mrc p15, 6, r3, c12, c12, 5 @ ICC_SRE_EL3 +orr r3, #0x9 @ FIXME: No defines for SRE_EL3 values? +mcr p15, 6, r3, c12, c12, 5 +mrc p15, 0, r3, c12, c12, 5 @ ICC_SRE_EL1 +orr r3, #(ICC_SRE_EL1_SRE) +mcr p15, 0, r3, c12, c12, 5 + +@ Like ICC_SRE_EL3, enable EL1 access to ICC_SRE and system register access +@ for EL2. +mrc p15, 4, r3, c12, c9, 5 @ ICC_SRE_EL2 aka ICC_HSRE +orr r3, r3, #(ICC_SRE_EL2_ENABLE | ICC_SRE_EL2_SRE) +mcr p15, 4, r3, c12, c9, 5 +isb + +@ Back to SVC mode +cps #SVC_MODE +skip_zx_hack: +``` diff --git a/MAINTAINERS b/MAINTAINERS index b768b9da37a4..697287d1b372 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3774,7 +3774,9 @@ F: drivers/video/fbdev/wmt_ge_rops.* =20 ARM/ZTE ZX29 SOC SUPPORT M: Stefan D=C3=B6singer +F: Documentation/arch/arm/zte/ F: Documentation/devicetree/bindings/arm/zte.yaml +F: arch/arm/mach-zte/ =20 ARM/ZYNQ ARCHITECTURE M: Michal Simek diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ec33376f8e2b..4217ed704e48 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -464,6 +464,8 @@ source "arch/arm/mach-versatile/Kconfig" =20 source "arch/arm/mach-vt8500/Kconfig" =20 +source "arch/arm/mach-zte/Kconfig" + source "arch/arm/mach-zynq/Kconfig" =20 # ARMv7-M architecture diff --git a/arch/arm/Makefile b/arch/arm/Makefile index b7de4b6b284c..573813ef5e77 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -223,6 +223,7 @@ machine-$(CONFIG_ARCH_SUNXI) +=3D sunxi machine-$(CONFIG_ARCH_TEGRA) +=3D tegra machine-$(CONFIG_ARCH_U8500) +=3D ux500 machine-$(CONFIG_ARCH_VT8500) +=3D vt8500 +machine-$(CONFIG_ARCH_ZTE) +=3D zte machine-$(CONFIG_ARCH_ZYNQ) +=3D zynq machine-$(CONFIG_PLAT_VERSATILE) +=3D versatile machine-$(CONFIG_PLAT_SPEAR) +=3D spear diff --git a/arch/arm/mach-zte/Kconfig b/arch/arm/mach-zte/Kconfig new file mode 100644 index 000000000000..d3b404ca488d --- /dev/null +++ b/arch/arm/mach-zte/Kconfig @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0-only +menuconfig ARCH_ZTE + bool "ZTE zx family" + depends on ARCH_MULTI_V7 + help + Support for ZTE zx-based family of processors. + +if ARCH_ZTE + +config SOC_ZX297520V3 + bool "zx297520v3 SoC" + default y + select ARM_GIC_V3 + # This board does not have PSCI firmware, but ARM_GIC_V3 depends on + # ARM_PSCI_FW being enabled. + select ARM_PSCI_FW + select ARM_AMBA + select HAVE_ARM_ARCH_TIMER + select PM_GENERIC_DOMAINS if PM + help + Support for ZTE zx297520v3 SoC. It is a single core SoC used in cheap + LTE to WiFi routers. These devices can be identified by the occurrence + of the string "zx297520v3" in the boot output and /proc/cpuinfo of + their stock firmware. + + Please read Documentation/arch/arm/zte/zx297520v3.rst on how to boot + the kernel. + +endif diff --git a/arch/arm/mach-zte/Makefile b/arch/arm/mach-zte/Makefile new file mode 100644 index 000000000000..1bfe4fddd6af --- /dev/null +++ b/arch/arm/mach-zte/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_SOC_ZX297520V3) +=3D zx297520v3.o diff --git a/arch/arm/mach-zte/zx297520v3.c b/arch/arm/mach-zte/zx297520v3.c new file mode 100644 index 000000000000..06f71348459e --- /dev/null +++ b/arch/arm/mach-zte/zx297520v3.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2026 Stefan D=C3=B6singer + */ + +#include +#include + +static const char *const zx297520v3_dt_compat[] __initconst =3D { + "zte,zx297520v3", + NULL, +}; + +DT_MACHINE_START(ZX, "ZTE zx297520v3 (Device Tree)") + .dt_compat =3D zx297520v3_dt_compat, +MACHINE_END --=20 2.53.0 From nobody Mon May 25 16:35:37 2026 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 824B233BBA7 for ; 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a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 This is based on the removed zx29 code. A separate (more complicated) patch will re-add the register map to the pl011 serial driver. Reviewed-by: Linus Walleij Signed-off-by: Stefan D=C3=B6singer --- Patch changelog: v8: Adjust UART01x_FR_BUSY to match the different ZX UART registers (Sashiko). I am unsure about UART01x_FR_TXFF and my boards do not expose flow control pins to allow me to test if it works. I am unsure about the virtual address. It doesn't seem to matter, as long as it is a valid address. This address is based on the old removed code. Is there a rule-of-thumb physical to virtual mapping I can use to give a sensible default value? --- arch/arm/Kconfig.debug | 12 ++++++++++++ arch/arm/include/debug/pl01x.S | 9 +++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 366f162e147d..98d8a5a60048 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -1331,6 +1331,16 @@ choice This option selects UART0 on VIA/Wondermedia System-on-a-chip devices, including VT8500, WM8505, WM8650 and WM8850. =20 + config DEBUG_ZTE_ZX + bool "Kernel low-level debugging via zx29 UART" + select DEBUG_UART_PL01X + depends on ARCH_ZTE + help + Say Y here if you are enabling ZTE zx297520v3 SOC and need + debug UART support. This UART is a PL011 with different + register addresses. The UART for boot messages on zx29 boards + is usually UART1 and is operating at 921600 8N1. + config DEBUG_ZYNQ_UART0 bool "Kernel low-level debugging on Xilinx Zynq using UART0" depends on ARCH_ZYNQ @@ -1545,6 +1555,7 @@ config DEBUG_UART_8250 =20 config DEBUG_UART_PHYS hex "Physical base address of debug UART" + default 0x01408000 if DEBUG_ZTE_ZX default 0x01c28000 if DEBUG_SUNXI_UART0 default 0x01c28400 if DEBUG_SUNXI_UART1 default 0x01d0c000 if DEBUG_DAVINCI_DA8XX_UART1 @@ -1701,6 +1712,7 @@ config DEBUG_UART_VIRT default 0xf31004c0 if DEBUG_MESON_UARTAO default 0xf4090000 if DEBUG_LPC32XX default 0xf4200000 if DEBUG_GEMINI + default 0xf4708000 if DEBUG_ZTE_ZX default 0xf6200000 if DEBUG_PXA_UART1 default 0xf7000000 if DEBUG_SUN9I_UART0 default 0xf7000000 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART0 diff --git a/arch/arm/include/debug/pl01x.S b/arch/arm/include/debug/pl01x.S index c7e02d0628bf..9dcdeed2357d 100644 --- a/arch/arm/include/debug/pl01x.S +++ b/arch/arm/include/debug/pl01x.S @@ -8,6 +8,15 @@ */ #include =20 +#ifdef CONFIG_DEBUG_ZTE_ZX +#undef UART01x_DR +#undef UART01x_FR +#undef UART01x_FR_BUSY +#define UART01x_DR 0x04 +#define UART01x_FR 0x14 +#define UART01x_FR_BUSY (1<<8) +#endif + #ifdef CONFIG_DEBUG_UART_PHYS .macro addruart, rp, rv, tmp ldr \rp, =3DCONFIG_DEBUG_UART_PHYS --=20 2.53.0 From nobody Mon May 25 16:35:37 2026 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B59733D511 for ; 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a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 This is based on code removed in commit 89d4f98ae90d ("ARM: remove zte zx platform"). I did not bring back the zx29-uart .compatible as the arm,primecell-periphid does the job. Reviewed-by: Linus Walleij Signed-off-by: Stefan D=C3=B6singer --- Changes since v4: Use ZTE's JEDEC ID instead of 0xfe for the DT-Provided AMBA ID. --- drivers/tty/serial/amba-pl011.c | 42 +++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 42 insertions(+) diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl01= 1.c index 7f17d288c807..f24cc403d9e0 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@ -216,6 +216,38 @@ static struct vendor_data vendor_st =3D { .get_fifosize =3D get_fifosize_st, }; =20 +static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] =3D { + [REG_DR] =3D ZX_UART011_DR, + [REG_FR] =3D ZX_UART011_FR, + [REG_LCRH_RX] =3D ZX_UART011_LCRH, + [REG_LCRH_TX] =3D ZX_UART011_LCRH, + [REG_IBRD] =3D ZX_UART011_IBRD, + [REG_FBRD] =3D ZX_UART011_FBRD, + [REG_CR] =3D ZX_UART011_CR, + [REG_IFLS] =3D ZX_UART011_IFLS, + [REG_IMSC] =3D ZX_UART011_IMSC, + [REG_RIS] =3D ZX_UART011_RIS, + [REG_MIS] =3D ZX_UART011_MIS, + [REG_ICR] =3D ZX_UART011_ICR, + [REG_DMACR] =3D ZX_UART011_DMACR, +}; + +static unsigned int get_fifosize_zte(struct amba_device *dev) +{ + return 16; +} + +static struct vendor_data vendor_zte =3D { + .reg_offset =3D pl011_zte_offsets, + .access_32b =3D true, + .ifls =3D UART011_IFLS_RX4_8 | UART011_IFLS_TX4_8, + .fr_busy =3D ZX_UART01x_FR_BUSY, + .fr_dsr =3D ZX_UART01x_FR_DSR, + .fr_cts =3D ZX_UART01x_FR_CTS, + .fr_ri =3D ZX_UART011_FR_RI, + .get_fifosize =3D get_fifosize_zte, +}; + /* Deals with DMA transactions */ =20 struct pl011_dmabuf { @@ -3081,6 +3113,16 @@ static const struct amba_id pl011_ids[] =3D { .mask =3D 0x00ffffff, .data =3D &vendor_st, }, + { + /* This is an invented ID. The actual hardware that contains + * these ZTE UARTs (zx29 boards) has no AMBA PIDs stored. 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Wed, 06 May 2026 12:34:14 -0700 (PDT) From: =?utf-8?q?Stefan_D=C3=B6singer?= Date: Wed, 06 May 2026 22:33:22 +0300 Subject: [PATCH v8 5/6] ARM: dts: zte: Add D-Link DWR-932M support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260506-send-v8-5-f1bdf3243b34@gmail.com> References: <20260506-send-v8-0-f1bdf3243b34@gmail.com> In-Reply-To: <20260506-send-v8-0-f1bdf3243b34@gmail.com> To: Jonathan Corbet , Shuah Khan , Russell King , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , Linus Walleij , Drew Fustini , Greg Kroah-Hartman , Jiri Slaby Cc: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, soc@lists.linux.dev, linux-serial@vger.kernel.org, =?utf-8?q?Stefan_D=C3=B6singer?= X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 This adds base DT definition for zx297520v3 and one board that consumes it. The stock kernel does not use the armv7 timer, but it seems to work fine. The board has other board-specific timers that would need a driver and I see no reason to bother with them since the arm standard timer works. The caveat is the non-standard GIC setup needed to handle the timer's level-low PPI. This is the responsibility of the boot loader and documented in Documentation/arch/arm/zte/zx297520v3.rst. Reviewed-by: Linus Walleij Signed-off-by: Stefan D=C3=B6singer --- Changes in v8: Remove redundant label, use "arm,pl011" for uart0 and 2 too. v6: Squash board + timer + uart patches into one v5: Prepend the SoC name in the device specific DTS filename. v4: Declare all uarts Remove the UART aliases for now. I can revisit this when I get my hands on a board that exposes two UARTs. --- MAINTAINERS | 1 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/zte/Makefile | 3 + arch/arm/boot/dts/zte/zx297520v3-dlink-dwr932m.dts | 22 +++++ arch/arm/boot/dts/zte/zx297520v3.dtsi | 103 +++++++++++++++++= ++++ 5 files changed, 130 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 697287d1b372..b0b774aace55 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3776,6 +3776,7 @@ ARM/ZTE ZX29 SOC SUPPORT M: Stefan D=C3=B6singer F: Documentation/arch/arm/zte/ F: Documentation/devicetree/bindings/arm/zte.yaml +F: arch/arm/boot/dts/zte/ F: arch/arm/mach-zte/ =20 ARM/ZYNQ ARCHITECTURE diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index efe38eb25301..28fba538d552 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -39,3 +39,4 @@ subdir-y +=3D unisoc subdir-y +=3D vt8500 subdir-y +=3D xen subdir-y +=3D xilinx +subdir-y +=3D zte diff --git a/arch/arm/boot/dts/zte/Makefile b/arch/arm/boot/dts/zte/Makefile new file mode 100644 index 000000000000..f052cfbd636c --- /dev/null +++ b/arch/arm/boot/dts/zte/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only +dtb-$(CONFIG_SOC_ZX297520V3) +=3D \ + zx297520v3-dlink-dwr932m.dtb diff --git a/arch/arm/boot/dts/zte/zx297520v3-dlink-dwr932m.dts b/arch/arm/= boot/dts/zte/zx297520v3-dlink-dwr932m.dts new file mode 100644 index 000000000000..1700f46aba86 --- /dev/null +++ b/arch/arm/boot/dts/zte/zx297520v3-dlink-dwr932m.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026 Stefan D=C3=B6singer + */ + +/dts-v1/; + +#include "zx297520v3.dtsi" + +/ { + model =3D "D-Link DWR-932M"; + compatible =3D "dlink,dwr932m", "zte,zx297520v3"; + + memory@20000000 { + device_type =3D "memory"; + reg =3D <0x20000000 0x04000000>; + }; +}; + +&uart1 { + status =3D "okay"; +}; diff --git a/arch/arm/boot/dts/zte/zx297520v3.dtsi b/arch/arm/boot/dts/zte/= zx297520v3.dtsi new file mode 100644 index 000000000000..a16c30a164bb --- /dev/null +++ b/arch/arm/boot/dts/zte/zx297520v3.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026 Stefan D=C3=B6singer + */ + +#include + +/ { + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0>; + }; + }; + + /* Base bus clock and default for the UART. It will be replaced once a cl= ock driver has + * been added. + */ + uartclk: uartclk-26000000 { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <26000000>; + }; + + timer { + compatible =3D "arm,armv7-timer"; + interrupts =3D , + , + , + ; + clock-frequency =3D <26000000>; + interrupt-parent =3D <&gic>; + /* I don't think uboot sets CNTVOFF and the stock kernel doesn't use the + * arm timer at all. Since this is a single CPU system I don't think it + * really matters that the offset is random though. + */ + arm,cpu-registers-not-fw-configured; + }; + + soc { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "simple-bus"; + interrupt-parent =3D <&gic>; + ranges; + + /* The GIC has a non-standard way of configuring ints between level-low/= level + * high or rising edge/falling edge at 0xf2202070 and onwards. See AP_IN= T_MODE_BASE + * and AP_PPI_MODE_REG in the ZTE kernel, although the offsets in the ke= rnel source + * seem wrong. + * + * Everything defaults to active-high/rising edge, but the timer is acti= ve-low. We + * currently rely on the boot loader to change timer IRQs to active-low = for us for + * now. + */ + gic: interrupt-controller@f2000000 { + compatible =3D "arm,gic-v3"; + interrupt-controller; + #interrupt-cells =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <1>; + reg =3D <0xf2000000 0x10000>, + <0xf2040000 0x20000>; + }; + + uart0: serial@131000 { + compatible =3D "arm,pl011", "arm,primecell"; + arm,primecell-periphid =3D <0x0018c011>; + reg =3D <0x00131000 0x1000>; + interrupts =3D ; + clocks =3D <&uartclk>, <&uartclk>; + clock-names =3D "uartclk", "apb_pclk"; + status =3D "disabled"; + }; + + uart1: serial@1408000 { + compatible =3D "arm,pl011", "arm,primecell"; + arm,primecell-periphid =3D <0x0018c011>; + reg =3D <0x01408000 0x1000>; + interrupts =3D ; + clocks =3D <&uartclk>, <&uartclk>; + clock-names =3D "uartclk", "apb_pclk"; + status =3D "disabled"; + }; + + uart2: serial@140d000 { + compatible =3D "arm,pl011", "arm,primecell"; + arm,primecell-periphid =3D <0x0018c011>; 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Wed, 06 May 2026 12:34:20 -0700 (PDT) From: =?utf-8?q?Stefan_D=C3=B6singer?= Date: Wed, 06 May 2026 22:33:23 +0300 Subject: [PATCH v8 6/6] ARM: zte: defconfig: Add a zx29 defconfig file Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260506-send-v8-6-f1bdf3243b34@gmail.com> References: <20260506-send-v8-0-f1bdf3243b34@gmail.com> In-Reply-To: <20260506-send-v8-0-f1bdf3243b34@gmail.com> To: Jonathan Corbet , Shuah Khan , Russell King , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , Linus Walleij , Drew Fustini , Greg Kroah-Hartman , Jiri Slaby Cc: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, soc@lists.linux.dev, linux-serial@vger.kernel.org, =?utf-8?q?Stefan_D=C3=B6singer?= X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 This enables existing drivers for hardware that is present on this board even if it is not present in the DT yet. Reviewed-by: Linus Walleij Signed-off-by: Stefan D=C3=B6singer --- Changes: v8: Remove BINFMT_FLAT. I have no idea how that slipped in (Sashik= o) Changes: v5 to v6: Regenerate the file with make savedefconfig. An open question: What's the appropriate name? zx29_defconfig? zte_defconfig? zte_zx29_defconfig? There's e.g. stm32_defconfig without an extra mention of STMicro in the name. --- MAINTAINERS | 1 + arch/arm/configs/zx29_defconfig | 53 +++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 54 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index b0b774aace55..0b392a364e32 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3777,6 +3777,7 @@ M: Stefan D=C3=B6singer F: Documentation/arch/arm/zte/ F: Documentation/devicetree/bindings/arm/zte.yaml F: arch/arm/boot/dts/zte/ +F: arch/arm/configs/zx29_defconfig F: arch/arm/mach-zte/ =20 ARM/ZYNQ ARCHITECTURE diff --git a/arch/arm/configs/zx29_defconfig b/arch/arm/configs/zx29_defcon= fig new file mode 100644 index 000000000000..b7f77e7a618f --- /dev/null +++ b/arch/arm/configs/zx29_defconfig @@ -0,0 +1,53 @@ +CONFIG_SYSVIPC=3Dy +CONFIG_BLK_DEV_INITRD=3Dy +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZ4 is not set +CONFIG_EXPERT=3Dy +CONFIG_KALLSYMS_ALL=3Dy +CONFIG_ARCH_ZTE=3Dy +CONFIG_ARM_PSCI=3Dy +CONFIG_ARM_APPENDED_DTB=3Dy +CONFIG_CMDLINE=3D"console=3DttyAMA0 earlyprintk root=3D/dev/ram rw" +CONFIG_CPU_FREQ=3Dy +CONFIG_CPUFREQ_DT_PLATDEV=3Dy +# CONFIG_SUSPEND is not set +CONFIG_PM=3Dy +CONFIG_NET=3Dy +CONFIG_PACKET=3Dy +CONFIG_UNIX=3Dy +CONFIG_INET=3Dy +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_ALLOW_DEV_COREDUMP is not set +CONFIG_MTD=3Dy +CONFIG_MTD_BLOCK=3Dy +CONFIG_BLK_DEV_RAM=3Dy +CONFIG_BLK_DEV_RAM_COUNT=3D4 +CONFIG_SRAM=3Dy +CONFIG_KEYBOARD_GPIO_POLLED=3Dy +# CONFIG_INPUT_MOUSE is not set +CONFIG_VT_HW_CONSOLE_BINDING=3Dy +CONFIG_SERIAL_AMBA_PL011=3Dy +CONFIG_SERIAL_AMBA_PL011_CONSOLE=3Dy +CONFIG_SERIAL_DEV_BUS=3Dy +# CONFIG_HW_RANDOM is not set +CONFIG_PINCTRL=3Dy +CONFIG_GPIOLIB=3Dy +CONFIG_GPIO_GENERIC_PLATFORM=3Dy +CONFIG_POWER_RESET=3Dy +CONFIG_MFD_SYSCON=3Dy +CONFIG_REGULATOR=3Dy +CONFIG_REGULATOR_FIXED_VOLTAGE=3Dy +# CONFIG_HID is not set +CONFIG_USB_DWC2=3Dy +CONFIG_USB_GADGET=3Dy +CONFIG_MMC=3Dy +CONFIG_MMC_DW=3Dy +CONFIG_RESET_CONTROLLER=3Dy +CONFIG_RESET_SIMPLE=3Dy +CONFIG_JFFS2_FS=3Dy +CONFIG_PRINTK_TIME=3Dy +CONFIG_DEBUG_LL=3Dy +CONFIG_EARLY_PRINTK=3Dy --=20 2.53.0