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Reviewed-by: Mike Tipton Reviewed-by: Krzysztof Kozlowski Signed-off-by: Vivek Aknurwar --- .../bindings/interconnect/qcom,hawi-rpmh.yaml | 131 ++++++++++++++++ include/dt-bindings/interconnect/qcom,hawi-rpmh.h | 165 +++++++++++++++++= ++++ 2 files changed, 296 insertions(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,hawi-rpmh.= yaml b/Documentation/devicetree/bindings/interconnect/qcom,hawi-rpmh.yaml new file mode 100644 index 000000000000..49a2dca5db62 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,hawi-rpmh.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,hawi-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on Hawi + +maintainers: + - Vivek Aknurwar + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provide= r is + able to communicate with the BCM through the Resource State Coordinator = (RSC) + associated with each execution environment. Provider nodes must point to= at + least one RPMh device child node pertaining to their RSC and each provid= er + can map to multiple RPMh resources. + + See also: include/dt-bindings/interconnect/qcom,hawi-rpmh.h + +properties: + compatible: + enum: + - qcom,hawi-aggre1-noc + - qcom,hawi-clk-virt + - qcom,hawi-cnoc-main + - qcom,hawi-gem-noc + - qcom,hawi-llclpi-noc + - qcom,hawi-lpass-ag-noc + - qcom,hawi-lpass-lpiaon-noc + - qcom,hawi-lpass-lpicx-noc + - qcom,hawi-mc-virt + - qcom,hawi-mmss-noc + - qcom,hawi-nsp-noc + - qcom,hawi-pcie-anoc + - qcom,hawi-stdst-cfg + - qcom,hawi-stdst-main + - qcom,hawi-system-noc + + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 3 + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,hawi-clk-virt + - qcom,hawi-mc-virt + then: + properties: + reg: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + enum: + - qcom,hawi-pcie-anoc + then: + properties: + clocks: + items: + - description: aggre-NOC PCIe AXI clock + - description: cfg-NOC PCIe a-NOC AHB clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,hawi-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre USB3 PRIM AXI clock + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,hawi-aggre1-noc + - qcom,hawi-pcie-anoc + then: + required: + - clocks + else: + properties: + clocks: false + +unevaluatedProperties: false + +examples: + - | + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clk_virt: interconnect-0 { + compatible =3D "qcom,hawi-clk-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre_noc: interconnect@f00000 { + compatible =3D "qcom,hawi-aggre1-noc"; + reg =3D <0x0 0xf00000 0x0 0x54400>; + #interconnect-cells =3D <2>; + clocks =3D <&gcc_aggre_ufs_phy_axi_clk>, + <&gcc_aggre_usb3_prim_axi_clk>, + <&rpmhcc_ipa_clk>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + }; diff --git a/include/dt-bindings/interconnect/qcom,hawi-rpmh.h b/include/dt= -bindings/interconnect/qcom,hawi-rpmh.h new file mode 100644 index 000000000000..a8b649679846 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,hawi-rpmh.h @@ -0,0 +1,165 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_HAWI_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_HAWI_H + +#define MASTER_QSPI_0 0 +#define MASTER_QUP_2 1 +#define MASTER_QUP_3 2 +#define MASTER_QUP_4 3 +#define MASTER_CRYPTO 4 +#define MASTER_IPA 5 +#define MASTER_QUP_1 6 +#define MASTER_SOCCP_PROC 7 +#define MASTER_QDSS_ETR 8 +#define MASTER_QDSS_ETR_1 9 +#define MASTER_SDCC_2 10 +#define MASTER_SDCC_4 11 +#define MASTER_UFS_MEM 12 +#define MASTER_USB3 13 +#define SLAVE_A1NOC_SNOC 14 + +#define MASTER_DDR_EFF_VETO 0 +#define MASTER_QUP_CORE_0 1 +#define MASTER_QUP_CORE_1 2 +#define MASTER_QUP_CORE_2 3 +#define MASTER_QUP_CORE_3 4 +#define MASTER_QUP_CORE_4 5 +#define SLAVE_DDR_EFF_VETO 6 +#define SLAVE_QUP_CORE_0 7 +#define SLAVE_QUP_CORE_1 8 +#define SLAVE_QUP_CORE_2 9 +#define SLAVE_QUP_CORE_3 10 +#define SLAVE_QUP_CORE_4 11 + +#define MASTER_GEM_NOC_CNOC 0 +#define MASTER_GEM_NOC_PCIE_SNOC 1 +#define SLAVE_AOSS 2 +#define SLAVE_IPA_CFG 3 +#define SLAVE_IPC_ROUTER_FENCE 4 +#define SLAVE_SOCCP 5 +#define SLAVE_TME_CFG 6 +#define SLAVE_CNOC_CFG 7 +#define SLAVE_DDRSS_CFG 8 +#define SLAVE_IMEM 9 +#define SLAVE_PCIE_0 10 +#define SLAVE_PCIE_1 11 + +#define MASTER_GIC 0 +#define MASTER_GPU_TCU 1 +#define MASTER_SYS_TCU 2 +#define MASTER_APPSS_PROC 3 +#define MASTER_GFX3D 4 +#define MASTER_LPASS_GEM_NOC 5 +#define MASTER_MSS_PROC 6 +#define MASTER_MNOC_HF_MEM_NOC 7 +#define MASTER_MNOC_SF_MEM_NOC 8 +#define MASTER_COMPUTE_NOC 9 +#define MASTER_ANOC_PCIE_GEM_NOC 10 +#define MASTER_QPACE 11 +#define MASTER_SNOC_SF_MEM_NOC 12 +#define MASTER_WLAN_Q6 13 +#define SLAVE_GEM_NOC_CNOC 14 +#define SLAVE_LLCC 15 +#define SLAVE_MEM_NOC_PCIE_SNOC 16 + +#define MASTER_LPIAON_NOC_LLCLPI_NOC 0 +#define SLAVE_LPASS_LPI_CC 1 +#define SLAVE_LLCC_ISLAND 2 +#define SLAVE_SERVICE_LLCLPI_NOC 3 +#define SLAVE_SERVICE_LLCLPI_NOC_CHIPCX 4 + +#define MASTER_LPIAON_NOC 0 +#define SLAVE_LPASS_GEM_NOC 1 + +#define MASTER_LPASS_LPINOC 0 +#define SLAVE_LPIAON_NOC_LLCLPI_NOC 1 +#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 2 + +#define MASTER_LPASS_PROC 0 +#define SLAVE_LPICX_NOC_LPIAON_NOC 1 + +#define MASTER_LLCC 0 +#define MASTER_DDR_RT 1 +#define SLAVE_EBI1 2 +#define SLAVE_DDR_RT 3 + +#define MASTER_CAMNOC_HF 0 +#define MASTER_CAMNOC_NRT_ICP_SF 1 +#define MASTER_CAMNOC_RT_CDM_SF 2 +#define MASTER_CAMNOC_SF 3 +#define MASTER_MDP 4 +#define MASTER_MDSS_DCP 5 +#define MASTER_CDSP_HCP 6 +#define MASTER_VIDEO_CV_PROC 7 +#define MASTER_VIDEO_EVA 8 +#define MASTER_VIDEO_MVP 9 +#define MASTER_VIDEO_V_PROC 10 +#define SLAVE_MNOC_HF_MEM_NOC 11 +#define SLAVE_MNOC_SF_MEM_NOC 12 + +#define MASTER_CDSP_PROC 0 +#define SLAVE_CDSP_MEM_NOC 1 + +#define MASTER_PCIE_ANOC_CFG 0 +#define MASTER_PCIE_0 1 +#define MASTER_PCIE_1 2 +#define SLAVE_ANOC_PCIE_GEM_NOC 3 +#define SLAVE_SERVICE_PCIE_ANOC 4 + +#define MASTER_CFG_CENTER 0 +#define MASTER_CFG_EAST 1 +#define MASTER_CFG_MM 2 +#define MASTER_CFG_NORTH 3 +#define MASTER_CFG_SOUTH 4 +#define MASTER_CFG_SOUTHWEST 5 +#define SLAVE_AHB2PHY_SOUTH 6 +#define SLAVE_BOOT_ROM 7 +#define SLAVE_CAMERA_CFG 8 +#define SLAVE_CLK_CTL 9 +#define SLAVE_CRYPTO_CFG 10 +#define SLAVE_DISPLAY_CFG 11 +#define SLAVE_EVA_CFG 12 +#define SLAVE_GFX3D_CFG 13 +#define SLAVE_I2C 14 +#define SLAVE_IMEM_CFG 15 +#define SLAVE_IPC_ROUTER_CFG 16 +#define SLAVE_IRIS_CFG 17 +#define SLAVE_CNOC_MSS 18 +#define SLAVE_PCIE_0_CFG 19 +#define SLAVE_PCIE_1_CFG 20 +#define SLAVE_PRNG 21 +#define SLAVE_QSPI_0 22 +#define SLAVE_QUP_1 23 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2f56fd92780sm4958372eec.23.2026.05.06.11.38.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2026 11:38:50 -0700 (PDT) From: Vivek Aknurwar Date: Wed, 06 May 2026 11:38:47 -0700 Subject: [PATCH v4 2/2] interconnect: qcom: add Hawi interconnect provider driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260506-icc-hawi-v4-2-35447fdc482b@oss.qualcomm.com> References: <20260506-icc-hawi-v4-0-35447fdc482b@oss.qualcomm.com> In-Reply-To: <20260506-icc-hawi-v4-0-35447fdc482b@oss.qualcomm.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mike Tipton , Vivek Aknurwar , Konrad Dybcio , Dmitry Baryshkov , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1778092728; l=52282; i=vivek.aknurwar@oss.qualcomm.com; s=20260311; h=from:subject:message-id; bh=eH+NHsKZkM30+iVr6hb+dMEO9wQdoPYZvNNWGzP4IG0=; b=aIu7yv3vYJ9D4m7/mBCjfkt/tJHvjOP05f3pUjWPT9XR7cSDGCmHXI0XLam9hCogzmEsl6SGw WgMGXeSns1tDFHEbVnn+Z3ZIKvvaeTvQ4xL9UhUZw9Q1G2KHgUSoe4Z X-Developer-Key: i=vivek.aknurwar@oss.qualcomm.com; a=ed25519; pk=WIVIbn3nJR9YRWNRyJiEbvpgoHhNyYrmVqMUXWqAIC0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA2MDE4MiBTYWx0ZWRfXyWoZsIBvHwK1 ODi+QI9IG3CjgPhqqgp7qVzPjG0XCelhn8SIr1cVt22HZES6st96kBC80r7Agd8PdVL1mB3UC/9 9z9dYivDLMnj+ciZzG/n/PtUPd1nRKqt0tFcqEbqCUzQS4C3gCbCDypFZtCY4iQds3I80eCPweA 95GG6P7d9CmKGeoqpl+ajvrLxaNUUBI6E9oa6IVHTre0SR/0HtXTIWh4k1Ey+TwEGoL31IC0onK Lyw4lhsrliRpFdk/nclJBbcRPHKc0pPpKMNHlvW/xoZR4aEFHNZcGZ/Xe83u7ple/3JFqX/AoTG uqymsCRXJPFU8s4bbIpdottW0lWiNcu4gJd53Be0x+EqTdU4JISWcF8DAjBer/x2GO7AoRbEgPp GM3czl1uU4h/Ne6nuDC7UvU7Men5p3Zt8xWviF8U+CTjWq/unaF9VTksjG2Xl/YNUYb8rqSyhj8 65oCwsi1isla8IimPsQ== X-Proofpoint-ORIG-GUID: 1IJ5H3_ql_Ojk62MLECQ31-lZkbNgUPF X-Proofpoint-GUID: 1IJ5H3_ql_Ojk62MLECQ31-lZkbNgUPF X-Authority-Analysis: v=2.4 cv=W8wIkxWk c=1 sm=1 tr=0 ts=69fb8abd cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=dpl9HiSh3CTwRQrow5IA:9 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-06_01,2026-05-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 bulkscore=0 impostorscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605060182 Add driver for the Qualcomm interconnect buses found in Hawi based platforms. The topology consists of several NoCs that are controlled by a remote processor that collects the aggregated bandwidth for each master-slave pair. Reviewed-by: Mike Tipton Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Acked-by: Krzysztof Kozlowski Signed-off-by: Vivek Aknurwar --- drivers/interconnect/qcom/Kconfig | 9 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/hawi.c | 2028 ++++++++++++++++++++++++++++++++= ++++ 3 files changed, 2039 insertions(+) diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/= Kconfig index 786b4eda44b4..0f3ba252c51d 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -26,6 +26,15 @@ config INTERCONNECT_QCOM_GLYMUR This is a driver for the Qualcomm Network-on-Chip on glymur-based platforms. =20 +config INTERCONNECT_QCOM_HAWI + tristate "Qualcomm HAWI interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + help + This is a driver for the Qualcomm Network-on-Chip on hawi-based + platforms. + config INTERCONNECT_QCOM_KAANAPALI tristate "Qualcomm Kaanapali interconnect driver" depends on INTERCONNECT_QCOM_RPMH_POSSIBLE diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom= /Makefile index cdf2c6c9fbf3..51aeb07a1707 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -6,6 +6,7 @@ interconnect_qcom-y :=3D icc-common.o icc-bcm-voter-objs :=3D bcm-voter.o qnoc-eliza-objs :=3D eliza.o qnoc-glymur-objs :=3D glymur.o +qnoc-hawi-objs :=3D hawi.o qnoc-kaanapali-objs :=3D kaanapali.o qnoc-milos-objs :=3D milos.o qnoc-msm8909-objs :=3D msm8909.o @@ -51,6 +52,7 @@ icc-smd-rpm-objs :=3D smd-rpm.o icc-rpm.o icc-rpm-clock= s.o obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) +=3D icc-bcm-voter.o obj-$(CONFIG_INTERCONNECT_QCOM_ELIZA) +=3D qnoc-eliza.o obj-$(CONFIG_INTERCONNECT_QCOM_GLYMUR) +=3D qnoc-glymur.o +obj-$(CONFIG_INTERCONNECT_QCOM_HAWI) +=3D qnoc-hawi.o obj-$(CONFIG_INTERCONNECT_QCOM_KAANAPALI) +=3D qnoc-kaanapali.o obj-$(CONFIG_INTERCONNECT_QCOM_MILOS) +=3D qnoc-milos.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8909) +=3D qnoc-msm8909.o diff --git a/drivers/interconnect/qcom/hawi.c b/drivers/interconnect/qcom/h= awi.c new file mode 100644 index 000000000000..6ece9828c62d --- /dev/null +++ b/drivers/interconnect/qcom/hawi.c @@ -0,0 +1,2028 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + */ + +#include +#include +#include +#include +#include +#include + +#include "bcm-voter.h" +#include "icc-rpmh.h" + +static struct qcom_icc_node ddr_eff_veto_slave =3D { + .name =3D "ddr_eff_veto_slave", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qup0_core_slave =3D { + .name =3D "qup0_core_slave", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qup1_core_slave =3D { + .name =3D "qup1_core_slave", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qup2_core_slave =3D { + .name =3D "qup2_core_slave", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qup3_core_slave =3D { + .name =3D "qup3_core_slave", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qup4_core_slave =3D { + .name =3D "qup4_core_slave", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_aoss =3D { + .name =3D "qhs_aoss", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ipa =3D { + .name =3D "qhs_ipa", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ipc_router_fence =3D { + .name =3D "qhs_ipc_router_fence", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_soccp =3D { + .name =3D "qhs_soccp", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tme_cfg =3D { + .name =3D "qhs_tme_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qss_ddrss_cfg =3D { + .name =3D "qss_ddrss_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qxs_imem =3D { + .name =3D "qxs_imem", + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node xs_pcie =3D { + .name =3D "xs_pcie", + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node xs_pcie_g4x1 =3D { + .name =3D "xs_pcie_g4x1", + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qhs_lpi_cc =3D { + .name =3D "qhs_lpi_cc", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_lb =3D { + .name =3D "qns_lb", + .channels =3D 4, + .buswidth =3D 32, +}; + +static struct qcom_icc_node srvc_llclpi_noc =3D { + .name =3D "srvc_llclpi_noc", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node srvc_llclpi_noc_chipcx =3D { + .name =3D "srvc_llclpi_noc_chipcx", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node ebi =3D { + .name =3D "ebi", + .channels =3D 4, + .buswidth =3D 4, +}; + +static struct qcom_icc_node ddr_rt_slave =3D { + .name =3D "ddr_rt_slave", + .channels =3D 4, + .buswidth =3D 4, +}; + +static struct qcom_icc_node srvc_pcie_aggre_noc =3D { + .name =3D "srvc_pcie_aggre_noc", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ahb2phy0 =3D { + .name =3D "qhs_ahb2phy0", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_boot_rom =3D { + .name =3D "qhs_boot_rom", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_camera_cfg =3D { + .name =3D "qhs_camera_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_clk_ctl =3D { + .name =3D "qhs_clk_ctl", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_crypto_cfg =3D { + .name =3D "qhs_crypto_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_display_cfg =3D { + .name =3D "qhs_display_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_eva_cfg =3D { + .name =3D "qhs_eva_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg =3D { + .name =3D "qhs_gpuss_cfg", + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qhs_i2c =3D { + .name =3D "qhs_i2c", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_imem_cfg =3D { + .name =3D "qhs_imem_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ipc_router =3D { + .name =3D "qhs_ipc_router", + .channels =3D 4, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_iris_cfg =3D { + .name =3D "qhs_iris_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_mss_cfg =3D { + .name =3D "qhs_mss_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie_cfg =3D { + .name =3D "qhs_pcie_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie_g4x1_cfg =3D { + .name =3D "qhs_pcie_g4x1_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_prng =3D { + .name =3D "qhs_prng", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qspi =3D { + .name =3D "qhs_qspi", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup1 =3D { + .name =3D "qhs_qup1", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup2 =3D { + .name =3D "qhs_qup2", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup3 =3D { + .name =3D "qhs_qup3", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup4 =3D { + .name =3D "qhs_qup4", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_sdc2 =3D { + .name =3D "qhs_sdc2", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_sdc4 =3D { + .name =3D "qhs_sdc4", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm =3D { + .name =3D "qhs_tlmm", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg =3D { + .name =3D "qhs_ufs_mem_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3 =3D { + .name =3D "qhs_usb3", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { + .name =3D "qhs_vsense_ctrl_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qss_qdss_cfg =3D { + .name =3D "qss_qdss_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qss_qdss_stm =3D { + .name =3D "qss_qdss_stm", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qss_tcsr =3D { + .name =3D "qss_tcsr", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg =3D { + .name =3D "xs_sys_tcu_cfg", + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node ddr_eff_veto_master =3D { + .name =3D "ddr_eff_veto_master", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &ddr_eff_veto_slave }, +}; + +static struct qcom_icc_node qup0_core_master =3D { + .name =3D "qup0_core_master", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qup0_core_slave }, +}; + +static struct qcom_icc_node qup1_core_master =3D { + .name =3D "qup1_core_master", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qup1_core_slave }, +}; + +static struct qcom_icc_node qup2_core_master =3D { + .name =3D "qup2_core_master", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qup2_core_slave }, +}; + +static struct qcom_icc_node qup3_core_master =3D { + .name =3D "qup3_core_master", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qup3_core_slave }, +}; + +static struct qcom_icc_node qup4_core_master =3D { + .name =3D "qup4_core_master", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qup4_core_slave }, +}; + +static struct qcom_icc_node qnm_gemnoc_pcie =3D { + .name =3D "qnm_gemnoc_pcie", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .link_nodes =3D { &xs_pcie, &xs_pcie_g4x1 }, +}; + +static struct qcom_icc_node qnm_lpiaon_noc_llclpi_noc =3D { + .name =3D "qnm_lpiaon_noc_llclpi_noc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 4, + .link_nodes =3D { &qhs_lpi_cc, &qns_lb, + &srvc_llclpi_noc, &srvc_llclpi_noc_chipcx }, +}; + +static struct qcom_icc_node llcc_mc =3D { + .name =3D "llcc_mc", + .channels =3D 4, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &ebi }, +}; + +static struct qcom_icc_node ddr_rt_mc =3D { + .name =3D "ddr_rt_mc", + .channels =3D 4, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &ddr_rt_slave }, +}; + +static struct qcom_icc_node qsm_pcie_anoc_cfg =3D { + .name =3D "qsm_pcie_anoc_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &srvc_pcie_aggre_noc }, +}; + +static struct qcom_icc_node qsm_cfg_east =3D { + .name =3D "qsm_cfg_east", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 4, + .link_nodes =3D { &qhs_crypto_cfg, &qhs_gpuss_cfg, + &qhs_qup2, &qhs_vsense_ctrl_cfg }, +}; + +static struct qcom_icc_node qsm_cfg_mm =3D { + .name =3D "qsm_cfg_mm", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 5, + .link_nodes =3D { &qhs_boot_rom, &qhs_camera_cfg, + &qhs_display_cfg, &qhs_eva_cfg, + &qhs_iris_cfg }, +}; + +static struct qcom_icc_node qsm_cfg_north =3D { + .name =3D "qsm_cfg_north", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 5, + .link_nodes =3D { &qhs_pcie_cfg, &qhs_pcie_g4x1_cfg, + &qhs_qup3, &qhs_qup4, + &qhs_sdc2 }, +}; + +static struct qcom_icc_node qsm_cfg_south =3D { + .name =3D "qsm_cfg_south", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 6, + .link_nodes =3D { &qhs_ahb2phy0, &qhs_qspi, + &qhs_qup1, &qhs_sdc4, + &qhs_ufs_mem_cfg, &qhs_usb3 }, +}; + +static struct qcom_icc_node qsm_cfg_southwest =3D { + .name =3D "qsm_cfg_southwest", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 2, + .link_nodes =3D { &qhs_ipc_router, &qhs_mss_cfg }, +}; + +static struct qcom_icc_node qns_llcc =3D { + .name =3D "qns_llcc", + .channels =3D 4, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &llcc_mc }, +}; + +static struct qcom_icc_node qns_pcie =3D { + .name =3D "qns_pcie", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qnm_gemnoc_pcie }, +}; + +static struct qcom_icc_node qns_llc_lpinoc =3D { + .name =3D "qns_llc_lpinoc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &qnm_lpiaon_noc_llclpi_noc }, +}; + +static struct qcom_icc_node qss_pcie_anoc_cfg =3D { + .name =3D "qss_pcie_anoc_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qsm_pcie_anoc_cfg }, +}; + +static struct qcom_icc_node qss_stdst_east_cfg =3D { + .name =3D "qss_stdst_east_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qsm_cfg_east }, +}; + +static struct qcom_icc_node qss_stdst_mm_cfg =3D { + .name =3D "qss_stdst_mm_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qsm_cfg_mm }, +}; + +static struct qcom_icc_node qss_stdst_north_cfg =3D { + .name =3D "qss_stdst_north_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qsm_cfg_north }, +}; + +static struct qcom_icc_node qss_stdst_south_cfg =3D { + .name =3D "qss_stdst_south_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qsm_cfg_south }, +}; + +static struct qcom_icc_node qss_stdst_southwest_cfg =3D { + .name =3D "qss_stdst_southwest_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qsm_cfg_southwest }, +}; + +static struct qcom_icc_node alm_gic =3D { + .name =3D "alm_gic", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x14d000 }, + .prio =3D 4, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_llcc }, +}; + +static struct qcom_icc_node qnm_qpace =3D { + .name =3D "qnm_qpace", + .channels =3D 1, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x153000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_llcc }, +}; + +static struct qcom_icc_node qsm_cfg_center =3D { + .name =3D "qsm_cfg_center", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 10, + .link_nodes =3D { &qhs_clk_ctl, &qhs_i2c, + &qhs_imem_cfg, &qhs_prng, + &qhs_tlmm, &qss_pcie_anoc_cfg, + &qss_qdss_cfg, &qss_qdss_stm, + &qss_tcsr, &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_node qss_stdst_center_cfg =3D { + .name =3D "qss_stdst_center_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qsm_cfg_center }, +}; + +static struct qcom_icc_node qsm_cnoc_main =3D { + .name =3D "qsm_cnoc_main", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 6, + .link_nodes =3D { &qss_stdst_center_cfg, &qss_stdst_east_cfg, + &qss_stdst_mm_cfg, &qss_stdst_north_cfg, + &qss_stdst_south_cfg, &qss_stdst_southwest_cfg }, +}; + +static struct qcom_icc_node qss_cfg =3D { + .name =3D "qss_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qsm_cnoc_main }, +}; + +static struct qcom_icc_node qnm_gemnoc_cnoc =3D { + .name =3D "qnm_gemnoc_cnoc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 8, + .link_nodes =3D { &qhs_aoss, &qhs_ipa, + &qhs_ipc_router_fence, &qhs_soccp, + &qhs_tme_cfg, &qss_cfg, + &qss_ddrss_cfg, &qxs_imem }, +}; + +static struct qcom_icc_node qns_gem_noc_cnoc =3D { + .name =3D "qns_gem_noc_cnoc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &qnm_gemnoc_cnoc }, +}; + +static struct qcom_icc_node alm_gpu_tcu =3D { + .name =3D "alm_gpu_tcu", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x145000 }, + .prio =3D 1, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 2, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node alm_sys_tcu =3D { + .name =3D "alm_sys_tcu", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x147000 }, + .prio =3D 6, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 2, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node chm_apps =3D { + .name =3D "chm_apps", + .channels =3D 4, + .buswidth =3D 32, + .num_links =3D 3, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_gpu =3D { + .name =3D "qnm_gpu", + .channels =3D 4, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 4, + .port_offsets =3D { 0x51000, 0x53000, 0xd1000, 0xd3000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 3, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_lpass_gemnoc =3D { + .name =3D "qnm_lpass_gemnoc", + .channels =3D 1, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x149000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 3, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_mdsp =3D { + .name =3D "qnm_mdsp", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 3, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_mnoc_hf =3D { + .name =3D "qnm_mnoc_hf", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x55000, 0xd5000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 3, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_mnoc_sf =3D { + .name =3D "qnm_mnoc_sf", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x57000, 0xd7000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 3, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_nsp_gemnoc =3D { + .name =3D "qnm_nsp_gemnoc", + .channels =3D 4, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 4, + .port_offsets =3D { 0x59000, 0x5b000, 0xd9000, 0xdb000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 3, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_pcie =3D { + .name =3D "qnm_pcie", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x14b000 }, + .prio =3D 2, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 2, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node qnm_snoc_sf =3D { + .name =3D "qnm_snoc_sf", + .channels =3D 1, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x14f000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 3, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_wlan_q6 =3D { + .name =3D "qnm_wlan_q6", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 3, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qns_lpass_ag_noc_gemnoc =3D { + .name =3D "qns_lpass_ag_noc_gemnoc", + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qnm_lpass_gemnoc }, +}; + +static struct qcom_icc_node qns_mem_noc_hf =3D { + .name =3D "qns_mem_noc_hf", + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qnm_mnoc_hf }, +}; + +static struct qcom_icc_node qns_mem_noc_sf =3D { + .name =3D "qns_mem_noc_sf", + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qnm_mnoc_sf }, +}; + +static struct qcom_icc_node qns_nsp_gemnoc =3D { + .name =3D "qns_nsp_gemnoc", + .channels =3D 4, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qnm_nsp_gemnoc }, +}; + +static struct qcom_icc_node qns_pcie_gemnoc =3D { + .name =3D "qns_pcie_gemnoc", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D { &qnm_pcie }, +}; + +static struct qcom_icc_node qns_gemnoc_sf =3D { + .name =3D "qns_gemnoc_sf", + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qnm_snoc_sf }, +}; + +static struct qcom_icc_node qnm_lpiaon_noc =3D { + .name =3D "qnm_lpiaon_noc", + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qns_lpass_ag_noc_gemnoc }, +}; + +static struct qcom_icc_node qnm_camnoc_hf =3D { + .name =3D "qnm_camnoc_hf", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x2a000, 0x2b000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_node qnm_camnoc_nrt_icp_sf =3D { + .name =3D "qnm_camnoc_nrt_icp_sf", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2c000 }, + .prio =3D 4, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_camnoc_rt_cdm_sf =3D { + .name =3D "qnm_camnoc_rt_cdm_sf", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x38000 }, + .prio =3D 2, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_camnoc_sf =3D { + .name =3D "qnm_camnoc_sf", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x2d000, 0x2e000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_mdp =3D { + .name =3D "qnm_mdp", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x2f000, 0x30000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_node qnm_mdss_dcp =3D { + .name =3D "qnm_mdss_dcp", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x39000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_vapss_hcp =3D { + .name =3D "qnm_vapss_hcp", + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_cv_cpu =3D { + .name =3D "qnm_video_cv_cpu", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x34000 }, + .prio =3D 4, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_eva =3D { + .name =3D "qnm_video_eva", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x35000, 0x36000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_mvp =3D { + .name =3D "qnm_video_mvp", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x32000, 0x33000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_v_cpu =3D { + .name =3D "qnm_video_v_cpu", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x37000 }, + .prio =3D 4, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_nsp =3D { + .name =3D "qnm_nsp", + .channels =3D 4, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qns_nsp_gemnoc }, +}; + +static struct qcom_icc_node xm_pcie =3D { + .name =3D "xm_pcie", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xc000 }, + .prio =3D 3, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_pcie_gemnoc }, +}; + +static struct qcom_icc_node xm_pcie_g4x1 =3D { + .name =3D "xm_pcie_g4x1", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xd000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_pcie_gemnoc }, +}; + +static struct qcom_icc_node qnm_aggre_noc =3D { + .name =3D "qnm_aggre_noc", + .channels =3D 1, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x20000 }, + .prio =3D 2, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qnm_apss_noc =3D { + .name =3D "qnm_apss_noc", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x1e000 }, + .prio =3D 2, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qnm_cnoc_data =3D { + .name =3D "qnm_cnoc_data", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x1f000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qns_a1noc_snoc =3D { + .name =3D "qns_a1noc_snoc", + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qnm_aggre_noc }, +}; + +static struct qcom_icc_node qns_lpass_aggnoc =3D { + .name =3D "qns_lpass_aggnoc", + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qnm_lpiaon_noc }, +}; + +static struct qcom_icc_node qhm_qspi =3D { + .name =3D "qhm_qspi", + .channels =3D 1, + .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x49000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qhm_qup2 =3D { + .name =3D "qhm_qup2", + .channels =3D 1, + .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x48000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qhm_qup3 =3D { + .name =3D "qhm_qup3", + .channels =3D 1, + .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x46000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qhm_qup4 =3D { + .name =3D "qhm_qup4", + .channels =3D 1, + .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x47000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qxm_crypto =3D { + .name =3D "qxm_crypto", + .channels =3D 1, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x40000 }, + .prio =3D 2, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qxm_ipa =3D { + .name =3D "qxm_ipa", + .channels =3D 1, + .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x41000 }, + .prio =3D 2, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qxm_qup1 =3D { + .name =3D "qxm_qup1", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x4d000 }, + .prio =3D 2, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qxm_soccp =3D { + .name =3D "qxm_soccp", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x45000 }, + .prio =3D 2, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_qdss_etr_0 =3D { + .name =3D "xm_qdss_etr_0", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x42000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_qdss_etr_1 =3D { + .name =3D "xm_qdss_etr_1", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x43000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_sdc2 =3D { + .name =3D "xm_sdc2", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x44000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_sdc4 =3D { + .name =3D "xm_sdc4", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x4a000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_ufs_mem =3D { + .name =3D "xm_ufs_mem", + .channels =3D 1, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x4b000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_usb3 =3D { + .name =3D "xm_usb3", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x4c000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qnm_lpass_lpinoc =3D { + .name =3D "qnm_lpass_lpinoc", + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 2, + .link_nodes =3D { &qns_llc_lpinoc, &qns_lpass_aggnoc }, +}; + +static struct qcom_icc_node qns_lpi_aon_noc =3D { + .name =3D "qns_lpi_aon_noc", + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qnm_lpass_lpinoc }, +}; + +static struct qcom_icc_node qnm_lpinoc_dsp_qns4m =3D { + .name =3D "qnm_lpinoc_dsp_qns4m", + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qns_lpi_aon_noc }, +}; + +static struct qcom_icc_bcm bcm_acv =3D { + .name =3D "ACV", + .enable_mask =3D BIT(3), + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_ce0 =3D { + .name =3D "CE0", + .num_nodes =3D 1, + .nodes =3D { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 =3D { + .name =3D "CN0", + .enable_mask =3D BIT(0), + .keepalive =3D true, + .num_nodes =3D 24, + .nodes =3D { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie, + &qhs_aoss, &qhs_ipa, + &qhs_ipc_router_fence, &qhs_soccp, + &qhs_tme_cfg, &qss_cfg, + &qss_ddrss_cfg, &qxs_imem, + &xs_pcie, &xs_pcie_g4x1, + &qsm_cfg_center, &qsm_cfg_east, + &qsm_cfg_mm, &qsm_cfg_north, + &qsm_cfg_south, &qsm_cfg_southwest, + &qhs_ahb2phy0, &qhs_boot_rom, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_crypto_cfg, &qhs_eva_cfg }, +}; + +static struct qcom_icc_bcm bcm_cn1 =3D { + .name =3D "CN1", + .num_nodes =3D 1, + .nodes =3D { &qhs_display_cfg }, +}; + +static struct qcom_icc_bcm bcm_co0 =3D { + .name =3D "CO0", + .enable_mask =3D BIT(0), + .num_nodes =3D 2, + .nodes =3D { &qnm_nsp, &qns_nsp_gemnoc }, +}; + +static struct qcom_icc_bcm bcm_de0 =3D { + .name =3D "DE0", + .enable_mask =3D BIT(0), + .num_nodes =3D 1, + .nodes =3D { &ddr_eff_veto_slave }, +}; + +static struct qcom_icc_bcm bcm_lp0 =3D { + .name =3D "LP0", + .num_nodes =3D 5, + .nodes =3D { &qnm_lpiaon_noc_llclpi_noc, &qns_lb, + &qnm_lpass_lpinoc, &qns_llc_lpinoc, + &qns_lpass_aggnoc }, +}; + +static struct qcom_icc_bcm bcm_mc0 =3D { + .name =3D "MC0", + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mc5 =3D { + .name =3D "MC5", + .num_nodes =3D 1, + .nodes =3D { &ddr_rt_slave }, +}; + +static struct qcom_icc_bcm bcm_mm0 =3D { + .name =3D "MM0", + .num_nodes =3D 1, + .nodes =3D { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_mm1 =3D { + .name =3D "MM1", + .enable_mask =3D BIT(0), + .num_nodes =3D 9, + .nodes =3D { &qnm_camnoc_hf, &qnm_camnoc_nrt_icp_sf, + &qnm_camnoc_rt_cdm_sf, &qnm_camnoc_sf, + &qnm_vapss_hcp, &qnm_video_cv_cpu, + &qnm_video_mvp, &qnm_video_v_cpu, + &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_qpc0 =3D { + .name =3D "QPC0", + .num_nodes =3D 1, + .nodes =3D { &qnm_qpace }, +}; + +static struct qcom_icc_bcm bcm_qup0 =3D { + .name =3D "QUP0", + .keepalive =3D true, + .vote_scale =3D 1, + .num_nodes =3D 1, + .nodes =3D { &qup0_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup1 =3D { + .name =3D "QUP1", + .keepalive =3D true, + .vote_scale =3D 1, + .num_nodes =3D 1, + .nodes =3D { &qup1_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup2 =3D { + .name =3D "QUP2", + .keepalive =3D true, + .vote_scale =3D 1, + .num_nodes =3D 1, + .nodes =3D { &qup2_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup3 =3D { + .name =3D "QUP3", + .keepalive =3D true, + .vote_scale =3D 1, + .num_nodes =3D 1, + .nodes =3D { &qup3_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup4 =3D { + .name =3D "QUP4", + .keepalive =3D true, + .vote_scale =3D 1, + .num_nodes =3D 1, + .nodes =3D { &qup4_core_slave }, +}; + +static struct qcom_icc_bcm bcm_sh0 =3D { + .name =3D "SH0", + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh1 =3D { + .name =3D "SH1", + .enable_mask =3D BIT(0), + .num_nodes =3D 15, + .nodes =3D { &alm_gic, &alm_gpu_tcu, + &alm_sys_tcu, &chm_apps, + &qnm_gpu, &qnm_lpass_gemnoc, + &qnm_mdsp, &qnm_mnoc_hf, + &qnm_mnoc_sf, &qnm_nsp_gemnoc, + &qnm_pcie, &qnm_snoc_sf, + &qnm_wlan_q6, &qns_gem_noc_cnoc, + &qns_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn0 =3D { + .name =3D "SN0", + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn2 =3D { + .name =3D "SN2", + .num_nodes =3D 1, + .nodes =3D { &qnm_aggre_noc }, +}; + +static struct qcom_icc_bcm bcm_sn3 =3D { + .name =3D "SN3", + .num_nodes =3D 1, + .nodes =3D { &qns_pcie_gemnoc }, +}; + +static struct qcom_icc_bcm * const aggre1_noc_bcms[] =3D { + &bcm_ce0, +}; + +static struct qcom_icc_node * const aggre1_noc_nodes[] =3D { + [MASTER_QSPI_0] =3D &qhm_qspi, + [MASTER_QUP_2] =3D &qhm_qup2, + [MASTER_QUP_3] =3D &qhm_qup3, + [MASTER_QUP_4] =3D &qhm_qup4, + [MASTER_CRYPTO] =3D &qxm_crypto, + [MASTER_IPA] =3D &qxm_ipa, + [MASTER_QUP_1] =3D &qxm_qup1, + [MASTER_SOCCP_PROC] =3D &qxm_soccp, + [MASTER_QDSS_ETR] =3D &xm_qdss_etr_0, + [MASTER_QDSS_ETR_1] =3D &xm_qdss_etr_1, + [MASTER_SDCC_2] =3D &xm_sdc2, + [MASTER_SDCC_4] =3D &xm_sdc4, + [MASTER_UFS_MEM] =3D &xm_ufs_mem, + [MASTER_USB3] =3D &xm_usb3, + [SLAVE_A1NOC_SNOC] =3D &qns_a1noc_snoc, +}; + +static const struct regmap_config hawi_aggre1_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x54400, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc hawi_aggre1_noc =3D { + .config =3D &hawi_aggre1_noc_regmap_config, + .nodes =3D aggre1_noc_nodes, + .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), + .bcms =3D aggre1_noc_bcms, + .num_bcms =3D ARRAY_SIZE(aggre1_noc_bcms), + .qos_requires_clocks =3D true, +}; + +static struct qcom_icc_bcm * const clk_virt_bcms[] =3D { + &bcm_de0, + &bcm_qup0, + &bcm_qup1, + &bcm_qup2, + &bcm_qup3, + &bcm_qup4, +}; + +static struct qcom_icc_node * const clk_virt_nodes[] =3D { + [MASTER_DDR_EFF_VETO] =3D &ddr_eff_veto_master, + [MASTER_QUP_CORE_0] =3D &qup0_core_master, + [MASTER_QUP_CORE_1] =3D &qup1_core_master, + [MASTER_QUP_CORE_2] =3D &qup2_core_master, + [MASTER_QUP_CORE_3] =3D &qup3_core_master, + [MASTER_QUP_CORE_4] =3D &qup4_core_master, + [SLAVE_DDR_EFF_VETO] =3D &ddr_eff_veto_slave, + [SLAVE_QUP_CORE_0] =3D &qup0_core_slave, + [SLAVE_QUP_CORE_1] =3D &qup1_core_slave, + [SLAVE_QUP_CORE_2] =3D &qup2_core_slave, + [SLAVE_QUP_CORE_3] =3D &qup3_core_slave, + [SLAVE_QUP_CORE_4] =3D &qup4_core_slave, +}; + +static const struct qcom_icc_desc hawi_clk_virt =3D { + .nodes =3D clk_virt_nodes, + .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), + .bcms =3D clk_virt_bcms, + .num_bcms =3D ARRAY_SIZE(clk_virt_bcms), +}; + +static struct qcom_icc_bcm * const cnoc_main_bcms[] =3D { + &bcm_cn0, +}; + +static struct qcom_icc_node * const cnoc_main_nodes[] =3D { + [MASTER_GEM_NOC_CNOC] =3D &qnm_gemnoc_cnoc, + [MASTER_GEM_NOC_PCIE_SNOC] =3D &qnm_gemnoc_pcie, + [SLAVE_AOSS] =3D &qhs_aoss, + [SLAVE_IPA_CFG] =3D &qhs_ipa, + [SLAVE_IPC_ROUTER_FENCE] =3D &qhs_ipc_router_fence, + [SLAVE_SOCCP] =3D &qhs_soccp, + [SLAVE_TME_CFG] =3D &qhs_tme_cfg, + [SLAVE_CNOC_CFG] =3D &qss_cfg, + [SLAVE_DDRSS_CFG] =3D &qss_ddrss_cfg, + [SLAVE_IMEM] =3D &qxs_imem, + [SLAVE_PCIE_0] =3D &xs_pcie, + [SLAVE_PCIE_1] =3D &xs_pcie_g4x1, +}; + +static const struct regmap_config hawi_cnoc_main_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x20000, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc hawi_cnoc_main =3D { + .config =3D &hawi_cnoc_main_regmap_config, + .nodes =3D cnoc_main_nodes, + .num_nodes =3D ARRAY_SIZE(cnoc_main_nodes), + .bcms =3D cnoc_main_bcms, + .num_bcms =3D ARRAY_SIZE(cnoc_main_bcms), +}; + +static struct qcom_icc_bcm * const gem_noc_bcms[] =3D { + &bcm_qpc0, + &bcm_sh0, + &bcm_sh1, +}; + +static struct qcom_icc_node * const gem_noc_nodes[] =3D { + [MASTER_GIC] =3D &alm_gic, + [MASTER_GPU_TCU] =3D &alm_gpu_tcu, + [MASTER_SYS_TCU] =3D &alm_sys_tcu, + [MASTER_APPSS_PROC] =3D &chm_apps, + [MASTER_GFX3D] =3D &qnm_gpu, + [MASTER_LPASS_GEM_NOC] =3D &qnm_lpass_gemnoc, + [MASTER_MSS_PROC] =3D &qnm_mdsp, + [MASTER_MNOC_HF_MEM_NOC] =3D &qnm_mnoc_hf, + [MASTER_MNOC_SF_MEM_NOC] =3D &qnm_mnoc_sf, + [MASTER_COMPUTE_NOC] =3D &qnm_nsp_gemnoc, + [MASTER_ANOC_PCIE_GEM_NOC] =3D &qnm_pcie, + [MASTER_QPACE] =3D &qnm_qpace, + [MASTER_SNOC_SF_MEM_NOC] =3D &qnm_snoc_sf, + [MASTER_WLAN_Q6] =3D &qnm_wlan_q6, + [SLAVE_GEM_NOC_CNOC] =3D &qns_gem_noc_cnoc, + [SLAVE_LLCC] =3D &qns_llcc, + [SLAVE_MEM_NOC_PCIE_SNOC] =3D &qns_pcie, +}; + +static const struct regmap_config hawi_gem_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x160200, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc hawi_gem_noc =3D { + .config =3D &hawi_gem_noc_regmap_config, + .nodes =3D gem_noc_nodes, + .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), + .bcms =3D gem_noc_bcms, + .num_bcms =3D ARRAY_SIZE(gem_noc_bcms), +}; + +static struct qcom_icc_bcm * const llclpi_noc_bcms[] =3D { + &bcm_lp0, +}; + +static struct qcom_icc_node * const llclpi_noc_nodes[] =3D { + [MASTER_LPIAON_NOC_LLCLPI_NOC] =3D &qnm_lpiaon_noc_llclpi_noc, + [SLAVE_LPASS_LPI_CC] =3D &qhs_lpi_cc, + [SLAVE_LLCC_ISLAND] =3D &qns_lb, + [SLAVE_SERVICE_LLCLPI_NOC] =3D &srvc_llclpi_noc, + [SLAVE_SERVICE_LLCLPI_NOC_CHIPCX] =3D &srvc_llclpi_noc_chipcx, +}; + +static const struct regmap_config hawi_llclpi_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x17200, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc hawi_llclpi_noc =3D { + .config =3D &hawi_llclpi_noc_regmap_config, + .nodes =3D llclpi_noc_nodes, + .num_nodes =3D ARRAY_SIZE(llclpi_noc_nodes), + .bcms =3D llclpi_noc_bcms, + .num_bcms =3D ARRAY_SIZE(llclpi_noc_bcms), +}; + +static struct qcom_icc_node * const lpass_ag_noc_nodes[] =3D { + [MASTER_LPIAON_NOC] =3D &qnm_lpiaon_noc, + [SLAVE_LPASS_GEM_NOC] =3D &qns_lpass_ag_noc_gemnoc, +}; + +static const struct regmap_config hawi_lpass_ag_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xc080, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc hawi_lpass_ag_noc =3D { + .config =3D &hawi_lpass_ag_noc_regmap_config, + .nodes =3D lpass_ag_noc_nodes, + .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), +}; + +static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] =3D { + &bcm_lp0, +}; + +static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] =3D { + [MASTER_LPASS_LPINOC] =3D &qnm_lpass_lpinoc, + [SLAVE_LPIAON_NOC_LLCLPI_NOC] =3D &qns_llc_lpinoc, + [SLAVE_LPIAON_NOC_LPASS_AG_NOC] =3D &qns_lpass_aggnoc, +}; + +static const struct regmap_config hawi_lpass_lpiaon_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x19080, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc hawi_lpass_lpiaon_noc =3D { + .config =3D &hawi_lpass_lpiaon_noc_regmap_config, + .nodes =3D lpass_lpiaon_noc_nodes, + .num_nodes =3D ARRAY_SIZE(lpass_lpiaon_noc_nodes), + .bcms =3D lpass_lpiaon_noc_bcms, + .num_bcms =3D ARRAY_SIZE(lpass_lpiaon_noc_bcms), +}; + +static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] =3D { + [MASTER_LPASS_PROC] =3D &qnm_lpinoc_dsp_qns4m, + [SLAVE_LPICX_NOC_LPIAON_NOC] =3D &qns_lpi_aon_noc, +}; + +static const struct regmap_config hawi_lpass_lpicx_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x46080, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc hawi_lpass_lpicx_noc =3D { + .config =3D &hawi_lpass_lpicx_noc_regmap_config, + .nodes =3D lpass_lpicx_noc_nodes, + .num_nodes =3D ARRAY_SIZE(lpass_lpicx_noc_nodes), +}; + +static struct qcom_icc_bcm * const mc_virt_bcms[] =3D { + &bcm_acv, + &bcm_mc0, + &bcm_mc5, +}; + +static struct qcom_icc_node * const mc_virt_nodes[] =3D { + [MASTER_LLCC] =3D &llcc_mc, + [MASTER_DDR_RT] =3D &ddr_rt_mc, + [SLAVE_EBI1] =3D &ebi, + [SLAVE_DDR_RT] =3D &ddr_rt_slave, +}; + +static const struct qcom_icc_desc hawi_mc_virt =3D { + .nodes =3D mc_virt_nodes, + .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), + .bcms =3D mc_virt_bcms, + .num_bcms =3D ARRAY_SIZE(mc_virt_bcms), +}; + +static struct qcom_icc_bcm * const mmss_noc_bcms[] =3D { + &bcm_mm0, + &bcm_mm1, +}; + +static struct qcom_icc_node * const mmss_noc_nodes[] =3D { + [MASTER_CAMNOC_HF] =3D &qnm_camnoc_hf, + [MASTER_CAMNOC_NRT_ICP_SF] =3D &qnm_camnoc_nrt_icp_sf, + [MASTER_CAMNOC_RT_CDM_SF] =3D &qnm_camnoc_rt_cdm_sf, + [MASTER_CAMNOC_SF] =3D &qnm_camnoc_sf, + [MASTER_MDP] =3D &qnm_mdp, + [MASTER_MDSS_DCP] =3D &qnm_mdss_dcp, + [MASTER_CDSP_HCP] =3D &qnm_vapss_hcp, + [MASTER_VIDEO_CV_PROC] =3D &qnm_video_cv_cpu, + [MASTER_VIDEO_EVA] =3D &qnm_video_eva, + [MASTER_VIDEO_MVP] =3D &qnm_video_mvp, + [MASTER_VIDEO_V_PROC] =3D &qnm_video_v_cpu, + [SLAVE_MNOC_HF_MEM_NOC] =3D &qns_mem_noc_hf, + [SLAVE_MNOC_SF_MEM_NOC] =3D &qns_mem_noc_sf, +}; + +static const struct regmap_config hawi_mmss_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x5f800, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc hawi_mmss_noc =3D { + .config =3D &hawi_mmss_noc_regmap_config, + .nodes =3D mmss_noc_nodes, + .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), + .bcms =3D mmss_noc_bcms, + .num_bcms =3D ARRAY_SIZE(mmss_noc_bcms), +}; + +static struct qcom_icc_bcm * const nsp_noc_bcms[] =3D { + &bcm_co0, +}; + +static struct qcom_icc_node * const nsp_noc_nodes[] =3D { + [MASTER_CDSP_PROC] =3D &qnm_nsp, + [SLAVE_CDSP_MEM_NOC] =3D &qns_nsp_gemnoc, +}; + +static const struct regmap_config hawi_nsp_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x21280, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc hawi_nsp_noc =3D { + .config =3D &hawi_nsp_noc_regmap_config, + .nodes =3D nsp_noc_nodes, + .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), + .bcms =3D nsp_noc_bcms, + .num_bcms =3D ARRAY_SIZE(nsp_noc_bcms), +}; + +static struct qcom_icc_bcm * const pcie_anoc_bcms[] =3D { + &bcm_sn3, +}; + +static struct qcom_icc_node * const pcie_anoc_nodes[] =3D { + [MASTER_PCIE_ANOC_CFG] =3D &qsm_pcie_anoc_cfg, + [MASTER_PCIE_0] =3D &xm_pcie, + [MASTER_PCIE_1] =3D &xm_pcie_g4x1, + [SLAVE_ANOC_PCIE_GEM_NOC] =3D &qns_pcie_gemnoc, + [SLAVE_SERVICE_PCIE_ANOC] =3D &srvc_pcie_aggre_noc, +}; + +static const struct regmap_config hawi_pcie_anoc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x12400, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc hawi_pcie_anoc =3D { + .config =3D &hawi_pcie_anoc_regmap_config, + .nodes =3D pcie_anoc_nodes, + .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), + .bcms =3D pcie_anoc_bcms, + .num_bcms =3D ARRAY_SIZE(pcie_anoc_bcms), + .qos_requires_clocks =3D true, +}; + +static struct qcom_icc_bcm * const stdst_cfg_bcms[] =3D { + &bcm_cn0, + &bcm_cn1, +}; + +static struct qcom_icc_node * const stdst_cfg_nodes[] =3D { + [MASTER_CFG_CENTER] =3D &qsm_cfg_center, + [MASTER_CFG_EAST] =3D &qsm_cfg_east, + [MASTER_CFG_MM] =3D &qsm_cfg_mm, + [MASTER_CFG_NORTH] =3D &qsm_cfg_north, + [MASTER_CFG_SOUTH] =3D &qsm_cfg_south, + [MASTER_CFG_SOUTHWEST] =3D &qsm_cfg_southwest, + [SLAVE_AHB2PHY_SOUTH] =3D &qhs_ahb2phy0, + [SLAVE_BOOT_ROM] =3D &qhs_boot_rom, + [SLAVE_CAMERA_CFG] =3D &qhs_camera_cfg, + [SLAVE_CLK_CTL] =3D &qhs_clk_ctl, + [SLAVE_CRYPTO_CFG] =3D &qhs_crypto_cfg, + [SLAVE_DISPLAY_CFG] =3D &qhs_display_cfg, + [SLAVE_EVA_CFG] =3D &qhs_eva_cfg, + [SLAVE_GFX3D_CFG] =3D &qhs_gpuss_cfg, + [SLAVE_I2C] =3D &qhs_i2c, + [SLAVE_IMEM_CFG] =3D &qhs_imem_cfg, + [SLAVE_IPC_ROUTER_CFG] =3D &qhs_ipc_router, + [SLAVE_IRIS_CFG] =3D &qhs_iris_cfg, + [SLAVE_CNOC_MSS] =3D &qhs_mss_cfg, + [SLAVE_PCIE_0_CFG] =3D &qhs_pcie_cfg, + [SLAVE_PCIE_1_CFG] =3D &qhs_pcie_g4x1_cfg, + [SLAVE_PRNG] =3D &qhs_prng, + [SLAVE_QSPI_0] =3D &qhs_qspi, + [SLAVE_QUP_1] =3D &qhs_qup1, + [SLAVE_QUP_2] =3D &qhs_qup2, + [SLAVE_QUP_3] =3D &qhs_qup3, + [SLAVE_QUP_4] =3D &qhs_qup4, + [SLAVE_SDCC_2] =3D &qhs_sdc2, + [SLAVE_SDCC_4] =3D &qhs_sdc4, + [SLAVE_TLMM] =3D &qhs_tlmm, + [SLAVE_UFS_MEM_CFG] =3D &qhs_ufs_mem_cfg, + [SLAVE_USB3] =3D &qhs_usb3, + [SLAVE_VSENSE_CTRL_CFG] =3D &qhs_vsense_ctrl_cfg, + [SLAVE_PCIE_ANOC_CFG] =3D &qss_pcie_anoc_cfg, + [SLAVE_QDSS_CFG] =3D &qss_qdss_cfg, + [SLAVE_QDSS_STM] =3D &qss_qdss_stm, + [SLAVE_TCSR] =3D &qss_tcsr, + [SLAVE_TCU] =3D &xs_sys_tcu_cfg, +}; + +static const struct regmap_config hawi_stdst_cfg_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xb1000, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc hawi_stdst_cfg =3D { + .config =3D &hawi_stdst_cfg_regmap_config, + .nodes =3D stdst_cfg_nodes, + .num_nodes =3D ARRAY_SIZE(stdst_cfg_nodes), + .bcms =3D stdst_cfg_bcms, + .num_bcms =3D ARRAY_SIZE(stdst_cfg_bcms), +}; + +static struct qcom_icc_node * const stdst_main_nodes[] =3D { + [MASTER_CNOC_STARDUST] =3D &qsm_cnoc_main, + [SLAVE_STARDUST_CENTER_CFG] =3D &qss_stdst_center_cfg, + [SLAVE_STARDUST_EAST_CFG] =3D &qss_stdst_east_cfg, + [SLAVE_STARDUST_MM_CFG] =3D &qss_stdst_mm_cfg, + [SLAVE_STARDUST_NORTH_CFG] =3D &qss_stdst_north_cfg, + [SLAVE_STARDUST_SOUTH_CFG] =3D &qss_stdst_south_cfg, + [SLAVE_STARDUST_SOUTHWEST_CFG] =3D &qss_stdst_southwest_cfg, +}; + +static const struct regmap_config hawi_stdst_main_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x10000, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc hawi_stdst_main =3D { + .config =3D &hawi_stdst_main_regmap_config, + .nodes =3D stdst_main_nodes, + .num_nodes =3D ARRAY_SIZE(stdst_main_nodes), +}; + +static struct qcom_icc_bcm * const system_noc_bcms[] =3D { + &bcm_sn0, + &bcm_sn2, +}; + +static struct qcom_icc_node * const system_noc_nodes[] =3D { + [MASTER_A1NOC_SNOC] =3D &qnm_aggre_noc, + [MASTER_APSS_NOC] =3D &qnm_apss_noc, + [MASTER_CNOC_SNOC] =3D &qnm_cnoc_data, + [SLAVE_SNOC_GEM_NOC_SF] =3D &qns_gemnoc_sf, +}; + +static const struct regmap_config hawi_system_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x20080, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc hawi_system_noc =3D { + .config =3D &hawi_system_noc_regmap_config, + .nodes =3D system_noc_nodes, + .num_nodes =3D ARRAY_SIZE(system_noc_nodes), + .bcms =3D system_noc_bcms, + .num_bcms =3D ARRAY_SIZE(system_noc_bcms), +}; + +static const struct of_device_id qnoc_of_match[] =3D { + { .compatible =3D "qcom,hawi-aggre1-noc", .data =3D &hawi_aggre1_noc }, + { .compatible =3D "qcom,hawi-clk-virt", .data =3D &hawi_clk_virt }, + { .compatible =3D "qcom,hawi-cnoc-main", .data =3D &hawi_cnoc_main }, + { .compatible =3D "qcom,hawi-gem-noc", .data =3D &hawi_gem_noc }, + { .compatible =3D "qcom,hawi-llclpi-noc", .data =3D &hawi_llclpi_noc }, + { .compatible =3D "qcom,hawi-lpass-ag-noc", .data =3D &hawi_lpass_ag_noc = }, + { .compatible =3D "qcom,hawi-lpass-lpiaon-noc", .data =3D &hawi_lpass_lpi= aon_noc }, + { .compatible =3D "qcom,hawi-lpass-lpicx-noc", .data =3D &hawi_lpass_lpic= x_noc }, + { .compatible =3D "qcom,hawi-mc-virt", .data =3D &hawi_mc_virt }, + { .compatible =3D "qcom,hawi-mmss-noc", .data =3D &hawi_mmss_noc }, + { .compatible =3D "qcom,hawi-nsp-noc", .data =3D &hawi_nsp_noc }, + { .compatible =3D "qcom,hawi-pcie-anoc", .data =3D &hawi_pcie_anoc }, + { .compatible =3D "qcom,hawi-stdst-cfg", .data =3D &hawi_stdst_cfg }, + { .compatible =3D "qcom,hawi-stdst-main", .data =3D &hawi_stdst_main }, + { .compatible =3D "qcom,hawi-system-noc", .data =3D &hawi_system_noc }, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver =3D { + .probe =3D qcom_icc_rpmh_probe, + .remove =3D qcom_icc_rpmh_remove, + .driver =3D { + .name =3D "qnoc-hawi", + .of_match_table =3D qnoc_of_match, + .sync_state =3D icc_sync_state, + }, +}; + +static int __init qnoc_driver_init(void) +{ + return platform_driver_register(&qnoc_driver); +} +core_initcall(qnoc_driver_init); + +static void __exit qnoc_driver_exit(void) +{ + platform_driver_unregister(&qnoc_driver); +} +module_exit(qnoc_driver_exit); + +MODULE_DESCRIPTION("Qualcomm Hawi NoC driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1