From nobody Sat Jun 13 16:26:32 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5FEAF47F2C4; Wed, 6 May 2026 14:10:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778076651; cv=none; b=KXuYNk+VoEIVJJfPueVbPp/M5ye/qSMoYsSWxP9uAJAfXE7nQwJcD27k95yIoIPvgGv1XIpTiQufmPd0N4HpnWEyxbWea5hNnwT8VuNYvl0HWCZaFF4Nqjhi7nO36stM9XHi3m5y7bGT9PI2RvZjVenylPt+GCoiZw+rruM49m8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778076651; c=relaxed/simple; bh=F9x43ZEfRU7wK83sMqGbjCkgc03IOGpd8Al76pMWLN0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hYbmDuWSlnXY+E++LABhDXA+Mf0NhpHE9Zu1/40hIjs9ElRJwr6e1n1jGjk3LDHU+eX6PS/yaBjWbdda+rXUgvGXvu5mqv9O4PXM5Ck8JwM+WKkrJ8EoosyVpgKuhv/ClCXNUxjEvALqxKvHZkr7u4SRxKzjs85CXJrDbigu8DQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=Gg2YnvfC; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Gg2YnvfC" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 38BE81A3551; Wed, 6 May 2026 14:10:48 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 0E2A16053C; Wed, 6 May 2026 14:10:48 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 87D4C107F1644; Wed, 6 May 2026 16:10:46 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1778076647; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=oIGsjd/LijliH2kV2hyJFY2dEYw5fLzhdT3QlZJobf4=; b=Gg2YnvfCzTmyJlxv3sllWicBiCSCFKpJ/hcZbrYaNJArPV0bwNA2kju0Sqblfl3FkIQgfk NZz5kuHR7Y8emHbSwGgHq5nhysU+cbNbZgPRoVrjNV2LbvyydSLH0AWvDYK3oE0hKsAiDn D5Fz9TiOe1wIc706oRNKSh2dLFvR0g4ffYnevOYNk/vO11E7FPrtlKt8YcTp0bMiAgTbj8 t5+jV6NJ1rkl6bEVhj0fEvg9oIiK1LPUWK+QkKXjZQAV2hD8CfSnKfU0RLTK3gsyDo2z8B 6MhWMldMC9spu3qZFx5n+6q1Vl9plSrnQmmbfnXd8WoqF0WHat8LQN918Sa2Vg== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Wed, 06 May 2026 16:10:35 +0200 Subject: [PATCH v2 1/2] dmaengine: fsl-edma: Implement device_prep_peripheral_dma_vec Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260506-fsl-edma-dyn-sg-v2-1-66439cdd414e@bootlin.com> References: <20260506-fsl-edma-dyn-sg-v2-0-66439cdd414e@bootlin.com> In-Reply-To: <20260506-fsl-edma-dyn-sg-v2-0-66439cdd414e@bootlin.com> To: Frank Li , Vinod Koul Cc: Thomas Petazzoni , Frank Li , imx@lists.linux.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.15.2 X-Last-TLS-Session-Version: TLSv1.3 Add implementation of .device_prep_peripheral_dma_vec() callback to setup a scatter/gather DMA transfer from an array of dma_vec structures. Setup a cyclic transfer if the DMA_PREP_REPEAT flag is set. Signed-off-by: Beno=C3=AEt Monin --- drivers/dma/fsl-edma-common.c | 110 ++++++++++++++++++++++++++++++++++++++= ++++ drivers/dma/fsl-edma-common.h | 4 ++ drivers/dma/fsl-edma-main.c | 2 + 3 files changed, 116 insertions(+) diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index bb7531c456df..26a5ecf493b9 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -673,6 +673,116 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyc= lic( return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); } =20 +struct dma_async_tx_descriptor *fsl_edma_prep_peripheral_dma_vec( + struct dma_chan *chan, const struct dma_vec *vecs, + size_t nb, enum dma_transfer_direction direction, + unsigned long flags) +{ + struct fsl_edma_chan *fsl_chan =3D to_fsl_edma_chan(chan); + struct fsl_edma_desc *fsl_desc; + dma_addr_t src_addr, dst_addr, last_sg; + u16 soff, doff, iter; + u32 nbytes; + int i; + + if (!is_slave_direction(direction)) + return NULL; + + if (!fsl_edma_prep_slave_dma(fsl_chan, direction)) + return NULL; + + fsl_desc =3D fsl_edma_alloc_desc(fsl_chan, nb); + if (!fsl_desc) + return NULL; + fsl_desc->iscyclic =3D flags & DMA_PREP_REPEAT; + fsl_desc->dirn =3D direction; + + if (direction =3D=3D DMA_MEM_TO_DEV) { + if (!fsl_chan->cfg.src_addr_width) + fsl_chan->cfg.src_addr_width =3D fsl_chan->cfg.dst_addr_width; + fsl_chan->attr =3D + fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width, + fsl_chan->cfg.dst_addr_width); + nbytes =3D fsl_chan->cfg.dst_addr_width * + fsl_chan->cfg.dst_maxburst; + } else { + if (!fsl_chan->cfg.dst_addr_width) + fsl_chan->cfg.dst_addr_width =3D fsl_chan->cfg.src_addr_width; + fsl_chan->attr =3D + fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width, + fsl_chan->cfg.dst_addr_width); + nbytes =3D fsl_chan->cfg.src_addr_width * + fsl_chan->cfg.src_maxburst; + } + + for (i =3D 0; i < nb; i++) { + if (direction =3D=3D DMA_MEM_TO_DEV) { + src_addr =3D vecs[i].addr; + dst_addr =3D fsl_chan->dma_dev_addr; + soff =3D fsl_chan->cfg.dst_addr_width; + doff =3D 0; + } else if (direction =3D=3D DMA_DEV_TO_MEM) { + src_addr =3D fsl_chan->dma_dev_addr; + dst_addr =3D vecs[i].addr; + soff =3D 0; + doff =3D fsl_chan->cfg.src_addr_width; + } else { + /* DMA_DEV_TO_DEV */ + src_addr =3D fsl_chan->cfg.src_addr; + dst_addr =3D fsl_chan->cfg.dst_addr; + soff =3D 0; + doff =3D 0; + } + + /* + * Choose the suitable burst length if dma_vec length is not + * multiple of burst length so that the whole transfer length is + * multiple of minor loop(burst length). + */ + if (vecs[i].len % nbytes) { + u32 width =3D (direction =3D=3D DMA_DEV_TO_MEM) ? doff : soff; + u32 burst =3D (direction =3D=3D DMA_DEV_TO_MEM) ? + fsl_chan->cfg.src_maxburst : + fsl_chan->cfg.dst_maxburst; + int j; + + for (j =3D burst; j > 1; j--) { + if (!(vecs[i].len % (j * width))) { + nbytes =3D j * width; + break; + } + } + /* Set burst size as 1 if there's no suitable one */ + if (j =3D=3D 1) + nbytes =3D width; + } + iter =3D vecs[i].len / nbytes; + if (i < nb - 1) { + last_sg =3D fsl_desc->tcd[(i + 1)].ptcd; + fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, + dst_addr, fsl_chan->attr, soff, + nbytes, 0, iter, iter, doff, last_sg, + false, false, true); + } else { + if (fsl_desc->iscyclic) { + last_sg =3D fsl_desc->tcd[0].ptcd; + fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, + dst_addr, fsl_chan->attr, soff, + nbytes, 0, iter, iter, doff, last_sg, + true, false, true); + } else { + last_sg =3D 0; + fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, + dst_addr, fsl_chan->attr, soff, + nbytes, 0, iter, iter, doff, last_sg, + true, true, false); + } + } + } + + return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); +} + struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, enum dma_transfer_direction direction, diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h index 205a96489094..0d028048701d 100644 --- a/drivers/dma/fsl-edma-common.h +++ b/drivers/dma/fsl-edma-common.h @@ -496,6 +496,10 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cycl= ic( struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, size_t period_len, enum dma_transfer_direction direction, unsigned long flags); +struct dma_async_tx_descriptor *fsl_edma_prep_peripheral_dma_vec( + struct dma_chan *chan, const struct dma_vec *vecs, + size_t nb, enum dma_transfer_direction direction, + unsigned long flags); struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, enum dma_transfer_direction direction, diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c index 36155ab1602a..6693b4270a1a 100644 --- a/drivers/dma/fsl-edma-main.c +++ b/drivers/dma/fsl-edma-main.c @@ -841,6 +841,8 @@ static int fsl_edma_probe(struct platform_device *pdev) fsl_edma->dma_dev.device_free_chan_resources =3D fsl_edma_free_chan_resources; fsl_edma->dma_dev.device_tx_status =3D fsl_edma_tx_status; + fsl_edma->dma_dev.device_prep_peripheral_dma_vec + =3D fsl_edma_prep_peripheral_dma_vec; fsl_edma->dma_dev.device_prep_slave_sg =3D fsl_edma_prep_slave_sg; fsl_edma->dma_dev.device_prep_dma_cyclic =3D fsl_edma_prep_dma_cyclic; fsl_edma->dma_dev.device_prep_dma_memcpy =3D fsl_edma_prep_memcpy; --=20 2.54.0 From nobody Sat Jun 13 16:26:32 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB9E447F2E4; Wed, 6 May 2026 14:10:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778076652; cv=none; b=BMrk+rXJqoV8vEjfIRZ7f+PLRuowbf9NF+v0tO5UqQHz5TDvc9WbdKYBYEx/JQGZhTT65rnVvu9OrCd87tD3BEYCJicDPtSdfRun/MDSRJBVfzCbDK2DcgiagUuR9suYyAp4Rw1ZzVMjkJ+FNRSrU/nQyFoe0MGC2pvboa9G6xU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778076652; c=relaxed/simple; bh=1bwhwdfvJlIzsKkfaxkktge9gzD6L0rgkayWyCUNTsY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=k238fhRLz/t319EXTgXBRchvxZLCAK7yzv2iBKRq/qWheF1eyEHXqIf+RBFvGYH0ed/09vKkdjtDSsboN8NBji5ckeXfjXwmTq/kZs0hNYHK55DEX3+yyJIZCqfRlUelqXgWlO0v4jEWKgmtOdb8SkkogX+UabuO/uedSlCRSng= ARC-Authentication-Results: i=1; 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Wed, 6 May 2026 16:10:47 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1778076648; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=aQaOLDa6vezVg2B4JDopiCIwlU8Ntmkdr40yY+rXlOE=; b=nykStisR8Wi7ZQ9Eb4vjpnhsyAWt3tF0zF/p60/x5QJHZwFpkegkv5N8ceOoUo8issltIk 3SX+bnsEmM6s5XU5Pj4GipTPb7nbhr9ZpJUabTYepuTNwplZvWmQhTQMblDmEWJylFkDbm cA8cnu8+3K+ooJTnedPeg47XOu7qOLVcMZtwGG/Uymvhf0Si6Xy+eMpdyPd/dHI8jOonyw boSDKMS3CNDwSj+L2TFzsviBEuCPe2oZnSs+VcYLd8OViURCumqgeiDqwg6yo3drrKhZPT E2bDdCx/+6ZnZvNawGpqOsLakUeerMcqV4K6DxyeuRtvEtMZOcbF7l1H+5aj7Q== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Wed, 06 May 2026 16:10:36 +0200 Subject: [PATCH v2 2/2] dmaengine: fsl-edma: Support dynamic scatter/gather chaining Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260506-fsl-edma-dyn-sg-v2-2-66439cdd414e@bootlin.com> References: <20260506-fsl-edma-dyn-sg-v2-0-66439cdd414e@bootlin.com> In-Reply-To: <20260506-fsl-edma-dyn-sg-v2-0-66439cdd414e@bootlin.com> To: Frank Li , Vinod Koul Cc: Thomas Petazzoni , Frank Li , imx@lists.linux.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.15.2 X-Last-TLS-Session-Version: TLSv1.3 Implement dynamic linking of scatter/gather transfers to enable chaining multiple DMA descriptors without stopping the channel. This avoids waiting for the channel to go idle if there is another transaction already issued. Add fsl_edma_link_sg() to dynamically link the last TCD of a previously submitted descriptor to the first TCD of a new descriptor by setting the scatter/gather address and the E_SG flag, and keeping the channel active by clearing the DREQ bit. Linking is only done if the last TCD was set to disable the DMA channel, to prevent corrupting cyclic transaction. Update fsl_edma_xfer_desc() to avoid re-initializing the hardware when a transfer is already in progress, allowing seamless chaining of descriptors. Modify the transfer completion handler to check the DONE flag in the channel CSR before marking the transfer complete. Since this flag is only available on SoC with the split registers layout, we only link transactions for DMA controllers flagged with FSL_EDMA_DRV_SPLIT_REG. Add trace event for scatter/gather linking operations. Signed-off-by: Beno=C3=AEt Monin --- drivers/dma/fsl-edma-common.c | 64 +++++++++++++++++++++++++++++++++++++++= +--- drivers/dma/fsl-edma-trace.h | 5 ++++ 2 files changed, 65 insertions(+), 4 deletions(-) diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index 26a5ecf493b9..7094c747defa 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -58,7 +58,10 @@ void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_= chan) list_del(&fsl_chan->edesc->vdesc.node); vchan_cookie_complete(&fsl_chan->edesc->vdesc); fsl_chan->edesc =3D NULL; - fsl_chan->status =3D DMA_COMPLETE; + if (!(fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_SPLIT_REG) || + (edma_readl_chreg(fsl_chan, ch_csr) & EDMA_V3_CH_CSR_DONE)) { + fsl_chan->status =3D DMA_COMPLETE; + } } else { vchan_cyclic_callback(&fsl_chan->edesc->vdesc); } @@ -673,6 +676,51 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cycl= ic( return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); } =20 +static void fsl_edma_link_sg(struct fsl_edma_chan *fsl_chan, struct fsl_ed= ma_desc *fsl_desc) +{ + u32 flags =3D fsl_edma_drvflags(fsl_chan); + struct virt_dma_desc *vdesc; + struct fsl_edma_desc *prev_desc; + struct fsl_edma_hw_tcd *last_tcd; + u16 csr; + + if (!(flags & FSL_EDMA_DRV_SPLIT_REG)) + return; + + guard(spinlock_irqsave)(&fsl_chan->vchan.lock); + + vdesc =3D list_last_entry_or_null(&fsl_chan->vchan.desc_issued, + struct virt_dma_desc, node); + if (!vdesc) + vdesc =3D list_last_entry_or_null(&fsl_chan->vchan.desc_submitted, + struct virt_dma_desc, node); + if (!vdesc) + return; + + prev_desc =3D to_fsl_edma_desc(vdesc); + last_tcd =3D prev_desc->tcd[prev_desc->n_tcds - 1].vtcd; + + csr =3D fsl_edma_get_tcd_to_cpu(fsl_chan, last_tcd, csr); + if (!(csr & EDMA_TCD_CSR_D_REQ)) + return; + + fsl_edma_set_tcd_to_le(fsl_chan, last_tcd, fsl_desc->tcd[0].ptcd, dlast_s= ga); + + csr &=3D ~EDMA_TCD_CSR_D_REQ; + csr |=3D EDMA_TCD_CSR_E_SG; + fsl_edma_set_tcd_to_le(fsl_chan, last_tcd, csr, csr); + + if (prev_desc =3D=3D fsl_chan->edesc && prev_desc->n_tcds =3D=3D 1) { + if (flags & FSL_EDMA_DRV_CLEAR_DONE_E_SG) + edma_writel_chreg(fsl_chan, edma_readl_chreg(fsl_chan, ch_csr), ch_csr); + + edma_cp_tcd_to_reg(fsl_chan, last_tcd, dlast_sga); + edma_cp_tcd_to_reg(fsl_chan, last_tcd, csr); + } + + trace_edma_link_sg(fsl_chan, last_tcd); +} + struct dma_async_tx_descriptor *fsl_edma_prep_peripheral_dma_vec( struct dma_chan *chan, const struct dma_vec *vecs, size_t nb, enum dma_transfer_direction direction, @@ -780,6 +828,9 @@ struct dma_async_tx_descriptor *fsl_edma_prep_periphera= l_dma_vec( } } =20 + if (!fsl_desc->iscyclic) + fsl_edma_link_sg(fsl_chan, fsl_desc); + return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); } =20 @@ -883,6 +934,8 @@ struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( } } =20 + fsl_edma_link_sg(fsl_chan, fsl_desc); + return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); } =20 @@ -925,9 +978,12 @@ void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan) if (!vdesc) return; fsl_chan->edesc =3D to_fsl_edma_desc(vdesc); - fsl_edma_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd); - fsl_edma_enable_request(fsl_chan); - fsl_chan->status =3D DMA_IN_PROGRESS; + + if (fsl_chan->status !=3D DMA_IN_PROGRESS) { + fsl_edma_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd); + fsl_edma_enable_request(fsl_chan); + fsl_chan->status =3D DMA_IN_PROGRESS; + } } =20 void fsl_edma_issue_pending(struct dma_chan *chan) diff --git a/drivers/dma/fsl-edma-trace.h b/drivers/dma/fsl-edma-trace.h index d3541301a247..ac319d2dbb90 100644 --- a/drivers/dma/fsl-edma-trace.h +++ b/drivers/dma/fsl-edma-trace.h @@ -119,6 +119,11 @@ DEFINE_EVENT(edma_log_tcd, edma_fill_tcd, TP_ARGS(chan, tcd) ); =20 +DEFINE_EVENT(edma_log_tcd, edma_link_sg, + TP_PROTO(struct fsl_edma_chan *chan, void *tcd), + TP_ARGS(chan, tcd) +); + #endif =20 /* this part must be outside header guard */ --=20 2.54.0