From nobody Sat Jun 13 21:03:55 2026 Received: from e3i722.smtp2go.com (e3i722.smtp2go.com [158.120.86.210]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8C322D781B for ; Tue, 5 May 2026 12:48:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=158.120.86.210 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777985307; cv=none; b=PT+QHtrsTapNE/q+BJZDtCkUoFDxfkQOUaAiYw4P65T59vV5FrrOIHFi5mbLZT78UN/PFIj5Mdu+G+0bcXJUYyDiNLi8iSUfA300coKDG9pKTyjrs6Taik7pUzppV5wUDcbN8PRR37b8vCOrHyWQM/2LqOYemM3y5Bpsiu1m0e0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777985307; c=relaxed/simple; bh=mk+rFQLU+jQ2sP/cds/Xv011r7PxGkbieb1wnjY/+7A=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=B/4zs77rMSqGQsMa1iiIFnjLQJIJOkuYQLQmiI8MBIUzk/hJbYgvN2WiPk5T2PayczyGpu3dApH7ySnaaojND4lV2ZeZATJA04vjgZi48qJXANVliHXaF9E1aCUVlRQUGMK+rdyvjyleI9F243ZktFiexW8/hVW+SDJ3UME7MCk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=asem.it; spf=pass smtp.mailfrom=em1174574.asem.it; dkim=pass (2048-bit key) header.d=asem.it header.i=@asem.it header.b=QOt4FLfF; arc=none smtp.client-ip=158.120.86.210 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=asem.it Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=em1174574.asem.it Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=asem.it header.i=@asem.it header.b="QOt4FLfF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=asem.it; i=@asem.it; q=dns/txt; s=s1174574; t=1777984096; h=from : subject : to : message-id : date; bh=LX0JgHkYWsWkuj5Lnu48cQL8XdFDHKX3eJL79r215z0=; b=QOt4FLfFG+1siNNEysDj4gc96ZXFuU5PlIXbuTo88aAFRDFEmmsmT/DvHyZqNQ5T/a5cC U7cslAyGJJipTt65bdYR0kdkSKJ1F+m+VdQ9nLN53IH4Kw3lGk5wGRWJJDZ9Wqe0PSvSS+c BSafnTjcua6FECS6iMllSyBGur9u7sGhCt1yslV19Fs98r4a1vo/2nJO1cMWdLewE4qmvC7 9aPpwnHL0e1Z/mh10lp1OLtg+OCQwqrb4CswTAtWJB8W95co398wC7PXJQ6fgENl/D86pNm M2Hfyiws6MOXCG+qpIMQDNBFw2BJQyeYal0SJqh2iGdpXXddhl4sQVbrr4PQ== Received: from [10.86.249.198] (helo=asas054.asem.intra) by smtpcorp.com with esmtpa (Exim 4.99.1-S2G) (envelope-from ) id 1wKEsn-4o5NDgrm55y-ur0n; Tue, 05 May 2026 12:28:13 +0000 Received: from asem-ThinkStation-P330.asem.intra ([172.16.23.8]) by asas054.asem.intra with Microsoft SMTPSVC(10.0.14393.4169); Tue, 5 May 2026 14:28:11 +0200 From: Luca Ellero To: Cc: Luca Ellero , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] net: phy: dp83867: add MDI-X management Date: Tue, 5 May 2026 14:27:30 +0200 Message-ID: <20260505122751.233764-1-l.ellero@asem.it> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 05 May 2026 12:28:11.0853 (UTC) FILETIME=[A35B27D0:01DCDC8A] X-Report-Abuse: Please forward a copy of this message, including all headers, to Feedback-ID: 1174574m:1174574aXfMg4B:1174574s4bGKX1ra- X-smtpcorp-track: UvTO5csN7j6r.fDy2dbeXwmDH.6vCvNQ_zNUG Content-Type: text/plain; charset="utf-8" ethtool on this phy device always reports "MDI-X: Unknown" and doesn't support forcing it to on or off. This patch adds support for reading/forcing MDI-X mode from ethtool properly. Signed-off-by: Luca Ellero Reviewed-by: Andrew Lunn --- drivers/net/phy/dp83867.c | 60 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 3fb2293f568f..88255e92b4cd 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -103,6 +103,10 @@ #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12) #define DP83867_PHYCR_SGMII_EN BIT(11) #define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10) +#define DP83867_PHYCR_MDIX_MASK GENMASK(6, 5) +#define DP83867_PHYCR_MDIX_MDI (0x0 << 5) +#define DP83867_PHYCR_MDIX_MDIX (0x1 << 5) +#define DP83867_PHYCR_MDIX_AUTO (0x3 << 5) =20 /* RGMIIDCTL bits */ #define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf @@ -123,6 +127,10 @@ #define DP83867_PHYSTS_100 BIT(14) #define DP83867_PHYSTS_DUPLEX BIT(13) #define DP83867_PHYSTS_LINK BIT(10) +#define DP83867_PHYSTS_MDIX_CD BIT(9) +#define DP83867_PHYSTS_MDIX_AB BIT(8) +#define DP83867_PHYSTS_MDIX_MASK (DP83867_PHYSTS_MDIX_AB | \ + DP83867_PHYSTS_MDIX_CD) =20 /* CFG2 bits */ #define DP83867_DOWNSHIFT_EN (BIT(8) | BIT(9)) @@ -391,6 +399,22 @@ static int dp83867_read_status(struct phy_device *phyd= ev) else phydev->speed =3D SPEED_10; =20 + if (!(status & DP83867_PHYSTS_LINK)) { + phydev->mdix =3D ETH_TP_MDI_INVALID; + } else { + switch (status & DP83867_PHYSTS_MDIX_MASK) { + case 0: + phydev->mdix =3D ETH_TP_MDI; + break; + case DP83867_PHYSTS_MDIX_MASK: + phydev->mdix =3D ETH_TP_MDI_X; + break; + default: + phydev->mdix =3D ETH_TP_MDI_INVALID; + break; + } + } + return 0; } =20 @@ -714,6 +738,8 @@ static int dp83867_config_init(struct phy_device *phyde= v) struct dp83867_private *dp83867 =3D phydev->priv; int ret, val, bs; =20 + phydev->mdix_ctrl =3D ETH_TP_MDI_AUTO; + /* Force speed optimization for the PHY even if it strapped */ ret =3D phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN, DP83867_DOWNSHIFT_EN); @@ -873,6 +899,39 @@ static int dp83867_config_init(struct phy_device *phyd= ev) return 0; } =20 +static int dp83867_config_mdix(struct phy_device *phydev, u8 ctrl) +{ + int val; + + switch (ctrl) { + case ETH_TP_MDI: + val =3D DP83867_PHYCR_MDIX_MDI; + break; + case ETH_TP_MDI_X: + val =3D DP83867_PHYCR_MDIX_MDIX; + break; + case ETH_TP_MDI_AUTO: + val =3D DP83867_PHYCR_MDIX_AUTO; + break; + default: + return -EINVAL; + } + + return phy_modify(phydev, MII_DP83867_PHYCTRL, + DP83867_PHYCR_MDIX_MASK, val); +} + +static int dp83867_config_aneg(struct phy_device *phydev) +{ + int ret; + + ret =3D dp83867_config_mdix(phydev, phydev->mdix_ctrl); + if (ret) + return ret; + + return genphy_config_aneg(phydev); +} + static int dp83867_phy_reset(struct phy_device *phydev) { int err; @@ -1127,6 +1186,7 @@ static struct phy_driver dp83867_driver[] =3D { =20 .probe =3D dp83867_probe, .config_init =3D dp83867_config_init, + .config_aneg =3D dp83867_config_aneg, .soft_reset =3D dp83867_phy_reset, =20 .read_status =3D dp83867_read_status, --=20 2.43.0