From nobody Sat Jun 13 23:11:40 2026 Received: from mail-pj1-f52.google.com (mail-pj1-f52.google.com [209.85.216.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FCB4407586 for ; Tue, 5 May 2026 10:40:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777977622; cv=none; b=PYWBS1xM/AtKhXjWdGFf1rQYrBz9a5V0m2UQXEIryGCwzpFLP2Pff0jCllGLzRoIK8I3IFkMB9I3ecHwXqCxtvBww8k0r3oipfmIUO/p46CQg0uK6qQfr2cli6LpdMfNrebZOVTkbWMfSzQIdmvSuDJPzhc4OvlNxZAwMk4zYHM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777977622; c=relaxed/simple; bh=YgX6zDqwgAjF1wfOfkqJgvIaxwi+YUqagxblfy0AVXE=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=Tdb7ypmnjZMXM8Ufl7pQ+MFIDDAOGWLnxzaBeMcXMqysvQaJQm/qfqUL8PZyfoXsKGGWEy38efMedIQkt3RIjzOQ7W08siVOqpx28hP+qAksuyiYj4zSfz2UlZwafLfbcidIG2b+zCsFOLmIgljRdnJGMdbHndIogefLrmiLyxA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=YMXXEW5v; arc=none smtp.client-ip=209.85.216.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="YMXXEW5v" Received: by mail-pj1-f52.google.com with SMTP id 98e67ed59e1d1-3650453fb28so2120690a91.2 for ; Tue, 05 May 2026 03:40:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1777977619; x=1778582419; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=Ca+XUMwON/y8z0Ya9sLBgz3BNFKT0t9cdvMxmASzxGQ=; b=YMXXEW5vflEtT79Z9Z8LrNLQ72feAa6PICfVUsxd1vvp79RG84V3UHcWDm7Vmiu8fr ZGg9fPz2ldQIP7djYZvR8xsK7kyyW85pcZq/Xr7ttP70AJrcoQBTziSJqDwSu0jSr8M0 loWzbP11oymC4/IF6XEttAPA4rlITRngSAV2o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777977619; x=1778582419; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=Ca+XUMwON/y8z0Ya9sLBgz3BNFKT0t9cdvMxmASzxGQ=; b=HUjKaJf0sC+OJVfpre4XMY5OpauQLDhYycoscIXeost4lAoEI4Vi7FiZFZVm/3Z3jr iG40eyBAtN38PS07NL6nS2qqLw4tjnrNTZScihHmqMX1nPlP3Wc8q7nxtcd4e7lgB+L6 vw5zVXSY9GNkLINAlFKbeedD/1D2S9nuCrzZn8F6pxLwU29zqWMPnL+Oemb7f1aif1i9 W8YCArkU6oBEwF2+Xc8qJJYBmkgmMjwG5zkr2fhAI7bvjbjmw2cJSwnyW/M0tB/ZXbWn pZKnLn4/ftnuWLXFhbpdbkfLUyeeWbDnmNTUp8dpgRCfZ0B4dDMlAz90gO/9AqP223Up 9rmA== X-Forwarded-Encrypted: i=1; AFNElJ/ryoLSF5Q6LxDbfFMliAl0rkCMOIXuWstBvj9TsxeCK9Y0vdnI/sX3nCIblk+OPhzw99snn9lRfXauTZA=@vger.kernel.org X-Gm-Message-State: AOJu0Yy0RhMOXvfB0ayzvwRCJ2x8PDZsrQ8l+tvB47pAbjA1DGMzBcqG pJghZ16TBcHG2mkf1hhfiVL454CbEL7A59Xi0lVTx3xTqiKc5ZciFeEhtI4LRr/g0A== X-Gm-Gg: AeBDietT865WfiEDvBjujalgNxUkGUdz++PbiteskznNl3HkyGdVdYnD7cD0ZSUmrxo 6COaYXvw0F/sGtJtAqPluLYrQR3H99RE0JAl+YjJWXea903UjtDlJ8E125Otaf1TiBROWGYrIl8 RPRVxoomjqN6FcI8ZgpT6Zs9reW3C96IkhJMipY8uZBex9CSlWMXo1wv7zqThF8GGNxAASdlwiG Wep9z0e0M6XWLzn1g5UKsb+IubfNFrcS+J64+gqsczE+ALKgHMkpf+l54fuTztiYizjT9jC+wZ6 7I0xHo1jUOR6PxHck61RqcrkPbhM0XGRQnEMORvqzDCDUbFz72E/rWjkIhfjqfxB0cSmIsqbaQ1 w80K4d62V2YP5aNEyAKVGPyc1gzCfutAF79UGRvcpo26S+depxmZOoX5MUmPBMrEn+qeFINgWu6 AXCdx97NIlPEc9yRSBcfaTVOODvXukI7n6sD3iT++YnB6DF1GjpbTvrX/8uRvz4rK/dM/1HlGXQ QyaYATfjvHb7cSnQuc= X-Received: by 2002:a17:902:d585:b0:2b4:5e65:5d0e with SMTP id d9443c01a7336-2ba535db45fmr22307405ad.10.1777977619585; Tue, 05 May 2026 03:40:19 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2a00:79e0:201d:8:f1d4:2ef0:7d08:9dd8]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b9cae1e293sm141015395ad.45.2026.05.05.03.40.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 May 2026 03:40:19 -0700 (PDT) From: Chen-Yu Tsai To: Sean Wang , Matthias Brugger , AngeloGioacchino Del Regno , Linus Walleij Cc: Chen-Yu Tsai , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2] pinctrl: mediatek: paris: bypass pinctrl GPIO layer in set GPIO direction Date: Tue, 5 May 2026 18:39:57 +0800 Message-ID: <20260505104003.1811841-1-wenst@chromium.org> X-Mailer: git-send-email 2.54.0.545.g6539524ca2-goog Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" pinctrl_gpio_direction_input() / pinctrl_gpio_direction_output() take the pinctrl mutex. This causes a gpiochip operations to need to sleep. Worse yet, the .can_sleep field in the gpiochip is not set. This causes the shared GPIO proxy to trip over, as it uses gpiod_cansleep() to check whether it can use a spinlock or needs a mutex. In this case, it ends up taking a spinlock, then calls pinctrl_gpio_direction_output(), which takes a mutex. This causes a huge warning. While this class of Mediatek hardware does not have separate clear/set registers, the pinctrl context has a spinlock that is taken whenever a register read-modify-write is done. Also, once the GPIO function is selected / muxed in, further GPIO operations do not involve pinctrl operations or state. The GPIO direction and level values do not require toggling the pinmux or any other pin config options. Switch to directly calling mtk_pinmux_gpio_set_direction() in the GPIO set direction callbacks to avoid taking the pinctrl mutex. Drop the .gpio_set_direction field in mtk_pmxops to signal we are no longer using the pinctrl GPIO layer for setting the direction. Signed-off-by: Chen-Yu Tsai --- This was pinctrl: mediatek: paris: Directly modify registers to set GPIO directi= on Changes since v1: - Dropped .gpio_set_direction field in mtk_pmxops - Call mtk_pinmux_gpio_set_direction() from mtk_gpio_direction_(output|input)() - Updated commit subject and message - Link to v1: https://lore.kernel.org/all/20260427021021.2049015-1-wenst@chromium.org/ --- drivers/pinctrl/mediatek/pinctrl-paris.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/med= iatek/pinctrl-paris.c index 6bf37d8085fa..23f04b24fd65 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -771,7 +771,6 @@ static const struct pinmux_ops mtk_pmxops =3D { .get_function_name =3D mtk_pmx_get_func_name, .get_function_groups =3D mtk_pmx_get_func_groups, .set_mux =3D mtk_pmx_set_mux, - .gpio_set_direction =3D mtk_pinmux_gpio_set_direction, .gpio_request_enable =3D mtk_pinmux_gpio_request_enable, }; =20 @@ -886,19 +885,22 @@ static int mtk_gpio_set(struct gpio_chip *chip, unsig= ned int gpio, int value) =20 static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int g= pio) { - return pinctrl_gpio_direction_input(chip, gpio); + struct mtk_pinctrl *hw =3D gpiochip_get_data(chip); + + return mtk_pinmux_gpio_set_direction(hw->pctrl, NULL, gpio, true); } =20 static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int = gpio, int value) { + struct mtk_pinctrl *hw =3D gpiochip_get_data(chip); int ret; =20 ret =3D mtk_gpio_set(chip, gpio, value); if (ret) return ret; =20 - return pinctrl_gpio_direction_output(chip, gpio); + return mtk_pinmux_gpio_set_direction(hw->pctrl, NULL, gpio, false); } =20 static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) --=20 2.54.0.545.g6539524ca2-goog