From nobody Sun Jun 14 00:14:08 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97BC83D171E; Tue, 5 May 2026 07:13:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777965232; cv=none; b=JZ7Q8cuSOjifDO/KXiszaNuJcnDC1o5z6rOLN80kUpr2ClX+EpqG+xGGRkQ83GcKnyRUCGrdJqgZkvrpnWBbB7KKZqoYS1rB6+6ahtP+pCHGN0ZZ2UX+09KnUy9T4pSW8EXiVbVRCMWew4JWY+OWiPG/phbYjXq1sG9TkN7aq4w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777965232; c=relaxed/simple; bh=Wb9iATfXW8/7d/+1AO6j/ytPYVfI1bbWli+zPTIAHOo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Nb8Tb9fQ6V7gvagnaYFc7Z8JbcVAy2iadg82SC7h/g4jg1FqSmhlL1wUOGYxMENTkDC9M0zVWEdXmmxYibwN1znrOvqJJNm0w/iqjpbgKEMoWtqqBKT1SlKw8OGWAM8ZwGgv0tHHa42O4qr9ma6lsQYK+/SLL9l4JDqvx2abTuE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=rAccC1e+; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="rAccC1e+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1777965231; x=1809501231; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Wb9iATfXW8/7d/+1AO6j/ytPYVfI1bbWli+zPTIAHOo=; b=rAccC1e+o/hEX3gKm9K0yQSH0oR2DsgBHfGqXbq7vaRm3dGpjtBkTOvL seLomHMfiafMWrBIQb8DZA6yJqA0J3lUK6VxLzeQ5swV3vvp5YgbCZSp4 rEyYMZ48fbTxB1keRtvbAwithwRuof6isVM5uVrO3GPiBAsFzG3gcL8X/ 6He8Ig+bdvTjXnREupo2p8vJ+kgJZdzck+2z+Az2QClF2tFpFSQFbte8M DFwpKphI0c9W9jJRQH1NKwBy24f8OSsxAiEGjvqy2MAn73NiiTK11LEKh vzdjlrPKu47lnKvM8mB6yK/ABxRvJXBEPi1cTGC6q/ShTVbwry9rBOYSg g==; X-CSE-ConnectionGUID: KCFYOMZvRKygeX0nADignw== X-CSE-MsgGUID: 2FbC94D9Si+NVQDEp7pSVw== X-IronPort-AV: E=Sophos;i="6.23,217,1770620400"; d="scan'208";a="56268024" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2026 00:13:50 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.87.152) by chn-vm-ex1.mchp-main.com (10.10.87.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.37; Tue, 5 May 2026 00:13:50 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 5 May 2026 00:13:42 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v5 1/5] dt-bindings: i3c: mipi-i3c-hci: add Microchip SAMA7D65 compatible Date: Tue, 5 May 2026 12:43:23 +0530 Message-ID: <20260505071327.125787-2-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260505071327.125787-1-manikandan.m@microchip.com> References: <20260505071327.125787-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the microchip,sama7d65-i3c-hci compatible string to the MIPI I3C HCI binding. The Microchip SAMA7D65 I3C controller is based on the MIPI HCI specification but requires two clocks, so add a conditional constraint when this compatible is present. Signed-off-by: Manikandan Muralidharan Acked-by: Conor Dooley --- Changes in v5: - drop min/maxItems around clock - use else clause - cosmetic fixes Changes in v4: - Define and describe the clock in the top-level properties --- .../devicetree/bindings/i3c/mipi-i3c-hci.yaml | 27 ++++++++++++++++--- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml b/Docu= mentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml index 39bb1a1784c9..d488fb420945 100644 --- a/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml +++ b/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml @@ -9,9 +9,6 @@ title: MIPI I3C HCI maintainers: - Nicolas Pitre =20 -allOf: - - $ref: /schemas/i3c/i3c.yaml# - description: | MIPI I3C Host Controller Interface =20 @@ -28,9 +25,17 @@ description: | =20 properties: compatible: - const: mipi-i3c-hci + enum: + - mipi-i3c-hci + - microchip,sama7d65-i3c-hci reg: maxItems: 1 + + clocks: + items: + - description: Peripheral bus clock + - description: System Generic clock + interrupts: maxItems: 1 =20 @@ -39,6 +44,20 @@ required: - reg - interrupts =20 +allOf: + - $ref: /schemas/i3c/i3c.yaml# + - if: + properties: + compatible: + contains: + const: microchip,sama7d65-i3c-hci + then: + required: + - clocks + else: + properties: + clocks: false + unevaluatedProperties: false =20 examples: --=20 2.25.1 From nobody Sun Jun 14 00:14:08 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4605C3C197F; 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charset="utf-8" From: Durai Manickam KR Add peripheral clock description for I3C. Signed-off-by: Durai Manickam KR Signed-off-by: Manikandan Muralidharan --- changes in v3: - Fixed indentation issues --- drivers/clk/at91/sama7d65.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c index 7dee2b160ffb..ba8ff413fa2c 100644 --- a/drivers/clk/at91/sama7d65.c +++ b/drivers/clk/at91/sama7d65.c @@ -677,6 +677,7 @@ static struct { { .n =3D "uhphs_clk", .p =3D PCK_PARENT_HW_MCK5, .id =3D 101, }, { .n =3D "dsi_clk", .p =3D PCK_PARENT_HW_MCK3, .id =3D 103, }, { .n =3D "lvdsc_clk", .p =3D PCK_PARENT_HW_MCK3, .id =3D 104, }, + { .n =3D "i3cc_clk", .p =3D PCK_PARENT_HW_MCK8, .id =3D 105, }, }; =20 /* --=20 2.25.1 From nobody Sun Jun 14 00:14:08 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D4893AF664; Tue, 5 May 2026 07:14:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Add support for microchip sama7d65 SoC I3C HCI master only IP with additional clock support to enable bulk clock acquisition Signed-off-by: Manikandan Muralidharan Reviewed-by: Adrian Hunter --- Changes in v5: - Remove HCI_QUIRK_CLK_SUPPORT quirk and call devm_clk_bulk_get_all_enabled unconditionally Changes in v4: - Remove the clock index variable MCHP_I3C_CLK_IDX Changes in v3: - Make use of existing HCI_QUIRK_* code base - Introduce HCI_QUIRK_CLK_SUPPORT to handle/enable the required Peripheral and system generic clk in bulk Changes in v2: - Platform specific changes are integrated in the existing mipi-i3c-hci driver by introducing separate MCHP_HCI_QUIRK_* quirks and vendor specific quirk files --- drivers/i3c/master/mipi-i3c-hci/core.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index b781dbed2165..20d32a9eb62c 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -8,6 +8,7 @@ */ =20 #include +#include #include #include #include @@ -970,6 +971,7 @@ static int i3c_hci_probe(struct platform_device *pdev) { const struct mipi_i3c_hci_platform_data *pdata =3D pdev->dev.platform_dat= a; struct i3c_hci *hci; + struct clk_bulk_data *clks; int irq, ret; =20 hci =3D devm_kzalloc(&pdev->dev, sizeof(*hci), GFP_KERNEL); @@ -1001,6 +1003,11 @@ static int i3c_hci_probe(struct platform_device *pde= v) if (!hci->quirks && platform_get_device_id(pdev)) hci->quirks =3D platform_get_device_id(pdev)->driver_data; =20 + ret =3D devm_clk_bulk_get_all_enabled(&pdev->dev, &clks); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, + "Failed to get clocks\n"); + ret =3D i3c_hci_init(hci); if (ret) return ret; @@ -1031,6 +1038,9 @@ static void i3c_hci_remove(struct platform_device *pd= ev) =20 static const __maybe_unused struct of_device_id i3c_hci_of_match[] =3D { { .compatible =3D "mipi-i3c-hci", }, + { .compatible =3D "microchip,sama7d65-i3c-hci", + .data =3D (void *)(HCI_QUIRK_PIO_MODE | HCI_QUIRK_OD_PP_TIMING | + HCI_QUIRK_RESP_BUF_THLD) }, {}, }; MODULE_DEVICE_TABLE(of, i3c_hci_of_match); --=20 2.25.1 From nobody Sun Jun 14 00:14:08 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD04E3AE191; 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charset="utf-8" From: Durai Manickam KR Add I3C controller for sama7d65 SoC. Signed-off-by: Durai Manickam KR Signed-off-by: Manikandan Muralidharan --- Changes in v3: - Remove clock-names property as driver enables the clk in bulk --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index 67253bbc08df..ec200848c153 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -1055,5 +1055,13 @@ gic: interrupt-controller@e8c11000 { #address-cells =3D <0>; interrupt-controller; }; + + i3c: i3c@e9000000 { + compatible =3D "microchip,sama7d65-i3c-hci"; + reg =3D <0xe9000000 0x300>; + interrupts =3D ; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 105>, <&pmc PMC_TYPE_GCK 105>; + status =3D "disabled"; + }; }; }; --=20 2.25.1 From nobody Sun Jun 14 00:14:08 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9881D3AF664; Tue, 5 May 2026 07:14:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777965268; cv=none; b=TWMM41joTdkXk3pfKij1tWi9TWuZCtOaaTcbHkUleog7ZQRjmOrT/nUPpwi4fSxgRt4Ucy8N7WWuPI2/CEgKkZLcsU91ZkzlmgPrKhy/X6zeyDVJzIQQUQ7Fr/24MUh7LPTRVOQeG5jjlxGnOGK54sR7hcN7QbCy5NAiFJXjWuQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777965268; c=relaxed/simple; bh=l9bA/eE3RaqYV6iGVrbz/B+b5uORXkfe54GCXRYuS68=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=IRt6FVqgpsKSABRF1+o454LQFA+IgYDyGMntZ74xCjUREzzI/GJoqmaBc6EDoEPK+s84GILdX/g1FOta+w64I4rne9slQRt08VlBzsDA/0gkU6Te8BCnBVvBJmbOh6rhMLTHhzWaUoZAmRdEZj8WQ6JDlz1xy25pC/xqU5srg1I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=oy5PN/Ld; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="oy5PN/Ld" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1777965267; x=1809501267; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=l9bA/eE3RaqYV6iGVrbz/B+b5uORXkfe54GCXRYuS68=; b=oy5PN/LdNPpKQ6RAsIl9DXm4XcEFT74KQKmd/BJGxT1aiatweasUl/jH kz5psqwLUSWtYmxULSkJPfafF72MnqXFQ92MnqltH7P/zlYnQ8QrQagkL +3ZG+eNSF0BUFnLwoUH4hdXs0h84nVQR7RODEyyUBesySvFSTWGdklZhs nZ4VQafvxKgyJ3pVcDncUAU9ZdoayrKYuV3ESQcpKbD9YPMAPx2f7XU81 wzT3FNKUktXEW846yqZeBdg9rAQR8gFhUHEIsMv4XinRqtQjD8LkrZScN 1D66CK45LJYa5xSQXQTZxiArY/8UX0qUQfaV51q5xocyQEFB5K1cAHaLi w==; X-CSE-ConnectionGUID: s7sp3y7iQRKo4KR6kTb+IQ== X-CSE-MsgGUID: upekR60xT9eg6/j1cGcY+Q== X-IronPort-AV: E=Sophos;i="6.23,217,1770620400"; d="scan'208";a="57457024" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2026 00:14:27 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.87.152) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.37; Tue, 5 May 2026 00:14:26 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 5 May 2026 00:14:18 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , CC: , Durai Manickam KR Subject: [PATCH v5 5/5] ARM: configs: at91: sama7: add sama7d65 i3c-hci Date: Tue, 5 May 2026 12:43:27 +0530 Message-ID: <20260505071327.125787-6-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260505071327.125787-1-manikandan.m@microchip.com> References: <20260505071327.125787-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Durai Manickam KR Enable the configs needed for I3C framework and microchip sama7d65 i3c-hci driver. Signed-off-by: Durai Manickam KR Signed-off-by: Manikandan Muralidharan --- arch/arm/configs/sama7_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/sama7_defconfig b/arch/arm/configs/sama7_defc= onfig index e52f671ccec4..6470c7d3fe8a 100644 --- a/arch/arm/configs/sama7_defconfig +++ b/arch/arm/configs/sama7_defconfig @@ -117,6 +117,8 @@ CONFIG_HW_RANDOM=3Dy CONFIG_I2C=3Dy CONFIG_I2C_CHARDEV=3Dy CONFIG_I2C_AT91=3Dy +CONFIG_I3C=3Dy +CONFIG_MIPI_I3C_HCI=3Dy CONFIG_SPI=3Dy CONFIG_SPI_ATMEL=3Dy CONFIG_SPI_ATMEL_QUADSPI=3Dy --=20 2.25.1