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Tue, 05 May 2026 09:41:22 -0700 (PDT) Received: from [169.254.0.2] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-364be00b175sm17944836a91.9.2026.05.05.09.41.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 May 2026 09:41:21 -0700 (PDT) From: Raviteja Laggyshetty Date: Tue, 05 May 2026 16:41:11 +0000 Subject: [PATCH v3 1/2] dt-bindings: interconnect: document the RPM Network-On-Chip interconnect in Shikra SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260505-shikra_icc-v3-1-8e03ff27c007@oss.qualcomm.com> References: <20260505-shikra_icc-v3-0-8e03ff27c007@oss.qualcomm.com> In-Reply-To: <20260505-shikra_icc-v3-0-8e03ff27c007@oss.qualcomm.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Raviteja Laggyshetty , Odelu Kukatla , Krzysztof Kozlowski X-Mailer: b4 0.15.0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA1MDE2MCBTYWx0ZWRfXyT1PhSWPTi5U Swj8OgGoAXrYunv4Zh0T3ij4S+yt7JjWMIWDdXrYnJwbpAr9L0VFm5eGau/1FjrXPL92t4RA5is yfUG4cKDZUT3Uyltu3Ihq0tWP2rj0WCPskj3lTTr0etiIZ7YmEfuqrjaXCTI6Kk/2fvFuP7Ash6 Ko3A2P030TBFnyVmvFG25576WmJyg6rLWza18ASDXeErvYoibXDp2G3kfn+qdGAEk2wIfGaKwnO 41fMpsoQyxnEGvGsuLijafUm/HD+P2ELopNc3yIF5kG8/opwHLoG4q3hoNkmF4mUiXflUwMNJZl CyOhOq95qHp8n+7EAXh5r8VMQME7QG0+GgAPXEUBQt5hWqoU5P6dRqwbC6HJYqrCMfPm51Uj1e4 PRcqOSxCqN7s7mcEfR2UEG4Ezyll/k3lw5deG6cAB4QasqErX99451yTZbE9USlC9J4dYhkilr6 6V3DherYhr0fxE7oLtA== X-Authority-Analysis: v=2.4 cv=SPBykuvH c=1 sm=1 tr=0 ts=69fa1db3 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=8QtCtDovb98T9R5Wn5QA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-GUID: QtXTQPA2slqibZntst95JFRGEejvUvjL X-Proofpoint-ORIG-GUID: QtXTQPA2slqibZntst95JFRGEejvUvjL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-05_02,2026-04-30_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 bulkscore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605050160 Document the RPM Network-On-Chip Interconnect for the Qualcomm Shikra platform. Co-developed-by: Odelu Kukatla Signed-off-by: Odelu Kukatla Reviewed-by: Krzysztof Kozlowski Signed-off-by: Raviteja Laggyshetty --- .../bindings/interconnect/qcom,shikra.yaml | 134 +++++++++++++++++= ++++ include/dt-bindings/interconnect/qcom,shikra.h | 121 +++++++++++++++++= ++ 2 files changed, 255 insertions(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,shikra.yam= l b/Documentation/devicetree/bindings/interconnect/qcom,shikra.yaml new file mode 100644 index 000000000000..a0c26de94ccf --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,shikra.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,shikra.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Shikra Network-On-Chip interconnect + +maintainers: + - Raviteja Laggyshetty + +description: + The Qualcomm Shikra interconnect providers support adjusting the + bandwidth requirements between the various NoC fabrics. + +properties: + compatible: + enum: + - qcom,shikra-config-noc + - qcom,shikra-mem-noc-core + - qcom,shikra-sys-noc + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + +# Child node's properties +patternProperties: + '^interconnect-[a-z0-9]+$': + type: object + description: + The interconnect providers do not have a separate QoS register space, + but share parent's space. + + $ref: qcom,rpm-common.yaml# + + properties: + compatible: + enum: + - qcom,shikra-clk-virt + - qcom,shikra-mc-virt + - qcom,shikra-mmrt-virt + - qcom,shikra-mmnrt-virt + + required: + - compatible + + unevaluatedProperties: false + +required: + - compatible + - reg + +allOf: + - $ref: qcom,rpm-common.yaml# + - if: + properties: + compatible: + const: qcom,shikra-mem-noc-core + + then: + properties: + clocks: + items: + - description: GPU-NoC AXI clock + + clock-names: + items: + - const: gpu_axi + patternProperties: + '^interconnect-[a-z0-9]+$': false + + - if: + properties: + compatible: + const: qcom,shikra-sys-noc + + then: + properties: + clocks: + items: + - description: EMAC0-NoC AXI clock. + - description: EMAC1-NoC AXI clock. + - description: USB2-NoC AXI clock. + - description: USB3-NoC AXI clock. + + clock-names: + items: + - const: emac0_axi + - const: emac1_axi + - const: usb2_axi + - const: usb3_axi + + - if: + properties: + compatible: + const: qcom,shikra-config-noc + + then: + properties: + clocks: false + clock-names: false + patternProperties: + '^interconnect-[a-z0-9]+$': false + +unevaluatedProperties: false + +examples: + - | + interconnect@1880000 { + compatible =3D "qcom,shikra-sys-noc"; + reg =3D <0x01880000 0x6a080>; + #interconnect-cells =3D <2>; + clocks =3D <&gcc_emac0_axi_sys_noc_clk>, + <&gcc_emac1_axi_sys_noc_clk>, + <&gcc_sys_noc_usb2_prim_axi_clk>, + <&gcc_sys_noc_usb3_prim_axi_clk>; + clock-names =3D "emac0_axi", + "emac1_axi", + "usb2_axi", + "usb3_axi"; + + interconnect-clk { + compatible =3D "qcom,shikra-clk-virt"; + #interconnect-cells =3D <2>; + }; + }; diff --git a/include/dt-bindings/interconnect/qcom,shikra.h b/include/dt-bi= ndings/interconnect/qcom,shikra.h new file mode 100644 index 000000000000..a42ea22ee162 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,shikra.h @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SHIKRA_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SHIKRA_H + +#define MASTER_QUP_CORE_0 0 +#define SLAVE_QUP_CORE_0 1 + +#define SNOC_CNOC_MAS 0 +#define MASTER_QDSS_DAP 1 +#define SLAVE_AHB2PHY_USB 2 +#define SLAVE_APSS_THROTTLE_CFG 3 +#define SLAVE_AUDIO 4 +#define SLAVE_BOOT_ROM 5 +#define SLAVE_CAMERA_NRT_THROTTLE_CFG 6 +#define SLAVE_CAMERA_CFG 7 +#define SLAVE_CDSP_THROTTLE_CFG 8 +#define SLAVE_CLK_CTL 9 +#define SLAVE_DSP_CFG 10 +#define SLAVE_RBCPR_CX_CFG 11 +#define SLAVE_RBCPR_MX_CFG 12 +#define SLAVE_CRYPTO_0_CFG 13 +#define SLAVE_DDR_SS_CFG 14 +#define SLAVE_DISPLAY_CFG 15 +#define SLAVE_EMAC0_CFG 16 +#define SLAVE_EMAC1_CFG 17 +#define SLAVE_GPU_CFG 18 +#define SLAVE_GPU_THROTTLE_CFG 19 +#define SLAVE_HWKM 20 +#define SLAVE_IMEM_CFG 21 +#define SLAVE_MAPSS 22 +#define SLAVE_MDSP_MPU_CFG 23 +#define SLAVE_MESSAGE_RAM 24 +#define SLAVE_MSS 25 +#define SLAVE_PCIE_CFG 26 +#define SLAVE_PDM 27 +#define SLAVE_PIMEM_CFG 28 +#define SLAVE_PKA_WRAPPER_CFG 29 +#define SLAVE_PMIC_ARB 30 +#define SLAVE_QDSS_CFG 31 +#define SLAVE_QM_CFG 32 +#define SLAVE_QM_MPU_CFG 33 +#define SLAVE_QPIC 34 +#define SLAVE_QUP_0 35 +#define SLAVE_RPM 36 +#define SLAVE_SDCC_1 37 +#define SLAVE_SDCC_2 38 +#define SLAVE_SECURITY 39 +#define SLAVE_SNOC_CFG 40 +#define SNOC_SF_THROTTLE_CFG 41 +#define SLAVE_TLMM 42 +#define SLAVE_TSCSS 43 +#define SLAVE_USB2 44 +#define SLAVE_USB3 45 +#define SLAVE_VENUS_CFG 46 +#define SLAVE_VENUS_THROTTLE_CFG 47 +#define SLAVE_VSENSE_CTRL_CFG 48 +#define SLAVE_SERVICE_CNOC 49 + +#define MASTER_LLCC 0 +#define SLAVE_EBI_CH0 1 + +#define MASTER_GRAPHICS_3D 0 +#define MASTER_MNOC_HF_MEM_NOC 1 +#define MASTER_ANOC_PCIE_MEM_NOC 2 +#define MASTER_SNOC_SF_MEM_NOC 3 +#define MASTER_AMPSS_M0 4 +#define MASTER_SYS_TCU 5 +#define SLAVE_LLCC 6 +#define SLAVE_MEMNOC_SNOC 7 +#define SLAVE_MEM_NOC_PCIE_SNOC 8 + +#define MASTER_CAMNOC_SF 0 +#define MASTER_VIDEO_P0 1 +#define MASTER_VIDEO_PROC 2 +#define SLAVE_MMNRT_VIRT 3 + +#define MASTER_CAMNOC_HF 0 +#define MASTER_MDP_PORT0 1 +#define MASTER_MMRT_VIRT 2 +#define SLAVE_MM_MEMNOC 3 + +#define MASTER_SNOC_CFG 0 +#define MASTER_TIC 1 +#define MASTER_ANOC_SNOC 2 +#define MASTER_MEMNOC_PCIE 3 +#define MASTER_MEMNOC_SNOC 4 +#define MASTER_PIMEM 5 +#define MASTER_PCIE2_0 6 +#define MASTER_QDSS_BAM 7 +#define MASTER_QPIC 8 +#define MASTER_QUP_0 9 +#define CNOC_SNOC_MAS 10 +#define MASTER_AUDIO 11 +#define MASTER_EMAC_0 12 +#define MASTER_EMAC_1 13 +#define MASTER_QDSS_ETR 14 +#define MASTER_SDCC_1 15 +#define MASTER_SDCC_2 16 +#define MASTER_USB2_0 17 +#define MASTER_USB3 18 +#define MASTER_CRYPTO_CORE0 19 +#define SLAVE_APPSS 20 +#define SLAVE_MCUSS 21 +#define SLAVE_WCSS 22 +#define SLAVE_MEMNOC_SF 23 +#define SNOC_CNOC_SLV 24 +#define SLAVE_BOOTIMEM 25 +#define SLAVE_OCIMEM 26 +#define SLAVE_PIMEM 27 +#define SLAVE_SERVICE_SNOC 28 +#define SLAVE_PCIE2_0 29 +#define SLAVE_QDSS_STM 30 +#define SLAVE_TCU 31 +#define SLAVE_PCIE_MEMNOC 32 +#define SLAVE_ANOC_SNOC 33 + +#endif --=20 2.43.0 From nobody Sat Jun 13 20:29:44 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59935492187 for ; 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The topology consists of several NoCs that are controlled by a remote processor that collects the aggregated bandwidth for each master-slave pairs. Co-developed-by: Odelu Kukatla Signed-off-by: Odelu Kukatla Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Raviteja Laggyshetty --- drivers/interconnect/qcom/Kconfig | 9 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/shikra.c | 1837 ++++++++++++++++++++++++++++++++= ++++ 3 files changed, 1848 insertions(+) diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/= Kconfig index 786b4eda44b4..c7c7df2a6ddb 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -283,6 +283,15 @@ config INTERCONNECT_QCOM_SDX75 This is a driver for the Qualcomm Network-on-Chip on sdx75-based platforms. =20 +config INTERCONNECT_QCOM_SHIKRA + tristate "Qualcomm SHIKRA interconnect driver" + depends on INTERCONNECT_QCOM + depends on QCOM_SMD_RPM + select INTERCONNECT_QCOM_SMD_RPM + help + This is a driver for the Qualcomm Network-on-Chip on shikra-based + platforms. + config INTERCONNECT_QCOM_SM6115 tristate "Qualcomm SM6115 interconnect driver" depends on INTERCONNECT_QCOM diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom= /Makefile index cdf2c6c9fbf3..7c1834d383d2 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -35,6 +35,7 @@ qnoc-sdm845-objs :=3D sdm845.o qnoc-sdx55-objs :=3D sdx55.o qnoc-sdx65-objs :=3D sdx65.o qnoc-sdx75-objs :=3D sdx75.o +qnoc-shikra-objs :=3D shikra.o qnoc-sm6115-objs :=3D sm6115.o qnoc-sm6350-objs :=3D sm6350.o qnoc-sm7150-objs :=3D sm7150.o @@ -80,6 +81,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) +=3D qnoc-sdm845.o obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) +=3D qnoc-sdx55.o obj-$(CONFIG_INTERCONNECT_QCOM_SDX65) +=3D qnoc-sdx65.o obj-$(CONFIG_INTERCONNECT_QCOM_SDX75) +=3D qnoc-sdx75.o +obj-$(CONFIG_INTERCONNECT_QCOM_SHIKRA) +=3D qnoc-shikra.o obj-$(CONFIG_INTERCONNECT_QCOM_SM6115) +=3D qnoc-sm6115.o obj-$(CONFIG_INTERCONNECT_QCOM_SM6350) +=3D qnoc-sm6350.o obj-$(CONFIG_INTERCONNECT_QCOM_SM7150) +=3D qnoc-sm7150.o diff --git a/drivers/interconnect/qcom/shikra.c b/drivers/interconnect/qcom= /shikra.c new file mode 100644 index 000000000000..bc40d1592fb3 --- /dev/null +++ b/drivers/interconnect/qcom/shikra.c @@ -0,0 +1,1837 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "icc-rpm.h" + +static const char * const sys_noc_intf_clocks[] =3D { + "emac0_axi", + "emac1_axi", + "usb2_axi", + "usb3_axi", +}; + +static const char * const memnoc_intf_clocks[] =3D { + "gpu_axi", +}; + +enum { + SHIKRA_MASTER_QUP_CORE_0 =3D 1, + SHIKRA_SNOC_CNOC_MAS, + SHIKRA_MASTER_QDSS_DAP, + SHIKRA_MASTER_LLCC, + SHIKRA_MASTER_GRAPHICS_3D, + SHIKRA_MASTER_MNOC_HF_MEM_NOC, + SHIKRA_MASTER_ANOC_PCIE_MEM_NOC, + SHIKRA_MASTER_SNOC_SF_MEM_NOC, + SHIKRA_MASTER_AMPSS_M0, + SHIKRA_MASTER_SYS_TCU, + SHIKRA_MASTER_CAMNOC_SF, + SHIKRA_MASTER_VIDEO_P0, + SHIKRA_MASTER_VIDEO_PROC, + SHIKRA_MASTER_CAMNOC_HF, + SHIKRA_MASTER_MDP_PORT0, + SHIKRA_MASTER_MMRT_VIRT, + SHIKRA_MASTER_SNOC_CFG, + SHIKRA_MASTER_TIC, + SHIKRA_MASTER_ANOC_SNOC, + SHIKRA_MASTER_MEMNOC_PCIE, + SHIKRA_MASTER_MEMNOC_SNOC, + SHIKRA_MASTER_PIMEM, + SHIKRA_MASTER_PCIE2_0, + SHIKRA_MASTER_QDSS_BAM, + SHIKRA_MASTER_QPIC, + SHIKRA_MASTER_QUP_0, + SHIKRA_CNOC_SNOC_MAS, + SHIKRA_MASTER_AUDIO, + SHIKRA_MASTER_EMAC_0, + SHIKRA_MASTER_EMAC_1, + SHIKRA_MASTER_QDSS_ETR, + SHIKRA_MASTER_SDCC_1, + SHIKRA_MASTER_SDCC_2, + SHIKRA_MASTER_USB2_0, + SHIKRA_MASTER_USB3, + SHIKRA_MASTER_CRYPTO_CORE0, + + SHIKRA_SLAVE_QUP_CORE_0, + SHIKRA_SLAVE_AHB2PHY_USB, + SHIKRA_SLAVE_APSS_THROTTLE_CFG, + SHIKRA_SLAVE_AUDIO, + SHIKRA_SLAVE_BOOT_ROM, + SHIKRA_SLAVE_CAMERA_NRT_THROTTLE_CFG, + SHIKRA_SLAVE_CAMERA_CFG, + SHIKRA_SLAVE_CDSP_THROTTLE_CFG, + SHIKRA_SLAVE_CLK_CTL, + SHIKRA_SLAVE_DSP_CFG, + SHIKRA_SLAVE_RBCPR_CX_CFG, + SHIKRA_SLAVE_RBCPR_MX_CFG, + SHIKRA_SLAVE_CRYPTO_0_CFG, + SHIKRA_SLAVE_DDR_SS_CFG, + SHIKRA_SLAVE_DISPLAY_CFG, + SHIKRA_SLAVE_EMAC0_CFG, + SHIKRA_SLAVE_EMAC1_CFG, + SHIKRA_SLAVE_GPU_CFG, + SHIKRA_SLAVE_GPU_THROTTLE_CFG, + SHIKRA_SLAVE_HWKM, + SHIKRA_SLAVE_IMEM_CFG, + SHIKRA_SLAVE_MAPSS, + SHIKRA_SLAVE_MDSP_MPU_CFG, + SHIKRA_SLAVE_MESSAGE_RAM, + SHIKRA_SLAVE_MSS, + SHIKRA_SLAVE_PCIE_CFG, + SHIKRA_SLAVE_PDM, + SHIKRA_SLAVE_PIMEM_CFG, + SHIKRA_SLAVE_PKA_WRAPPER_CFG, + SHIKRA_SLAVE_PMIC_ARB, + SHIKRA_SLAVE_QDSS_CFG, + SHIKRA_SLAVE_QM_CFG, + SHIKRA_SLAVE_QM_MPU_CFG, + SHIKRA_SLAVE_QPIC, + SHIKRA_SLAVE_QUP_0, + SHIKRA_SLAVE_RPM, + SHIKRA_SLAVE_SDCC_1, + SHIKRA_SLAVE_SDCC_2, + SHIKRA_SLAVE_SECURITY, + SHIKRA_SLAVE_SNOC_CFG, + SHIKRA_SNOC_SF_THROTTLE_CFG, + SHIKRA_SLAVE_TLMM, + SHIKRA_SLAVE_TSCSS, + SHIKRA_SLAVE_USB2, + SHIKRA_SLAVE_USB3, + SHIKRA_SLAVE_VENUS_CFG, + SHIKRA_SLAVE_VENUS_THROTTLE_CFG, + SHIKRA_SLAVE_VSENSE_CTRL_CFG, + SHIKRA_SLAVE_SERVICE_CNOC, + SHIKRA_SLAVE_EBI_CH0, + SHIKRA_SLAVE_LLCC, + SHIKRA_SLAVE_MEMNOC_SNOC, + SHIKRA_SLAVE_MEM_NOC_PCIE_SNOC, + SHIKRA_SLAVE_MMNRT_VIRT, + SHIKRA_SLAVE_MM_MEMNOC, + SHIKRA_SLAVE_APPSS, + SHIKRA_SLAVE_MCUSS, + SHIKRA_SLAVE_WCSS, + SHIKRA_SLAVE_MEMNOC_SF, + SHIKRA_SNOC_CNOC_SLV, + SHIKRA_SLAVE_BOOTIMEM, + SHIKRA_SLAVE_OCIMEM, + SHIKRA_SLAVE_PIMEM, + SHIKRA_SLAVE_SERVICE_SNOC, + SHIKRA_SLAVE_PCIE2_0, + SHIKRA_SLAVE_QDSS_STM, + SHIKRA_SLAVE_TCU, + SHIKRA_SLAVE_PCIE_MEMNOC, + SHIKRA_SLAVE_ANOC_SNOC, +}; + +/* Master nodes */ +static const u16 qup0_core_master_links[] =3D { + SHIKRA_SLAVE_QUP_CORE_0, +}; + +static struct qcom_icc_node qup0_core_master =3D { + .id =3D SHIKRA_MASTER_QUP_CORE_0, + .name =3D "qup0_core_master", + .buswidth =3D 4, + .mas_rpm_id =3D 170, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(qup0_core_master_links), + .links =3D qup0_core_master_links, +}; + +static const u16 qnm_snoc_cnoc_links[] =3D { + SHIKRA_SLAVE_AHB2PHY_USB, + SHIKRA_SLAVE_APSS_THROTTLE_CFG, + SHIKRA_SLAVE_AUDIO, + SHIKRA_SLAVE_BOOT_ROM, + SHIKRA_SLAVE_CAMERA_NRT_THROTTLE_CFG, + SHIKRA_SLAVE_CAMERA_CFG, + SHIKRA_SLAVE_CDSP_THROTTLE_CFG, + SHIKRA_SLAVE_CLK_CTL, + SHIKRA_SLAVE_DSP_CFG, + SHIKRA_SLAVE_RBCPR_CX_CFG, + SHIKRA_SLAVE_RBCPR_MX_CFG, + SHIKRA_SLAVE_CRYPTO_0_CFG, + SHIKRA_SLAVE_DDR_SS_CFG, + SHIKRA_SLAVE_DISPLAY_CFG, + SHIKRA_SLAVE_EMAC0_CFG, + SHIKRA_SLAVE_EMAC1_CFG, + SHIKRA_SLAVE_GPU_CFG, + SHIKRA_SLAVE_GPU_THROTTLE_CFG, + SHIKRA_SLAVE_HWKM, + SHIKRA_SLAVE_IMEM_CFG, + SHIKRA_SLAVE_MAPSS, + SHIKRA_SLAVE_MDSP_MPU_CFG, + SHIKRA_SLAVE_MESSAGE_RAM, + SHIKRA_SLAVE_MSS, + SHIKRA_SLAVE_PCIE_CFG, + SHIKRA_SLAVE_PDM, + SHIKRA_SLAVE_PIMEM_CFG, + SHIKRA_SLAVE_PKA_WRAPPER_CFG, + SHIKRA_SLAVE_PMIC_ARB, + SHIKRA_SLAVE_QDSS_CFG, + SHIKRA_SLAVE_QM_CFG, + SHIKRA_SLAVE_QM_MPU_CFG, + SHIKRA_SLAVE_QPIC, + SHIKRA_SLAVE_QUP_0, + SHIKRA_SLAVE_RPM, + SHIKRA_SLAVE_SDCC_1, + SHIKRA_SLAVE_SDCC_2, + SHIKRA_SLAVE_SECURITY, + SHIKRA_SLAVE_SNOC_CFG, + SHIKRA_SNOC_SF_THROTTLE_CFG, + SHIKRA_SLAVE_TLMM, + SHIKRA_SLAVE_TSCSS, + SHIKRA_SLAVE_USB2, + SHIKRA_SLAVE_USB3, + SHIKRA_SLAVE_VENUS_CFG, + SHIKRA_SLAVE_VENUS_THROTTLE_CFG, + SHIKRA_SLAVE_VSENSE_CTRL_CFG, + SHIKRA_SLAVE_SERVICE_CNOC, +}; + +static struct qcom_icc_node qnm_snoc_cnoc =3D { + .id =3D SHIKRA_SNOC_CNOC_MAS, + .name =3D "qnm_snoc_cnoc", + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(qnm_snoc_cnoc_links), + .links =3D qnm_snoc_cnoc_links, +}; + +static const u16 xm_dap_links[] =3D { + SHIKRA_SLAVE_AHB2PHY_USB, + SHIKRA_SLAVE_APSS_THROTTLE_CFG, + SHIKRA_SLAVE_AUDIO, + SHIKRA_SLAVE_BOOT_ROM, + SHIKRA_SLAVE_CAMERA_NRT_THROTTLE_CFG, + SHIKRA_SLAVE_CAMERA_CFG, + SHIKRA_SLAVE_CDSP_THROTTLE_CFG, + SHIKRA_SLAVE_CLK_CTL, + SHIKRA_SLAVE_DSP_CFG, + SHIKRA_SLAVE_RBCPR_CX_CFG, + SHIKRA_SLAVE_RBCPR_MX_CFG, + SHIKRA_SLAVE_CRYPTO_0_CFG, + SHIKRA_SLAVE_DDR_SS_CFG, + SHIKRA_SLAVE_DISPLAY_CFG, + SHIKRA_SLAVE_EMAC0_CFG, + SHIKRA_SLAVE_EMAC1_CFG, + SHIKRA_SLAVE_GPU_CFG, + SHIKRA_SLAVE_GPU_THROTTLE_CFG, + SHIKRA_SLAVE_HWKM, + SHIKRA_SLAVE_IMEM_CFG, + SHIKRA_SLAVE_MAPSS, + SHIKRA_SLAVE_MDSP_MPU_CFG, + SHIKRA_SLAVE_MESSAGE_RAM, + SHIKRA_SLAVE_MSS, + SHIKRA_SLAVE_PCIE_CFG, + SHIKRA_SLAVE_PDM, + SHIKRA_SLAVE_PIMEM_CFG, + SHIKRA_SLAVE_PKA_WRAPPER_CFG, + SHIKRA_SLAVE_PMIC_ARB, + SHIKRA_SLAVE_QDSS_CFG, + SHIKRA_SLAVE_QM_CFG, + SHIKRA_SLAVE_QM_MPU_CFG, + SHIKRA_SLAVE_QPIC, + SHIKRA_SLAVE_QUP_0, + SHIKRA_SLAVE_RPM, + SHIKRA_SLAVE_SDCC_1, + SHIKRA_SLAVE_SDCC_2, + SHIKRA_SLAVE_SECURITY, + SHIKRA_SLAVE_SNOC_CFG, + SHIKRA_SNOC_SF_THROTTLE_CFG, + SHIKRA_SLAVE_TLMM, + SHIKRA_SLAVE_TSCSS, + SHIKRA_SLAVE_USB2, + SHIKRA_SLAVE_USB3, + SHIKRA_SLAVE_VENUS_CFG, + SHIKRA_SLAVE_VENUS_THROTTLE_CFG, + SHIKRA_SLAVE_VSENSE_CTRL_CFG, + SHIKRA_SLAVE_SERVICE_CNOC, +}; + +static struct qcom_icc_node xm_dap =3D { + .id =3D SHIKRA_MASTER_QDSS_DAP, + .name =3D "xm_dap", + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(xm_dap_links), + .links =3D xm_dap_links, +}; + +static const u16 llcc_mc_links[] =3D { + SHIKRA_SLAVE_EBI_CH0, +}; + +static struct qcom_icc_node llcc_mc =3D { + .id =3D SHIKRA_MASTER_LLCC, + .name =3D "llcc_mc", + .buswidth =3D 4, + .channels =3D 2, + .mas_rpm_id =3D 190, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(llcc_mc_links), + .links =3D llcc_mc_links, +}; + +static const u16 qnm_gpu_links[] =3D { + SHIKRA_SLAVE_LLCC, + SHIKRA_SLAVE_MEMNOC_SNOC, + SHIKRA_SLAVE_MEM_NOC_PCIE_SNOC, +}; + +static struct qcom_icc_node qnm_gpu =3D { + .id =3D SHIKRA_MASTER_GRAPHICS_3D, + .name =3D "qnm_gpu", + .buswidth =3D 16, + .qos.ap_owned =3D true, + .qos.qos_port =3D 6, + .qos.urg_fwd_en =3D false, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(qnm_gpu_links), + .links =3D qnm_gpu_links, +}; + +static const u16 qnm_mnoc_hf_links[] =3D { + SHIKRA_SLAVE_LLCC, + SHIKRA_SLAVE_MEMNOC_SNOC, + SHIKRA_SLAVE_MEM_NOC_PCIE_SNOC, +}; + +static struct qcom_icc_node qnm_mnoc_hf =3D { + .id =3D SHIKRA_MASTER_MNOC_HF_MEM_NOC, + .name =3D "qnm_mnoc_hf", + .buswidth =3D 16, + .qos.ap_owned =3D true, + .qos.qos_port =3D 7, + .qos.urg_fwd_en =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(qnm_mnoc_hf_links), + .links =3D qnm_mnoc_hf_links, +}; + +static const u16 qnm_pcie_links[] =3D { + SHIKRA_SLAVE_LLCC, + SHIKRA_SLAVE_MEMNOC_SNOC, +}; + +static struct qcom_icc_node qnm_pcie =3D { + .id =3D SHIKRA_MASTER_ANOC_PCIE_MEM_NOC, + .name =3D "qnm_pcie", + .buswidth =3D 8, + .qos.ap_owned =3D true, + .qos.qos_port =3D 4, + .qos.urg_fwd_en =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .mas_rpm_id =3D 185, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(qnm_pcie_links), + .links =3D qnm_pcie_links, +}; + +static const u16 qnm_snoc_sf_links[] =3D { + SHIKRA_SLAVE_LLCC, + SHIKRA_SLAVE_MEMNOC_SNOC, + SHIKRA_SLAVE_MEM_NOC_PCIE_SNOC, +}; + +static struct qcom_icc_node qnm_snoc_sf =3D { + .id =3D SHIKRA_MASTER_SNOC_SF_MEM_NOC, + .name =3D "qnm_snoc_sf", + .buswidth =3D 16, + .qos.ap_owned =3D true, + .qos.qos_port =3D 3, + .qos.urg_fwd_en =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .mas_rpm_id =3D 76, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(qnm_snoc_sf_links), + .links =3D qnm_snoc_sf_links, +}; + +static const u16 xm_apps_links[] =3D { + SHIKRA_SLAVE_LLCC, + SHIKRA_SLAVE_MEMNOC_SNOC, + SHIKRA_SLAVE_MEM_NOC_PCIE_SNOC, +}; + +static struct qcom_icc_node xm_apps =3D { + .id =3D SHIKRA_MASTER_AMPSS_M0, + .name =3D "xm_apps", + .buswidth =3D 16, + .qos.ap_owned =3D true, + .qos.qos_port =3D 5, + .qos.urg_fwd_en =3D false, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .mas_rpm_id =3D 0, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(xm_apps_links), + .links =3D xm_apps_links, +}; + +static const u16 xm_tcu_links[] =3D { + SHIKRA_SLAVE_LLCC, + SHIKRA_SLAVE_MEMNOC_SNOC, +}; + +static struct qcom_icc_node xm_tcu =3D { + .id =3D SHIKRA_MASTER_SYS_TCU, + .name =3D "xm_tcu", + .buswidth =3D 8, + .qos.ap_owned =3D true, + .qos.qos_port =3D 2, + .qos.urg_fwd_en =3D false, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 6, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(xm_tcu_links), + .links =3D xm_tcu_links, +}; + +static const u16 qnm_camera_nrt_links[] =3D { + SHIKRA_SLAVE_MMNRT_VIRT, +}; + +static struct qcom_icc_node qnm_camera_nrt =3D { + .id =3D SHIKRA_MASTER_CAMNOC_SF, + .name =3D "qnm_camera_nrt", + .buswidth =3D 32, + .qos.ap_owned =3D true, + .qos.qos_port =3D 3, + .qos.urg_fwd_en =3D false, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 3, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(qnm_camera_nrt_links), + .links =3D qnm_camera_nrt_links, +}; + +static const u16 qxm_venus0_links[] =3D { + SHIKRA_SLAVE_MMNRT_VIRT, +}; + +static struct qcom_icc_node qxm_venus0 =3D { + .id =3D SHIKRA_MASTER_VIDEO_P0, + .name =3D "qxm_venus0", + .buswidth =3D 16, + .qos.ap_owned =3D true, + .qos.qos_port =3D 8, + .qos.urg_fwd_en =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(qxm_venus0_links), + .links =3D qxm_venus0_links, +}; + +static const u16 qxm_venus_cpu_links[] =3D { + SHIKRA_SLAVE_MMNRT_VIRT, +}; + +static struct qcom_icc_node qxm_venus_cpu =3D { + .id =3D SHIKRA_MASTER_VIDEO_PROC, + .name =3D "qxm_venus_cpu", + .buswidth =3D 8, + .qos.ap_owned =3D true, + .qos.qos_port =3D 12, + .qos.urg_fwd_en =3D false, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(qxm_venus_cpu_links), + .links =3D qxm_venus_cpu_links, +}; + +static const u16 qnm_camera_rt_links[] =3D { + SHIKRA_SLAVE_MM_MEMNOC, +}; + +static struct qcom_icc_node qnm_camera_rt =3D { + .id =3D SHIKRA_MASTER_CAMNOC_HF, + .name =3D "qnm_camera_rt", + .buswidth =3D 32, + .qos.ap_owned =3D true, + .qos.qos_port =3D 9, + .qos.urg_fwd_en =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(qnm_camera_rt_links), + .links =3D qnm_camera_rt_links, +}; + +static const u16 qxm_mdp0_links[] =3D { + SHIKRA_SLAVE_MM_MEMNOC, +}; + +static struct qcom_icc_node qxm_mdp0 =3D { + .id =3D SHIKRA_MASTER_MDP_PORT0, + .name =3D "qxm_mdp0", + .buswidth =3D 16, + .qos.ap_owned =3D true, + .qos.qos_port =3D 4, + .qos.urg_fwd_en =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(qxm_mdp0_links), + .links =3D qxm_mdp0_links, +}; + +static const u16 mmrt_virt_master_links[] =3D { + SHIKRA_SLAVE_MM_MEMNOC, +}; + +static struct qcom_icc_node mmrt_virt_master =3D { + .id =3D SHIKRA_MASTER_MMRT_VIRT, + .name =3D "mmrt_virt_master", + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mmrt_virt_master_links), + .links =3D mmrt_virt_master_links, +}; + +static const u16 qhm_snoc_cfg_links[] =3D { + SHIKRA_SLAVE_SERVICE_SNOC, +}; + +static struct qcom_icc_node qhm_snoc_cfg =3D { + .id =3D SHIKRA_MASTER_SNOC_CFG, + .name =3D "qhm_snoc_cfg", + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(qhm_snoc_cfg_links), + .links =3D qhm_snoc_cfg_links, +}; + +static const u16 qhm_tic_links[] =3D { + SHIKRA_SLAVE_APPSS, + SHIKRA_SLAVE_MCUSS, + SHIKRA_SLAVE_WCSS, + SHIKRA_SLAVE_MEMNOC_SF, + SHIKRA_SNOC_CNOC_SLV, + SHIKRA_SLAVE_BOOTIMEM, + SHIKRA_SLAVE_OCIMEM, + SHIKRA_SLAVE_PIMEM, + SHIKRA_SLAVE_QDSS_STM, + SHIKRA_SLAVE_TCU, +}; + +static struct qcom_icc_node qhm_tic =3D { + .id =3D SHIKRA_MASTER_TIC, + .name =3D "qhm_tic", + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(qhm_tic_links), + .links =3D qhm_tic_links, +}; + +static const u16 qnm_anoc_snoc_links[] =3D { + SHIKRA_SLAVE_MEMNOC_SF, +}; + +static struct qcom_icc_node qnm_anoc_snoc =3D { + .id =3D SHIKRA_MASTER_ANOC_SNOC, + .name =3D "qnm_anoc_snoc", + .buswidth =3D 16, + .mas_rpm_id =3D 110, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(qnm_anoc_snoc_links), + .links =3D qnm_anoc_snoc_links, +}; + +static const u16 qnm_memnoc_pcie_links[] =3D { + SHIKRA_SLAVE_PCIE2_0, +}; + +static struct qcom_icc_node qnm_memnoc_pcie =3D { + .id =3D SHIKRA_MASTER_MEMNOC_PCIE, + .name =3D "qnm_memnoc_pcie", + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(qnm_memnoc_pcie_links), + .links =3D qnm_memnoc_pcie_links, +}; + +static const u16 qnm_memnoc_snoc_links[] =3D { + SHIKRA_SLAVE_APPSS, + SHIKRA_SLAVE_MCUSS, + SHIKRA_SLAVE_WCSS, + SHIKRA_SNOC_CNOC_SLV, + SHIKRA_SLAVE_BOOTIMEM, + SHIKRA_SLAVE_OCIMEM, + SHIKRA_SLAVE_PIMEM, + SHIKRA_SLAVE_QDSS_STM, + SHIKRA_SLAVE_TCU, +}; + +static struct qcom_icc_node qnm_memnoc_snoc =3D { + .id =3D SHIKRA_MASTER_MEMNOC_SNOC, + .name =3D "qnm_memnoc_snoc", + .buswidth =3D 8, + .mas_rpm_id =3D 184, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(qnm_memnoc_snoc_links), + .links =3D qnm_memnoc_snoc_links, +}; + +static const u16 qxm_pimem_links[] =3D { + SHIKRA_SLAVE_MEMNOC_SF, + SHIKRA_SLAVE_OCIMEM, +}; + +static struct qcom_icc_node qxm_pimem =3D { + .id =3D SHIKRA_MASTER_PIMEM, + .name =3D "qxm_pimem", + .buswidth =3D 8, + .qos.ap_owned =3D true, + .qos.qos_port =3D 14, + .qos.urg_fwd_en =3D false, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 2, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(qxm_pimem_links), + .links =3D qxm_pimem_links, +}; + +static const u16 xm_pcie2_0_links[] =3D { + SHIKRA_SLAVE_PCIE_MEMNOC, +}; + +static struct qcom_icc_node xm_pcie2_0 =3D { + .id =3D SHIKRA_MASTER_PCIE2_0, + .name =3D "xm_pcie2_0", + .buswidth =3D 8, + .qos.ap_owned =3D true, + .qos.qos_port =3D 21, + .qos.urg_fwd_en =3D false, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 2, + .mas_rpm_id =3D 186, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(xm_pcie2_0_links), + .links =3D xm_pcie2_0_links, +}; + +static const u16 qhm_qdss_bam_links[] =3D { + SHIKRA_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node qhm_qdss_bam =3D { + .id =3D SHIKRA_MASTER_QDSS_BAM, + .name =3D "qhm_qdss_bam", + .buswidth =3D 4, + .qos.ap_owned =3D true, + .qos.qos_port =3D 2, + .qos.urg_fwd_en =3D false, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 2, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(qhm_qdss_bam_links), + .links =3D qhm_qdss_bam_links, +}; + +static const u16 qhm_qpic_links[] =3D { + SHIKRA_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node qhm_qpic =3D { + .id =3D SHIKRA_MASTER_QPIC, + .name =3D "qhm_qpic", + .buswidth =3D 4, + .qos.ap_owned =3D true, + .qos.qos_port =3D 1, + .qos.urg_fwd_en =3D false, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 2, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(qhm_qpic_links), + .links =3D qhm_qpic_links, +}; + +static const u16 qhm_qup0_links[] =3D { + SHIKRA_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node qhm_qup0 =3D { + .id =3D SHIKRA_MASTER_QUP_0, + .name =3D "qhm_qup0", + .buswidth =3D 4, + .qos.ap_owned =3D true, + .qos.qos_port =3D 0, + .qos.urg_fwd_en =3D false, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 2, + .mas_rpm_id =3D 166, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(qhm_qup0_links), + .links =3D qhm_qup0_links, +}; + +static const u16 qnm_cnoc_snoc_links[] =3D { + SHIKRA_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node qnm_cnoc_snoc =3D { + .id =3D SHIKRA_CNOC_SNOC_MAS, + .name =3D "qnm_cnoc_snoc", + .buswidth =3D 4, + .qos.ap_owned =3D true, + .qos.qos_port =3D 7, + .qos.urg_fwd_en =3D false, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 2, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(qnm_cnoc_snoc_links), + .links =3D qnm_cnoc_snoc_links, +}; + +static const u16 qxm_audio_links[] =3D { + SHIKRA_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node qxm_audio =3D { + .id =3D SHIKRA_MASTER_AUDIO, + .name =3D "qxm_audio", + .buswidth =3D 8, + .qos.ap_owned =3D true, + .qos.qos_port =3D 22, + .qos.urg_fwd_en =3D false, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 3, + .mas_rpm_id =3D 78, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(qxm_audio_links), + .links =3D qxm_audio_links, +}; + +static const u16 xm_emac_0_links[] =3D { + SHIKRA_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node xm_emac_0 =3D { + .id =3D SHIKRA_MASTER_EMAC_0, + .name =3D "xm_emac_0", + .buswidth =3D 8, + .qos.ap_owned =3D true, + .qos.qos_port =3D 19, + .qos.urg_fwd_en =3D false, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 2, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(xm_emac_0_links), + .links =3D xm_emac_0_links, +}; + +static const u16 xm_emac_1_links[] =3D { + SHIKRA_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node xm_emac_1 =3D { + .id =3D SHIKRA_MASTER_EMAC_1, + .name =3D "xm_emac_1", + .buswidth =3D 8, + .qos.ap_owned =3D true, + .qos.qos_port =3D 20, + .qos.urg_fwd_en =3D false, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 2, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(xm_emac_1_links), + .links =3D xm_emac_1_links, +}; + +static const u16 xm_qdss_etr_links[] =3D { + SHIKRA_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node xm_qdss_etr =3D { + .id =3D SHIKRA_MASTER_QDSS_ETR, + .name =3D "xm_qdss_etr", + .buswidth =3D 8, + .qos.ap_owned =3D true, + .qos.qos_port =3D 11, + .qos.urg_fwd_en =3D false, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 2, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(xm_qdss_etr_links), + .links =3D xm_qdss_etr_links, +}; + +static const u16 xm_sdc1_links[] =3D { + SHIKRA_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node xm_sdc1 =3D { + .id =3D SHIKRA_MASTER_SDCC_1, + .name =3D "xm_sdc1", + .buswidth =3D 8, + .qos.ap_owned =3D true, + .qos.qos_port =3D 13, + .qos.urg_fwd_en =3D false, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 2, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(xm_sdc1_links), + .links =3D xm_sdc1_links, +}; + +static const u16 xm_sdc2_links[] =3D { + SHIKRA_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node xm_sdc2 =3D { + .id =3D SHIKRA_MASTER_SDCC_2, + .name =3D "xm_sdc2", + .buswidth =3D 8, + .qos.ap_owned =3D true, + .qos.qos_port =3D 17, + .qos.urg_fwd_en =3D false, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 2, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(xm_sdc2_links), + .links =3D xm_sdc2_links, +}; + +static const u16 xm_usb2_0_links[] =3D { + SHIKRA_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node xm_usb2_0 =3D { + .id =3D SHIKRA_MASTER_USB2_0, + .name =3D "xm_usb2_0", + .buswidth =3D 8, + .qos.ap_owned =3D true, + .qos.qos_port =3D 24, + .qos.urg_fwd_en =3D false, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 2, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(xm_usb2_0_links), + .links =3D xm_usb2_0_links, +}; + +static const u16 xm_usb3_0_links[] =3D { + SHIKRA_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node xm_usb3_0 =3D { + .id =3D SHIKRA_MASTER_USB3, + .name =3D "xm_usb3_0", + .buswidth =3D 8, + .qos.ap_owned =3D true, + .qos.qos_port =3D 18, + .qos.urg_fwd_en =3D false, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 2, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(xm_usb3_0_links), + .links =3D xm_usb3_0_links, +}; + +static const u16 crypto_c0_links[] =3D { + SHIKRA_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node crypto_c0 =3D { + .id =3D SHIKRA_MASTER_CRYPTO_CORE0, + .name =3D "crypto_c0", + .buswidth =3D 8, + .qos.ap_owned =3D true, + .qos.qos_port =3D 16, + .qos.urg_fwd_en =3D false, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 2, + .mas_rpm_id =3D 23, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(crypto_c0_links), + .links =3D crypto_c0_links, +}; + +/* Slave nodes */ +static struct qcom_icc_node qup0_core_slave =3D { + .id =3D SHIKRA_SLAVE_QUP_CORE_0, + .name =3D "qup0_core_slave", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 264, +}; + +static struct qcom_icc_node qhs_ahb2phy_usb =3D { + .id =3D SHIKRA_SLAVE_AHB2PHY_USB, + .name =3D "qhs_ahb2phy_usb", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_apss_throttle_cfg =3D { + .id =3D SHIKRA_SLAVE_APSS_THROTTLE_CFG, + .name =3D "qhs_apss_throttle_cfg", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_audio =3D { + .id =3D SHIKRA_SLAVE_AUDIO, + .name =3D "qhs_audio", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_boot_rom =3D { + .id =3D SHIKRA_SLAVE_BOOT_ROM, + .name =3D "qhs_boot_rom", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_camera_nrt_throttle_cfg =3D { + .id =3D SHIKRA_SLAVE_CAMERA_NRT_THROTTLE_CFG, + .name =3D "qhs_camera_nrt_throttle_cfg", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_camera_ss_cfg =3D { + .id =3D SHIKRA_SLAVE_CAMERA_CFG, + .name =3D "qhs_camera_ss_cfg", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_cdsp_throttle_cfg =3D { + .id =3D SHIKRA_SLAVE_CDSP_THROTTLE_CFG, + .name =3D "qhs_cdsp_throttle_cfg", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_clk_ctl =3D { + .id =3D SHIKRA_SLAVE_CLK_CTL, + .name =3D "qhs_clk_ctl", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_compute_dsp_cfg =3D { + .id =3D SHIKRA_SLAVE_DSP_CFG, + .name =3D "qhs_compute_dsp_cfg", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_cpr_cx =3D { + .id =3D SHIKRA_SLAVE_RBCPR_CX_CFG, + .name =3D "qhs_cpr_cx", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_cpr_mx =3D { + .id =3D SHIKRA_SLAVE_RBCPR_MX_CFG, + .name =3D "qhs_cpr_mx", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_crypto0_cfg =3D { + .id =3D SHIKRA_SLAVE_CRYPTO_0_CFG, + .name =3D "qhs_crypto0_cfg", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_ddr_ss_cfg =3D { + .id =3D SHIKRA_SLAVE_DDR_SS_CFG, + .name =3D "qhs_ddr_ss_cfg", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_disp_ss_cfg =3D { + .id =3D SHIKRA_SLAVE_DISPLAY_CFG, + .name =3D "qhs_disp_ss_cfg", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_emac0_cfg =3D { + .id =3D SHIKRA_SLAVE_EMAC0_CFG, + .name =3D "qhs_emac0_cfg", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_emac1_cfg =3D { + .id =3D SHIKRA_SLAVE_EMAC1_CFG, + .name =3D "qhs_emac1_cfg", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_gpu_cfg =3D { + .id =3D SHIKRA_SLAVE_GPU_CFG, + .name =3D "qhs_gpu_cfg", + .channels =3D 1, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_gpu_throttle_cfg =3D { + .id =3D SHIKRA_SLAVE_GPU_THROTTLE_CFG, + .name =3D "qhs_gpu_throttle_cfg", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_hwkm =3D { + .id =3D SHIKRA_SLAVE_HWKM, + .name =3D "qhs_hwkm", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_imem_cfg =3D { + .id =3D SHIKRA_SLAVE_IMEM_CFG, + .name =3D "qhs_imem_cfg", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_mapss =3D { + .id =3D SHIKRA_SLAVE_MAPSS, + .name =3D "qhs_mapss", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_mdsp_mpu_cfg =3D { + .id =3D SHIKRA_SLAVE_MDSP_MPU_CFG, + .name =3D "qhs_mdsp_mpu_cfg", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_mesg_ram =3D { + .id =3D SHIKRA_SLAVE_MESSAGE_RAM, + .name =3D "qhs_mesg_ram", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_mss =3D { + .id =3D SHIKRA_SLAVE_MSS, + .name =3D "qhs_mss", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_pcie_cfg =3D { + .id =3D SHIKRA_SLAVE_PCIE_CFG, + .name =3D "qhs_pcie_cfg", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_pdm =3D { + .id =3D SHIKRA_SLAVE_PDM, + .name =3D "qhs_pdm", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_pimem_cfg =3D { + .id =3D SHIKRA_SLAVE_PIMEM_CFG, + .name =3D "qhs_pimem_cfg", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_pka_wrapper =3D { + .id =3D SHIKRA_SLAVE_PKA_WRAPPER_CFG, + .name =3D "qhs_pka_wrapper", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_pmic_arb =3D { + .id =3D SHIKRA_SLAVE_PMIC_ARB, + .name =3D "qhs_pmic_arb", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_qdss_cfg =3D { + .id =3D SHIKRA_SLAVE_QDSS_CFG, + .name =3D "qhs_qdss_cfg", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_qm_cfg =3D { + .id =3D SHIKRA_SLAVE_QM_CFG, + .name =3D "qhs_qm_cfg", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_qm_mpu_cfg =3D { + .id =3D SHIKRA_SLAVE_QM_MPU_CFG, + .name =3D "qhs_qm_mpu_cfg", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_qpic =3D { + .id =3D SHIKRA_SLAVE_QPIC, + .name =3D "qhs_qpic", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_qup0 =3D { + .id =3D SHIKRA_SLAVE_QUP_0, + .name =3D "qhs_qup0", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_rpm =3D { + .id =3D SHIKRA_SLAVE_RPM, + .name =3D "qhs_rpm", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_sdc1 =3D { + .id =3D SHIKRA_SLAVE_SDCC_1, + .name =3D "qhs_sdc1", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_sdc2 =3D { + .id =3D SHIKRA_SLAVE_SDCC_2, + .name =3D "qhs_sdc2", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_security =3D { + .id =3D SHIKRA_SLAVE_SECURITY, + .name =3D "qhs_security", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static const u16 qhs_snoc_cfg_links[] =3D { + SHIKRA_MASTER_SNOC_CFG, +}; + +static struct qcom_icc_node qhs_snoc_cfg =3D { + .id =3D SHIKRA_SLAVE_SNOC_CFG, + .name =3D "qhs_snoc_cfg", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D 1, + .links =3D qhs_snoc_cfg_links, +}; + +static struct qcom_icc_node qhs_snoc_sf_throttle_cfg =3D { + .id =3D SHIKRA_SNOC_SF_THROTTLE_CFG, + .name =3D "qhs_snoc_sf_throttle_cfg", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_tlmm =3D { + .id =3D SHIKRA_SLAVE_TLMM, + .name =3D "qhs_tlmm", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_tscss =3D { + .id =3D SHIKRA_SLAVE_TSCSS, + .name =3D "qhs_tscss", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_usb2 =3D { + .id =3D SHIKRA_SLAVE_USB2, + .name =3D "qhs_usb2", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_usb3 =3D { + .id =3D SHIKRA_SLAVE_USB3, + .name =3D "qhs_usb3", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_venus_cfg =3D { + .id =3D SHIKRA_SLAVE_VENUS_CFG, + .name =3D "qhs_venus_cfg", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_venus_throttle_cfg =3D { + .id =3D SHIKRA_SLAVE_VENUS_THROTTLE_CFG, + .name =3D "qhs_venus_throttle_cfg", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { + .id =3D SHIKRA_SLAVE_VSENSE_CTRL_CFG, + .name =3D "qhs_vsense_ctrl_cfg", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node srvc_cnoc =3D { + .id =3D SHIKRA_SLAVE_SERVICE_CNOC, + .name =3D "srvc_cnoc", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node ebi =3D { + .id =3D SHIKRA_SLAVE_EBI_CH0, + .name =3D "ebi", + .channels =3D 2, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 0, +}; + +static const u16 qns_llcc_links[] =3D { + SHIKRA_MASTER_LLCC, +}; + +static struct qcom_icc_node qns_llcc =3D { + .id =3D SHIKRA_SLAVE_LLCC, + .name =3D "qns_llcc", + .channels =3D 2, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 312, + .num_links =3D 1, + .links =3D qns_llcc_links, +}; + +static const u16 qns_memnoc_snoc_links[] =3D { + SHIKRA_MASTER_MEMNOC_SNOC, +}; + +static struct qcom_icc_node qns_memnoc_snoc =3D { + .id =3D SHIKRA_SLAVE_MEMNOC_SNOC, + .name =3D "qns_memnoc_snoc", + .channels =3D 1, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 314, + .num_links =3D 1, + .links =3D qns_memnoc_snoc_links, +}; + +static const u16 qns_pcie_links[] =3D { + SHIKRA_MASTER_MEMNOC_PCIE, +}; + +static struct qcom_icc_node qns_pcie =3D { + .id =3D SHIKRA_SLAVE_MEM_NOC_PCIE_SNOC, + .name =3D "qns_pcie", + .channels =3D 1, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D 1, + .links =3D qns_pcie_links, +}; + +static const u16 mmnrt_virt_slave_links[] =3D { + SHIKRA_MASTER_MMRT_VIRT, +}; + +static struct qcom_icc_node mmnrt_virt_slave =3D { + .id =3D SHIKRA_SLAVE_MMNRT_VIRT, + .name =3D "mmnrt_virt_slave", + .channels =3D 1, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D 1, + .links =3D mmnrt_virt_slave_links, +}; + +static const u16 qns_mm_memnoc_links[] =3D { + SHIKRA_MASTER_MNOC_HF_MEM_NOC, +}; + +static struct qcom_icc_node qns_mm_memnoc =3D { + .id =3D SHIKRA_SLAVE_MM_MEMNOC, + .name =3D "qns_mm_memnoc", + .channels =3D 1, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D 1, + .links =3D qns_mm_memnoc_links, +}; + +static struct qcom_icc_node qhs_apss =3D { + .id =3D SHIKRA_SLAVE_APPSS, + .name =3D "qhs_apss", + .channels =3D 1, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_mcuss =3D { + .id =3D SHIKRA_SLAVE_MCUSS, + .name =3D "qhs_mcuss", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 319, +}; + +static struct qcom_icc_node qhs_wcss =3D { + .id =3D SHIKRA_SLAVE_WCSS, + .name =3D "qhs_wcss", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 23, +}; + +static const u16 qns_memnoc_sf_links[] =3D { + SHIKRA_MASTER_SNOC_SF_MEM_NOC, +}; + +static struct qcom_icc_node qns_memnoc_sf =3D { + .id =3D SHIKRA_SLAVE_MEMNOC_SF, + .name =3D "qns_memnoc_sf", + .channels =3D 1, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 313, + .num_links =3D 1, + .links =3D qns_memnoc_sf_links, +}; + +static const u16 qns_snoc_cnoc_links[] =3D { + SHIKRA_SNOC_CNOC_MAS, +}; + +static struct qcom_icc_node qns_snoc_cnoc =3D { + .id =3D SHIKRA_SNOC_CNOC_SLV, + .name =3D "qns_snoc_cnoc", + .channels =3D 1, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 25, + .num_links =3D 1, + .links =3D qns_snoc_cnoc_links, +}; + +static struct qcom_icc_node qxs_bootimem =3D { + .id =3D SHIKRA_SLAVE_BOOTIMEM, + .name =3D "qxs_bootimem", + .channels =3D 1, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qxs_imem =3D { + .id =3D SHIKRA_SLAVE_OCIMEM, + .name =3D "qxs_imem", + .channels =3D 1, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 26, +}; + +static struct qcom_icc_node qxs_pimem =3D { + .id =3D SHIKRA_SLAVE_PIMEM, + .name =3D "qxs_pimem", + .channels =3D 1, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node srvc_snoc =3D { + .id =3D SHIKRA_SLAVE_SERVICE_SNOC, + .name =3D "srvc_snoc", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node xs_pcie2_0 =3D { + .id =3D SHIKRA_SLAVE_PCIE2_0, + .name =3D "xs_pcie2_0", + .channels =3D 1, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node xs_qdss_stm =3D { + .id =3D SHIKRA_SLAVE_QDSS_STM, + .name =3D "xs_qdss_stm", + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 30, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg =3D { + .id =3D SHIKRA_SLAVE_TCU, + .name =3D "xs_sys_tcu_cfg", + .channels =3D 1, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static const u16 qns_pcie_memnoc_links[] =3D { + SHIKRA_MASTER_ANOC_PCIE_MEM_NOC, +}; + +static struct qcom_icc_node qns_pcie_memnoc =3D { + .id =3D SHIKRA_SLAVE_PCIE_MEMNOC, + .name =3D "qns_pcie_memnoc", + .channels =3D 1, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 317, + .num_links =3D 1, + .links =3D qns_pcie_memnoc_links, +}; + +static const u16 qns_anoc_snoc_links[] =3D { + SHIKRA_MASTER_ANOC_SNOC, +}; + +static struct qcom_icc_node qns_anoc_snoc =3D { + .id =3D SHIKRA_SLAVE_ANOC_SNOC, + .name =3D "qns_anoc_snoc", + .channels =3D 1, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 141, + .num_links =3D 1, + .links =3D qns_anoc_snoc_links, +}; + +/* NoC descriptors */ +static struct qcom_icc_node * const shikra_clk_virt_nodes[] =3D { + [MASTER_QUP_CORE_0] =3D &qup0_core_master, + [SLAVE_QUP_CORE_0] =3D &qup0_core_slave, +}; + +static const struct qcom_icc_desc shikra_clk_virt =3D { + .type =3D QCOM_ICC_QNOC, + .nodes =3D shikra_clk_virt_nodes, + .num_nodes =3D ARRAY_SIZE(shikra_clk_virt_nodes), + .bus_clk_desc =3D &qup_clk, + .keep_alive =3D true, +}; + +static struct qcom_icc_node * const shikra_config_noc_nodes[] =3D { + [SNOC_CNOC_MAS] =3D &qnm_snoc_cnoc, + [MASTER_QDSS_DAP] =3D &xm_dap, + [SLAVE_AHB2PHY_USB] =3D &qhs_ahb2phy_usb, + [SLAVE_APSS_THROTTLE_CFG] =3D &qhs_apss_throttle_cfg, + [SLAVE_AUDIO] =3D &qhs_audio, + [SLAVE_BOOT_ROM] =3D &qhs_boot_rom, + [SLAVE_CAMERA_NRT_THROTTLE_CFG] =3D &qhs_camera_nrt_throttle_cfg, + [SLAVE_CAMERA_CFG] =3D &qhs_camera_ss_cfg, + [SLAVE_CDSP_THROTTLE_CFG] =3D &qhs_cdsp_throttle_cfg, + [SLAVE_CLK_CTL] =3D &qhs_clk_ctl, + [SLAVE_DSP_CFG] =3D &qhs_compute_dsp_cfg, + [SLAVE_RBCPR_CX_CFG] =3D &qhs_cpr_cx, + [SLAVE_RBCPR_MX_CFG] =3D &qhs_cpr_mx, + [SLAVE_CRYPTO_0_CFG] =3D &qhs_crypto0_cfg, + [SLAVE_DDR_SS_CFG] =3D &qhs_ddr_ss_cfg, + [SLAVE_DISPLAY_CFG] =3D &qhs_disp_ss_cfg, + [SLAVE_EMAC0_CFG] =3D &qhs_emac0_cfg, + [SLAVE_EMAC1_CFG] =3D &qhs_emac1_cfg, + [SLAVE_GPU_CFG] =3D &qhs_gpu_cfg, + [SLAVE_GPU_THROTTLE_CFG] =3D &qhs_gpu_throttle_cfg, + [SLAVE_HWKM] =3D &qhs_hwkm, + [SLAVE_IMEM_CFG] =3D &qhs_imem_cfg, + [SLAVE_MAPSS] =3D &qhs_mapss, + [SLAVE_MDSP_MPU_CFG] =3D &qhs_mdsp_mpu_cfg, + [SLAVE_MESSAGE_RAM] =3D &qhs_mesg_ram, + [SLAVE_MSS] =3D &qhs_mss, + [SLAVE_PCIE_CFG] =3D &qhs_pcie_cfg, + [SLAVE_PDM] =3D &qhs_pdm, + [SLAVE_PIMEM_CFG] =3D &qhs_pimem_cfg, + [SLAVE_PKA_WRAPPER_CFG] =3D &qhs_pka_wrapper, + [SLAVE_PMIC_ARB] =3D &qhs_pmic_arb, + [SLAVE_QDSS_CFG] =3D &qhs_qdss_cfg, + [SLAVE_QM_CFG] =3D &qhs_qm_cfg, + [SLAVE_QM_MPU_CFG] =3D &qhs_qm_mpu_cfg, + [SLAVE_QPIC] =3D &qhs_qpic, + [SLAVE_QUP_0] =3D &qhs_qup0, + [SLAVE_RPM] =3D &qhs_rpm, + [SLAVE_SDCC_1] =3D &qhs_sdc1, + [SLAVE_SDCC_2] =3D &qhs_sdc2, + [SLAVE_SECURITY] =3D &qhs_security, + [SLAVE_SNOC_CFG] =3D &qhs_snoc_cfg, + [SNOC_SF_THROTTLE_CFG] =3D &qhs_snoc_sf_throttle_cfg, + [SLAVE_TLMM] =3D &qhs_tlmm, + [SLAVE_TSCSS] =3D &qhs_tscss, + [SLAVE_USB2] =3D &qhs_usb2, + [SLAVE_USB3] =3D &qhs_usb3, + [SLAVE_VENUS_CFG] =3D &qhs_venus_cfg, + [SLAVE_VENUS_THROTTLE_CFG] =3D &qhs_venus_throttle_cfg, + [SLAVE_VSENSE_CTRL_CFG] =3D &qhs_vsense_ctrl_cfg, + [SLAVE_SERVICE_CNOC] =3D &srvc_cnoc, +}; + +static const struct regmap_config shikra_config_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x8080, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc shikra_config_noc =3D { + .type =3D QCOM_ICC_QNOC, + .nodes =3D shikra_config_noc_nodes, + .num_nodes =3D ARRAY_SIZE(shikra_config_noc_nodes), + .bus_clk_desc =3D &bus_1_clk, + .regmap_cfg =3D &shikra_config_noc_regmap_config, + .keep_alive =3D true, +}; + +static struct qcom_icc_node * const shikra_mc_virt_nodes[] =3D { + [MASTER_LLCC] =3D &llcc_mc, + [SLAVE_EBI_CH0] =3D &ebi, +}; + +static const struct qcom_icc_desc shikra_mc_virt =3D { + .type =3D QCOM_ICC_QNOC, + .nodes =3D shikra_mc_virt_nodes, + .num_nodes =3D ARRAY_SIZE(shikra_mc_virt_nodes), + .bus_clk_desc =3D &bimc_clk, + .keep_alive =3D true, + .ab_coeff =3D 152, +}; + +static struct qcom_icc_node * const shikra_mem_noc_core_nodes[] =3D { + [MASTER_GRAPHICS_3D] =3D &qnm_gpu, + [MASTER_MNOC_HF_MEM_NOC] =3D &qnm_mnoc_hf, + [MASTER_ANOC_PCIE_MEM_NOC] =3D &qnm_pcie, + [MASTER_SNOC_SF_MEM_NOC] =3D &qnm_snoc_sf, + [MASTER_AMPSS_M0] =3D &xm_apps, + [MASTER_SYS_TCU] =3D &xm_tcu, + [SLAVE_LLCC] =3D &qns_llcc, + [SLAVE_MEMNOC_SNOC] =3D &qns_memnoc_snoc, + [SLAVE_MEM_NOC_PCIE_SNOC] =3D &qns_pcie, +}; + +static const struct regmap_config shikra_mem_noc_core_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x43080, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc shikra_mem_noc_core =3D { + .type =3D QCOM_ICC_QNOC, + .nodes =3D shikra_mem_noc_core_nodes, + .num_nodes =3D ARRAY_SIZE(shikra_mem_noc_core_nodes), + .bus_clk_desc =3D &mem_1_clk, + .regmap_cfg =3D &shikra_mem_noc_core_regmap_config, + .intf_clocks =3D memnoc_intf_clocks, + .num_intf_clocks =3D ARRAY_SIZE(memnoc_intf_clocks), + .qos_offset =3D 0x28000, + .keep_alive =3D true, + .ab_coeff =3D 142, +}; + +static struct qcom_icc_node * const shikra_mmnrt_virt_nodes[] =3D { + [MASTER_CAMNOC_SF] =3D &qnm_camera_nrt, + [MASTER_VIDEO_P0] =3D &qxm_venus0, + [MASTER_VIDEO_PROC] =3D &qxm_venus_cpu, + [SLAVE_MMNRT_VIRT] =3D &mmnrt_virt_slave, +}; + +static const struct regmap_config shikra_sys_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x6a080, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc shikra_mmnrt_virt =3D { + .type =3D QCOM_ICC_QNOC, + .nodes =3D shikra_mmnrt_virt_nodes, + .num_nodes =3D ARRAY_SIZE(shikra_mmnrt_virt_nodes), + .bus_clk_desc =3D &mmaxi_0_clk, + .regmap_cfg =3D &shikra_sys_noc_regmap_config, + .qos_offset =3D 0x51000, + .keep_alive =3D true, + .ab_coeff =3D 142, +}; + +static struct qcom_icc_node * const shikra_mmrt_virt_nodes[] =3D { + [MASTER_CAMNOC_HF] =3D &qnm_camera_rt, + [MASTER_MDP_PORT0] =3D &qxm_mdp0, + [MASTER_MMRT_VIRT] =3D &mmrt_virt_master, + [SLAVE_MM_MEMNOC] =3D &qns_mm_memnoc, +}; + +static const struct qcom_icc_desc shikra_mmrt_virt =3D { + .type =3D QCOM_ICC_QNOC, + .nodes =3D shikra_mmrt_virt_nodes, + .num_nodes =3D ARRAY_SIZE(shikra_mmrt_virt_nodes), + .bus_clk_desc =3D &mmaxi_1_clk, + .regmap_cfg =3D &shikra_sys_noc_regmap_config, + .qos_offset =3D 0x51000, + .keep_alive =3D true, + .ab_coeff =3D 142, +}; + +static struct qcom_icc_node * const shikra_sys_noc_nodes[] =3D { + [MASTER_SNOC_CFG] =3D &qhm_snoc_cfg, + [MASTER_TIC] =3D &qhm_tic, + [MASTER_ANOC_SNOC] =3D &qnm_anoc_snoc, + [MASTER_MEMNOC_PCIE] =3D &qnm_memnoc_pcie, + [MASTER_MEMNOC_SNOC] =3D &qnm_memnoc_snoc, + [MASTER_PIMEM] =3D &qxm_pimem, + [MASTER_PCIE2_0] =3D &xm_pcie2_0, + [MASTER_QDSS_BAM] =3D &qhm_qdss_bam, + [MASTER_QPIC] =3D &qhm_qpic, + [MASTER_QUP_0] =3D &qhm_qup0, + [CNOC_SNOC_MAS] =3D &qnm_cnoc_snoc, + [MASTER_AUDIO] =3D &qxm_audio, + [MASTER_EMAC_0] =3D &xm_emac_0, + [MASTER_EMAC_1] =3D &xm_emac_1, + [MASTER_QDSS_ETR] =3D &xm_qdss_etr, + [MASTER_SDCC_1] =3D &xm_sdc1, + [MASTER_SDCC_2] =3D &xm_sdc2, + [MASTER_USB2_0] =3D &xm_usb2_0, + [MASTER_USB3] =3D &xm_usb3_0, + [MASTER_CRYPTO_CORE0] =3D &crypto_c0, + [SLAVE_APPSS] =3D &qhs_apss, + [SLAVE_MCUSS] =3D &qhs_mcuss, + [SLAVE_WCSS] =3D &qhs_wcss, + [SLAVE_MEMNOC_SF] =3D &qns_memnoc_sf, + [SNOC_CNOC_SLV] =3D &qns_snoc_cnoc, + [SLAVE_BOOTIMEM] =3D &qxs_bootimem, + [SLAVE_OCIMEM] =3D &qxs_imem, + [SLAVE_PIMEM] =3D &qxs_pimem, + [SLAVE_SERVICE_SNOC] =3D &srvc_snoc, + [SLAVE_PCIE2_0] =3D &xs_pcie2_0, + [SLAVE_QDSS_STM] =3D &xs_qdss_stm, + [SLAVE_TCU] =3D &xs_sys_tcu_cfg, + [SLAVE_PCIE_MEMNOC] =3D &qns_pcie_memnoc, + [SLAVE_ANOC_SNOC] =3D &qns_anoc_snoc, +}; + +static const struct qcom_icc_desc shikra_sys_noc =3D { + .type =3D QCOM_ICC_QNOC, + .nodes =3D shikra_sys_noc_nodes, + .num_nodes =3D ARRAY_SIZE(shikra_sys_noc_nodes), + .bus_clk_desc =3D &bus_2_clk, + .regmap_cfg =3D &shikra_sys_noc_regmap_config, + .intf_clocks =3D sys_noc_intf_clocks, + .num_intf_clocks =3D ARRAY_SIZE(sys_noc_intf_clocks), + .qos_offset =3D 0x51000, + .keep_alive =3D true, +}; + +static const struct of_device_id shikra_qnoc_of_match[] =3D { + { .compatible =3D "qcom,shikra-clk-virt", .data =3D &shikra_clk_virt }, + { .compatible =3D "qcom,shikra-config-noc", .data =3D &shikra_config_noc = }, + { .compatible =3D "qcom,shikra-mc-virt", .data =3D &shikra_mc_virt }, + { .compatible =3D "qcom,shikra-mem-noc-core", .data =3D &shikra_mem_noc_c= ore }, + { .compatible =3D "qcom,shikra-mmnrt-virt", .data =3D &shikra_mmnrt_virt = }, + { .compatible =3D "qcom,shikra-mmrt-virt", .data =3D &shikra_mmrt_virt }, + { .compatible =3D "qcom,shikra-sys-noc", .data =3D &shikra_sys_noc }, + { }, +}; +MODULE_DEVICE_TABLE(of, shikra_qnoc_of_match); + +static struct platform_driver shikra_qnoc_driver =3D { + .probe =3D qnoc_probe, + .remove =3D qnoc_remove, + .driver =3D { + .name =3D "qnoc-shikra", + .of_match_table =3D shikra_qnoc_of_match, + .sync_state =3D icc_sync_state, + }, +}; + +static int __init qnoc_driver_init(void) +{ + return platform_driver_register(&shikra_qnoc_driver); +} +core_initcall(qnoc_driver_init); + +static void __exit qnoc_driver_exit(void) +{ + platform_driver_unregister(&shikra_qnoc_driver); +} +module_exit(qnoc_driver_exit); + +MODULE_DESCRIPTION("Qualcomm Shikra NoC driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0