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Tue, 05 May 2026 13:10:02 -0700 (PDT) From: William Bright Date: Tue, 05 May 2026 21:09:51 +0100 Subject: [PATCH v2 1/4] dt-bindings: vendor-prefixes: Add IMDT Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260505-imdt-qcs8550-sbc-rfc-v2-1-b4767d0dd421@imd-tec.com> References: <20260505-imdt-qcs8550-sbc-rfc-v2-0-b4767d0dd421@imd-tec.com> In-Reply-To: <20260505-imdt-qcs8550-sbc-rfc-v2-0-b4767d0dd421@imd-tec.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, William Bright X-Mailer: b4 0.15.2 Add IMDT (IMD Technologies Ltd) to the vendor prefixes list. Signed-off-by: William Bright --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index ee7fd3cfe203..2db12a1cb6e1 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -769,6 +769,8 @@ patternProperties: description: ILI Technology Corporation (ILITEK) "^imagis,.*": description: Imagis Technologies Co., Ltd. + "^imdt,.*": + description: IMD Technologies Ltd. "^img,.*": description: Imagination Technologies Ltd. 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Tue, 05 May 2026 13:10:04 -0700 (PDT) From: William Bright Date: Tue, 05 May 2026 21:09:52 +0100 Subject: [PATCH v2 2/4] dt-bindings: qcom: Document IMDT QCS8550 SBC and SoM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260505-imdt-qcs8550-sbc-rfc-v2-2-b4767d0dd421@imd-tec.com> References: <20260505-imdt-qcs8550-sbc-rfc-v2-0-b4767d0dd421@imd-tec.com> In-Reply-To: <20260505-imdt-qcs8550-sbc-rfc-v2-0-b4767d0dd421@imd-tec.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, William Bright X-Mailer: b4 0.15.2 Document the IMDT QCS8550 SBC which consists of an IMDT QCS8550 SoM soldered onto an IMDT QCS8550 carrier board. The IMDT QCS8550 SoM consists of a QCS8550, UFS and PMICs. Signed-off-by: William Bright --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index cc29b06621a9..97735d31f1cf 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1073,6 +1073,13 @@ properties: - sony,pdx234 - const: qcom,sm8550 =20 + - items: + - enum: + - imdt,qcs8550-sbc + - const: imdt,qcs8550-som + - const: qcom,qcs8550 + - const: qcom,sm8550 + - items: - enum: - qcom,qcs8550-aim300-aiot --=20 2.43.0 From nobody Sat Jun 13 19:14:51 2026 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5C543DB64A for ; Tue, 5 May 2026 20:10:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 05 May 2026 13:10:05 -0700 (PDT) Received: from [127.0.1.1] ([2a00:23c6:2736:8e01:fc8c:f883:9efa:3625]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48e5285ffc5sm1752205e9.2.2026.05.05.13.10.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 May 2026 13:10:05 -0700 (PDT) From: William Bright Date: Tue, 05 May 2026 21:09:53 +0100 Subject: [PATCH v2 3/4] arm64: dts: qcom: Add IMDT QCS8550 SoM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260505-imdt-qcs8550-sbc-rfc-v2-3-b4767d0dd421@imd-tec.com> References: <20260505-imdt-qcs8550-sbc-rfc-v2-0-b4767d0dd421@imd-tec.com> In-Reply-To: <20260505-imdt-qcs8550-sbc-rfc-v2-0-b4767d0dd421@imd-tec.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, William Bright X-Mailer: b4 0.15.2 The IMDT QCS8550 SoM is a System-on-Module from IMD Technologies Ltd built around the Qualcomm QCS8550 SoC. It is intended to be soldered onto a carrier board that supplies VPH_PWR and exposes the off-module peripherals. Add qcs8550-imdt-som.dtsi describing the SoM's PMICs (PM8550, PM8550VE, PM8550VS, PMK8550) and the apps_rsc PMIC outputs. Compared to other SM8550/QCS8550 boards, this SoM excludes the PM8550B charger PMIC. Assisted-by: Claude:claude-opus-4.7 Signed-off-by: William Bright --- arch/arm64/boot/dts/qcom/qcs8550-imdt-som.dtsi | 319 +++++++++++++++++++++= ++++ 1 file changed, 319 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8550-imdt-som.dtsi b/arch/arm64/bo= ot/dts/qcom/qcs8550-imdt-som.dtsi new file mode 100644 index 000000000000..816cbd254dea --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs8550-imdt-som.dtsi @@ -0,0 +1,319 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026 IMD Technologies Ltd + */ + +#include +#include "qcs8550.dtsi" +#include "pm8550.dtsi" +#define PMK8550VE_SID 5 +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id =3D "b"; + + vdd-l1-l4-l10-supply =3D <&vreg_s6g_1p86>; + vdd-l2-l13-l14-supply =3D <&vreg_bob1>; + vdd-l3-supply =3D <&vreg_s4g_1p25>; + vdd-l5-l16-supply =3D <&vreg_bob1>; + vdd-l6-l7-supply =3D <&vreg_bob1>; + vdd-l8-l9-supply =3D <&vreg_bob1>; + vdd-l11-supply =3D <&vreg_s4g_1p25>; + vdd-l12-supply =3D <&vreg_s6g_1p86>; + vdd-l15-supply =3D <&vreg_s6g_1p86>; + vdd-l17-supply =3D <&vreg_bob2>; + + /* + * PMIC outputs whose testpoints lack capacitors are + * omitted to prevent accidental use: + * L1B_1P8, L4B_1P8, L6B_1P8, L7B_1P8, L8B_1P8, + * L13B_3P0, L14B_3P2. + * Other outputs are unused. + */ + vreg_bob1: bob1 { + regulator-name =3D "vreg_bob1"; + regulator-min-microvolt =3D <3296000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; + + vreg_bob2: bob2 { + regulator-name =3D "vreg_bob2"; + regulator-min-microvolt =3D <2720000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name =3D "vreg_l5b_3p1"; + regulator-min-microvolt =3D <3104000>; + regulator-max-microvolt =3D <3104000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name =3D "vreg_l15b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name =3D "vreg_l17b_2p5"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <2504000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vdd-l1-supply =3D <&vreg_s4g_1p25>; + vdd-l2-supply =3D <&vreg_s4e_0p95>; + vdd-l3-supply =3D <&vreg_s4e_0p95>; + + vreg_l3c_0p9: ldo3 { + regulator-name =3D "vreg_l3c_0p9"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-2 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "d"; + + vdd-l1-supply =3D <&vreg_s4e_0p95>; + vdd-l2-supply =3D <&vreg_s4e_0p95>; + vdd-l3-supply =3D <&vreg_s4e_0p95>; + + vreg_l1d_0p88: ldo1 { + regulator-name =3D "vreg_l1d_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + /* ldo2 supplies SM8550 VDD_LPI_MX */ + }; + + regulators-3 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "e"; + + vdd-l1-supply =3D <&vreg_s4e_0p95>; + vdd-l2-supply =3D <&vreg_s4e_0p95>; + vdd-l3-supply =3D <&vreg_s4g_1p25>; + + vreg_s4e_0p95: smps4 { + regulator-name =3D "vreg_s4e_0p95"; + regulator-min-microvolt =3D <904000>; + regulator-max-microvolt =3D <984000>; + regulator-initial-mode =3D ; + }; + + vreg_s5e_1p08: smps5 { + regulator-name =3D "vreg_s5e_1p08"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <1120000>; + regulator-initial-mode =3D ; + }; + + vreg_l1e_0p88: ldo1 { + regulator-name =3D "vreg_l1e_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2e_0p9: ldo2 { + regulator-name =3D "vreg_l2e_0p9"; + regulator-min-microvolt =3D <904000>; + regulator-max-microvolt =3D <970000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name =3D "vreg_l3e_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-4 { + compatible =3D "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id =3D "f"; + + vdd-l1-supply =3D <&vreg_s4e_0p95>; + vdd-l2-supply =3D <&vreg_s4e_0p95>; + vdd-l3-supply =3D <&vreg_s4e_0p95>; + + vreg_s4f_0p5: smps4 { + regulator-name =3D "vreg_s4f_0p5"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <700000>; + regulator-initial-mode =3D ; + }; + + vreg_l1f_0p9: ldo1 { + regulator-name =3D "vreg_l1f_0p9"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2f_0p88: ldo2 { + regulator-name =3D "vreg_l2f_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3f_0p88: ldo3 { + regulator-name =3D "vreg_l3f_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-5 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "g"; + + vdd-l1-supply =3D <&vreg_s4g_1p25>; + vdd-l2-supply =3D <&vreg_s4g_1p25>; + vdd-l3-supply =3D <&vreg_s4g_1p25>; + + vreg_s1g_1p25: smps1 { + regulator-name =3D "vreg_s1g_1p25"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1300000>; + regulator-initial-mode =3D ; + }; + + vreg_s2g_0p85: smps2 { + regulator-name =3D "vreg_s2g_0p85"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1000000>; + regulator-initial-mode =3D ; + }; + + vreg_s3g_0p8: smps3 { + regulator-name =3D "vreg_s3g_0p8"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1004000>; + regulator-initial-mode =3D ; + }; + + vreg_s4g_1p25: smps4 { + regulator-name =3D "vreg_s4g_1p25"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1352000>; + regulator-initial-mode =3D ; + }; + + vreg_s5g_0p85: smps5 { + regulator-name =3D "vreg_s5g_0p85"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1004000>; + regulator-initial-mode =3D ; + }; + + vreg_s6g_1p86: smps6 { + regulator-name =3D "vreg_s6g_1p86"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l1g_1p2: ldo1 { + regulator-name =3D "vreg_l1g_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name =3D "vreg_l3g_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; +}; + +&pm8550vs_c { + status =3D "okay"; +}; + +&pm8550vs_d { + status =3D "okay"; +}; + +&pm8550vs_d_gpios { + status =3D "okay"; +}; + +&pm8550vs_e { + status =3D "okay"; +}; + +&pm8550vs_g { + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32764>; +}; + +&xo_board { + clock-frequency =3D <76800000>; +}; --=20 2.43.0 From nobody Sat Jun 13 19:14:51 2026 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D83D3DD52B for ; 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Tue, 05 May 2026 13:10:06 -0700 (PDT) Received: from [127.0.1.1] ([2a00:23c6:2736:8e01:fc8c:f883:9efa:3625]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48e5285ffc5sm1752205e9.2.2026.05.05.13.10.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 May 2026 13:10:06 -0700 (PDT) From: William Bright Date: Tue, 05 May 2026 21:09:54 +0100 Subject: [PATCH v2 4/4] arm64: dts: qcom: Add IMDT QCS8550 SBC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260505-imdt-qcs8550-sbc-rfc-v2-4-b4767d0dd421@imd-tec.com> References: <20260505-imdt-qcs8550-sbc-rfc-v2-0-b4767d0dd421@imd-tec.com> In-Reply-To: <20260505-imdt-qcs8550-sbc-rfc-v2-0-b4767d0dd421@imd-tec.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, William Bright X-Mailer: b4 0.15.2 The IMDT QCS8550 SBC is a two-board design from IMD Technologies Ltd built around the Qualcomm QCS8550 SoC. An IMDT QCS8550 SoM is soldered onto the IMDT QCS8550 carrier board that supplies VPH_PWR and exposes the off-module peripherals. With this DTS, the board can boot to shell with a UFS rootfs with debugging through uart7. USB and ethernet also are fully functional. Features enabled are: - On-board regulators - uSD - UART - UFS - PCIe0 - PCIe1 - USB (gadget only) - Ethernet via LAN7430 (PCIe1) - ADSP, CDSP Assisted-by: Claude:claude-opus-4.7 Signed-off-by: William Bright --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/qcs8550-imdt-sbc.dts | 827 ++++++++++++++++++++++= ++++ 2 files changed, 828 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 88c5c0c1cb8e..d38fb3c43c13 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -181,6 +181,7 @@ qcs8300-ride-el2-dtbs :=3D qcs8300-ride.dtb monaco-el2.= dtbo =20 dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8300-ride-el2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8550-aim300-aiot.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8550-imdt-sbc.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs9100-ride.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs9100-ride-r3.dtb =20 diff --git a/arch/arm64/boot/dts/qcom/qcs8550-imdt-sbc.dts b/arch/arm64/boo= t/dts/qcom/qcs8550-imdt-sbc.dts new file mode 100644 index 000000000000..d8ed92e746a2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs8550-imdt-sbc.dts @@ -0,0 +1,827 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026 IMD Technologies Ltd + */ + +/dts-v1/; + +#include "qcs8550-imdt-som.dtsi" + +/ { + model =3D "IMDT QCS8550 SBC"; + compatible =3D "imdt,qcs8550-sbc", "imdt,qcs8550-som", + "qcom,qcs8550", "qcom,sm8550"; + chassis-type =3D "embedded"; + + aliases { + serial0 =3D &uart7; + serial1 =3D &uart14; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + backlight: backlight { + compatible =3D "gpio-backlight"; + gpios =3D <&pm8550_gpios 6 GPIO_ACTIVE_HIGH>; + default-on; + }; + + cam_1v2_reg: regulator-cam-1v2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "cam_1v2_reg"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + vin-supply =3D <&hr_cam_pwr>; + }; + + cam_1v8_reg: regulator-cam-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "cam_1v8_reg"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&hr_cam_pwr>; + }; + + cam_2v8_reg: regulator-cam-2v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "cam_2v8_reg"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + vin-supply =3D <&hr_cam_pwr>; + }; + + cam_3v3_reg: regulator-cam-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "cam_3v3_reg"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&hr_cam_pwr>; + }; + + display_panel_pwr_en: regulator-display-panel-en { + compatible =3D "regulator-fixed"; + regulator-name =3D "display_panel_pwr_en"; + regulator-min-microvolt =3D <8000000>; + regulator-max-microvolt =3D <8000000>; + startup-delay-us =3D <10000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&panel_en_default>; + + gpio =3D <&tlmm 123 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&som_vph_pwr>; + }; + + /* 5V VIN to backlight LED driver PMIC */ + dsi_5v_en: regulator-dsi-5v-en { + compatible =3D "regulator-fixed"; + regulator-name =3D "dsi_5v_en"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&dsi_5v_en_default>; + + gpio =3D <&tlmm 140 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&som_vph_pwr>; + + regulator-always-on; + regulator-boot-on; + }; + + /* Enables 1V2, 1V8_CAM and 3V3_CAM */ + hr_cam_pwr: regulator-hr-cam-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "hr_cam_pwr"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hr_cam_en_default>; + + gpio =3D <&tlmm 146 GPIO_ACTIVE_LOW>; + + vin-supply =3D <&som_vph_pwr>; + + regulator-always-on; + regulator-boot-on; + }; + + /* Enables V2MB_3V8 and V2ME_3V3 */ + m2_pd_pwr: regulator-m2-pd-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "m2_pd_pwr"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&m2_pd_en_default>; + + gpio =3D <&tlmm 144 GPIO_ACTIVE_LOW>; + + vin-supply =3D <&som_vph_pwr>; + + regulator-always-on; + regulator-boot-on; + + gpio-open-drain; + }; + + per_1v8_reg: regulator-per-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "per_1v8_reg"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&per_pwr>; + }; + + per_3v3_reg: regulator-per-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "per_3v3_reg"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&per_pwr>; + }; + + per_5v_reg: regulator-per-5v { + compatible =3D "regulator-fixed"; + regulator-name =3D "per_5v_reg"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&per_pwr>; + }; + + /* Enables 5V_PER, 3V3_PER and 1V8_PER */ + per_pwr: regulator-per-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "per_pwr"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwr_per_en_default>; + + gpio =3D <&tlmm 142 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&som_vph_pwr>; + + regulator-always-on; + regulator-boot-on; + }; + + sdhci_2_vqmmc: regulator-sdhci-2-vqmmc { + compatible =3D "regulator-gpio"; + + regulator-name =3D "sdhci_2_vqmmc"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-type =3D "voltage"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sd_vset_default>; + + gpios =3D <&tlmm 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + + gpios-states =3D <0>; + states =3D <3300000 0>, + <1800000 1>; + + startup-delay-us =3D <10000>; + }; + + sdhci_4_vqmmc: regulator-sdhci-4-vqmmc { + compatible =3D "regulator-fixed"; + regulator-name =3D "sdhci_4_vqmmc"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + som_vph_pwr: regulator-som-vph-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "som_vph_pwr"; + regulator-min-microvolt =3D <3900000>; + regulator-max-microvolt =3D <3900000>; + regulator-always-on; + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_sd_3v3_reg: regulator-vsys-sd-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vsys_sd_3v3_reg"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_wlan_3v3_reg: regulator-vsys-wlan-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vsys_wlan_3v3_reg"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + /* + * NXP IW416 chip enables: PMIC_EN (master) and WLAN_EN. + * Held asserted (low) before SDHC4 powers up, then + * released after vmmc/vqmmc are stable. + */ + reset-gpios =3D <&tlmm 19 GPIO_ACTIVE_LOW>, + <&tlmm 5 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms =3D <50>; + }; +}; + +&apps_rsc { + regulators-0 { + vdd-bob1-supply =3D <&vph_pwr>; + vdd-bob2-supply =3D <&vph_pwr>; + }; + + regulators-3 { + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + }; + + regulators-4 { + vdd-s4-supply =3D <&vph_pwr>; + }; + + regulators-5 { + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-s6-supply =3D <&vph_pwr>; + }; +}; + +&gpi_dma1 { + status =3D "okay"; +}; + +&gpu { + status =3D "okay"; +}; + +&gpu_zap_shader { + firmware-name =3D "qcom/sm8550/a740_zap.mbn"; + /* Zap shader doesn't load so is disabled */ + status =3D "disabled"; +}; + +&i2c_master_hub_0 { + status =3D "okay"; +}; + +&i2c_hub_2 { + clock-frequency =3D <400000>; + status =3D "okay"; + + ptn3222: redriver@43 { + compatible =3D "nxp,ptn3222"; + reg =3D <0x43>; + #phy-cells =3D <0>; + + vdd1v8-supply =3D <&vreg_l15b_1p8>; + vdd3v3-supply =3D <&vreg_l5b_3p1>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&eusb2_repeater_reset_default>; + + reset-gpios =3D <&pm8550vs_d_gpios 4 GPIO_ACTIVE_LOW>; + }; +}; + +&ipa { + qcom,gsi-loader =3D "self"; + memory-region =3D <&ipa_fw_mem>; + firmware-name =3D "qcom/sm8550/ipa_fws.mbn"; + status =3D "okay"; +}; + +&iris { + status =3D "okay"; +}; + +&lpass_rxmacro { + status =3D "disabled"; +}; + +&lpass_tlmm { + status =3D "disabled"; +}; + +&lpass_txmacro { + status =3D "disabled"; +}; + +&lpass_vamacro { + status =3D "disabled"; +}; + +&lpass_wsa2macro { + status =3D "disabled"; +}; + +&lpass_wsamacro { + status =3D "disabled"; +}; + +&pcie0 { + wake-gpios =3D <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios =3D <&tlmm 94 GPIO_ACTIVE_LOW>; + + /* + * pcie0 hosts the M.2 Key-E slot. Apply the SDIO reset + * de-assert here so any module's chip enable is settled + * before pcie0 trains its link. + */ + pinctrl-0 =3D <&pcie0_default_state>, <&m2e_sdio_resetn_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie0_phy { + vdda-phy-supply =3D <&vreg_l1e_0p88>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; +}; + +&pcie1 { + wake-gpios =3D <&tlmm 99 GPIO_ACTIVE_HIGH>; + perst-gpios =3D <&tlmm 97 GPIO_ACTIVE_LOW>; + + /* + * pcie_switch_sel_default and gbe_reset_default are board-init + * lines that must be stable before pcie1 trains its link: the + * PCIe switch needs its mode-select strap settled, and the + * downstream LAN743x must be out of reset to enumerate. + * Applying them via pcie1's pinctrl-0 fires them during + * qcom-pcie probe, before bus enumeration. + */ + pinctrl-0 =3D <&pcie1_default_state>, + <&pcie_switch_sel_default>, + <&gbe_reset_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie1_phy { + vdda-phy-supply =3D <&vreg_l3c_0p9>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + vdda-qref-supply =3D <&vreg_l1e_0p88>; + + status =3D "okay"; +}; + +&pm8550_gpios { + sd_card_detect_default: sd-card-detect-default-state { + pins =3D "gpio12"; + function =3D "normal"; + input-enable; + output-disable; + bias-disable; + power-source =3D <1>; /* 1.8 V */ + }; +}; + +&pm8550vs_d_gpios { + eusb2_repeater_reset_default: eusb2-repeater-reset-default-state { + pins =3D "gpio4"; + function =3D "normal"; + + input-enable; + output-enable; + bias-disable; + + drive-push-pull; + power-source =3D <1>; /* 1.8V */ + qcom,drive-strength =3D <3>; + }; +}; + +&pmk8550_gpios { + pmk8550_sleep_clk: sleep-clk-state { + pins =3D "gpio3"; + function =3D "func1"; + input-disable; + output-enable; + bias-disable; + power-source =3D <1>; /* 1.8 V */ + }; +}; + +&pon_pwrkey { + status =3D "okay"; +}; + +&pon_resin { + linux,code =3D ; + + status =3D "okay"; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/sm8550/adsp.mbn", + "qcom/sm8550/adsp_dtb.mbn"; + status =3D "okay"; +}; + +&remoteproc_cdsp { + firmware-name =3D "qcom/sm8550/cdsp.mbn", + "qcom/sm8550/cdsp_dtb.mbn"; + status =3D "okay"; +}; + +&remoteproc_mpss { + firmware-name =3D "qcom/sm8550/modem.mbn", + "qcom/sm8550/modem_dtb.mbn"; + status =3D "okay"; +}; + +&sdc2_default { + clk-pins { + drive-strength =3D <16>; + }; + + cmd-pins { + /delete-property/ bias-pull-up; + bias-disable; + drive-strength =3D <16>; + }; + + data-pins { + /delete-property/ bias-pull-up; + bias-disable; + drive-strength =3D <16>; + }; +}; + +&sdhc_2 { + cd-gpios =3D <&pm8550_gpios 12 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&sdc2_default>, <&sd_card_detect_default>; + pinctrl-1 =3D <&sdc2_default>, <&sd_card_detect_default>; + pinctrl-names =3D "default", "sleep"; + + vmmc-supply =3D <&vsys_sd_3v3_reg>; + vqmmc-supply =3D <&sdhci_2_vqmmc>; + + bus-width =3D <4>; + no-sdio; + no-mmc; + + status =3D "okay"; +}; + +&tlmm { + /* Reserved I/Os for NFC */ + gpio-reserved-ranges =3D <32 8>; + + bt_default: bt-default-state { + bt-en-pins { + pins =3D "gpio81"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + }; + + sw-ctrl-pins { + pins =3D "gpio82"; + function =3D "gpio"; + bias-pull-down; + }; + }; + + dsi_5v_en_default: dsi-5v-en-default-state { + pins =3D "gpio140"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-down; + }; + + goodix_int_default: goodix-int-default-state { + goodix-int-pins { + pins =3D "gpio88"; + function =3D "gpio"; + bias-disable; + }; + }; + + goodix_reset_default: goodix-reset-default-state { + goodix-reset-pins { + pins =3D "gpio122"; + function =3D "gpio"; + drive-strength =3D <8>; + drive-open-drain; + bias-disable; + }; + }; + + hr_cam_en_default: hr-cam-en-default-state { + hr-cam-en-pins { + pins =3D "gpio146"; + function =3D "gpio"; + drive-strength =3D <16>; + }; + }; + + lt9611_irq_pin: lt9611-irq-state { + pins =3D "gpio8"; + function =3D "gpio"; + bias-disable; + }; + + lt9611_rst_pin: lt9611-rst-state { + pins =3D "gpio7"; + function =3D "gpio"; + output-high; + }; + + m2_pd_en_default: m2-pd-en-default-state { + m2-pd-en-pins { + pins =3D "gpio144"; + function =3D "gpio"; + drive-strength =3D <16>; + drive-open-drain; + }; + }; + + panel_en_default: panel-en-default-state { + pins =3D "gpio123"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-down; + }; + + panel_reset_default: panel-reset-default-state { + pins =3D "gpio133"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-disable; + drive-open-drain; + }; + + pwr_per_en_default: pwr-per-en-default-state { + pwr-per-en-pins { + pins =3D "gpio142"; + function =3D "gpio"; + drive-strength =3D <16>; + }; + }; + + sd_vset_default: sd-vset-default-state { + sd-vset-pins { + pins =3D "gpio4"; + function =3D "gpio"; + bias-disable; + drive-strength =3D <16>; + }; + }; + + sdc4_default: sdc4-default-state { + clk-pins { + pins =3D "gpio50"; + function =3D "sdc4_clk"; + bias-disable; + drive-strength =3D <16>; + }; + + cmd-pins { + pins =3D "gpio51"; + function =3D "sdc4_cmd"; + bias-disable; + drive-strength =3D <16>; + }; + + data0-pins { + pins =3D "gpio89"; + function =3D "sdc40"; + bias-disable; + drive-strength =3D <16>; + }; + + data1-pins { + pins =3D "gpio90"; + function =3D "sdc41"; + bias-disable; + drive-strength =3D <16>; + }; + + data2-pins { + pins =3D "gpio48"; + function =3D "sdc42"; + bias-disable; + drive-strength =3D <16>; + }; + + data3-pins { + pins =3D "gpio49"; + function =3D "sdc43"; + bias-disable; + drive-strength =3D <16>; + }; + }; + + sdc4_sleep: sdc4-sleep-state { + clk-pins { + pins =3D "gpio50"; + function =3D "sdc4_clk"; + bias-disable; + drive-strength =3D <2>; + }; + + cmd-pins { + pins =3D "gpio51"; + function =3D "sdc4_cmd"; + bias-disable; + drive-strength =3D <2>; + }; + + data0-pins { + pins =3D "gpio89"; + function =3D "sdc40"; + bias-disable; + drive-strength =3D <2>; + }; + + data1-pins { + pins =3D "gpio90"; + function =3D "sdc41"; + bias-disable; + drive-strength =3D <2>; + }; + + data2-pins { + pins =3D "gpio48"; + function =3D "sdc42"; + bias-disable; + drive-strength =3D <2>; + }; + + data3-pins { + pins =3D "gpio49"; + function =3D "sdc43"; + bias-disable; + drive-strength =3D <2>; + }; + }; + + wcd_default: wcd-reset-n-active-state { + pins =3D "gpio108"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + output-low; + }; + + wlan_en: wlan-en-state { + pins =3D "gpio80"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-down; + }; + + audio-speaker-dac-reset-default-state { + pins =3D "gpio171"; + function =3D "gpio"; + drive-strength =3D <2>; + drive-open-drain; + }; + + /* + * Drive LAN743x reset high (de-asserted) when pcie1 probes, + * so the PHY enumerates on the bus. Open-drain matches the + * board's external pull-up on the reset line. + */ + gbe_reset_default: gbe-reset-default-state { + pins =3D "gpio138"; + function =3D "gpio"; + drive-strength =3D <2>; + drive-open-drain; + bias-disable; + output-high; + }; + + /* + * We drive this GPIO physically high on the M2 Key-E + * connector to make sure the module is enabled. An M2 + * Key-E module could be using this pin as a chip enable. + */ + m2e_sdio_resetn_default: m2e-sdio-resetn-default-state { + pins =3D "gpio41"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + output-high; + }; + + /* Force the on-board PCIe switch to select the GbE upstream port. */ + pcie_switch_sel_default: pcie-switch-sel-default-state { + pins =3D "gpio16"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + output-low; + }; +}; + +&uart7 { + status =3D "okay"; +}; + +&uart14 { + status =3D "okay"; + + /* + * NXP IW416 WiFi+BT combo, BT side over UART. The btnxpuart + * driver auto-detects the chip ID at runtime; the upstream + * binding only enumerates 88w8987/8997 compatibles, so use + * the closest match until an iw416-bt compatible is added. + */ + bluetooth { + compatible =3D "nxp,88w8987-bt"; + fw-init-baudrate =3D <115200>; + max-speed =3D <3000000>; + firmware-name =3D "uartiw416_bt.bin"; + reset-gpios =3D <&tlmm 160 GPIO_ACTIVE_LOW>; + }; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 210 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l17b_2p5>; + vcc-max-microamp =3D <1300000>; + vccq-supply =3D <&vreg_l1g_1p2>; + vccq-max-microamp =3D <1200000>; + vdd-hba-supply =3D <&vreg_l3g_1p2>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l1d_0p88>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; +}; + +&usb_1 { + /delete-property/ usb-role-switch; + dr_mode =3D "peripheral"; + + status =3D "okay"; +}; + +&usb_1_hsphy { + vdd-supply =3D <&vreg_l1e_0p88>; + vdda12-supply =3D <&vreg_l3e_1p2>; + + phys =3D <&ptn3222>; + + status =3D "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply =3D <&vreg_l3e_1p2>; + vdda-pll-supply =3D <&vreg_l3f_0p88>; + + status =3D "okay"; +}; --=20 2.43.0