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Fix aest_dev_is_oncore() to check irq_is_percpu() on the registered IRQ. Only nodes whose FHI or ERI is a per-CPU PPI take the oncore path, nodes with an SPI take aest_online_dev(). 2. alloc_aest_node_name() uses processor_id for the node name of all processor nodes. Shared/global nodes have processor_id=3D0 (the field is unused when SHARED/GLOBAL is set), so every shared node and the per-PE node for CPU 0 both got the name "processor.0", making error logs ambiguous. For shared/global nodes, build the name as "processor.." (e.g. "processor.cache.1") so each node has a unique, meaningful identifier. Per-PE nodes keep the original "processor." form. Also add proc_flags to struct aest_event so aest_print() can distinguish shared from per-PE nodes and print an appropriate message. Signed-off-by: Umang Chheda --- drivers/ras/aest/aest-core.c | 54 ++++++++++++++++++++++++++++++++++++++++= ---- drivers/ras/aest/aest.h | 15 +++++++++++- 2 files changed, 64 insertions(+), 5 deletions(-) diff --git a/drivers/ras/aest/aest-core.c b/drivers/ras/aest/aest-core.c index 6a2d84b47721..b4f4c975da1d 100644 --- a/drivers/ras/aest/aest-core.c +++ b/drivers/ras/aest/aest-core.c @@ -49,7 +49,19 @@ static void aest_print(struct aest_event *event) =20 switch (event->type) { case ACPI_AEST_PROCESSOR_ERROR_NODE: - pr_err("%s Error from CPU%d\n", pfx_seq, event->id0); + /* + * For shared/global nodes (e.g. cluster L3 cache, DSU), + * id0 is the CPU that handled the interrupt =E2=80=94 not the error + * source itself. The node_name already identifies the resource + * (e.g. "processor.cache.1"). Print a distinct message so the + * log is not confused with a per-PE CPU error. + */ + if (event->proc_flags & + (ACPI_AEST_PROC_FLAG_SHARED | ACPI_AEST_PROC_FLAG_GLOBAL)) + pr_err("%s Error from shared processor resource (interrupt handled on C= PU%d)\n", + pfx_seq, event->id0); + else + pr_err("%s Error from CPU%d\n", pfx_seq, event->id0); break; case ACPI_AEST_MEMORY_ERROR_NODE: pr_err("%s Error from memory at SRAT proximity domain %#x\n", @@ -133,6 +145,7 @@ static void init_aest_event(struct aest_event *event, info->processor->processor_id); =20 event->id1 =3D info->processor->resource_type; + event->proc_flags =3D info->processor->flags; break; case ACPI_AEST_MEMORY_ERROR_NODE: event->id0 =3D info->memory->srat_proximity_domain; @@ -175,6 +188,7 @@ static int aest_node_gen_pool_add(struct aest_device *a= dev, if (!event) return -ENOMEM; =20 + memset(event, 0, sizeof(*event)); init_aest_event(event, record, regs); llist_add(&event->llnode, &adev->event_list); =20 @@ -730,9 +744,41 @@ static char *alloc_aest_node_name(struct aest_node *no= de) =20 switch (node->type) { case ACPI_AEST_PROCESSOR_ERROR_NODE: - name =3D devm_kasprintf(node->adev->dev, GFP_KERNEL, "%s.%d", - aest_node_name[node->type], - node->info->processor->processor_id); + /* + * Shared/global processor nodes (e.g. cluster L3 cache, DSU) + * have processor_id=3D0 and use smp_processor_id() at error-log + * time =E2=80=94 using processor_id in the name would produce the same + * "processor.0" string for every shared node and every CPU0 + * per-PE node, making logs ambiguous. + * + * For shared/global nodes, build the name from the resource + * type and the device id so each node gets a unique, meaningful + * name (e.g. "processor.cache.1", "processor.tlb.2"). + * + * For per-PE nodes, keep the original "processor." form. + */ + if (node->info->processor->flags & + (ACPI_AEST_PROC_FLAG_SHARED | ACPI_AEST_PROC_FLAG_GLOBAL)) { + static const char *const res_name[] =3D { + [ACPI_AEST_CACHE_RESOURCE] =3D "cache", + [ACPI_AEST_TLB_RESOURCE] =3D "tlb", + [ACPI_AEST_GENERIC_RESOURCE] =3D "generic", + }; + u8 rtype =3D node->info->processor->resource_type; + const char *rstr =3D (rtype < ARRAY_SIZE(res_name) && + res_name[rtype]) ? res_name[rtype] : "unknown"; + + name =3D devm_kasprintf(node->adev->dev, GFP_KERNEL, + "%s.%s.%d", + aest_node_name[node->type], + rstr, + node->adev->id); + } else { + name =3D devm_kasprintf(node->adev->dev, GFP_KERNEL, + "%s.%d", + aest_node_name[node->type], + node->info->processor->processor_id); + } break; case ACPI_AEST_MEMORY_ERROR_NODE: case ACPI_AEST_SMMU_ERROR_NODE: diff --git a/drivers/ras/aest/aest.h b/drivers/ras/aest/aest.h index 9d67d79eb4a2..9704af97fee8 100644 --- a/drivers/ras/aest/aest.h +++ b/drivers/ras/aest/aest.h @@ -8,6 +8,7 @@ #include #include #include +#include =20 #define MAX_GSI_PER_NODE 2 #define DEFAULT_CE_THRESHOLD 1 @@ -94,6 +95,8 @@ struct aest_event { /* Vendor node : hardware ID. */ char *hid; u32 index; + /* Processor node: ACPI_AEST_PROC_FLAG_* bitmask (SHARED/GLOBAL) */ + u8 proc_flags; u64 ce_threshold; int addressing_mode; struct ras_ext_regs regs; @@ -387,7 +390,17 @@ static inline void aest_sync(struct aest_node *node) =20 static inline bool aest_dev_is_oncore(struct aest_device *adev) { - return adev->type =3D=3D ACPI_AEST_PROCESSOR_ERROR_NODE; + /* + * A processor node is "on-core" (uses PPI + cpuhp) only when its + * interrupt is a per-CPU PPI. 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This always selects the slot for the CPU executing the init code, so all debugfs files ended up referencing the same per CPU aest_device instance instead of the CPU indicated by the loop variable. - The code referenced adev->nodes[i], i.e. the template nodes allocated before __setup_ppi, rather than the per-CPU copies at percpu_dev->nodes[i]. The IRQ handler updates CE counters in the per-CPU records created by __setup_ppi, the template records are never touched at runtime, so err_count always read as zero. Fix this by: - Using per_cpu_ptr(adev->adev_oncore, cpu) when iterating over CPUs. Wiring debugfs files to percpu_dev->nodes[i] so counters reflect the data updated by the IRQ handler. - Using adev->nodes[i].name for debugfs directory names. The per-CPU node receives name via a shallow memcpy and is not the authoritative source. Signed-off-by: Umang Chheda --- drivers/ras/aest/aest-sysfs.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/ras/aest/aest-sysfs.c b/drivers/ras/aest/aest-sysfs.c index 66e9c1103f99..f710503e4d74 100644 --- a/drivers/ras/aest/aest-sysfs.c +++ b/drivers/ras/aest/aest-sysfs.c @@ -189,16 +189,23 @@ aest_oncore_dev_init_debugfs(struct aest_device *adev) char name[16]; =20 for_each_possible_cpu(cpu) { - percpu_dev =3D this_cpu_ptr(adev->adev_oncore); + percpu_dev =3D per_cpu_ptr(adev->adev_oncore, cpu); =20 - snprintf(name, sizeof(name), "processor%u%u", cpu); + snprintf(name, sizeof(name), "processor%u", cpu); percpu_dev->debugfs =3D debugfs_create_dir(name, adev->debugfs); =20 for (i =3D 0; i < adev->node_cnt; i++) { - node =3D &adev->nodes[i]; - - node->debugfs =3D debugfs_create_dir(node->name, - percpu_dev->debugfs); + node =3D &percpu_dev->nodes[i]; + + /* + * Use adev->nodes[i].name (the original) rather than + * node->name from the per-CPU copy. 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Fix both functions to skip records where the corresponding bit is set in node->record_implemented, consistent with how aest_node_foreach_record() handles the same bitmap. Signed-off-by: Umang Chheda --- drivers/ras/aest/aest-sysfs.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/ras/aest/aest-sysfs.c b/drivers/ras/aest/aest-sysfs.c index f710503e4d74..b36190bb3b3e 100644 --- a/drivers/ras/aest/aest-sysfs.c +++ b/drivers/ras/aest/aest-sysfs.c @@ -52,7 +52,8 @@ static int aest_node_err_count_show(struct seq_file *m, v= oid *data) int i; =20 for (i =3D 0; i < node->record_count; i++) - aest_error_count(&node->records[i], &count); + if (!test_bit(i, node->record_implemented)) + aest_error_count(&node->records[i], &count); =20 seq_printf(m, "CE: %llu\n" "DE: %llu\n" @@ -174,8 +175,11 @@ aest_node_init_debugfs(struct aest_node *node) record =3D &node->records[i]; if (!record->name) continue; + /* Skip records not implemented on this node. */ + if (test_bit(i, node->record_implemented)) + continue; record->debugfs =3D debugfs_create_dir(record->name, - node->debugfs); + node->debugfs); aest_record_init_debugfs(record); } } --=20 2.34.1 From nobody Sat Jun 13 20:58:59 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 648C1429811 for ; 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There is no way for the user to suppress this behaviour, which makes it difficult to test UE injection or to run in environments where a kernel panic on every UE is undesirable. Add a module parameter `aest_panic_on_ue` When set to 0 the driver logs the UE and continues instead of panicking. Usage: # Boot time (kernel cmdline) aest.aest_panic_on_ue=3D0 # Runtime echo 0 > /sys/module/aest/parameters/aest_panic_on_ue Signed-off-by: Umang Chheda --- drivers/ras/aest/aest-core.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/ras/aest/aest-core.c b/drivers/ras/aest/aest-core.c index b4f4c975da1d..9ce782a66edf 100644 --- a/drivers/ras/aest/aest-core.c +++ b/drivers/ras/aest/aest-core.c @@ -22,6 +22,11 @@ DEFINE_PER_CPU(struct aest_device, percpu_adev); #undef pr_fmt #define pr_fmt(fmt) "AEST: " fmt =20 +static bool aest_panic_on_ue; +module_param(aest_panic_on_ue, bool, 0644); +MODULE_PARM_DESC(aest_panic_on_ue, + "Panic on unrecoverable error: 0=3Doff 1=3Don (default: 1)"); + #ifdef CONFIG_DEBUG_FS struct dentry *aest_debugfs; #endif @@ -342,9 +347,11 @@ void aest_proc_record(struct aest_record *record, void= *data, bool fake) aest_record_info( record, "Simulated error! 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a=ed25519-sha256; t=1777983885; l=17370; i=umang.chheda@oss.qualcomm.com; s=20260328; h=from:subject:message-id; bh=UHYiBMmAeYcwT/oKI59kIU40Oa6oQXNeQvw8DW7wwUc=; b=f4X30PASN24PpuxlrbpxYQZBWzx209SeZljlnp69AjiGRkj+36R5vxwg3Qy5cQBrM/hbFOpjx u4UP5xT2z8ODHJb/19T3Ngha9QvMUP2gtbjutRuGfrAcWKWTjmmt8b6 X-Developer-Key: i=umang.chheda@oss.qualcomm.com; a=ed25519; pk=3+tjZ+PFFYphz0Vvu4B14pBQSzqcG0jZAQspTaDRQYA= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA1MDExNyBTYWx0ZWRfXy95S6I0o6E1s MVZDziJhLZ+BBJeI9bKv/2PbbKyKCgm//Uv+nsFGW5RuanxkA+t869Q+hg1qM0qKuHVVQnsoEyQ 0Al8E0vf//aekk6ZmtvLTRCy6/FSrvBqK2G+C23F38l/11oVZeZnxq2QhSfXtMGYXrK9iSeBSH8 aBBc6MmWnD7OXuilGfEJgGdmetmM/UXQ3RmHWAPg5NsFzVQukLzvs3jreUBvKT44rQliD+fAHPA yJxbpHGdR0c7YO2xckTF9jKtZ9vd8yghfWlHL44I51NO4NWVFzNqkv77lfvpR1cFKqRxnEHWXXV 1ybHzkQjB1mk8Y02RI3u9+bsBnJOpxnKZpZL8cLAFz16kDJ8C/LQjnD8DjoD/kdLtVZn9hixHOU 6jCS/kf26ySAQ+aA4Dq2w6uMjeT2kwruvz9LtmO9ixO9TRtmR/3P+aB0aeI1GB57oHu2K2CubKv FF3ETv6yebqEh2fZ+UQ== X-Proofpoint-ORIG-GUID: 3_-ATaULrdlTPREMbi-6W-k8xWi43yEo X-Proofpoint-GUID: 3_-ATaULrdlTPREMbi-6W-k8xWi43yEo X-Authority-Analysis: v=2.4 cv=edoNubEH c=1 sm=1 tr=0 ts=69f9e1b5 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=vTNCWx79gXjKDdEYbRgA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-05_02,2026-04-30_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 bulkscore=0 clxscore=1015 spamscore=0 priorityscore=1501 malwarescore=0 adultscore=0 impostorscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605050117 The Arm Error Source Table (AEST) specification describes how firmware exposes RAS error source topology to the operating system. On ACPI systems this information is provided via the AEST ACPI table. Introduce Device Tree bindings that provide an equivalent description of AEST error sources for DT-based platforms. Signed-off-by: Umang Chheda --- .../devicetree/bindings/arm/arm,aest.yaml | 406 +++++++++++++++++= ++++ include/dt-bindings/arm/aest.h | 43 +++ 2 files changed, 449 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/arm,aest.yaml b/Document= ation/devicetree/bindings/arm/arm,aest.yaml new file mode 100644 index 000000000000..7809a0d38270 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,aest.yaml @@ -0,0 +1,406 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,aest.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm Error Source Table (AEST) + +maintainers: + - Umang Chheda + +description: + The Arm Error Source Table (AEST) describes RAS error sources and their + register interfaces. Each error source exposes one or more error records + through either system registers or a memory-mapped register window, and + may signal errors via interrupts. The top-level node acts as a container + for one or more child nodes, each describing a single AEST error source. + Refer to the Arm AEST specification (DEN0085 / DDI 0587B) for details. + Flag bit constants for use in DT source files are defined in + . + +properties: + compatible: + const: arm,aest + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + +required: + - compatible + +additionalProperties: false + +patternProperties: + "^aest-[a-z0-9-]+(@[0-9a-f]+)?$": + type: object + description: + An AEST error source node describing one error source defined by + the Arm AEST specification. + + properties: + compatible: + description: + Identifies the type of AEST error source. Each value corresponds= to + a distinct error source class defined by the Arm AEST specificat= ion. + arm,aest-proxy represents a proxy error source that forwards err= ors + from another error source. + enum: + - arm,aest-processor + - arm,aest-memory + - arm,aest-smmu + - arm,aest-gic + - arm,aest-pcie + - arm,aest-vendor + - arm,aest-proxy + + reg: + description: + Register ranges for the error source. Absence of reg implies + system-register access (interface type 0). A single range implies + memory-mapped access (interface type 1). Two ranges imply + single-record memory-mapped access (interface type 2). + minItems: 1 + maxItems: 4 + + reg-names: + description: + Names for the register ranges. The base error-record window is + unnamed (or first entry). Optional named ranges provide access to + the fault-injection, error-group, and interrupt-config register + windows defined by the AEST specification. + minItems: 1 + maxItems: 4 + items: + enum: + - fault-inject + - err-group + - irq-config + + interrupts: + description: Interrupts associated with the error source. + minItems: 1 + maxItems: 2 + + interrupt-names: + description: Names of the interrupts associated with the error sou= rce. + minItems: 1 + maxItems: 2 + items: + enum: + - fhi + - eri + + arm,fhi-flags: + description: + Bitmask of flags for the fault-handling interrupt (FHI), as defi= ned + in the AEST node interrupt structure flags field. Constants are + defined in - AEST_IRQ_MODE_LEVEL (0), + AEST_IRQ_MODE_EDGE (1). + $ref: /schemas/types.yaml#/definitions/uint32 + + arm,eri-flags: + description: + Bitmask of flags for the error-recovery interrupt (ERI), as defi= ned + in the AEST node interrupt structure flags field. Constants are + defined in . + $ref: /schemas/types.yaml#/definitions/uint32 + + arm,interface-flags: + description: | + Bitmask of interface flags for the error source, as defined in t= he + AEST node interface flags field. Constants are defined in + : + AEST_XFACE_SHARED (bit 0) - shared error source, + AEST_XFACE_CLEAR_MISC (bit 1) - clear MISC registers on err= or, + AEST_XFACE_ERROR_DEVICE (bit 2) - error node device present, + AEST_XFACE_AFFINITY (bit 3) - affinity information valid, + AEST_XFACE_ERROR_GROUP (bit 4) - error group register window= present, + AEST_XFACE_FAULT_INJECT (bit 5) - fault injection register wi= ndow present, + AEST_XFACE_INT_CONFIG (bit 6) - interrupt config register w= indow present. + For system-register interface nodes (no reg property), only + AEST_XFACE_CLEAR_MISC is meaningful; the MMIO window flags + (AEST_XFACE_ERROR_GROUP, AEST_XFACE_FAULT_INJECT, + AEST_XFACE_INT_CONFIG) have no effect without a base address. + $ref: /schemas/types.yaml#/definitions/uint32 + + arm,group-format: + description: | + Page-granularity of the error record group register window, which + determines the MMIO mapping size, the number of ERRGSR registers, + and the width of the record-implemented and status-reporting bit= maps. + Constants are defined in : + AEST_GROUP_FORMAT_4K (0) - 4K window, 1 ERRGSR, up to 64 reco= rds, + AEST_GROUP_FORMAT_16K (1) - 16K window, 4 ERRGSRs, up to 256 r= ecords, + AEST_GROUP_FORMAT_64K (2) - 64K window, 14 ERRGSRs, up to 896 = records. + Required for memory-mapped nodes (reg present) where it controls + the ioremap size and ERRGSR layout. For system-register nodes + (no reg property) this property is optional and defaults to + AEST_GROUP_FORMAT_4K. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + + arm,num-records: + description: Number of error records implemented by this error sou= rce. + $ref: /schemas/types.yaml#/definitions/uint32 + + arm,record-impl: + description: + Bitmap of implemented error records within this error source. Bi= t N + set to 0 means error record N is implemented and must be polled. + $ref: /schemas/types.yaml#/definitions/uint64-array + + arm,status-reporting: + description: + Bitmap indicating which error records support status reporting v= ia + the ERRGSR register. Bit N set to 1 means record N does not repo= rt + through ERRGSR and must be polled explicitly. + $ref: /schemas/types.yaml#/definitions/uint64-array + + arm,addressing-mode: + description: + Bitmap indicating the address type reported in ERR_ADDR for each + error record. Bit N set to 0 means record N reports System Physi= cal + Addresses (SPA); bit N set to 1 means record N reports node-spec= ific + Logical Addresses (LA) that require OS translation to SPA. + $ref: /schemas/types.yaml#/definitions/uint64-array + + arm,processor-flags: + description: + Bitmask indicating the scope of a processor error source, as def= ined + in the AEST processor node flags field. Constants are defined in + - AEST_PROC_GLOBAL (bit 0), + AEST_PROC_SHARED (bit 1). + $ref: /schemas/types.yaml#/definitions/uint32 + + arm,resource-type: + description: | + Type of processor resource associated with this error source. + Constants are defined in : + AEST_RESOURCE_CACHE (0), + AEST_RESOURCE_TLB (1), + AEST_RESOURCE_GENERIC (2). + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + + arm,cache-ref: + description: + Phandle to the cache node associated with this processor error s= ource. + $ref: /schemas/types.yaml#/definitions/phandle + + arm,tlb-level: + description: TLB level identifier for this processor TLB error sou= rce. + $ref: /schemas/types.yaml#/definitions/uint32 + + arm,resource-ref: + description: + Generic resource reference identifier for this processor error s= ource. + $ref: /schemas/types.yaml#/definitions/uint32 + + arm,proximity-domain: + description: + SRAT proximity domain of the memory node associated with this er= ror + source. + $ref: /schemas/types.yaml#/definitions/uint32 + + arm,smmu-ref: + description: + Phandle to the SMMU node in the IORT associated with this error + source. + $ref: /schemas/types.yaml#/definitions/phandle + + arm,smmu-subcomponent: + description: + SMMU subcomponent reference identifier for this error source, as + defined in the AEST SMMU node structure. + $ref: /schemas/types.yaml#/definitions/uint32 + + arm,gic-type: + description: | + GIC component type for this error source, as defined in the AEST= GIC + node structure. Constants are defined in : + AEST_GIC_CPU (0), + AEST_GIC_DISTRIBUTOR (1), + AEST_GIC_REDISTRIBUTOR (2), + AEST_GIC_ITS (3). + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + arm,gic-instance: + description: + GIC instance identifier for this error source, used to distingui= sh + multiple instances of the same GIC component type. + $ref: /schemas/types.yaml#/definitions/uint32 + + arm,pcie-segment: + description: + PCI segment number of the PCIe root port associated with this er= ror + source, corresponding to the IORT node reference. + $ref: /schemas/types.yaml#/definitions/uint32 + + arm,vendor-hid: + description: + 8-character ACPI Hardware ID string identifying the vendor error + source, as defined in the AEST vendor node structure. + $ref: /schemas/types.yaml#/definitions/string + + arm,vendor-uid: + description: + ACPI unique instance identifier for this vendor error source, us= ed + to distinguish multiple instances with the same hardware ID. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - compatible + - arm,num-records + + allOf: + - if: + required: + - reg + then: + required: + - arm,group-format + - if: + properties: + compatible: + contains: + const: arm,aest-processor + then: + properties: + arm,processor-flags: {} + arm,resource-type: {} + arm,cache-ref: {} + arm,tlb-level: {} + arm,resource-ref: {} + else: + properties: + arm,processor-flags: false + arm,resource-type: false + arm,cache-ref: false + arm,tlb-level: false + arm,resource-ref: false + + - if: + properties: + compatible: + contains: + const: arm,aest-memory + then: + required: + - arm,proximity-domain + properties: + arm,proximity-domain: {} + else: + properties: + arm,proximity-domain: false + + - if: + properties: + compatible: + contains: + const: arm,aest-smmu + then: + required: + - arm,smmu-ref + properties: + arm,smmu-ref: {} + arm,smmu-subcomponent: {} + else: + properties: + arm,smmu-ref: false + arm,smmu-subcomponent: false + + - if: + properties: + compatible: + contains: + const: arm,aest-gic + then: + properties: + arm,gic-type: {} + arm,gic-instance: {} + else: + properties: + arm,gic-type: false + arm,gic-instance: false + + - if: + properties: + compatible: + contains: + const: arm,aest-pcie + then: + required: + - arm,pcie-segment + properties: + arm,pcie-segment: {} + else: + properties: + arm,pcie-segment: false + + - if: + properties: + compatible: + contains: + const: arm,aest-vendor + then: + required: + - arm,vendor-hid + properties: + arm,vendor-hid: {} + arm,vendor-uid: {} + else: + properties: + arm,vendor-hid: false + arm,vendor-uid: false + + unevaluatedProperties: false + +examples: + - | + #include + #include + + aest { + compatible =3D "arm,aest"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + /* System-register based processor error source (no reg property) = */ + aest-processor-0 { + compatible =3D "arm,aest-processor"; + arm,num-records =3D <2>; + arm,record-impl =3D /bits/ 64 <0x3>; + arm,status-reporting =3D /bits/ 64 <0x0>; + arm,addressing-mode =3D /bits/ 64 <0x0>; + arm,processor-flags =3D ; + arm,resource-type =3D ; + interrupts =3D ; + interrupt-names =3D "fhi"; + }; + + /* Memory-mapped memory controller error source */ + aest-memory-0@50010000 { + compatible =3D "arm,aest-memory"; + reg =3D <0x0 0x50010000 0x0 0x1000>, + <0x0 0x50011000 0x0 0x1000>, + <0x0 0x50012000 0x0 0x1000>; + reg-names =3D "err-group", "fault-inject", "irq-config"; + arm,group-format =3D ; + arm,num-records =3D <4>; + arm,record-impl =3D /bits/ 64 <0xf>; + arm,status-reporting =3D /bits/ 64 <0x0>; + arm,addressing-mode =3D /bits/ 64 <0x0>; + arm,interface-flags =3D ; + arm,proximity-domain =3D <0>; + interrupts =3D , + ; + interrupt-names =3D "fhi", "eri"; + }; + }; diff --git a/include/dt-bindings/arm/aest.h b/include/dt-bindings/arm/aest.h new file mode 100644 index 000000000000..43679314e98e --- /dev/null +++ b/include/dt-bindings/arm/aest.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for the Arm Error Source Table (AEST) + * DT binding (Documentation/devicetree/bindings/arm/arm,aest.yaml). + */ + +#ifndef _DT_BINDINGS_ARM_AEST_H +#define _DT_BINDINGS_ARM_AEST_H + +/* arm,interface-flags - AEST node interface flags field */ +#define AEST_XFACE_SHARED 1 +#define AEST_XFACE_CLEAR_MISC 2 +#define AEST_XFACE_ERROR_DEVICE 4 +#define AEST_XFACE_AFFINITY 8 +#define AEST_XFACE_ERROR_GROUP 16 +#define AEST_XFACE_FAULT_INJECT 32 +#define AEST_XFACE_INT_CONFIG 64 + +/* arm,fhi-flags / arm,eri-flags - AEST node interrupt flags field */ +#define AEST_IRQ_MODE_LEVEL 0 +#define AEST_IRQ_MODE_EDGE 1 + +/* arm,processor-flags - AEST processor node flags field */ +#define AEST_PROC_GLOBAL 1 +#define AEST_PROC_SHARED 2 + +/* arm,group-format - error record group register window page size */ +#define AEST_GROUP_FORMAT_4K 0 +#define AEST_GROUP_FORMAT_16K 1 +#define AEST_GROUP_FORMAT_64K 2 + +/* arm,resource-type - processor resource type */ +#define AEST_RESOURCE_CACHE 0 +#define AEST_RESOURCE_TLB 1 +#define AEST_RESOURCE_GENERIC 2 + +/* arm,gic-type - GIC component type */ +#define AEST_GIC_CPU 0 +#define AEST_GIC_DISTRIBUTOR 1 +#define AEST_GIC_REDISTRIBUTOR 2 +#define AEST_GIC_ITS 3 + +#endif /* _DT_BINDINGS_ARM_AEST_H */ --=20 2.34.1 From nobody Sat Jun 13 20:58:59 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB8DD428463 for ; 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Tue, 05 May 2026 05:25:30 -0700 (PDT) Received: from hu-uchheda-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c7ffbbaac5bsm12597998a12.6.2026.05.05.05.25.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 May 2026 05:25:29 -0700 (PDT) From: Umang Chheda Date: Tue, 05 May 2026 17:53:50 +0530 Subject: [PATCH 6/8] ras: aest: Add DT frontend for ARM AEST RAS error sources Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260505-aest-devicetree-support-v1-6-d5d6ffacf0a5@oss.qualcomm.com> References: <20260505-aest-devicetree-support-v1-0-d5d6ffacf0a5@oss.qualcomm.com> In-Reply-To: <20260505-aest-devicetree-support-v1-0-d5d6ffacf0a5@oss.qualcomm.com> To: Ruidong Tian , Tony Luck , Borislav Petkov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , catalin.marinas@arm.com, will@kernel.org, lpieralisi@kernel.org, rafael@kernel.org, mark.rutland@arm.com, Sudeep Holla Cc: linux-arm-msm@vger.kernel.org, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-edac@vger.kernel.org, Umang Chheda X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; 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The DT frontend parses the "arm,aest" Device Tree hierarchy and populates the same internal structures as the ACPI-based implementation. It is initialized at the same layer as ACPI and is mutually exclusive with it, ensuring identical behaviour regardless of the firmware interface in use. Signed-off-by: Umang Chheda --- drivers/ras/aest/Kconfig | 15 +- drivers/ras/aest/Makefile | 2 + drivers/ras/aest/aest-of.c | 673 +++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 688 insertions(+), 2 deletions(-) diff --git a/drivers/ras/aest/Kconfig b/drivers/ras/aest/Kconfig index 0b09a5d5acce..ca034255fadd 100644 --- a/drivers/ras/aest/Kconfig +++ b/drivers/ras/aest/Kconfig @@ -7,11 +7,22 @@ =20 config AEST tristate "ARM AEST Driver" - depends on ACPI_AEST && RAS - + depends on ACPI_AEST || OF_AEST + depends on RAS help The Arm Error Source Table (AEST) provides details on ACPI extensions that enable kernel-first handling of errors in a system that supports the Armv8 RAS extensions. =20 If set, the kernel will report and log hardware errors. + +config OF_AEST + bool "ARM Error Source Table DT Support" + depends on ARM64_RAS_EXTN && OF + help + Enable support for discovering ARM RAS error sources using the + Device Tree based Arm Error Source Table (AEST) specification. + This allows the kernel to enumerate and manage hardware error + reporting blocks described in firmware for ARMv8 and later + systems. Select this option if your platform describes AEST + nodes in Device Tree and relies on RAS error handling. diff --git a/drivers/ras/aest/Makefile b/drivers/ras/aest/Makefile index e5a45fde6d36..2997952901c0 100644 --- a/drivers/ras/aest/Makefile +++ b/drivers/ras/aest/Makefile @@ -6,3 +6,5 @@ aest-y :=3D aest-core.o aest-y +=3D aest-sysfs.o aest-y +=3D aest-inject.o aest-y +=3D aest-cmn.o + +obj-$(CONFIG_OF_AEST) +=3D aest-of.o diff --git a/drivers/ras/aest/aest-of.c b/drivers/ras/aest/aest-of.c new file mode 100644 index 000000000000..939db2c41742 --- /dev/null +++ b/drivers/ras/aest/aest-of.c @@ -0,0 +1,673 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include + +#undef pr_fmt +#define pr_fmt(fmt) "DT AEST: " fmt + +struct dt_aest_priv { + struct xarray aest_array; + u32 node_id; +}; + +static const struct of_device_id dt_aest_child_match[] =3D { + { .compatible =3D "arm,aest-processor", .data =3D (void *)ACPI_AEST_PROCE= SSOR_ERROR_NODE }, + { .compatible =3D "arm,aest-memory", .data =3D (void *)ACPI_AEST_MEMOR= Y_ERROR_NODE }, + { .compatible =3D "arm,aest-smmu", .data =3D (void *)ACPI_AEST_SMMU_= ERROR_NODE }, + { .compatible =3D "arm,aest-vendor", .data =3D (void *)ACPI_AEST_VENDO= R_ERROR_NODE }, + { .compatible =3D "arm,aest-gic", .data =3D (void *)ACPI_AEST_GIC_E= RROR_NODE }, + { .compatible =3D "arm,aest-pcie", .data =3D (void *)ACPI_AEST_PCIE_= ERROR_NODE }, + { .compatible =3D "arm,aest-proxy", .data =3D (void *)ACPI_AEST_PROXY= _ERROR_NODE }, + { } +}; + +static int dt_aest_node_type(struct device_node *np) +{ + const struct of_device_id *match; + + match =3D of_match_node(dt_aest_child_match, np); + if (!match) { + pr_warn("unknown compatible for %pOF\n", np); + return -EINVAL; + } + return (int)(uintptr_t)match->data; +} + +static struct aest_hnode *dt_aest_alloc_hnode(int node_type, u32 id) +{ + struct aest_hnode *ahnode; + + ahnode =3D kzalloc_obj(*ahnode, GFP_KERNEL); + if (!ahnode) + return NULL; + + INIT_LIST_HEAD(&ahnode->list); + ahnode->count =3D 0; + ahnode->id =3D id; + ahnode->type =3D node_type; + return ahnode; +} + +static int dt_aest_build_interface(struct device_node *np, + struct acpi_aest_node *anode) +{ + struct acpi_aest_node_interface_header *hdr; + struct acpi_aest_node_interface_common *common; + struct resource res; + struct resource named_res; + u32 gfmt =3D 0, flags =3D 0, nrec =3D 1; + u32 itype; + int ret; + size_t body_sz; + + /* + * Deduce interface type from the presence and count of reg entries: + * no reg -> system-register access (type 0) + * 1 range -> memory-mapped access (type 1) + * 2+ ranges -> single-record MMIO (type 2) + */ + if (!of_property_present(np, "reg")) + itype =3D ACPI_AEST_NODE_SYSTEM_REGISTER; + else if (of_property_count_elems_of_size(np, "reg", sizeof(u32)) <=3D + (of_n_addr_cells(np) + of_n_size_cells(np))) + itype =3D ACPI_AEST_NODE_MEMORY_MAPPED; + else + itype =3D ACPI_AEST_NODE_SINGLE_RECORD_MEMORY_MAPPED; + + of_property_read_u32(np, "arm,group-format", &gfmt); + of_property_read_u32(np, "arm,interface-flags", &flags); + of_property_read_u32(np, "arm,num-records", &nrec); + + switch (gfmt) { + case ACPI_AEST_NODE_GROUP_FORMAT_16K: + body_sz =3D sizeof(struct acpi_aest_node_interface_16k); + break; + case ACPI_AEST_NODE_GROUP_FORMAT_64K: + body_sz =3D sizeof(struct acpi_aest_node_interface_64k); + break; + default: + body_sz =3D sizeof(struct acpi_aest_node_interface_4k); + break; + } + + hdr =3D kzalloc(sizeof(*hdr) + body_sz, GFP_KERNEL); + if (!hdr) + return -ENOMEM; + + /* Fill header */ + hdr->type =3D (u8)itype; + hdr->group_format =3D (u8)gfmt; + hdr->flags =3D flags; + hdr->error_record_count =3D nrec; + hdr->error_record_index =3D 0; + + if (itype !=3D ACPI_AEST_NODE_SYSTEM_REGISTER) { + ret =3D of_address_to_resource(np, 0, &res); + if (ret) { + pr_err("node %pOF: missing 'reg' for MMIO interface\n", np); + kfree(hdr); + return ret; + } + hdr->address =3D res.start; + } + + switch (gfmt) { + case ACPI_AEST_NODE_GROUP_FORMAT_4K: { + struct acpi_aest_node_interface_4k *b =3D + (struct acpi_aest_node_interface_4k *)(hdr + 1); + of_property_read_u64(np, "arm,record-impl", + &b->error_record_implemented); + of_property_read_u64(np, "arm,status-reporting", + &b->error_status_reporting); + of_property_read_u64(np, "arm,addressing-mode", + &b->addressing_mode); + common =3D &b->common; + anode->record_implemented =3D + (unsigned long *)&b->error_record_implemented; + anode->status_reporting =3D + (unsigned long *)&b->error_status_reporting; + anode->addressing_mode =3D + (unsigned long *)&b->addressing_mode; + break; + } + case ACPI_AEST_NODE_GROUP_FORMAT_16K: { + struct acpi_aest_node_interface_16k *b =3D + (struct acpi_aest_node_interface_16k *)(hdr + 1); + of_property_read_u64_array(np, "arm,record-impl", + b->error_record_implemented, 4); + of_property_read_u64_array(np, "arm,status-reporting", + b->error_status_reporting, 4); + of_property_read_u64_array(np, "arm,addressing-mode", + b->addressing_mode, 4); + common =3D &b->common; + anode->record_implemented =3D + (unsigned long *)b->error_record_implemented; + anode->status_reporting =3D + (unsigned long *)b->error_status_reporting; + anode->addressing_mode =3D + (unsigned long *)b->addressing_mode; + break; + } + case ACPI_AEST_NODE_GROUP_FORMAT_64K: { + struct acpi_aest_node_interface_64k *b =3D + (struct acpi_aest_node_interface_64k *)(hdr + 1); + of_property_read_u64_array(np, "arm,record-impl", + b->error_record_implemented, 14); + of_property_read_u64_array(np, "arm,status-reporting", + b->error_status_reporting, 14); + of_property_read_u64_array(np, "arm,addressing-mode", + b->addressing_mode, 14); + common =3D &b->common; + anode->record_implemented =3D + (unsigned long *)b->error_record_implemented; + anode->status_reporting =3D + (unsigned long *)b->error_status_reporting; + anode->addressing_mode =3D + (unsigned long *)b->addressing_mode; + break; + } + default: + pr_err("node %pOF: unsupported group-format %u\n", np, gfmt); + kfree(hdr); + return -EINVAL; + } + + if (!of_address_to_resource(np, of_property_match_string( + np, "reg-names", "fault-inject"), &named_res)) + common->fault_inject_register_base =3D named_res.start; + + if (!of_address_to_resource(np, of_property_match_string( + np, "reg-names", "err-group"), &named_res)) + common->error_group_register_base =3D named_res.start; + + if (!of_address_to_resource(np, of_property_match_string( + np, "reg-names", "irq-config"), &named_res)) + common->interrupt_config_register_base =3D named_res.start; + + anode->interface_hdr =3D hdr; + anode->common =3D common; + + return 0; +} + +static int dt_aest_build_interrupt(struct device_node *np, + struct acpi_aest_node *anode) +{ + struct acpi_aest_node_interrupt_v2 *irq_arr; + int fhi_irq, eri_irq, count =3D 0; + u32 fhi_flags =3D 0, eri_flags =3D 0; + + of_property_read_u32(np, "arm,fhi-flags", &fhi_flags); + of_property_read_u32(np, "arm,eri-flags", &eri_flags); + + fhi_irq =3D of_irq_get_byname(np, "fhi"); + if (fhi_irq =3D=3D -EPROBE_DEFER) + return -EPROBE_DEFER; + if (fhi_irq < 0 && fhi_irq !=3D -EINVAL) { + const char *name =3D NULL; + + of_property_read_string(np, "interrupt-names", &name); + + pr_warn("node %pOF: failed to map FHI IRQ: %d (interrupt-names[0]=3D\"%s= \", want \"%s\")\n", + np, fhi_irq, name ?: "", "fhi"); + } + eri_irq =3D of_irq_get_byname(np, "eri"); + if (eri_irq =3D=3D -EPROBE_DEFER) + return -EPROBE_DEFER; + if (eri_irq < 0 && eri_irq !=3D -EINVAL) { + const char *name =3D NULL; + + of_property_read_string_index(np, "interrupt-names", 1, &name); + + pr_warn("node %pOF: failed to map ERI IRQ: %d (interrupt-names[1]=3D\"%s= \", want \"%s\")\n", + np, eri_irq, name ?: "", "eri"); + } + + if (fhi_irq > 0) + count++; + if (eri_irq > 0) + count++; + + if (!count) { + anode->interrupt =3D NULL; + anode->interrupt_count =3D 0; + return 0; + } + + irq_arr =3D kcalloc(count, sizeof(*irq_arr), GFP_KERNEL); + if (!irq_arr) + return -ENOMEM; + + count =3D 0; + if (fhi_irq > 0) { + irq_arr[count].gsiv =3D fhi_irq; + irq_arr[count].flags =3D AEST_INTERRUPT_MODE | fhi_flags; + irq_arr[count].type =3D ACPI_AEST_NODE_FAULT_HANDLING; + count++; + } + if (eri_irq > 0) { + irq_arr[count].gsiv =3D eri_irq; + irq_arr[count].flags =3D eri_flags; + irq_arr[count].type =3D ACPI_AEST_NODE_ERROR_RECOVERY; + count++; + } + + anode->interrupt =3D irq_arr; + anode->interrupt_count =3D count; + return 0; +} + +static int dt_aest_build_node_specific(struct device_node *np, + struct acpi_aest_node *anode, + int node_type) +{ + switch (node_type) { + + case ACPI_AEST_PROCESSOR_ERROR_NODE: { + struct acpi_aest_processor *proc; + u32 rtype =3D 0, pflags =3D 0; + + proc =3D kzalloc_obj(*proc, GFP_KERNEL); + if (!proc) + return -ENOMEM; + + of_property_read_u32(np, "arm,resource-type", &rtype); + of_property_read_u32(np, "arm,processor-flags", &pflags); + + proc->resource_type =3D (u8)rtype; + proc->flags =3D (u8)pflags; + + /* Processor cache/TLB/generic sub-structure */ + switch (rtype) { + case ACPI_AEST_CACHE_RESOURCE: { + struct acpi_aest_processor_cache *c; + struct device_node *cache_np; + + c =3D kzalloc_obj(*c, GFP_KERNEL); + if (!c) { + kfree(proc); + return -ENOMEM; + } + + cache_np =3D of_parse_phandle(np, "arm,cache-ref", 0); + if (cache_np) { + c->cache_reference =3D cache_np->phandle; + of_node_put(cache_np); + } + anode->cache =3D c; + break; + } + case ACPI_AEST_TLB_RESOURCE: { + struct acpi_aest_processor_tlb *t; + + t =3D kzalloc_obj(*t, GFP_KERNEL); + if (!t) { + kfree(proc); + return -ENOMEM; + } + of_property_read_u32(np, "arm,tlb-level", + &t->tlb_level); + anode->tlb =3D t; + break; + } + default: { + struct acpi_aest_processor_generic *g; + + g =3D kzalloc_obj(*g, GFP_KERNEL); + if (!g) { + kfree(proc); + return -ENOMEM; + } + of_property_read_u32(np, "arm,resource-ref", + &g->resource); + anode->generic =3D g; + break; + } + } + anode->processor =3D proc; + break; + } + + case ACPI_AEST_MEMORY_ERROR_NODE: { + struct acpi_aest_memory *mem; + + mem =3D kzalloc_obj(*mem, GFP_KERNEL); + + if (!mem) + return -ENOMEM; + of_property_read_u32(np, "arm,proximity-domain", + &mem->srat_proximity_domain); + anode->memory =3D mem; + break; + } + + case ACPI_AEST_SMMU_ERROR_NODE: { + struct acpi_aest_smmu *smmu; + struct device_node *smmu_np; + + smmu =3D kzalloc_obj(*smmu, GFP_KERNEL); + + if (!smmu) + return -ENOMEM; + smmu_np =3D of_parse_phandle(np, "arm,smmu-ref", 0); + if (smmu_np) { + /* Use the DT node offset as the IORT reference */ + smmu->iort_node_reference =3D smmu_np->phandle; + of_node_put(smmu_np); + } + of_property_read_u32(np, "arm,smmu-subcomponent", + &smmu->subcomponent_reference); + anode->smmu =3D smmu; + break; + } + + case ACPI_AEST_VENDOR_ERROR_NODE: { + struct acpi_aest_vendor_v2 *vendor; + const char *hid =3D "ARMHC000"; + + vendor =3D kzalloc_obj(*vendor, GFP_KERNEL); + + if (!vendor) + return -ENOMEM; + of_property_read_string(np, "arm,vendor-hid", &hid); + strscpy(vendor->acpi_hid, hid, sizeof(vendor->acpi_hid)); + of_property_read_u32(np, "arm,vendor-uid", + &vendor->acpi_uid); + anode->vendor =3D vendor; + break; + } + + case ACPI_AEST_GIC_ERROR_NODE: { + struct acpi_aest_gic *gic; + + gic =3D kzalloc_obj(*gic, GFP_KERNEL); + + if (!gic) + return -ENOMEM; + of_property_read_u32(np, "arm,gic-type", + &gic->interface_type); + of_property_read_u32(np, "arm,gic-instance", + &gic->instance_id); + anode->gic =3D gic; + break; + } + + case ACPI_AEST_PCIE_ERROR_NODE: { + struct acpi_aest_pcie *pcie; + + pcie =3D kzalloc_obj(*pcie, GFP_KERNEL); + + if (!pcie) + return -ENOMEM; + of_property_read_u32(np, "arm,pcie-segment", + &pcie->iort_node_reference); + anode->pcie =3D pcie; + break; + } + + case ACPI_AEST_PROXY_ERROR_NODE: + /* No node-specific data for proxy nodes */ + anode->spec_pointer =3D NULL; + break; + + default: + return -EINVAL; + } + + return 0; +} + +static struct acpi_aest_node * +dt_aest_alloc_anode(struct device_node *np, int node_type) +{ + struct acpi_aest_node *anode; + int ret; + + anode =3D kzalloc_obj(*anode, GFP_KERNEL); + if (!anode) + return ERR_PTR(-ENOMEM); + + INIT_LIST_HEAD(&anode->list); + anode->type =3D node_type; + + ret =3D dt_aest_build_interface(np, anode); + if (ret) + goto err_free; + + ret =3D dt_aest_build_node_specific(np, anode, node_type); + if (ret) + goto err_free; + + ret =3D dt_aest_build_interrupt(np, anode); + if (ret) + goto err_free; + + return anode; + +err_free: + kfree(anode->interface_hdr); + kfree(anode->spec_pointer); + kfree(anode->processor_spec_pointer); + kfree(anode); + return ERR_PTR(ret); +} + +static int dt_aest_init_one_node(struct device_node *np, + struct dt_aest_priv *priv) +{ + int node_type; + struct aest_hnode *ahnode; + struct acpi_aest_node *anode; + + node_type =3D dt_aest_node_type(np); + if (node_type < 0) { + pr_warn("unknown node type for %pOF, skipping\n", np); + return 0; + } + + ahnode =3D dt_aest_alloc_hnode(node_type, priv->node_id); + if (!ahnode) + return -ENOMEM; + + anode =3D dt_aest_alloc_anode(np, node_type); + if (IS_ERR(anode)) { + kfree(ahnode); + return PTR_ERR(anode); + } + + list_add_tail(&anode->list, &ahnode->list); + ahnode->count =3D 1; + + if (xa_err(xa_store(&priv->aest_array, priv->node_id, + ahnode, GFP_KERNEL))) { + kfree(anode); + kfree(ahnode); + return -ENOMEM; + } + priv->node_id++; + return 0; +} + +static int dt_aest_init_nodes(struct device_node *aest_root, + struct dt_aest_priv *priv) +{ + struct device_node *np; + int ret; + + for_each_available_child_of_node(aest_root, np) { + ret =3D dt_aest_init_one_node(np, priv); + if (ret) { + pr_err("failed to init node %pOF: %d\n", np, ret); + of_node_put(np); + return ret; + } + } + return 0; +} + +static struct platform_device *dt_aest_alloc_pdev(struct aest_hnode *ahnod= e, + int index) +{ + struct platform_device *pdev; + struct resource *res; + struct acpi_aest_node *anode; + int ret, size, j; + int irq[AEST_MAX_INTERRUPT_PER_NODE] =3D { 0 }; + + pdev =3D platform_device_alloc("AEST", index); + if (!pdev) + return ERR_PTR(-ENOMEM); + + res =3D kcalloc(ahnode->count + AEST_MAX_INTERRUPT_PER_NODE, + sizeof(*res), GFP_KERNEL); + if (!res) { + platform_device_put(pdev); + return ERR_PTR(-ENOMEM); + } + + j =3D 0; + list_for_each_entry(anode, &ahnode->list, list) { + if (anode->interface_hdr->type !=3D + ACPI_AEST_NODE_SYSTEM_REGISTER) { + res[j].name =3D AEST_NODE_NAME; + res[j].start =3D anode->interface_hdr->address; + + switch (anode->interface_hdr->group_format) { + case ACPI_AEST_NODE_GROUP_FORMAT_4K: + size =3D 4 * KB; break; + case ACPI_AEST_NODE_GROUP_FORMAT_16K: + size =3D 16 * KB; break; + case ACPI_AEST_NODE_GROUP_FORMAT_64K: + size =3D 64 * KB; break; + default: + size =3D 4 * KB; + } + res[j].end =3D res[j].start + size - 1; + res[j].flags =3D IORESOURCE_MEM; + j++; + } + + if (anode->interrupt && anode->interrupt_count > 0) { + int k; + + for (k =3D 0; k < anode->interrupt_count && + k < AEST_MAX_INTERRUPT_PER_NODE; k++) { + + struct acpi_aest_node_interrupt_v2 *intr =3D + &anode->interrupt[k]; + int itype =3D intr->type; + int virq =3D intr->gsiv; + struct irq_data *irqd; + + if (!virq) + continue; + if (itype >=3D AEST_MAX_INTERRUPT_PER_NODE) + continue; + if (irq[itype] =3D=3D virq) + continue; + irq[itype] =3D virq; + /* + * aest_config_irq() writes intr->gsiv directly + * to the hardware IRQ-config register, so it + * must hold the GIC hardware SPI number, not the + * Linux virtual IRQ. Convert here now that we + * have the virq in hand; the resource still gets + * the virq so devm_request_irq() works correctly. + */ + irqd =3D irq_get_irq_data(virq); + if (irqd) + intr->gsiv =3D irqd->hwirq; + + res[j].name =3D (itype =3D=3D ACPI_AEST_NODE_FAULT_HANDLING) + ? AEST_FHI_NAME : AEST_ERI_NAME; + res[j].start =3D virq; + res[j].end =3D virq; + res[j].flags =3D IORESOURCE_IRQ; + j++; + } + } + } + + ret =3D platform_device_add_resources(pdev, res, j); + kfree(res); + if (ret) { + platform_device_put(pdev); + return ERR_PTR(ret); + } + + ret =3D platform_device_add_data(pdev, &ahnode, sizeof(ahnode)); + if (ret) { + platform_device_put(pdev); + return ERR_PTR(ret); + } + + ret =3D platform_device_add(pdev); + if (ret) { + platform_device_put(pdev); + return ERR_PTR(ret); + } + + return pdev; +} + +static int dt_aest_alloc_pdevs(struct dt_aest_priv *priv) +{ + struct aest_hnode *ahnode; + unsigned long i; + int ret =3D 0, index =3D 0; + + xa_for_each(&priv->aest_array, i, ahnode) { + struct platform_device *pdev =3D + dt_aest_alloc_pdev(ahnode, index++); + if (IS_ERR(pdev)) { + ret =3D PTR_ERR(pdev); + pr_err("failed to alloc pdev for node %u: %d\n", + ahnode->id, ret); + break; + } + } + return ret; +} + +static int __init dt_aest_init(void) +{ + struct device_node *aest_root; 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The DT describes a processor error source covering all CPU cores and a shared L3 cache error source for the cluster. These nodes model the hardware error reporting blocks and associated interrupts as required by the Arm AEST specification. Co-developed-by: Faruque Ansari Signed-off-by: Faruque Ansari Signed-off-by: Umang Chheda --- arch/arm64/boot/dts/qcom/lemans.dtsi | 41 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qco= m/lemans.dtsi index fe6e76351823..199ea1f9a8d5 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -4,6 +4,7 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ =20 +#include #include #include #include @@ -29,6 +30,46 @@ / { #address-cells =3D <2>; #size-cells =3D <2>; =20 + aest { + compatible =3D "arm,aest"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + aest-processor-0 { + compatible =3D "arm,aest-processor"; + arm,num-records =3D <1>; + arm,record-impl =3D /bits/ 64 <0x0>; + arm,status-reporting =3D /bits/ 64 <0x0>; + arm,addressing-mode =3D /bits/ 64 <0x0>; + arm,processor-flags =3D ; + interrupts =3D ; + interrupt-names =3D "fhi"; + }; + + aest-l3-cluster0 { + compatible =3D "arm,aest-processor"; + arm,num-records =3D <2>; + arm,record-impl =3D /bits/ 64 <0x1>; + arm,status-reporting =3D /bits/ 64 <0x0>; + arm,addressing-mode =3D /bits/ 64 <0x0>; + arm,processor-flags =3D ; + interrupts =3D ; + interrupt-names =3D "fhi"; + }; + + aest-l3-cluster1 { + compatible =3D "arm,aest-processor"; + arm,num-records =3D <2>; + arm,record-impl =3D /bits/ 64 <0x1>; + arm,status-reporting =3D /bits/ 64 <0x0>; + arm,addressing-mode =3D /bits/ 64 <0x0>; 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Tue, 05 May 2026 05:25:43 -0700 (PDT) Received: from hu-uchheda-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c7ffbbaac5bsm12597998a12.6.2026.05.05.05.25.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 May 2026 05:25:43 -0700 (PDT) From: Umang Chheda Date: Tue, 05 May 2026 17:53:52 +0530 Subject: [PATCH 8/8] arm64: dts: qcom: monaco: add AEST error nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260505-aest-devicetree-support-v1-8-d5d6ffacf0a5@oss.qualcomm.com> References: <20260505-aest-devicetree-support-v1-0-d5d6ffacf0a5@oss.qualcomm.com> In-Reply-To: <20260505-aest-devicetree-support-v1-0-d5d6ffacf0a5@oss.qualcomm.com> To: Ruidong Tian , Tony Luck , Borislav Petkov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , catalin.marinas@arm.com, will@kernel.org, lpieralisi@kernel.org, rafael@kernel.org, mark.rutland@arm.com, Sudeep Holla Cc: linux-arm-msm@vger.kernel.org, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-edac@vger.kernel.org, Umang Chheda , Faruque Ansari X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; 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The DT describes a processor error source covering all CPU cores and a shared L3 cache error source for the cluster. These nodes model the hardware error reporting blocks and associated interrupts as required by the Arm AEST specification. Co-developed-by: Faruque Ansari Signed-off-by: Faruque Ansari Signed-off-by: Umang Chheda --- arch/arm64/boot/dts/qcom/monaco.dtsi | 41 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qco= m/monaco.dtsi index 7b1d57460f1e..8e43ceed7d84 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ =20 +#include #include #include #include @@ -29,6 +30,46 @@ / { #address-cells =3D <2>; #size-cells =3D <2>; =20 + aest { + compatible =3D "arm,aest"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + aest-processor-0 { + compatible =3D "arm,aest-processor"; + arm,num-records =3D <1>; + arm,record-impl =3D /bits/ 64 <0x0>; + arm,status-reporting =3D /bits/ 64 <0x0>; + arm,addressing-mode =3D /bits/ 64 <0x0>; + arm,processor-flags =3D ; + interrupts =3D ; + interrupt-names =3D "fhi"; + }; + + aest-l3-cluster0 { + compatible =3D "arm,aest-processor"; + arm,num-records =3D <2>; + arm,record-impl =3D /bits/ 64 <0x1>; + arm,status-reporting =3D /bits/ 64 <0x0>; + arm,addressing-mode =3D /bits/ 64 <0x0>; + arm,processor-flags =3D ; + interrupts =3D ; + interrupt-names =3D "fhi"; + }; + + aest-l3-cluster1 { + compatible =3D "arm,aest-processor"; + arm,num-records =3D <2>; + arm,record-impl =3D /bits/ 64 <0x1>; + arm,status-reporting =3D /bits/ 64 <0x0>; + arm,addressing-mode =3D /bits/ 64 <0x0>; + arm,processor-flags =3D ; + interrupts =3D ; + interrupt-names =3D "fhi"; + }; + }; + clocks { xo_board_clk: xo-board-clk { compatible =3D "fixed-clock"; --=20 2.34.1