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Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/5] dt-bindings: thermal: sun8i: Add A523 THS0/1 controllers Date: Mon, 4 May 2026 13:02:41 +0800 Message-ID: <20260504050245.646078-2-iuncuim@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260504050245.646078-1-iuncuim@gmail.com> References: <20260504050245.646078-1-iuncuim@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add dt-bindings description of the thermal sensors in the A523 processor. The controllers require activation of the additional frequency of the associated gpadc controller, so a mod clock property required. The calibration data is split into two cells that are in different areas of nvmem. Both controllers require access to both memory cell, so a new property nvmem-cells has been added. To maintain backward compatibility, the name of the old cell remains the same and the new nvmem-cell-names is called calibration-second-part Signed-off-by: Mikhail Kalashnikov Reviewed-by: Chen-Yu Tsai --- .../thermal/allwinner,sun8i-a83t-ths.yaml | 54 +++++++++++++++++-- 1 file changed, 51 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t= -ths.yaml b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-= ths.yaml index 3e61689f6..6020413c3 100644 --- a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.ya= ml +++ b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.ya= ml @@ -24,6 +24,8 @@ properties: - allwinner,sun50i-h5-ths - allwinner,sun50i-h6-ths - allwinner,sun50i-h616-ths + - allwinner,sun55i-a523-ths0 + - allwinner,sun55i-a523-ths1 =20 clocks: minItems: 1 @@ -47,11 +49,16 @@ properties: maxItems: 1 =20 nvmem-cells: - maxItems: 1 - description: Calibration data for thermal sensors + minItems: 1 + items: + - description: Calibration data for thermal sensors + - description: Additional cell in case of separate calibration data =20 nvmem-cell-names: - const: calibration + minItems: 1 + items: + - const: calibration + - const: calibration-second-part =20 allwinner,sram: maxItems: 1 @@ -107,6 +114,7 @@ allOf: enum: - allwinner,sun8i-h3-ths - allwinner,sun20i-d1-ths + - allwinner,sun55i-a523-ths0 =20 then: properties: @@ -132,6 +140,29 @@ allOf: - clock-names - resets =20 + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun55i-a523-ths0 + - allwinner,sun55i-a523-ths1 + then: + properties: + clocks: + minItems: 2 + nvmem-cells: + minItems: 2 + nvmem-cell-names: + minItems: 2 + else: + properties: + nvmem-cells: + maxItems: 1 + nvmem-cell-names: + items: + - const: calibration + required: - compatible - reg @@ -176,4 +207,21 @@ examples: #thermal-sensor-cells =3D <1>; }; =20 + - | + #include + #include + #include + + thermal-sensor@2009400 { + compatible =3D "allwinner,sun55i-a523-ths1"; + reg =3D <0x02009400 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_THS>, <&ccu CLK_GPADC1>; + clock-names =3D "bus", "mod"; + resets =3D <&ccu RST_BUS_THS>; + nvmem-cells =3D <&ths_calibration0>, <&ths_calibration1>; + nvmem-cell-names =3D "calibration", + "calibration-second-part"; + #thermal-sensor-cells =3D <1>; + }; ... --=20 2.54.0 From nobody Tue Jun 16 08:05:33 2026 Received: from mail-pj1-f46.google.com (mail-pj1-f46.google.com [209.85.216.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97C712472A2 for ; Mon, 4 May 2026 05:03:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777871021; cv=none; b=f4JlHgXmfuA8yylT3lPBM+9GLEF7rKBeN72uBfYHSzukcOJJrJAWA9HeO5cORXl1AKq8K7PEvcajlnqSxL9VyMI4nR5m3WachwsBZArJ2xkMvKVz6nTTIdx7z6L5XbIrJZZcAZjsEgptzsMdoK86PlwzsM5hSYaMFQWd3bkJUpg= ARC-Message-Signature: i=1; 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Sun, 03 May 2026 22:03:39 -0700 (PDT) Received: from archlinux ([2605:e440:15::152]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-365437b50b0sm2662908a91.0.2026.05.03.22.03.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 May 2026 22:03:39 -0700 (PDT) From: Mikhail Kalashnikov To: Vasily Khoruzhick , Yangtao Li , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/5] thermal/drivers/sun8i: replace devm_reset_control_get to devm_reset_control_get_shared_deasserted Date: Mon, 4 May 2026 13:02:42 +0800 Message-ID: <20260504050245.646078-3-iuncuim@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260504050245.646078-1-iuncuim@gmail.com> References: <20260504050245.646078-1-iuncuim@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The A523 processor has two temperature controllers, but they share a common reset line. Make it shared with the shared variant of devm_reset_control_get(), and also simplify the driver by switching to devm_reset_control_get_shared_deasserted(). Signed-off-by: Mikhail Kalashnikov Reviewed-by: Chen-Yu Tsai Reviewed-by: Chen-Yu Tsai --- drivers/thermal/sun8i_thermal.c | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_therma= l.c index 226747906..df0c26970 100644 --- a/drivers/thermal/sun8i_thermal.c +++ b/drivers/thermal/sun8i_thermal.c @@ -342,11 +342,6 @@ static int sun8i_ths_calibrate(struct ths_device *tmde= v) return ret; } =20 -static void sun8i_ths_reset_control_assert(void *data) -{ - reset_control_assert(data); -} - static struct regmap *sun8i_ths_get_sram_regmap(struct device_node *node) { struct platform_device *sram_pdev; @@ -389,19 +384,10 @@ static int sun8i_ths_resource_init(struct ths_device = *tmdev) return PTR_ERR(tmdev->regmap); =20 if (tmdev->chip->has_bus_clk_reset) { - tmdev->reset =3D devm_reset_control_get(dev, NULL); + tmdev->reset =3D devm_reset_control_get_shared_deasserted(dev, NULL); if (IS_ERR(tmdev->reset)) return PTR_ERR(tmdev->reset); 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Sun, 03 May 2026 22:03:54 -0700 (PDT) Received: from archlinux ([2605:e440:15::152]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-365437b50b0sm2662908a91.0.2026.05.03.22.03.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 May 2026 22:03:54 -0700 (PDT) From: Mikhail Kalashnikov To: Vasily Khoruzhick , Yangtao Li , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v4 3/5] thermal/drivers/sun8i: get calibration data from two nvmem cells Date: Mon, 4 May 2026 13:02:43 +0800 Message-ID: <20260504050245.646078-4-iuncuim@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260504050245.646078-1-iuncuim@gmail.com> References: <20260504050245.646078-1-iuncuim@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The A523 processor has calibration data in two nvmem cell. To be able to add support, the ability to add data from two cells into one array must be added. Signed-off-by: Mikhail Kalashnikov --- drivers/thermal/sun8i_thermal.c | 77 ++++++++++++++++++++++----------- 1 file changed, 52 insertions(+), 25 deletions(-) diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_therma= l.c index df0c26970..c4aaff8f7 100644 --- a/drivers/thermal/sun8i_thermal.c +++ b/drivers/thermal/sun8i_thermal.c @@ -301,43 +301,70 @@ static int sun50i_h6_ths_calibrate(struct ths_device = *tmdev, =20 static int sun8i_ths_calibrate(struct ths_device *tmdev) { - struct nvmem_cell *calcell; + struct nvmem_cell *calcell =3D NULL; struct device *dev =3D tmdev->dev; - u16 *caldata; - size_t callen; + struct device_node *np =3D dev_of_node(dev); + struct property *prop; + const char *cellname; + u8 *caldata =3D NULL; + size_t callen =3D 0; int ret =3D 0; =20 - calcell =3D nvmem_cell_get(dev, "calibration"); - if (IS_ERR(calcell)) { - if (PTR_ERR(calcell) =3D=3D -EPROBE_DEFER) - return -EPROBE_DEFER; - /* - * Even if the external calibration data stored in sid is - * not accessible, the THS hardware can still work, although - * the data won't be so accurate. - * - * The default value of calibration register is 0x800 for - * every sensor, and the calibration value is usually 0x7xx - * or 0x8xx, so they won't be away from the default value - * for a lot. - * - * So here we do not return error if the calibration data is - * not available, except the probe needs deferring. - */ - goto out; + of_property_for_each_string(np, "nvmem-cell-names", prop, cellname) { + size_t len; + u8 *caldatapart; + + calcell =3D of_nvmem_cell_get(np, cellname); + if (IS_ERR(calcell)) { + if (PTR_ERR(calcell) =3D=3D -EPROBE_DEFER) + return -EPROBE_DEFER; + /* + * Even if the external calibration data stored in sid is + * not accessible, the THS hardware can still work, although + * the data won't be so accurate. + * + * The default value of calibration register is 0x800 for + * every sensor, and the calibration value is usually 0x7xx + * or 0x8xx, so they won't be away from the default value + * for a lot. + * + * So here we do not return error if the calibration data is + * not available, except the probe needs deferring. + */ + goto out; + } + + caldatapart =3D nvmem_cell_read(calcell, &len); + nvmem_cell_put(calcell); + calcell =3D NULL; + if (IS_ERR(caldatapart)) { + ret =3D PTR_ERR(caldatapart); + goto out; + } + + caldata =3D devm_krealloc(dev, caldata, callen + len, GFP_KERNEL); + if (!caldata) { + kfree(caldatapart); + ret =3D -ENOMEM; + goto out; + } + + memcpy(caldata + callen, caldatapart, len); + callen +=3D len; + kfree(caldatapart); } =20 - caldata =3D nvmem_cell_read(calcell, &callen); if (IS_ERR(caldata)) { ret =3D PTR_ERR(caldata); goto out; } =20 - tmdev->chip->calibrate(tmdev, caldata, callen); + tmdev->chip->calibrate(tmdev, (u16 *)caldata, callen); =20 - kfree(caldata); + devm_kfree(dev, caldata); + caldata =3D NULL; out: - if (!IS_ERR(calcell)) + if (calcell && !IS_ERR(calcell)) nvmem_cell_put(calcell); return ret; } --=20 2.54.0 From nobody Tue Jun 16 08:05:33 2026 Received: from mail-pj1-f51.google.com (mail-pj1-f51.google.com [209.85.216.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88EE525393E for ; Mon, 4 May 2026 05:04:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Sun, 03 May 2026 22:04:08 -0700 (PDT) Received: from archlinux ([2605:e440:15::152]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-365437b50b0sm2662908a91.0.2026.05.03.22.03.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 May 2026 22:04:08 -0700 (PDT) From: Mikhail Kalashnikov To: Vasily Khoruzhick , Yangtao Li , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v4 4/5] thermal/drivers/sun8i: Add support for A523 THS0/1 controllers Date: Mon, 4 May 2026 13:02:44 +0800 Message-ID: <20260504050245.646078-5-iuncuim@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260504050245.646078-1-iuncuim@gmail.com> References: <20260504050245.646078-1-iuncuim@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The A523 processor has two temperature controllers, THS0 and THS1. THS0 has only one temperature sensor, which is located in the DRAM. THS1 does have 3 sensors: ths1_0 - "big" cores ths1_1 - "little" cores ths1_2 - gpu The datasheet mentions a fourth sensor in the NPU, but lacks any registers for operation other than calibration registers. The vendor code reads the value from ths1_2, but uses separate calibration data, so we get two different values from real one. Signed-off-by: Mikhail Kalashnikov Reviewed-by: Chen-Yu Tsai --- drivers/thermal/sun8i_thermal.c | 133 ++++++++++++++++++++++++++++++++ 1 file changed, 133 insertions(+) diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_therma= l.c index c4aaff8f7..3b73aafab 100644 --- a/drivers/thermal/sun8i_thermal.c +++ b/drivers/thermal/sun8i_thermal.c @@ -59,6 +59,12 @@ #define SUN50I_H6_THS_PC_TEMP_PERIOD(x) ((GENMASK(19, 0) & (x)) << 12) #define SUN50I_H6_THS_DATA_IRQ_STS(x) BIT(x) =20 +#define SUN55I_A523_DELIMITER 0x7c8 +#define SUN55I_A523_OFFSET_ABOVE 2736 +#define SUN55I_A523_OFFSET_BELOW 2825 +#define SUN55I_A523_SCALE_ABOVE 74 +#define SUN55I_A523_SCALE_BELOW 65 + struct tsensor { struct ths_device *tmdev; struct thermal_zone_device *tzd; @@ -114,6 +120,15 @@ static int sun50i_h5_calc_temp(struct ths_device *tmde= v, return -1590 * reg / 10 + 276000; } =20 +static int sun55i_a523_calc_temp(struct ths_device *tmdev, + int id, int reg) +{ + if (reg >=3D SUN55I_A523_DELIMITER) + return SUN55I_A523_SCALE_ABOVE * (SUN55I_A523_OFFSET_ABOVE - reg); + else + return SUN55I_A523_SCALE_BELOW * (SUN55I_A523_OFFSET_BELOW - reg); +} + static int sun8i_ths_get_temp(struct thermal_zone_device *tz, int *temp) { struct tsensor *s =3D thermal_zone_device_priv(tz); @@ -299,6 +314,97 @@ static int sun50i_h6_ths_calibrate(struct ths_device *= tmdev, return 0; } =20 +/* + * The A523 nvmem calibration values. The ths1_3 is not used as it + * doesn't have its own sensor and doesn't have any internal switch. + * Instead, the value from the ths1_2 sensor is used, which gives the + * illusion of an independent sensor for NPU and GPU when using + * different calibration values. + * + * efuse layout 0x38-0x3F (caldata[0..3]): + * caldata[0] caldata[1] caldata[2] caldata[3] + * 0 16 24 32 36 48 60 64 + * +---------------+---------------+---------------+---------------+ + * | | | temp | ths1_0 | ths1_1 | + + * +---------------+---------------+---------------+---------------+ + * + * efuse layout 0x44-0x4B (caldata[4..7]): + * caldata[4] caldata[5] caldata[6] caldata[7] + * 0 12 16 24 32 36 48 64 + * +---------------+---------------+---------------+---------------+ + * | ths1_2 | ths1_3 | ths0 | | + + * +---------------+---------------+---------------+---------------+ + */ +static int sun55i_a523_ths_calibrate(struct ths_device *tmdev, + u16 *caldata, int callen) +{ + struct device *dev =3D tmdev->dev; + int i, ft_temp; + + if (!caldata[0]) + return -EINVAL; + + ft_temp =3D (((caldata[2] << 8) | (caldata[1] >> 8)) & FT_TEMP_MASK) * 10= 0; + + for (i =3D 0; i < tmdev->chip->sensor_num; i++) { + int sensor_reg, sensor_temp, cdata, offset; + /* + * Chips ths0 and ths1 have common parameters for value + * calibration. To separate them we can use the number of + * temperature sensors on each chip. + * For ths0 this value is 1. + */ + if (tmdev->chip->sensor_num =3D=3D 1) { + sensor_reg =3D ((caldata[5] >> 8) | (caldata[6] << 8)) & TEMP_CALIB_MAS= K; + } else { + switch (i) { + case 0: + sensor_reg =3D (caldata[2] >> 4) & TEMP_CALIB_MASK; + break; + case 1: + sensor_reg =3D caldata[3] & TEMP_CALIB_MASK; + break; + case 2: + sensor_reg =3D caldata[4] & TEMP_CALIB_MASK; + break; + default: + sensor_reg =3D 0; + break; + } + } + + sensor_temp =3D tmdev->chip->calc_temp(tmdev, i, sensor_reg); + + /* + * Calibration data is CALIBRATE_DEFAULT - (calculated + * temperature from sensor reading at factory temperature + * minus actual factory temperature) * X (scale from + * temperature to register values) + */ + cdata =3D CALIBRATE_DEFAULT - + ((sensor_temp - ft_temp) / SUN55I_A523_SCALE_ABOVE); + + if (cdata & ~TEMP_CALIB_MASK) { + /* + * Calibration value more than 12-bit, but calibration + * register is 12-bit. In this case, ths hardware can + * still work without calibration, although the data + * won't be so accurate. + */ + dev_warn(dev, "sensor%d is not calibrated.\n", i); + continue; + } + + offset =3D (i % 2) * 16; + regmap_update_bits(tmdev->regmap, + SUN50I_H6_THS_TEMP_CALIB + (i / 2 * 4), + TEMP_CALIB_MASK << offset, + cdata << offset); + } + + return 0; +} + static int sun8i_ths_calibrate(struct ths_device *tmdev) { struct nvmem_cell *calcell =3D NULL; @@ -722,6 +828,31 @@ static const struct ths_thermal_chip sun50i_h616_ths = =3D { .calc_temp =3D sun8i_ths_calc_temp, }; =20 +/* The A523 has a shared reset line for both chips */ +static const struct ths_thermal_chip sun55i_a523_ths0 =3D { + .sensor_num =3D 1, + .has_bus_clk_reset =3D true, + .has_mod_clk =3D true, + .ft_deviation =3D 5000, + .temp_data_base =3D SUN50I_H6_THS_TEMP_DATA, + .calibrate =3D sun55i_a523_ths_calibrate, + .init =3D sun50i_h6_thermal_init, + .irq_ack =3D sun50i_h6_irq_ack, + .calc_temp =3D sun55i_a523_calc_temp, +}; + +static const struct ths_thermal_chip sun55i_a523_ths1 =3D { + .sensor_num =3D 3, + .has_bus_clk_reset =3D true, + .has_mod_clk =3D true, + .ft_deviation =3D 5000, + .temp_data_base =3D SUN50I_H6_THS_TEMP_DATA, + .calibrate =3D sun55i_a523_ths_calibrate, + .init =3D sun50i_h6_thermal_init, + .irq_ack =3D sun50i_h6_irq_ack, + .calc_temp =3D sun55i_a523_calc_temp, +}; + static const struct of_device_id of_ths_match[] =3D { { .compatible =3D "allwinner,sun8i-a83t-ths", .data =3D &sun8i_a83t_ths }, { .compatible =3D "allwinner,sun8i-h3-ths", .data =3D &sun8i_h3_ths }, @@ -732,6 +863,8 @@ static const struct of_device_id of_ths_match[] =3D { { .compatible =3D "allwinner,sun50i-h6-ths", .data =3D &sun50i_h6_ths }, { .compatible =3D "allwinner,sun20i-d1-ths", .data =3D &sun20i_d1_ths }, { .compatible =3D "allwinner,sun50i-h616-ths", .data =3D &sun50i_h616_ths= }, + { .compatible =3D "allwinner,sun55i-a523-ths0", .data =3D &sun55i_a523_th= s0 }, + { .compatible =3D "allwinner,sun55i-a523-ths1", .data =3D &sun55i_a523_th= s1 }, { /* sentinel */ }, }; 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Sun, 03 May 2026 22:04:22 -0700 (PDT) From: Mikhail Kalashnikov To: Vasily Khoruzhick , Yangtao Li , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v4 5/5] Allwinner: A523: add support for A523 THS0/1 controllers Date: Mon, 4 May 2026 13:02:45 +0800 Message-ID: <20260504050245.646078-6-iuncuim@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260504050245.646078-1-iuncuim@gmail.com> References: <20260504050245.646078-1-iuncuim@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The A523 processor has two temperature controllers, THS0 and THS1. THS0 has only one temperature sensor, which is located in the DRAM. THS1 does have 3 sensors: ths1_0 - "big" cores ths1_1 - "little" cores ths1_2 - gpu Add the thermal sensor configuration and the thermal zones. Trips temperature, polling-delay and sustainable-power parameters are derived from the manufacturer's BSP. Signed-off-by: Mikhail Kalashnikov --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 154 ++++++++++++++++++ 1 file changed, 154 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index 5afa8d92a..288a4710b 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include =20 / { interrupt-parent =3D <&gic>; @@ -26,6 +27,7 @@ cpu0: cpu@0 { device_type =3D "cpu"; reg =3D <0x000>; enable-method =3D "psci"; + #cooling-cells =3D <2>; }; =20 cpu1: cpu@100 { @@ -33,6 +35,7 @@ cpu1: cpu@100 { device_type =3D "cpu"; reg =3D <0x100>; enable-method =3D "psci"; + #cooling-cells =3D <2>; }; =20 cpu2: cpu@200 { @@ -40,6 +43,7 @@ cpu2: cpu@200 { device_type =3D "cpu"; reg =3D <0x200>; enable-method =3D "psci"; + #cooling-cells =3D <2>; }; =20 cpu3: cpu@300 { @@ -47,6 +51,7 @@ cpu3: cpu@300 { device_type =3D "cpu"; reg =3D <0x300>; enable-method =3D "psci"; + #cooling-cells =3D <2>; }; =20 cpu4: cpu@400 { @@ -54,6 +59,7 @@ cpu4: cpu@400 { device_type =3D "cpu"; reg =3D <0x400>; enable-method =3D "psci"; + #cooling-cells =3D <2>; }; =20 cpu5: cpu@500 { @@ -61,6 +67,7 @@ cpu5: cpu@500 { device_type =3D "cpu"; reg =3D <0x500>; enable-method =3D "psci"; + #cooling-cells =3D <2>; }; =20 cpu6: cpu@600 { @@ -68,6 +75,7 @@ cpu6: cpu@600 { device_type =3D "cpu"; reg =3D <0x600>; enable-method =3D "psci"; + #cooling-cells =3D <2>; }; =20 cpu7: cpu@700 { @@ -75,6 +83,7 @@ cpu7: cpu@700 { device_type =3D "cpu"; reg =3D <0x700>; enable-method =3D "psci"; + #cooling-cells =3D <2>; }; }; =20 @@ -565,12 +574,46 @@ dma: dma-controller@3002000 { #dma-cells =3D <1>; }; =20 + ths1: thermal-sensor@2009400 { + compatible =3D "allwinner,sun55i-a523-ths1"; + reg =3D <0x02009400 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_THS>, <&ccu CLK_GPADC1>; + clock-names =3D "bus", "mod"; + resets =3D <&ccu RST_BUS_THS>; + nvmem-cells =3D <&ths_calibration0>, <&ths_calibration1>; + nvmem-cell-names =3D "calibration", + "calibration-second-part"; + #thermal-sensor-cells =3D <1>; + }; + + ths0: thermal-sensor@200a000 { + compatible =3D "allwinner,sun55i-a523-ths0"; + reg =3D <0x0200a000 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_THS>, <&ccu CLK_GPADC0>; + clock-names =3D "bus", "mod"; + resets =3D <&ccu RST_BUS_THS>; + nvmem-cells =3D <&ths_calibration0>, <&ths_calibration1>; + nvmem-cell-names =3D "calibration", + "calibration-second-part"; + #thermal-sensor-cells =3D <0>; + }; + sid: efuse@3006000 { compatible =3D "allwinner,sun55i-a523-sid", "allwinner,sun50i-a64-sid"; reg =3D <0x03006000 0x1000>; #address-cells =3D <1>; #size-cells =3D <1>; + + ths_calibration0: ths-calibration0@38 { + reg =3D <0x38 0x8>; + }; + + ths_calibration1: ths-calibration1@44 { + reg =3D <0x44 0x8>; + }; }; =20 gic: interrupt-controller@3400000 { @@ -1087,4 +1130,115 @@ npu: npu@7122000 { power-domains =3D <&ppu PD_NPU>; }; }; + + thermal-zones { + cpu0_thermal: cpu0-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <1000>; + thermal-sensors =3D <&ths1 1>; + sustainable-power =3D <1200>; + + trips { + cpu0_threshold: cpu-trip-0 { + temperature =3D <70000>; + type =3D "passive"; + hysteresis =3D <0>; + }; + cpu0_target: cpu-trip-1 { + temperature =3D <90000>; + type =3D "passive"; + hysteresis =3D <0>; + }; + cpu0_critical: cpu-trip-2 { + temperature =3D <110000>; + type =3D "critical"; + hysteresis =3D <0>; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu0_target>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu4_thermal: cpu4-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <1000>; + thermal-sensors =3D <&ths1 0>; + sustainable-power =3D <1600>; + + trips { + cpu4_threshold: cpu-trip-0 { + temperature =3D <70000>; + type =3D "passive"; + hysteresis =3D <0>; + }; + cpu4_target: cpu-trip-1 { + temperature =3D <90000>; + type =3D "passive"; + hysteresis =3D <0>; + }; + cpu4_critical: cpu-trip-2 { + temperature =3D <110000>; + type =3D "critical"; + hysteresis =3D <0>; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu4_target>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <1000>; + thermal-sensors =3D <&ths1 2>; + sustainable-power =3D <2400>; + + gpu-trips { + gpu_temp_threshold: gpu-trip-0 { + temperature =3D <60000>; + type =3D "passive"; + hysteresis =3D <0>; + }; + gpu_temp_target: gpu-trip-1 { + temperature =3D <90000>; + type =3D "passive"; + hysteresis =3D <0>; + }; + gpu_temp_critical: gpu-trip-2 { + temperature =3D <110000>; + type =3D "critical"; + hysteresis =3D <0>; + }; + }; + }; + + ddr-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&ths0>; + + trips { + ddr_temp_critical: ddr-trip-0 { + temperature =3D <110000>; + type =3D "critical"; + hysteresis =3D <0>; + }; + }; + }; + }; }; --=20 2.54.0