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Mon, 04 May 2026 09:29:56 -0700 (PDT) From: Neil Armstrong Date: Mon, 04 May 2026 18:29:49 +0200 Subject: [PATCH RFC v2 1/6] arm64: dts: qcom: add PMIC5 Gen3 macros for channel numbers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260504-topic-sm8x50-adc5-gen3-v2-1-5cc04d6ecda0@linaro.org> References: <20260504-topic-sm8x50-adc5-gen3-v2-0-5cc04d6ecda0@linaro.org> In-Reply-To: <20260504-topic-sm8x50-adc5-gen3-v2-0-5cc04d6ecda0@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=18612; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=zQPnmLqFrFXjyZHDa1Pk823AqDYDK0kMLO58Q2tjToQ=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBp+MmAndPDN/Y85TGnzzRV4RFOyjdmaP3OcXzQ0fN+ Cc/sU9iJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCafjJgAAKCRB33NvayMhJ0dGeD/ 4ppT/Hn5iS5ENjnWwGDJA0RRvajyn3dCxOX9SMYedIxzLAupbyB2t5OgZuJTZv1ZKzLCKVEaEUVZYh QTs495uGk6qF7gMchgcz8niDZ/IFWwVzVLTu0goWJ+D/0goyW5//jYdjxgr/irsbKOo4biDhSLgoYd E0Y+WHgwwWaft+zWEru4wT1ymVuecNgFP6oodVHu5CSHnwLnmNFK+s6jhPa0C4zRbBLsBoYmX+KdrQ RabG/h0Fff2+HyC6o8T73yvF7Z/15AncJy4BRpq8YmbQH0ZfgB6Bwpsy4WzQBfRbgZ+d6LA2LUeuvj IwEqeu/0cqQ6c0czkJMFeQqJEgNpnEuIUMpa8k+Un1xV68lAYt+dnqZvuC+yyk2CCB0xEZBrv1zimE FMvKx1gLEP9AMvZzmTEp9ePxI0ViwwPpFKndgZMw3mfs207cZJiuaGr3lwRkZ7aMNzwbv+cXM/c26W p3yLrv7ZO17eh/eeLaUQTnGk7kja1Ja6CXJOhqRof/Cjwoao40oB4jPPNiq5qXIC5k73xzbV4QxLRP JK2xYacF7YAL6YYjBsBS4Rbg18tD5HgBWqrbw5URFd7+WiikeiLnclV+daayBrjjl4oepBWP5OBwNo VQ0n3Lq9zz31rWFwQGvMGKGuit2x6d0NZWegIwcnc+rSUKdiL72wuRNQr2zA== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add the PMIC5 Gen3 macros to calculate the channel numbers which is a combination of SPMI bus number and a constant for the sensor type and configuration. The macros definitions were taken out of [1] where it was initially in the dt-bindings include directory but since those are not hardware bindings but logical numbers, they can be moved to local includes instead to make the DT source more readable. [1] https://lore.kernel.org/all/20250826083657.4005727-4-jishnu.prakash@oss= .qualcomm.com/ Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/qcom,adc5-gen3-channels.h | 88 ++++++++++++++++++= ++++ arch/arm64/boot/dts/qcom/qcom,pm8550-adc5-gen3.h | 46 +++++++++++ arch/arm64/boot/dts/qcom/qcom,pm8550b-adc5-gen3.h | 85 ++++++++++++++++++= +++ arch/arm64/boot/dts/qcom/qcom,pm8550vx-adc5-gen3.h | 22 ++++++ arch/arm64/boot/dts/qcom/qcom,pmk8550-adc5-gen3.h | 52 +++++++++++++ 5 files changed, 293 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcom,adc5-gen3-channels.h b/arch/arm6= 4/boot/dts/qcom/qcom,adc5-gen3-channels.h new file mode 100644 index 000000000000..a8aac9ae6f40 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcom,adc5-gen3-channels.h @@ -0,0 +1,88 @@ + /* SPDX-License-Identifier: GPL-2.0 */ + /* + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserv= ed. + */ + +#ifndef _QCOM_ADC5_GEN3_CHANNELS_H +#define _QCOM_ADC5_GEN3_CHANNELS_H + +/* ADC channels for PMIC5 Gen3 */ + +#define ADC5_GEN3_REF_GND 0x00 +#define ADC5_GEN3_1P25VREF 0x01 +#define ADC5_GEN3_VREF_VADC 0x02 +#define ADC5_GEN3_DIE_TEMP 0x03 + +#define ADC5_GEN3_AMUX1_THM 0x04 +#define ADC5_GEN3_AMUX2_THM 0x05 +#define ADC5_GEN3_AMUX3_THM 0x06 +#define ADC5_GEN3_AMUX4_THM 0x07 +#define ADC5_GEN3_AMUX5_THM 0x08 +#define ADC5_GEN3_AMUX6_THM 0x09 +#define ADC5_GEN3_AMUX1_GPIO 0x0a +#define ADC5_GEN3_AMUX2_GPIO 0x0b +#define ADC5_GEN3_AMUX3_GPIO 0x0c +#define ADC5_GEN3_AMUX4_GPIO 0x0d + +#define ADC5_GEN3_CHG_TEMP 0x10 +#define ADC5_GEN3_USB_SNS_V_16 0x11 +#define ADC5_GEN3_VIN_DIV16_MUX 0x12 +#define ADC5_GEN3_VREF_BAT_THERM 0x15 +#define ADC5_GEN3_IIN_FB 0x17 +#define ADC5_GEN3_TEMP_ALARM_LITE 0x18 +#define ADC5_GEN3_IIN_SMB 0x19 +#define ADC5_GEN3_ICHG_SMB 0x1b +#define ADC5_GEN3_ICHG_FB 0xa1 + +/* 30k pull-up1 */ +#define ADC5_GEN3_AMUX1_THM_30K_PU 0x24 +#define ADC5_GEN3_AMUX2_THM_30K_PU 0x25 +#define ADC5_GEN3_AMUX3_THM_30K_PU 0x26 +#define ADC5_GEN3_AMUX4_THM_30K_PU 0x27 +#define ADC5_GEN3_AMUX5_THM_30K_PU 0x28 +#define ADC5_GEN3_AMUX6_THM_30K_PU 0x29 +#define ADC5_GEN3_AMUX1_GPIO_30K_PU 0x2a +#define ADC5_GEN3_AMUX2_GPIO_30K_PU 0x2b +#define ADC5_GEN3_AMUX3_GPIO_30K_PU 0x2c +#define ADC5_GEN3_AMUX4_GPIO_30K_PU 0x2d + +/* 100k pull-up2 */ +#define ADC5_GEN3_AMUX1_THM_100K_PU 0x44 +#define ADC5_GEN3_AMUX2_THM_100K_PU 0x45 +#define ADC5_GEN3_AMUX3_THM_100K_PU 0x46 +#define ADC5_GEN3_AMUX4_THM_100K_PU 0x47 +#define ADC5_GEN3_AMUX5_THM_100K_PU 0x48 +#define ADC5_GEN3_AMUX6_THM_100K_PU 0x49 +#define ADC5_GEN3_AMUX1_GPIO_100K_PU 0x4a +#define ADC5_GEN3_AMUX2_GPIO_100K_PU 0x4b +#define ADC5_GEN3_AMUX3_GPIO_100K_PU 0x4c +#define ADC5_GEN3_AMUX4_GPIO_100K_PU 0x4d + +/* 400k pull-up3 */ +#define ADC5_GEN3_AMUX1_THM_400K_PU 0x64 +#define ADC5_GEN3_AMUX2_THM_400K_PU 0x65 +#define ADC5_GEN3_AMUX3_THM_400K_PU 0x66 +#define ADC5_GEN3_AMUX4_THM_400K_PU 0x67 +#define ADC5_GEN3_AMUX5_THM_400K_PU 0x68 +#define ADC5_GEN3_AMUX6_THM_400K_PU 0x69 +#define ADC5_GEN3_AMUX1_GPIO_400K_PU 0x6a +#define ADC5_GEN3_AMUX2_GPIO_400K_PU 0x6b +#define ADC5_GEN3_AMUX3_GPIO_400K_PU 0x6c +#define ADC5_GEN3_AMUX4_GPIO_400K_PU 0x6d + +/* 1/3 Divider */ +#define ADC5_GEN3_AMUX1_GPIO_DIV3 0x8a +#define ADC5_GEN3_AMUX2_GPIO_DIV3 0x8b +#define ADC5_GEN3_AMUX3_GPIO_DIV3 0x8c +#define ADC5_GEN3_AMUX4_GPIO_DIV3 0x8d + +#define ADC5_GEN3_VPH_PWR 0x8e +#define ADC5_GEN3_VBAT_SNS_QBG 0x8f + +#define ADC5_GEN3_VBAT_SNS_CHGR 0x94 +#define ADC5_GEN3_VBAT_2S_MID_QBG 0x96 +#define ADC5_GEN3_VBAT_2S_MID_CHGR 0x9d + +#define ADC5_GEN3_OFFSET_EXT2 0xf8 + +#endif /* _QCOM_ADC5_GEN3_CHANNELS_H */ diff --git a/arch/arm64/boot/dts/qcom/qcom,pm8550-adc5-gen3.h b/arch/arm64/= boot/dts/qcom/qcom,pm8550-adc5-gen3.h new file mode 100644 index 000000000000..2a6338812d4e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcom,pm8550-adc5-gen3.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#ifndef _QCOM_PM8550_ACD5_GEN3_H +#define _QCOM_PM8550_ACD5_GEN3_H + +#include "qcom,adc5-gen3-channels.h" + +/* ADC channels for PM8550_ADC for PMIC5 Gen3 */ +#define PM8550_ADC5_GEN3_REF_GND(sid) ((sid) << 8 | ADC5_GEN3_REF_GND) +#define PM8550_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VREF) +#define PM8550_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_VAD= C) +#define PM8550_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEMP) + +#define PM8550_ADC5_GEN3_AMUX_THM1(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_TH= M) +#define PM8550_ADC5_GEN3_AMUX_THM2(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_TH= M) +#define PM8550_ADC5_GEN3_AMUX_THM3(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_TH= M) +#define PM8550_ADC5_GEN3_AMUX_THM4(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_TH= M) +#define PM8550_ADC5_GEN3_AMUX_THM5(sid) ((sid) << 8 | ADC5_GEN3_AMUX5_TH= M) +#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2(sid) ((sid) << 8 | ADC5_GEN3_AMU= X6_THM) +#define PM8550_ADC5_GEN3_AMUX1_GPIO3(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_G= PIO) +#define PM8550_ADC5_GEN3_AMUX2_GPIO4(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_G= PIO) +#define PM8550_ADC5_GEN3_AMUX3_GPIO7(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_G= PIO) +#define PM8550_ADC5_GEN3_AMUX4_GPIO12(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_= GPIO) + +/* 100k pull-up */ +#define PM8550_ADC5_GEN3_AMUX_THM1_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_A= MUX1_THM_100K_PU) +#define PM8550_ADC5_GEN3_AMUX_THM2_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_A= MUX2_THM_100K_PU) +#define PM8550_ADC5_GEN3_AMUX_THM3_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_A= MUX3_THM_100K_PU) +#define PM8550_ADC5_GEN3_AMUX_THM4_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_A= MUX4_THM_100K_PU) +#define PM8550_ADC5_GEN3_AMUX_THM5_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_A= MUX5_THM_100K_PU) +#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2_100K_PU(sid) ((sid) << 8 | ADC5_G= EN3_AMUX6_THM_100K_PU) +#define PM8550_ADC5_GEN3_AMUX1_GPIO3_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_= AMUX1_GPIO_100K_PU) +#define PM8550_ADC5_GEN3_AMUX2_GPIO4_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_= AMUX2_GPIO_100K_PU) +#define PM8550_ADC5_GEN3_AMUX3_GPIO7_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_= AMUX3_GPIO_100K_PU) +#define PM8550_ADC5_GEN3_AMUX4_GPIO12_100K_PU(sid) ((sid) << 8 | ADC5_GEN3= _AMUX4_GPIO_100K_PU) + +/* 1/3 Divider */ +#define PM8550_ADC5_GEN3_AMUX3_GPIO7_DIV3(sid) ((sid) << 8 | ADC5_GEN3_AM= UX3_GPIO_DIV3) +#define PM8550_ADC5_GEN3_AMUX4_GPIO12_DIV3(sid) ((sid) << 8 | ADC5_GEN3_A= MUX4_GPIO_DIV3) + +#define PM8550_ADC5_GEN3_VPH_PWR(sid) ((sid) << 8 | ADC5_GEN3_VPH_PWR) + +#endif /* _QCOM_PM8550_ACD5_GEN3_H */ diff --git a/arch/arm64/boot/dts/qcom/qcom,pm8550b-adc5-gen3.h b/arch/arm64= /boot/dts/qcom/qcom,pm8550b-adc5-gen3.h new file mode 100644 index 000000000000..312daa846f79 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcom,pm8550b-adc5-gen3.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#ifndef _QCOM_PM8550B_ACD5_GEN3_H +#define _QCOM_PM8550B_ACD5_GEN3_H + +#include "qcom,adc5-gen3-channels.h" + +/* ADC channels for PM8550B_ADC for PMIC5 Gen3 */ +#define PM8550B_ADC5_GEN3_REF_GND(sid) ((sid) << 8 | ADC5_GEN3_REF_GND) +#define PM8550B_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VREF) +#define PM8550B_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_VAD= C) +#define PM8550B_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEMP) + +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM(sid) ((sid) << 8 | ADC5_GEN= 3_AMUX1_THM) +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID(sid) ((sid) << 8 | ADC5_GEN3_A= MUX2_THM) +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V(sid) ((sid) << 8 | ADC5_GEN= 3_AMUX3_THM) +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM(sid) ((sid) << 8 | ADC5_GEN3= _AMUX4_THM) +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION(sid) ((sid) << 8 | ADC5_GEN3_A= MUX5_THM) +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10(sid) ((sid) << 8 | ADC5_GEN3_A= MUX6_THM) +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_= GPIO) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_= GPIO) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_= GPIO) +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12(sid) ((sid) << 8 | ADC5_GEN3_AMUX4= _GPIO) + +#define PM8550B_ADC5_GEN3_CHG_TEMP(sid) ((sid) << 8 | ADC5_GEN3_CHG_TEMP) +#define PM8550B_ADC5_GEN3_USB_SNS_V_16(sid) ((sid) << 8 | ADC5_GEN3_USB_S= NS_V_16) +#define PM8550B_ADC5_GEN3_VIN_DIV16_MUX(sid) ((sid) << 8 | ADC5_GEN3_VIN_= DIV16_MUX) +#define PM8550B_ADC5_GEN3_VREF_BAT_THERM(sid) ((sid) << 8 | ADC5_GEN3_VRE= F_BAT_THERM) +#define PM8550B_ADC5_GEN3_IIN_FB(sid) ((sid) << 8 | ADC5_GEN3_IIN_FB) +#define PM8550B_ADC5_GEN3_TEMP_ALARM_LITE(sid) ((sid) << 8 | ADC5_GEN3_TE= MP_ALARM_LITE) +#define PM8550B_ADC5_GEN3_SMB_IIN(sid) ((sid) << 8 | ADC5_GEN3_IIN_SMB) +#define PM8550B_ADC5_GEN3_SMB_ICHG(sid) ((sid) << 8 | ADC5_GEN3_ICHG_SMB) +#define PM8550B_ADC5_GEN3_ICHG_FB(sid) ((sid) << 8 | ADC5_GEN3_ICHG_FB) + +/* 30k pull-up */ +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_30K_PU(sid) ((sid) << 8 | A= DC5_GEN3_AMUX1_THM_30K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_30K_PU(sid) ((sid) << 8 | ADC= 5_GEN3_AMUX2_THM_30K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_30K_PU(sid) ((sid) << 8 | A= DC5_GEN3_AMUX3_THM_30K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_30K_PU(sid) ((sid) << 8 | AD= C5_GEN3_AMUX4_THM_30K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_30K_PU(sid) ((sid) << 8 | ADC5= _GEN3_AMUX5_THM_30K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_30K_PU(sid) ((sid) << 8 | ADC5= _GEN3_AMUX6_THM_30K_PU) +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_30K_PU(sid) ((sid) << 8 | ADC5_GEN3= _AMUX1_GPIO_30K_PU) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_30K_PU(sid) ((sid) << 8 | ADC5_GEN3= _AMUX2_GPIO_30K_PU) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_30K_PU(sid) ((sid) << 8 | ADC5_GEN3= _AMUX3_GPIO_30K_PU) +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_30K_PU(sid) ((sid) << 8 | ADC5_GEN= 3_AMUX4_GPIO_30K_PU) + +/* 100k pull-up */ +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU(sid) ((sid) << 8 | = ADC5_GEN3_AMUX1_THM_100K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_100K_PU(sid) ((sid) << 8 | ADC= 5_GEN3_AMUX2_THM_100K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_100K_PU(sid) ((sid) << 8 | = ADC5_GEN3_AMUX3_THM_100K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU(sid) ((sid) << 8 | A= DC5_GEN3_AMUX4_THM_100K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_100K_PU(sid) ((sid) << 8 | ADC= 5_GEN3_AMUX5_THM_100K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_100K_PU(sid) ((sid) << 8 | ADC= 5_GEN3_AMUX6_THM_100K_PU) +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_100K_PU(sid) ((sid) << 8 | ADC5_GEN= 3_AMUX1_GPIO_100K_PU) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_100K_PU(sid) ((sid) << 8 | ADC5_GEN= 3_AMUX2_GPIO_100K_PU) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_100K_PU(sid) ((sid) << 8 | ADC5_GEN= 3_AMUX3_GPIO_100K_PU) +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_100K_PU(sid) ((sid) << 8 | ADC5_GE= N3_AMUX4_GPIO_100K_PU) + +/* 400k pull-up */ +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_400K_PU(sid) ((sid) << 8 | = ADC5_GEN3_AMUX1_THM_400K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_400K_PU(sid) ((sid) << 8 | ADC= 5_GEN3_AMUX2_THM_400K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_400K_PU(sid) ((sid) << 8 | = ADC5_GEN3_AMUX3_THM_400K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_400K_PU(sid) ((sid) << 8 | A= DC5_GEN3_AMUX4_THM_400K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_400K_PU(sid) ((sid) << 8 | ADC= 5_GEN3_AMUX5_THM_400K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_400K_PU(sid) ((sid) << 8 | ADC= 5_GEN3_AMUX6_THM_400K_PU) +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_400K_PU(sid) ((sid) << 8 | ADC5_GEN= 3_AMUX1_GPIO_400K_PU) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_400K_PU(sid) ((sid) << 8 | ADC5_GEN= 3_AMUX2_GPIO_400K_PU) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_400K_PU(sid) ((sid) << 8 | ADC5_GEN= 3_AMUX3_GPIO_400K_PU) +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_400K_PU(sid) ((sid) << 8 | ADC5_GE= N3_AMUX4_GPIO_400K_PU) + +/* 1/3 Divider */ +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_DIV3(sid) ((sid) << 8 | ADC5_GEN3_A= MUX1_GPIO_DIV3) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_DIV3(sid) ((sid) << 8 | ADC5_GEN3_A= MUX2_GPIO_DIV3) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_DIV3(sid) ((sid) << 8 | ADC5_GEN3_A= MUX3_GPIO_DIV3) + +#define PM8550B_ADC5_GEN3_VPH_PWR(sid) ((sid) << 8 | ADC5_GEN3_VPH_PWR) +#define PM8550B_ADC5_GEN3_VBAT_SNS_QBG(sid) ((sid) << 8 | ADC5_GEN3_VBAT_= SNS_QBG) +#define PM8550B_ADC5_GEN3_VBAT_SNS_CHGR(sid) ((sid) << 8 | ADC5_GEN3_VBAT= _SNS_CHGR) +#define PM8550B_ADC5_GEN3_VBAT_2S_MID_QBG(sid) ((sid) << 8 | ADC5_GEN3_VB= AT_2S_MID_QBG) +#define PM8550B_ADC5_GEN3_VBAT_2S_MID_CHGR(sid) ((sid) << 8 | ADC5_GEN3_V= BAT_2S_MID_CHGR) + +#endif /* _QCOM_PM8550B_ACD5_GEN3_H */ diff --git a/arch/arm64/boot/dts/qcom/qcom,pm8550vx-adc5-gen3.h b/arch/arm6= 4/boot/dts/qcom/qcom,pm8550vx-adc5-gen3.h new file mode 100644 index 000000000000..7a261a7a9cb0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcom,pm8550vx-adc5-gen3.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#ifndef _QCOM_PM8550VX_ACD5_GEN3_H +#define _QCOM_PM8550VX_ACD5_GEN3_H + +#include "qcom,adc5-gen3-channels.h" + +/* ADC channels for PM8550VX_ADC for PMIC5 Gen3 */ +#define PM8550VS_ADC5_GEN3_REF_GND(sid) ((sid) << 8 | ADC5_GEN3_REF_GND) +#define PM8550VS_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VRE= F) +#define PM8550VS_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_V= ADC) +#define PM8550VS_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEM= P) + +#define PM8550VE_ADC5_GEN3_OFFSET_REF(sid) ((sid) << 8 | ADC5_GEN3_REF_G= ND) +#define PM8550VE_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VRE= F) +#define PM8550VE_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_V= ADC) +#define PM8550VE_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEMP) + +#endif /* _QCOM_PM8550VX_ACD5_GEN3_H */ diff --git a/arch/arm64/boot/dts/qcom/qcom,pmk8550-adc5-gen3.h b/arch/arm64= /boot/dts/qcom/qcom,pmk8550-adc5-gen3.h new file mode 100644 index 000000000000..60b3b9c60d4e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcom,pmk8550-adc5-gen3.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#ifndef _QCOM_PMK8550_ACD5_GEN3_H +#define _QCOM_PMK8550_ACD5_GEN3_H + +#include "qcom,adc5-gen3-channels.h" + +/* ADC channels for PMK8550_ADC for PMIC5 Gen3 */ +#define PMK8550_ADC5_GEN3_REF_GND(sid) ((sid) << 8 | ADC5_GEN3_REF_GND) +#define PMK8550_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VREF) +#define PMK8550_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_VAD= C) +#define PMK8550_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEMP) + +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM(sid) ((sid) << 8 | ADC5_GEN3_= AMUX1_THM) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1(sid) ((sid) << 8 | ADC5_GEN3_AM= UX2_THM) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2(sid) ((sid) << 8 | ADC5_GEN3_AM= UX3_THM) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3(sid) ((sid) << 8 | ADC5_GEN3_AM= UX4_THM) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4(sid) ((sid) << 8 | ADC5_GEN3_AM= UX5_THM) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5(sid) ((sid) << 8 | ADC5_GEN3_AM= UX6_THM) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_= GPIO) + +/* 30k pull-up */ +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_30K_PU(sid) ((sid) << 8 | ADC= 5_GEN3_AMUX1_THM_30K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_30K_PU(sid) ((sid) << 8 | ADC5_= GEN3_AMUX2_THM_30K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_30K_PU(sid) ((sid) << 8 | ADC5_= GEN3_AMUX3_THM_30K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_30K_PU(sid) ((sid) << 8 | ADC5_= GEN3_AMUX4_THM_30K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_30K_PU(sid) ((sid) << 8 | ADC5_= GEN3_AMUX5_THM_30K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_30K_PU(sid) ((sid) << 8 | ADC5_= GEN3_AMUX6_THM_30K_PU) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_30K_PU(sid) ((sid) << 8 | ADC5_GEN3= _AMUX1_GPIO_30K_PU) + +/* 100k pull-up */ +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU(sid) ((sid) << 8 | AD= C5_GEN3_AMUX1_THM_100K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_100K_PU(sid) ((sid) << 8 | ADC5= _GEN3_AMUX2_THM_100K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_100K_PU(sid) ((sid) << 8 | ADC5= _GEN3_AMUX3_THM_100K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_100K_PU(sid) ((sid) << 8 | ADC5= _GEN3_AMUX4_THM_100K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_100K_PU(sid) ((sid) << 8 | ADC5= _GEN3_AMUX5_THM_100K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_100K_PU(sid) ((sid) << 8 | ADC5= _GEN3_AMUX6_THM_100K_PU) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_100K_PU(sid) ((sid) << 8 | ADC5_GEN= 3_AMUX1_GPIO_100K_PU) + +/* 400k pull-up */ +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_400K_PU(sid) ((sid) << 8 | AD= C5_GEN3_AMUX1_THM_400K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_400K_PU(sid) ((sid) << 8 | ADC5= _GEN3_AMUX2_THM_400K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_400K_PU(sid) ((sid) << 8 | ADC5= _GEN3_AMUX3_THM_400K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_400K_PU(sid) ((sid) << 8 | ADC5= _GEN3_AMUX4_THM_400K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_400K_PU(sid) ((sid) << 8 | ADC5= _GEN3_AMUX5_THM_400K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_400K_PU(sid) ((sid) << 8 | ADC5= _GEN3_AMUX6_THM_400K_PU) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_400K_PU(sid) ((sid) << 8 | ADC5_GEN= 3_AMUX1_GPIO_400K_PU) + +#endif /* _QCOM_PMK8550_ACD5_GEN3_H */ --=20 2.34.1 From nobody Sun Jun 14 01:38:45 2026 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E9213E3C48 for ; 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Mon, 04 May 2026 09:29:57 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:106d:1080:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48a82301b7bsm405071055e9.11.2026.05.04.09.29.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 May 2026 09:29:57 -0700 (PDT) From: Neil Armstrong Date: Mon, 04 May 2026 18:29:50 +0200 Subject: [PATCH RFC v2 2/6] arm64: dts: qcom: pmk8550: add VADC node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260504-topic-sm8x50-adc5-gen3-v2-2-5cc04d6ecda0@linaro.org> References: <20260504-topic-sm8x50-adc5-gen3-v2-0-5cc04d6ecda0@linaro.org> In-Reply-To: <20260504-topic-sm8x50-adc5-gen3-v2-0-5cc04d6ecda0@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add the VADC node and the initial pmk8550 adc channels. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/pmk8550.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmk8550.dtsi b/arch/arm64/boot/dts/qc= om/pmk8550.dtsi index 3049eb6b46d7..515cae060f27 100644 --- a/arch/arm64/boot/dts/qcom/pmk8550.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8550.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include "qcom,pmk8550-adc5-gen3.h" =20 / { reboot-mode { @@ -44,6 +45,35 @@ pon_resin: resin { }; }; =20 + pmk8550_vadc: adc@9000 { + compatible =3D "qcom,spmi-adc5-gen3"; + reg =3D <0x9000>, <0x9100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>; + #io-channel-cells =3D <1>; + #thermal-sensor-cells =3D <1>; + + channel@0 { + reg =3D ; + label =3D "pmk8550_offset_ref"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@1 { + reg =3D ; + label =3D "pmk8550_vref_1p25"; + qcom,pre-scaling =3D <1 1>; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add the SPMI ADC channels on the PMK8550 SPMI5 ADC3 for the other PMICS on the system. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 279 ++++++++++++++++++++++++++++= ++++ 1 file changed, 279 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/= qcom/sm8550-qrd.dts index 2fb2e0be5e4c..8405cb9e0d6d 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -17,6 +17,9 @@ #include "pmk8550.dtsi" #include "pmr735d_a.dtsi" #include "pmr735d_b.dtsi" +#include "qcom,pm8550-adc5-gen3.h" +#include "qcom,pm8550b-adc5-gen3.h" +#include "qcom,pm8550vx-adc5-gen3.h" =20 / { model =3D "Qualcomm Technologies, Inc. SM8550 QRD"; @@ -205,6 +208,92 @@ platform { }; }; =20 + thermal-zones { + skin-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM1_100K_PU(1= )>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + + cam-flash-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM2_100K_PU(1= )>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + + wlan-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM3_100K_PU(1= )>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + + pa-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM4_100K_PU(1= )>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + + rear-tof-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM5_100K_PU(1= )>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + + usb-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550B_ADC5_GEN3_AMUX_THM4_USB_THER= M_100K_PU(7)>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + + wls-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_1= 00K_PU(7)>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible =3D "regulator-fixed"; regulator-name =3D "vph_pwr"; @@ -997,27 +1086,217 @@ led@3 { }; }; =20 +&pm8550_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550_ADC5_GEN3_DIE_TEMP(1)>; + io-channel-names =3D "thermal"; +}; + &pm8550b_eusb2_repeater { vdd18-supply =3D <&vreg_l15b_1p8>; vdd3-supply =3D <&vreg_l5b_3p1>; }; =20 +&pm8550b_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550B_ADC5_GEN3_DIE_TEMP(7)>; + io-channel-names =3D "thermal"; +}; + &pm8550vs_c { status =3D "okay"; }; =20 +&pm8550vs_c_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550VS_ADC5_GEN3_DIE_TEMP(2)>; + io-channel-names =3D "thermal"; +}; + &pm8550vs_d { status =3D "okay"; }; =20 +&pm8550vs_d_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550VS_ADC5_GEN3_DIE_TEMP(3)>; + io-channel-names =3D "thermal"; +}; + &pm8550vs_e { status =3D "okay"; }; =20 +&pm8550vs_e_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550VS_ADC5_GEN3_DIE_TEMP(4)>; + io-channel-names =3D "thermal"; +}; + &pm8550vs_g { status =3D "okay"; }; =20 +&pm8550vs_g_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550VS_ADC5_GEN3_DIE_TEMP(6)>; + io-channel-names =3D "thermal"; +}; + +&pm8550ve_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550VE_ADC5_GEN3_DIE_TEMP(PMK8550VE_SID)= >; + io-channel-names =3D "thermal"; +}; + +&pmk8550_vadc { + /* PM8550 Channel nodes */ + channel@100 { + reg =3D ; + label =3D "pm8550_offset_ref"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@101 { + reg =3D ; + label =3D "pm8550_vref_1p25"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@103 { + reg =3D ; + label =3D "pm8550_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@18e { + reg =3D ; + label =3D "pm8550_vph_pwr"; + qcom,pre-scaling =3D <1 3>; + }; + + channel@144 { + reg =3D ; + label =3D "pm8550_msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + qcom,adc-tm; + }; + + channel@145 { + reg =3D ; + label =3D "pm8550_cam_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + qcom,adc-tm; + }; + + channel@146 { + reg =3D ; + label =3D "pm8550_wlan_therm"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + qcom,adc-tm; + }; + + channel@147 { + reg =3D ; + label =3D "pm8550_pa_therm_1"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + qcom,adc-tm; + }; + + channel@148 { + reg =3D ; + label =3D "pm8550_rear_tof_therm"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + qcom,adc-tm; + }; + + /* PM8550VS_C Channel nodes */ + channel@203 { + reg =3D ; + label =3D "pm8550vs_c_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + /* PM8550VS_D Channel nodes */ + channel@303 { + reg =3D ; + label =3D "pm8550vs_d_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + /* PM8550VS_E Channel nodes */ + channel@403 { + reg =3D ; + label =3D "pm8550vs_e_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + /* PM8550VE Channel nodes */ + channel@503 { + reg =3D ; + label =3D "pm8550ve_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + /* PM8550VS_G Channel nodes */ + channel@603 { + reg =3D ; + label =3D "pm8550vs_g_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + /* PM8550B Channel nodes */ + channel@700 { + reg =3D ; + label =3D "pm8550b_offset_ref"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@701 { + reg =3D ; + label =3D "pm8550b_vref_1p25"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@703 { + reg =3D ; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add the SPMI ADC channels on the PMK8550 SPMI5 ADC3 for the other PMICS on the system. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 279 ++++++++++++++++++++++++++++= ++++ 1 file changed, 279 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/= qcom/sm8550-hdk.dts index ee13e6136a82..83cf48a623fc 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -16,6 +16,9 @@ #include "pm8550vs.dtsi" #include "pmk8550.dtsi" #include "pmr735d_a.dtsi" +#include "qcom,pm8550-adc5-gen3.h" +#include "qcom,pm8550b-adc5-gen3.h" +#include "qcom,pm8550vx-adc5-gen3.h" =20 / { model =3D "Qualcomm Technologies, Inc. SM8550 HDK"; @@ -280,6 +283,92 @@ platform { }; }; =20 + thermal-zones { + skin-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM1_100K_PU(1= )>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + + cam-flash-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM2_100K_PU(1= )>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + + wlan-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM3_100K_PU(1= )>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + + pa-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM4_100K_PU(1= )>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + + rear-tof-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM5_100K_PU(1= )>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + + usb-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550B_ADC5_GEN3_AMUX_THM4_USB_THER= M_100K_PU(7)>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + + wls-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_1= 00K_PU(7)>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + }; + wcn7850-pmu { compatible =3D "qcom,wcn7850-pmu"; =20 @@ -1102,27 +1191,217 @@ led@3 { }; }; =20 +&pm8550_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550_ADC5_GEN3_DIE_TEMP(1)>; + io-channel-names =3D "thermal"; +}; + &pm8550b_eusb2_repeater { vdd18-supply =3D <&vreg_l15b_1p8>; vdd3-supply =3D <&vreg_l5b_3p1>; }; =20 +&pm8550b_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550B_ADC5_GEN3_DIE_TEMP(7)>; + io-channel-names =3D "thermal"; +}; + &pm8550vs_c { status =3D "okay"; }; =20 +&pm8550vs_c_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550VS_ADC5_GEN3_DIE_TEMP(2)>; + io-channel-names =3D "thermal"; +}; + &pm8550vs_d { status =3D "okay"; }; =20 +&pm8550vs_d_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550VS_ADC5_GEN3_DIE_TEMP(3)>; + io-channel-names =3D "thermal"; +}; + &pm8550vs_e { status =3D "okay"; }; =20 +&pm8550vs_e_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550VS_ADC5_GEN3_DIE_TEMP(4)>; + io-channel-names =3D "thermal"; +}; + &pm8550vs_g { status =3D "okay"; }; =20 +&pm8550vs_g_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550VS_ADC5_GEN3_DIE_TEMP(6)>; + io-channel-names =3D "thermal"; +}; + +&pm8550ve_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550VE_ADC5_GEN3_DIE_TEMP(PMK8550VE_SID)= >; + io-channel-names =3D "thermal"; +}; + +&pmk8550_vadc { + /* PM8550 Channel nodes */ + channel@100 { + reg =3D ; + label =3D "pm8550_offset_ref"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@101 { + reg =3D ; + label =3D "pm8550_vref_1p25"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@103 { + reg =3D ; + label =3D "pm8550_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@18e { + reg =3D ; + label =3D "pm8550_vph_pwr"; + qcom,pre-scaling =3D <1 3>; + }; + + channel@144 { + reg =3D ; + label =3D "pm8550_msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + qcom,adc-tm; + }; + + channel@145 { + reg =3D ; + label =3D "pm8550_cam_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + qcom,adc-tm; + }; + + channel@146 { + reg =3D ; + label =3D "pm8550_wlan_therm"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + qcom,adc-tm; + }; + + channel@147 { + reg =3D ; + label =3D "pm8550_pa_therm_1"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + qcom,adc-tm; + }; + + channel@148 { + reg =3D ; + label =3D "pm8550_rear_tof_therm"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + qcom,adc-tm; + }; + + /* PM8550VS_C Channel nodes */ + channel@203 { + reg =3D ; + label =3D "pm8550vs_c_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + /* PM8550VS_D Channel nodes */ + channel@303 { + reg =3D ; + label =3D "pm8550vs_d_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + /* PM8550VS_E Channel nodes */ + channel@403 { + reg =3D ; + label =3D "pm8550vs_e_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + /* PM8550VE Channel nodes */ + channel@503 { + reg =3D ; + label =3D "pm8550ve_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + /* PM8550VS_G Channel nodes */ + channel@603 { + reg =3D ; + label =3D "pm8550vs_g_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + /* PM8550B Channel nodes */ + channel@700 { + reg =3D ; + label =3D "pm8550b_offset_ref"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@701 { + reg =3D ; + label =3D "pm8550b_vref_1p25"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@703 { + reg =3D ; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add the SPMI ADC channels on the PMK8550 SPMI5 ADC3 for the other PMICS on the system. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 279 ++++++++++++++++++++++++++++= ++++ 1 file changed, 279 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/= qcom/sm8650-qrd.dts index a3982ae22929..0f5f9e55586a 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -16,6 +16,9 @@ #include "pm8550vs.dtsi" #include "pmk8550.dtsi" #include "pmr735d_a.dtsi" +#include "qcom,pm8550-adc5-gen3.h" +#include "qcom,pm8550b-adc5-gen3.h" +#include "qcom,pm8550vx-adc5-gen3.h" =20 / { model =3D "Qualcomm Technologies, Inc. SM8650 QRD"; @@ -158,6 +161,92 @@ platform { }; }; =20 + thermal-zones { + skin-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM1_100K_PU(1= )>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + + cam-flash-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM2_100K_PU(1= )>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + + wlan-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM3_100K_PU(1= )>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + + pa-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM4_100K_PU(1= )>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + + rear-tof-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM5_100K_PU(1= )>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + + usb-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550B_ADC5_GEN3_AMUX_THM4_USB_THER= M_100K_PU(7)>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + + wls-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_1= 00K_PU(7)>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible =3D "regulator-fixed"; =20 @@ -1040,27 +1129,217 @@ led@3 { }; }; =20 +&pm8550_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550_ADC5_GEN3_DIE_TEMP(1)>; + io-channel-names =3D "thermal"; +}; + &pm8550b_eusb2_repeater { vdd18-supply =3D <&vreg_l15b_1p8>; vdd3-supply =3D <&vreg_l5b_3p1>; }; =20 +&pm8550b_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550B_ADC5_GEN3_DIE_TEMP(7)>; + io-channel-names =3D "thermal"; +}; + &pm8550vs_c { status =3D "okay"; }; =20 +&pm8550vs_c_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550VS_ADC5_GEN3_DIE_TEMP(2)>; + io-channel-names =3D "thermal"; +}; + &pm8550vs_d { status =3D "okay"; }; =20 +&pm8550vs_d_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550VS_ADC5_GEN3_DIE_TEMP(3)>; + io-channel-names =3D "thermal"; +}; + &pm8550vs_e { status =3D "okay"; }; =20 +&pm8550vs_e_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550VS_ADC5_GEN3_DIE_TEMP(4)>; + io-channel-names =3D "thermal"; +}; + &pm8550vs_g { status =3D "okay"; }; =20 +&pm8550vs_g_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550VS_ADC5_GEN3_DIE_TEMP(6)>; + io-channel-names =3D "thermal"; +}; + +&pm8550ve_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550VE_ADC5_GEN3_DIE_TEMP(PMK8550VE_SID)= >; + io-channel-names =3D "thermal"; +}; + +&pmk8550_vadc { + /* PM8550 Channel nodes */ + channel@100 { + reg =3D ; + label =3D "pm8550_offset_ref"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@101 { + reg =3D ; + label =3D "pm8550_vref_1p25"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@103 { + reg =3D ; + label =3D "pm8550_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@18e { + reg =3D ; + label =3D "pm8550_vph_pwr"; + qcom,pre-scaling =3D <1 3>; + }; + + channel@144 { + reg =3D ; + label =3D "pm8550_msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + qcom,adc-tm; + }; + + channel@145 { + reg =3D ; + label =3D "pm8550_cam_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + qcom,adc-tm; + }; + + channel@146 { + reg =3D ; + label =3D "pm8550_wlan_therm"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + qcom,adc-tm; + }; + + channel@147 { + reg =3D ; + label =3D "pm8550_pa_therm_1"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + qcom,adc-tm; + }; + + channel@148 { + reg =3D ; + label =3D "pm8550_rear_tof_therm"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + qcom,adc-tm; + }; + + /* PM8550VS_C Channel nodes */ + channel@203 { + reg =3D ; + label =3D "pm8550vs_c_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + /* PM8550VS_D Channel nodes */ + channel@303 { + reg =3D ; + label =3D "pm8550vs_d_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + /* PM8550VS_E Channel nodes */ + channel@403 { + reg =3D ; + label =3D "pm8550vs_e_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + /* PM8550VE Channel nodes */ + channel@503 { + reg =3D ; + label =3D "pm8550ve_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + /* PM8550VS_G Channel nodes */ + channel@603 { + reg =3D ; + label =3D "pm8550vs_g_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + /* PM8550B Channel nodes */ + channel@700 { + reg =3D ; + label =3D "pm8550b_offset_ref"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@701 { + reg =3D ; + label =3D "pm8550b_vref_1p25"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@703 { + reg =3D ; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add the SPMI ADC channels on the PMK8550 SPMI5 ADC3 for the other PMICS on the system. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 279 ++++++++++++++++++++++++++++= ++++ 1 file changed, 279 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/= qcom/sm8650-hdk.dts index eabc828c05b4..cc2d341760a9 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -15,6 +15,9 @@ #include "pm8550ve.dtsi" #include "pm8550vs.dtsi" #include "pmk8550.dtsi" +#include "qcom,pm8550-adc5-gen3.h" +#include "qcom,pm8550b-adc5-gen3.h" +#include "qcom,pm8550vx-adc5-gen3.h" =20 / { model =3D "Qualcomm Technologies, Inc. SM8650 HDK"; @@ -220,6 +223,92 @@ platform { }; }; =20 + thermal-zones { + skin-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM1_100K_PU(1= )>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + + cam-flash-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM2_100K_PU(1= )>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + + wlan-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM3_100K_PU(1= )>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + + pa-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM4_100K_PU(1= )>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + + rear-tof-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM5_100K_PU(1= )>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + + usb-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550B_ADC5_GEN3_AMUX_THM4_USB_THER= M_100K_PU(7)>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + + wls-thermal { + thermal-sensors =3D <&pmk8550_vadc PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_1= 00K_PU(7)>; + + trips { + active-config0 { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + }; + vph_pwr: regulator-vph-pwr { compatible =3D "regulator-fixed"; =20 @@ -1041,27 +1130,217 @@ led@3 { }; }; =20 +&pm8550_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550_ADC5_GEN3_DIE_TEMP(1)>; + io-channel-names =3D "thermal"; +}; + &pm8550b_eusb2_repeater { vdd18-supply =3D <&vreg_l15b_1p8>; vdd3-supply =3D <&vreg_l5b_3p1>; }; =20 +&pm8550b_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550B_ADC5_GEN3_DIE_TEMP(7)>; + io-channel-names =3D "thermal"; +}; + &pm8550vs_c { status =3D "okay"; }; =20 +&pm8550vs_c_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550VS_ADC5_GEN3_DIE_TEMP(2)>; + io-channel-names =3D "thermal"; +}; + &pm8550vs_d { status =3D "okay"; }; =20 +&pm8550vs_d_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550VS_ADC5_GEN3_DIE_TEMP(3)>; + io-channel-names =3D "thermal"; +}; + &pm8550vs_e { status =3D "okay"; }; =20 +&pm8550vs_e_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550VS_ADC5_GEN3_DIE_TEMP(4)>; + io-channel-names =3D "thermal"; +}; + &pm8550vs_g { status =3D "okay"; }; =20 +&pm8550vs_g_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550VS_ADC5_GEN3_DIE_TEMP(6)>; + io-channel-names =3D "thermal"; +}; + +&pm8550ve_temp_alarm { + io-channels =3D <&pmk8550_vadc PM8550VE_ADC5_GEN3_DIE_TEMP(PMK8550VE_SID)= >; + io-channel-names =3D "thermal"; +}; + +&pmk8550_vadc { + /* PM8550 Channel nodes */ + channel@100 { + reg =3D ; + label =3D "pm8550_offset_ref"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@101 { + reg =3D ; + label =3D "pm8550_vref_1p25"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@103 { + reg =3D ; + label =3D "pm8550_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@18e { + reg =3D ; + label =3D "pm8550_vph_pwr"; + qcom,pre-scaling =3D <1 3>; + }; + + channel@144 { + reg =3D ; + label =3D "pm8550_msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + qcom,adc-tm; + }; + + channel@145 { + reg =3D ; + label =3D "pm8550_cam_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + qcom,adc-tm; + }; + + channel@146 { + reg =3D ; + label =3D "pm8550_wlan_therm"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + qcom,adc-tm; + }; + + channel@147 { + reg =3D ; + label =3D "pm8550_pa_therm_1"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + qcom,adc-tm; + }; + + channel@148 { + reg =3D ; + label =3D "pm8550_rear_tof_therm"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + qcom,adc-tm; + }; + + /* PM8550VS_C Channel nodes */ + channel@203 { + reg =3D ; + label =3D "pm8550vs_c_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + /* PM8550VS_D Channel nodes */ + channel@303 { + reg =3D ; + label =3D "pm8550vs_d_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + /* PM8550VS_E Channel nodes */ + channel@403 { + reg =3D ; + label =3D "pm8550vs_e_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + /* PM8550VE Channel nodes */ + channel@503 { + reg =3D ; + label =3D "pm8550ve_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + /* PM8550VS_G Channel nodes */ + channel@603 { + reg =3D ; + label =3D "pm8550vs_g_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + /* PM8550B Channel nodes */ + channel@700 { + reg =3D ; + label =3D "pm8550b_offset_ref"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@701 { + reg =3D ; + label =3D "pm8550b_vref_1p25"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@703 { + reg =3D ; + label =3D "pm8550b_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@78e { + reg =3D ; + label =3D "pm8550b_vph_pwr"; + qcom,pre-scaling =3D <1 3>; + }; + + channel@78f { + reg =3D ; + label =3D "pm8550b_vbat_sns_qbg"; + qcom,pre-scaling =3D <1 6>; + }; + + channel@747 { + reg =3D ; + label =3D "pm8550b_usb_therm"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + qcom,adc-tm; + }; + + channel@749 { + reg =3D ; + label =3D "pm8550b_wls_therm"; + qcom,ratiometric; + qcom,pre-scaling =3D <1 1>; + qcom,adc-tm; + }; +}; + &pon_pwrkey { status =3D "okay"; }; --=20 2.34.1