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Fri, 01 May 2026 13:07:52 -0700 (PDT) From: Wadim Mueller To: wbg@kernel.org Cc: conor+dt@kernel.org, krzk+dt@kernel.org, robh@kernel.org, conor.dooley@microchip.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/3] dt-bindings: counter: add gpio-quadrature-encoder binding Date: Fri, 1 May 2026 22:07:47 +0200 Message-ID: <20260501200749.20029-2-wafgo01@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260501200749.20029-1-wafgo01@gmail.com> References: <20260501200749.20029-1-wafgo01@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add devicetree binding documentation for the GPIO-based quadrature encoder counter driver. The driver reads A/B quadrature signals and an optional index pulse via edge-triggered GPIO interrupts, supporting X1, X2, X4 quadrature decoding and pulse-direction mode. This is useful on SoCs that lack a dedicated hardware quadrature decoder or where the encoder is wired to generic GPIO pins. Signed-off-by: Wadim Mueller Acked-by: Conor Dooley --- .../counter/gpio-quadrature-encoder.yaml | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/counter/gpio-quadratu= re-encoder.yaml diff --git a/Documentation/devicetree/bindings/counter/gpio-quadrature-enco= der.yaml b/Documentation/devicetree/bindings/counter/gpio-quadrature-encode= r.yaml new file mode 100644 index 000000000..741396b29 --- /dev/null +++ b/Documentation/devicetree/bindings/counter/gpio-quadrature-encoder.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/counter/gpio-quadrature-encoder.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GPIO-based Quadrature Encoder + +maintainers: + - Wadim Mueller + +description: | + A generic GPIO-based quadrature encoder counter. Reads A/B quadrature + signals and an optional index pulse via edge-triggered GPIO interrupts. + Supports X1, X2, X4 quadrature decoding and pulse-direction mode. + + This is useful on SoCs that lack a dedicated hardware quadrature + decoder (eQEP, QEI, etc.) or where the encoder is wired to generic + GPIO pins rather than to a dedicated peripheral. + +properties: + compatible: + const: gpio-quadrature-encoder + + encoder-a-gpios: + maxItems: 1 + description: + GPIO connected to the encoder's A (phase A) output. + + encoder-b-gpios: + maxItems: 1 + description: + GPIO connected to the encoder's B (phase B) output. + + encoder-index-gpios: + maxItems: 1 + description: + Optional GPIO connected to the encoder's index (Z) output. + The index signal pulses once per revolution and can be used + as a reference point for absolute position tracking. + +required: + - compatible + - encoder-a-gpios + - encoder-b-gpios + +additionalProperties: false + +examples: + - | + #include + + quadrature-encoder { + compatible =3D "gpio-quadrature-encoder"; + encoder-a-gpios =3D <&gpio0 10 GPIO_ACTIVE_LOW>; + encoder-b-gpios =3D <&gpio0 11 GPIO_ACTIVE_LOW>; + encoder-index-gpios =3D <&gpio0 12 GPIO_ACTIVE_LOW>; + }; + +... --=20 2.52.0 From nobody Sun Jun 14 07:34:33 2026 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37B1B421F17 for ; Fri, 1 May 2026 20:07:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777666079; cv=none; b=biY4h6vhS0/PLzFGRAMN8RV4SPulueFdNxX4hT+Q67NbYWL72ck+iwiuI3Aww3Yvg4GFRMESSnu/h8g6+ac1cFNIZty+Fs+6VY3kAcAgRRgrmhnbKfc1/PnBn4zpyrRvMsCHYLDPei9UifXudGYk0ebHSwwBljQMOjkATJ5MzsE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777666079; c=relaxed/simple; bh=u1DjuLJv3B9UnrkHjQRMvjj8DrFn4X2FMIArEdPEwO4=; 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Fri, 01 May 2026 13:07:53 -0700 (PDT) From: Wadim Mueller To: wbg@kernel.org Cc: conor+dt@kernel.org, krzk+dt@kernel.org, robh@kernel.org, conor.dooley@microchip.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/3] counter: add GPIO-based quadrature encoder driver Date: Fri, 1 May 2026 22:07:48 +0200 Message-ID: <20260501200749.20029-3-wafgo01@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260501200749.20029-1-wafgo01@gmail.com> References: <20260501200749.20029-1-wafgo01@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a platform driver that turns ordinary GPIOs into a quadrature encoder counter device. The driver requests edge-triggered interrupts on the A and B (and optional Index) GPIOs and decodes the quadrature signal in software using a classic state-table approach. Supported counting modes: - Quadrature X1 (count on A rising edge only) - Quadrature X2 (count on both A edges) - Quadrature X4 (count on every A and B edge) - Pulse-direction (A =3D pulse, B =3D direction) An optional index signal resets the count to zero on its rising edge when enabled through sysfs. A configurable ceiling clamps the count to [0, ceiling]. Signed-off-by: Wadim Mueller --- drivers/counter/Kconfig | 15 + drivers/counter/Makefile | 1 + drivers/counter/gpio-quadrature-encoder.c | 710 ++++++++++++++++++++++ 3 files changed, 726 insertions(+) create mode 100644 drivers/counter/gpio-quadrature-encoder.c diff --git a/drivers/counter/Kconfig b/drivers/counter/Kconfig index d30d22dfe..72c5c8159 100644 --- a/drivers/counter/Kconfig +++ b/drivers/counter/Kconfig @@ -68,6 +68,21 @@ config INTEL_QEP To compile this driver as a module, choose M here: the module will be called intel-qep. =20 +config GPIO_QUADRATURE_ENCODER + tristate "GPIO-based quadrature encoder counter driver" + depends on GPIOLIB + help + Select this option to enable the GPIO-based quadrature encoder + counter driver. It reads A/B quadrature signals and an optional + index pulse via edge-triggered GPIO interrupts, supporting X1, X2, + X4 quadrature decoding and pulse-direction mode. + + This is useful on SoCs that lack a dedicated hardware quadrature + decoder or where the encoder is wired to generic GPIO pins. + + To compile this driver as a module, choose M here: the + module will be called gpio-quadrature-encoder. + config INTERRUPT_CNT tristate "Interrupt counter driver" depends on GPIOLIB diff --git a/drivers/counter/Makefile b/drivers/counter/Makefile index fa3c1d08f..2bef64d10 100644 --- a/drivers/counter/Makefile +++ b/drivers/counter/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_STM32_TIMER_CNT) +=3D stm32-timer-cnt.o obj-$(CONFIG_STM32_LPTIMER_CNT) +=3D stm32-lptimer-cnt.o obj-$(CONFIG_TI_EQEP) +=3D ti-eqep.o obj-$(CONFIG_FTM_QUADDEC) +=3D ftm-quaddec.o +obj-$(CONFIG_GPIO_QUADRATURE_ENCODER) +=3D gpio-quadrature-encoder.o obj-$(CONFIG_MICROCHIP_TCB_CAPTURE) +=3D microchip-tcb-capture.o obj-$(CONFIG_INTEL_QEP) +=3D intel-qep.o obj-$(CONFIG_TI_ECAP_CAPTURE) +=3D ti-ecap-capture.o diff --git a/drivers/counter/gpio-quadrature-encoder.c b/drivers/counter/gp= io-quadrature-encoder.c new file mode 100644 index 000000000..0822f0a8a --- /dev/null +++ b/drivers/counter/gpio-quadrature-encoder.c @@ -0,0 +1,710 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * GPIO-based Quadrature Encoder Counter Driver + * + * Reads quadrature encoder signals (A, B, and optional Index) via GPIOs. + * Supports X1, X2, X4 quadrature decoding and pulse-direction mode. + * + * Copyright (C) 2026 CMBlu Energy AG + * Author: Wadim Mueller + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +enum gpio_qenc_function { + GPIO_QENC_FUNC_QUAD_X1 =3D 0, + GPIO_QENC_FUNC_QUAD_X2, + GPIO_QENC_FUNC_QUAD_X4, + GPIO_QENC_FUNC_PULSE_DIR, +}; + +enum gpio_qenc_signal_id { + GPIO_QENC_SIGNAL_A =3D 0, + GPIO_QENC_SIGNAL_B, + GPIO_QENC_SIGNAL_INDEX, +}; + +struct gpio_qenc_priv { + struct gpio_desc *gpio_a; + struct gpio_desc *gpio_b; + struct gpio_desc *gpio_index; + + int irq_a; + int irq_b; + int irq_index; + + spinlock_t lock; + + s64 count; + u64 ceiling; + bool enabled; + enum counter_count_direction direction; + enum gpio_qenc_function function; + + int prev_a; + int prev_b; + + bool index_enabled; + + struct counter_signal signals[3]; + struct counter_synapse synapses[3]; + struct counter_count cnts; +}; + +/* + * Quadrature state table for X4 decoding. + * Rows =3D previous state (A<<1 | B), Columns =3D new state (A<<1 | B). + * Values: 0 =3D no change, +1 =3D forward, -1 =3D backward, 2 =3D error (= skip). + */ +static const int quad_table[4][4] =3D { + /* 00 01 10 11 <- new */ + /* 00 */ { 0, -1, 1, 2 }, + /* 01 */ { 1, 0, 2, -1 }, + /* 10 */ { -1, 2, 0, 1 }, + /* 11 */ { 2, 1, -1, 0 }, +}; + +static void gpio_qenc_update_count(struct gpio_qenc_priv *priv, int delta) +{ + s64 new_count; + + if (!delta) + return; + + new_count =3D priv->count + delta; + + if (priv->ceiling) { + if (new_count < 0) + new_count =3D 0; + else if (new_count > (s64)priv->ceiling) + new_count =3D priv->ceiling; + } + + priv->count =3D new_count; + priv->direction =3D (delta > 0) ? COUNTER_COUNT_DIRECTION_FORWARD + : COUNTER_COUNT_DIRECTION_BACKWARD; +} + +static irqreturn_t gpio_qenc_a_isr(int irq, void *dev_id) +{ + struct counter_device *counter =3D dev_id; + struct gpio_qenc_priv *priv =3D counter_priv(counter); + unsigned long flags; + int a, b, prev_state, new_state, delta; + + spin_lock_irqsave(&priv->lock, flags); + + if (!priv->enabled) + goto out; + + a =3D gpiod_get_value(priv->gpio_a); + b =3D gpiod_get_value(priv->gpio_b); + + prev_state =3D (priv->prev_a << 1) | priv->prev_b; + new_state =3D (a << 1) | b; + + switch (priv->function) { + case GPIO_QENC_FUNC_QUAD_X4: + delta =3D quad_table[prev_state][new_state]; + if (delta =3D=3D 2) + delta =3D 0; + gpio_qenc_update_count(priv, delta); + break; + + case GPIO_QENC_FUNC_QUAD_X2: + delta =3D quad_table[prev_state][new_state]; + if (delta =3D=3D 2) + delta =3D 0; + gpio_qenc_update_count(priv, delta); + break; + + case GPIO_QENC_FUNC_QUAD_X1: + if (!priv->prev_a && a) { + delta =3D b ? -1 : 1; + gpio_qenc_update_count(priv, delta); + } + break; + + case GPIO_QENC_FUNC_PULSE_DIR: + if (!priv->prev_a && a) { + delta =3D b ? -1 : 1; + gpio_qenc_update_count(priv, delta); + } + break; + } + + priv->prev_a =3D a; + priv->prev_b =3D b; + + spin_unlock_irqrestore(&priv->lock, flags); + + counter_push_event(counter, COUNTER_EVENT_CHANGE_OF_STATE, 0); + + return IRQ_HANDLED; + +out: + spin_unlock_irqrestore(&priv->lock, flags); + return IRQ_HANDLED; +} + +static irqreturn_t gpio_qenc_b_isr(int irq, void *dev_id) +{ + struct counter_device *counter =3D dev_id; + struct gpio_qenc_priv *priv =3D counter_priv(counter); + unsigned long flags; + int a, b, prev_state, new_state, delta; + + spin_lock_irqsave(&priv->lock, flags); + + if (!priv->enabled) + goto out; + + a =3D gpiod_get_value(priv->gpio_a); + b =3D gpiod_get_value(priv->gpio_b); + + prev_state =3D (priv->prev_a << 1) | priv->prev_b; + new_state =3D (a << 1) | b; + + switch (priv->function) { + case GPIO_QENC_FUNC_QUAD_X4: + delta =3D quad_table[prev_state][new_state]; + if (delta =3D=3D 2) + delta =3D 0; + gpio_qenc_update_count(priv, delta); + break; + + case GPIO_QENC_FUNC_QUAD_X2: + /* X2: only A-channel edges update count */ + break; + + case GPIO_QENC_FUNC_QUAD_X1: + case GPIO_QENC_FUNC_PULSE_DIR: + break; + } + + priv->prev_a =3D a; + priv->prev_b =3D b; + + spin_unlock_irqrestore(&priv->lock, flags); + return IRQ_HANDLED; + +out: + spin_unlock_irqrestore(&priv->lock, flags); + return IRQ_HANDLED; +} + +static irqreturn_t gpio_qenc_index_isr(int irq, void *dev_id) +{ + struct counter_device *counter =3D dev_id; + struct gpio_qenc_priv *priv =3D counter_priv(counter); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + + if (priv->enabled && priv->index_enabled) + priv->count =3D 0; + + spin_unlock_irqrestore(&priv->lock, flags); + + counter_push_event(counter, COUNTER_EVENT_INDEX, 0); + + return IRQ_HANDLED; +} + +static int gpio_qenc_count_read(struct counter_device *counter, + struct counter_count *count, u64 *val) +{ + struct gpio_qenc_priv *priv =3D counter_priv(counter); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + *val =3D (u64)priv->count; + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int gpio_qenc_count_write(struct counter_device *counter, + struct counter_count *count, const u64 val) +{ + struct gpio_qenc_priv *priv =3D counter_priv(counter); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + + if (priv->ceiling && val > priv->ceiling) { + spin_unlock_irqrestore(&priv->lock, flags); + return -EINVAL; + } + + priv->count =3D (s64)val; + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static const enum counter_function gpio_qenc_functions[] =3D { + COUNTER_FUNCTION_QUADRATURE_X1_A, + COUNTER_FUNCTION_QUADRATURE_X2_A, + COUNTER_FUNCTION_QUADRATURE_X4, + COUNTER_FUNCTION_PULSE_DIRECTION, +}; + +static int gpio_qenc_function_read(struct counter_device *counter, + struct counter_count *count, + enum counter_function *function) +{ + struct gpio_qenc_priv *priv =3D counter_priv(counter); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + + switch (priv->function) { + case GPIO_QENC_FUNC_QUAD_X1: + *function =3D COUNTER_FUNCTION_QUADRATURE_X1_A; + break; + case GPIO_QENC_FUNC_QUAD_X2: + *function =3D COUNTER_FUNCTION_QUADRATURE_X2_A; + break; + case GPIO_QENC_FUNC_QUAD_X4: + *function =3D COUNTER_FUNCTION_QUADRATURE_X4; + break; + case GPIO_QENC_FUNC_PULSE_DIR: + *function =3D COUNTER_FUNCTION_PULSE_DIRECTION; + break; + } + + spin_unlock_irqrestore(&priv->lock, flags); + return 0; +} + +static int gpio_qenc_function_write(struct counter_device *counter, + struct counter_count *count, + enum counter_function function) +{ + struct gpio_qenc_priv *priv =3D counter_priv(counter); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + + switch (function) { + case COUNTER_FUNCTION_QUADRATURE_X1_A: + priv->function =3D GPIO_QENC_FUNC_QUAD_X1; + break; + case COUNTER_FUNCTION_QUADRATURE_X2_A: + priv->function =3D GPIO_QENC_FUNC_QUAD_X2; + break; + case COUNTER_FUNCTION_QUADRATURE_X4: + priv->function =3D GPIO_QENC_FUNC_QUAD_X4; + break; + case COUNTER_FUNCTION_PULSE_DIRECTION: + priv->function =3D GPIO_QENC_FUNC_PULSE_DIR; + break; + default: + spin_unlock_irqrestore(&priv->lock, flags); + return -EINVAL; + } + + spin_unlock_irqrestore(&priv->lock, flags); + return 0; +} + +static const enum counter_synapse_action gpio_qenc_synapse_actions[] =3D { + COUNTER_SYNAPSE_ACTION_BOTH_EDGES, + COUNTER_SYNAPSE_ACTION_RISING_EDGE, + COUNTER_SYNAPSE_ACTION_NONE, +}; + +static int gpio_qenc_action_read(struct counter_device *counter, + struct counter_count *count, + struct counter_synapse *synapse, + enum counter_synapse_action *action) +{ + struct gpio_qenc_priv *priv =3D counter_priv(counter); + enum gpio_qenc_signal_id signal_id =3D synapse->signal->id; + + switch (priv->function) { + case GPIO_QENC_FUNC_QUAD_X4: + if (signal_id =3D=3D GPIO_QENC_SIGNAL_A || + signal_id =3D=3D GPIO_QENC_SIGNAL_B) + *action =3D COUNTER_SYNAPSE_ACTION_BOTH_EDGES; + else + *action =3D COUNTER_SYNAPSE_ACTION_RISING_EDGE; + return 0; + + case GPIO_QENC_FUNC_QUAD_X2: + if (signal_id =3D=3D GPIO_QENC_SIGNAL_A) + *action =3D COUNTER_SYNAPSE_ACTION_BOTH_EDGES; + else if (signal_id =3D=3D GPIO_QENC_SIGNAL_B) + *action =3D COUNTER_SYNAPSE_ACTION_NONE; + else + *action =3D COUNTER_SYNAPSE_ACTION_RISING_EDGE; + return 0; + + case GPIO_QENC_FUNC_QUAD_X1: + if (signal_id =3D=3D GPIO_QENC_SIGNAL_A) + *action =3D COUNTER_SYNAPSE_ACTION_RISING_EDGE; + else if (signal_id =3D=3D GPIO_QENC_SIGNAL_B) + *action =3D COUNTER_SYNAPSE_ACTION_NONE; + else + *action =3D COUNTER_SYNAPSE_ACTION_RISING_EDGE; + return 0; + + case GPIO_QENC_FUNC_PULSE_DIR: + if (signal_id =3D=3D GPIO_QENC_SIGNAL_A) + *action =3D COUNTER_SYNAPSE_ACTION_RISING_EDGE; + else + *action =3D COUNTER_SYNAPSE_ACTION_NONE; + return 0; + } + + return -EINVAL; +} + +static int gpio_qenc_signal_read(struct counter_device *counter, + struct counter_signal *signal, + enum counter_signal_level *level) +{ + struct gpio_qenc_priv *priv =3D counter_priv(counter); + struct gpio_desc *gpio; + int ret; + + switch (signal->id) { + case GPIO_QENC_SIGNAL_A: + gpio =3D priv->gpio_a; + break; + case GPIO_QENC_SIGNAL_B: + gpio =3D priv->gpio_b; + break; + case GPIO_QENC_SIGNAL_INDEX: + gpio =3D priv->gpio_index; + break; + default: + return -EINVAL; + } + + if (!gpio) + return -EINVAL; + + ret =3D gpiod_get_value(gpio); + if (ret < 0) + return ret; + + *level =3D ret ? COUNTER_SIGNAL_LEVEL_HIGH : COUNTER_SIGNAL_LEVEL_LOW; + return 0; +} + +static int gpio_qenc_events_configure(struct counter_device *counter) +{ + return 0; +} + +static int gpio_qenc_watch_validate(struct counter_device *counter, + const struct counter_watch *watch) +{ + if (watch->channel !=3D 0) + return -EINVAL; + + switch (watch->event) { + case COUNTER_EVENT_CHANGE_OF_STATE: + case COUNTER_EVENT_INDEX: + return 0; + default: + return -EINVAL; + } +} + +static const struct counter_ops gpio_qenc_ops =3D { + .count_read =3D gpio_qenc_count_read, + .count_write =3D gpio_qenc_count_write, + .function_read =3D gpio_qenc_function_read, + .function_write =3D gpio_qenc_function_write, + .action_read =3D gpio_qenc_action_read, + .signal_read =3D gpio_qenc_signal_read, + .events_configure =3D gpio_qenc_events_configure, + .watch_validate =3D gpio_qenc_watch_validate, +}; + +static int gpio_qenc_ceiling_read(struct counter_device *counter, + struct counter_count *count, u64 *val) +{ + struct gpio_qenc_priv *priv =3D counter_priv(counter); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + *val =3D priv->ceiling; + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int gpio_qenc_ceiling_write(struct counter_device *counter, + struct counter_count *count, const u64 val) +{ + struct gpio_qenc_priv *priv =3D counter_priv(counter); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + priv->ceiling =3D val; + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int gpio_qenc_enable_read(struct counter_device *counter, + struct counter_count *count, u8 *enable) +{ + struct gpio_qenc_priv *priv =3D counter_priv(counter); + + *enable =3D priv->enabled; + return 0; +} + +static int gpio_qenc_enable_write(struct counter_device *counter, + struct counter_count *count, u8 enable) +{ + struct gpio_qenc_priv *priv =3D counter_priv(counter); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + + if (priv->enabled =3D=3D !!enable) { + spin_unlock_irqrestore(&priv->lock, flags); + return 0; + } + + if (enable) { + priv->enabled =3D true; + spin_unlock_irqrestore(&priv->lock, flags); + enable_irq(priv->irq_a); + enable_irq(priv->irq_b); + if (priv->irq_index) + enable_irq(priv->irq_index); + } else { + priv->enabled =3D false; + spin_unlock_irqrestore(&priv->lock, flags); + disable_irq(priv->irq_a); + disable_irq(priv->irq_b); + if (priv->irq_index) + disable_irq(priv->irq_index); + } + + return 0; +} + +static int gpio_qenc_direction_read(struct counter_device *counter, + struct counter_count *count, u32 *direction) +{ + struct gpio_qenc_priv *priv =3D counter_priv(counter); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + *direction =3D priv->direction; + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int gpio_qenc_index_enable_read(struct counter_device *counter, + struct counter_count *count, u8 *val) +{ + struct gpio_qenc_priv *priv =3D counter_priv(counter); + + *val =3D priv->index_enabled; + return 0; +} + +static int gpio_qenc_index_enable_write(struct counter_device *counter, + struct counter_count *count, u8 val) +{ + struct gpio_qenc_priv *priv =3D counter_priv(counter); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + priv->index_enabled =3D !!val; + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static struct counter_comp gpio_qenc_count_ext[] =3D { + COUNTER_COMP_CEILING(gpio_qenc_ceiling_read, gpio_qenc_ceiling_write), + COUNTER_COMP_ENABLE(gpio_qenc_enable_read, gpio_qenc_enable_write), + COUNTER_COMP_DIRECTION(gpio_qenc_direction_read), + COUNTER_COMP_COUNT_BOOL("index_enabled", + gpio_qenc_index_enable_read, + gpio_qenc_index_enable_write), +}; + +static int gpio_qenc_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct counter_device *counter; + struct gpio_qenc_priv *priv; + bool has_index; + int num_signals; + int num_synapses; + int ret; + + counter =3D devm_counter_alloc(dev, sizeof(*priv)); + if (!counter) + return -ENOMEM; + + priv =3D counter_priv(counter); + spin_lock_init(&priv->lock); + + priv->gpio_a =3D devm_gpiod_get(dev, "encoder-a", GPIOD_IN); + if (IS_ERR(priv->gpio_a)) + return dev_err_probe(dev, PTR_ERR(priv->gpio_a), + "failed to get encoder-a GPIO\n"); + + priv->gpio_b =3D devm_gpiod_get(dev, "encoder-b", GPIOD_IN); + if (IS_ERR(priv->gpio_b)) + return dev_err_probe(dev, PTR_ERR(priv->gpio_b), + "failed to get encoder-b GPIO\n"); + + priv->gpio_index =3D devm_gpiod_get_optional(dev, "encoder-index", + GPIOD_IN); + if (IS_ERR(priv->gpio_index)) + return dev_err_probe(dev, PTR_ERR(priv->gpio_index), + "failed to get encoder-index GPIO\n"); + + has_index =3D !!priv->gpio_index; + + priv->irq_a =3D gpiod_to_irq(priv->gpio_a); + if (priv->irq_a < 0) + return dev_err_probe(dev, priv->irq_a, + "failed to get IRQ for encoder-a\n"); + + priv->irq_b =3D gpiod_to_irq(priv->gpio_b); + if (priv->irq_b < 0) + return dev_err_probe(dev, priv->irq_b, + "failed to get IRQ for encoder-b\n"); + + if (has_index) { + priv->irq_index =3D gpiod_to_irq(priv->gpio_index); + if (priv->irq_index < 0) + return dev_err_probe(dev, priv->irq_index, + "failed to get IRQ for encoder-index\n"); + } + + priv->prev_a =3D gpiod_get_value(priv->gpio_a); + priv->prev_b =3D gpiod_get_value(priv->gpio_b); + + priv->function =3D GPIO_QENC_FUNC_QUAD_X4; + priv->direction =3D COUNTER_COUNT_DIRECTION_FORWARD; + + num_signals =3D has_index ? 3 : 2; + + priv->signals[GPIO_QENC_SIGNAL_A].id =3D GPIO_QENC_SIGNAL_A; + priv->signals[GPIO_QENC_SIGNAL_A].name =3D "Signal A"; + + priv->signals[GPIO_QENC_SIGNAL_B].id =3D GPIO_QENC_SIGNAL_B; + priv->signals[GPIO_QENC_SIGNAL_B].name =3D "Signal B"; + + if (has_index) { + priv->signals[GPIO_QENC_SIGNAL_INDEX].id =3D + GPIO_QENC_SIGNAL_INDEX; + priv->signals[GPIO_QENC_SIGNAL_INDEX].name =3D "Index"; + } + + num_synapses =3D num_signals; + + priv->synapses[0].actions_list =3D gpio_qenc_synapse_actions; + priv->synapses[0].num_actions =3D ARRAY_SIZE(gpio_qenc_synapse_actions); + priv->synapses[0].signal =3D &priv->signals[GPIO_QENC_SIGNAL_A]; + + priv->synapses[1].actions_list =3D gpio_qenc_synapse_actions; + priv->synapses[1].num_actions =3D ARRAY_SIZE(gpio_qenc_synapse_actions); + priv->synapses[1].signal =3D &priv->signals[GPIO_QENC_SIGNAL_B]; + + if (has_index) { + priv->synapses[2].actions_list =3D gpio_qenc_synapse_actions; + priv->synapses[2].num_actions =3D + ARRAY_SIZE(gpio_qenc_synapse_actions); + priv->synapses[2].signal =3D + &priv->signals[GPIO_QENC_SIGNAL_INDEX]; + } + + priv->cnts.id =3D 0; + priv->cnts.name =3D "Position"; + priv->cnts.functions_list =3D gpio_qenc_functions; + priv->cnts.num_functions =3D ARRAY_SIZE(gpio_qenc_functions); + priv->cnts.synapses =3D priv->synapses; + priv->cnts.num_synapses =3D num_synapses; + priv->cnts.ext =3D gpio_qenc_count_ext; + priv->cnts.num_ext =3D ARRAY_SIZE(gpio_qenc_count_ext); + + counter->name =3D dev_name(dev); + counter->parent =3D dev; + counter->ops =3D &gpio_qenc_ops; + counter->signals =3D priv->signals; + counter->num_signals =3D num_signals; + counter->counts =3D &priv->cnts; + counter->num_counts =3D 1; + + irq_set_status_flags(priv->irq_a, IRQ_NOAUTOEN); + ret =3D devm_request_irq(dev, priv->irq_a, gpio_qenc_a_isr, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, + "gpio-qenc-a", counter); + if (ret) + return dev_err_probe(dev, ret, + "failed to request IRQ for encoder-a\n"); + + irq_set_status_flags(priv->irq_b, IRQ_NOAUTOEN); + ret =3D devm_request_irq(dev, priv->irq_b, gpio_qenc_b_isr, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, + "gpio-qenc-b", counter); + if (ret) + return dev_err_probe(dev, ret, + "failed to request IRQ for encoder-b\n"); + + if (has_index) { + irq_set_status_flags(priv->irq_index, IRQ_NOAUTOEN); + ret =3D devm_request_irq(dev, priv->irq_index, + gpio_qenc_index_isr, + IRQF_TRIGGER_RISING, + "gpio-qenc-index", counter); + if (ret) + return dev_err_probe(dev, ret, + "failed to request IRQ for encoder-index\n"); + } + + ret =3D devm_counter_add(dev, counter); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to add counter\n"); + + dev_info(dev, "GPIO quadrature encoder registered (signals: A, B%s)\n", + has_index ? ", Index" : ""); + + return 0; +} + +static const struct of_device_id gpio_qenc_of_match[] =3D { + { .compatible =3D "gpio-quadrature-encoder" }, + {} +}; +MODULE_DEVICE_TABLE(of, gpio_qenc_of_match); + +static struct platform_driver gpio_qenc_driver =3D { + .probe =3D gpio_qenc_probe, + .driver =3D { + .name =3D "gpio-quadrature-encoder", + .of_match_table =3D gpio_qenc_of_match, + }, +}; +module_platform_driver(gpio_qenc_driver); + +MODULE_ALIAS("platform:gpio-quadrature-encoder"); +MODULE_AUTHOR("Wadim Mueller "); +MODULE_DESCRIPTION("GPIO-based quadrature encoder counter driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("COUNTER"); --=20 2.52.0 From nobody Sun Jun 14 07:34:33 2026 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9128423145 for ; Fri, 1 May 2026 20:07:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 01 May 2026 13:07:55 -0700 (PDT) Received: from fedora ([2a02:8071:50c5:5c0::3323]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48a8fe953besm26829325e9.2.2026.05.01.13.07.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 May 2026 13:07:54 -0700 (PDT) From: Wadim Mueller To: wbg@kernel.org Cc: conor+dt@kernel.org, krzk+dt@kernel.org, robh@kernel.org, conor.dooley@microchip.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/3] MAINTAINERS: add entry for GPIO quadrature encoder counter driver Date: Fri, 1 May 2026 22:07:49 +0200 Message-ID: <20260501200749.20029-4-wafgo01@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260501200749.20029-1-wafgo01@gmail.com> References: <20260501200749.20029-1-wafgo01@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add myself as maintainer for the new gpio-quadrature-encoder counter driver and its devicetree binding. Signed-off-by: Wadim Mueller --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 06a8c7457..fca62baa7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11018,6 +11018,13 @@ F: Documentation/dev-tools/gpio-sloppy-logic-analy= zer.rst F: drivers/gpio/gpio-sloppy-logic-analyzer.c F: tools/gpio/gpio-sloppy-logic-analyzer.sh =20 +GPIO QUADRATURE ENCODER COUNTER DRIVER +M: Wadim Mueller +L: linux-iio@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/counter/gpio-quadrature-encoder.yaml +F: drivers/counter/gpio-quadrature-encoder.c + GPIO SUBSYSTEM M: Linus Walleij M: Bartosz Golaszewski --=20 2.52.0