From nobody Sat Jun 20 14:14:37 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D518F477989; Thu, 30 Apr 2026 16:33:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777566802; cv=none; b=jaq30uQHNlzGYG/xjk60MPjnAYEsr7k7/TCuT9xUFbrlWVT2RNixfF2h4MML50ExT9yY/5FGOnAZCeX3v/qrSRBsBU1lcXoC4ju7KSdNCv6UtfmhoTkjZ4XAurIx2u6W88bFaH6K1wTtYKxw4vAJqaKQ30+uuM9gNJyL9Seat6M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777566802; c=relaxed/simple; bh=37S/jeR+9UamGrjseRsSa49ojUjfRLdHxo7rQfBghLs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=EZUBfeXWev7gQUVw6Jse96SEsMrQzeyVXmV+mrvxlzzv/E+rAtYReLKZ/sLLRhN55N7cdI1ZyopwSIrr8BX0f9V/kyNmRgtteoZA3FS2LZcvdKw1II8lXtQi3qH8KhWIceaXXYnd7zMUdW+LfqNBzzcUfETUoeVY5CjIFzrX4BQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=mm+i5imG; arc=none smtp.client-ip=117.135.210.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="mm+i5imG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=a2 gixQBQxDx3b8t9YQ5XreDqRrVjp7DmMKI0uRw8O2g=; b=mm+i5imGdGyC9Y+zBx C6B0yWpDd1P21sVo8VA7rdsqzt3a9KLAbtAqY63t0BUW5NOcA+StbAO5Z9wiID4X /4hZDnqzvvl/wdl1QYS23RXWh7ukpmfCaEFXtukVKet73x1YlfrRg10BNSLLSDiI 3CIt+8bNF3UROOkyUKtw+tVNo= Received: from zhb.. (unknown []) by gzsmtp3 (Coremail) with SMTP id PigvCgA3t7MPhPNpY8phBw--.45309S3; Fri, 01 May 2026 00:32:19 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: ray.huang@amd.com, mario.limonciello@amd.com, rafael@kernel.org, viresh.kumar@linaro.org, sven@kernel.org, j@jannau.net Cc: perry.yuan@amd.com, kprateek.nayak@amd.com, neal@gompa.dev, linux-pm@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH 1/2] cpufreq/amd-pstate: Use FIELD_MODIFY() Date: Fri, 1 May 2026 00:32:12 +0800 Message-Id: <20260430163213.44695-2-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260430163213.44695-1-18255117159@163.com> References: <20260430163213.44695-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PigvCgA3t7MPhPNpY8phBw--.45309S3 X-Coremail-Antispam: 1Uf129KBjvJXoWxZr48KF4xKF45JFW5tw4rAFb_yoW5Aw4DpF W5CF4Iyr4Yqa1DtF43Ga1UWr1FqF1qkw4DJanIq397W3W5A3yUXa4vyw1UW34UZFyqgw15 uayUXFW3Ga1Sv3JanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pRa9akUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC6xR9IWnzhBSRRgAA3+ Content-Type: text/plain; charset="utf-8" Use FIELD_MODIFY() to remove open-coded bit manipulation. No functional change intended. Signed-off-by: Hans Zhang <18255117159@163.com> Reviewed-by: K Prateek Nayak --- drivers/cpufreq/amd-pstate.c | 26 ++++++++++---------------- 1 file changed, 10 insertions(+), 16 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 453084c67327..1037d1722263 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -246,12 +246,10 @@ static int msr_update_perf(struct cpufreq_policy *pol= icy, u8 min_perf, =20 value =3D prev =3D READ_ONCE(cpudata->cppc_req_cached); =20 - value &=3D ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK | - AMD_CPPC_DES_PERF_MASK | AMD_CPPC_EPP_PERF_MASK); - value |=3D FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, max_perf); - value |=3D FIELD_PREP(AMD_CPPC_DES_PERF_MASK, des_perf); - value |=3D FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, min_perf); - value |=3D FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp); + FIELD_MODIFY(AMD_CPPC_MAX_PERF_MASK, &value, max_perf); + FIELD_MODIFY(AMD_CPPC_DES_PERF_MASK, &value, des_perf); + FIELD_MODIFY(AMD_CPPC_MIN_PERF_MASK, &value, min_perf); + FIELD_MODIFY(AMD_CPPC_EPP_PERF_MASK, &value, epp); =20 if (trace_amd_pstate_epp_perf_enabled()) { union perf_cached perf =3D READ_ONCE(cpudata->perf); @@ -300,8 +298,7 @@ static int msr_set_epp(struct cpufreq_policy *policy, u= 8 epp) int ret; =20 value =3D prev =3D READ_ONCE(cpudata->cppc_req_cached); - value &=3D ~AMD_CPPC_EPP_PERF_MASK; - value |=3D FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp); + FIELD_MODIFY(AMD_CPPC_EPP_PERF_MASK, &value, epp); =20 if (trace_amd_pstate_epp_perf_enabled()) { union perf_cached perf =3D cpudata->perf; @@ -441,8 +438,7 @@ static int shmem_set_epp(struct cpufreq_policy *policy,= u8 epp) } =20 value =3D READ_ONCE(cpudata->cppc_req_cached); - value &=3D ~AMD_CPPC_EPP_PERF_MASK; - value |=3D FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp); + FIELD_MODIFY(AMD_CPPC_EPP_PERF_MASK, &value, epp); WRITE_ONCE(cpudata->cppc_req_cached, value); =20 return ret; @@ -575,12 +571,10 @@ static int shmem_update_perf(struct cpufreq_policy *p= olicy, u8 min_perf, =20 value =3D prev =3D READ_ONCE(cpudata->cppc_req_cached); =20 - value &=3D ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK | - AMD_CPPC_DES_PERF_MASK | AMD_CPPC_EPP_PERF_MASK); - value |=3D FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, max_perf); - value |=3D FIELD_PREP(AMD_CPPC_DES_PERF_MASK, des_perf); - value |=3D FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, min_perf); - value |=3D FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp); + FIELD_MODIFY(AMD_CPPC_MAX_PERF_MASK, &value, max_perf); + FIELD_MODIFY(AMD_CPPC_DES_PERF_MASK, &value, des_perf); + FIELD_MODIFY(AMD_CPPC_MIN_PERF_MASK, &value, min_perf); + FIELD_MODIFY(AMD_CPPC_EPP_PERF_MASK, &value, epp); =20 if (trace_amd_pstate_epp_perf_enabled()) { union perf_cached perf =3D READ_ONCE(cpudata->perf); --=20 2.34.1 From nobody Sat Jun 20 14:14:37 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4ACB2472789; Thu, 30 Apr 2026 16:33:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777566797; cv=none; b=VhMx1Qx+RaYOQYvFQjsrH33y98rYDQaJ7O+DBnM88QmCz/39fwr9Dihe5qKxeRCE1bQvihmc67e1XiL3R4e2S/SFjK4jusTUU/J/L4gduIqF131vaOZljJ1SY5DPMxQI6aY+34vT6+OvFovvwXy06vewHgwlVUluRBzoY0jUUTU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777566797; c=relaxed/simple; bh=3LxlcnS5Y5p5Z6K+rwjkNw6QjTHDkhYhq4FGmYnGRxc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=KndJdsFl8krSM4DEvTSSqk14p7TxbNm0VHt+/XAFkyYL7uyQBczDBqc38P571VKjdHyUuX9/yJtEXLy7n+wMCs6PolOYje7U/Wv97tAOwvzNpOjHbBJvkeb5I0NmVzW58PJ2CF084ogb5cCN1wiL8hRa8L1iRYeqCcxbAPUPX5s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=O2vlRDAB; arc=none smtp.client-ip=117.135.210.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="O2vlRDAB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=EO m+xIFim33ZE50JFySdupaKYtgcplsaCUyEBJYxNUw=; b=O2vlRDABfff7iDWhqb LLR7JpxKC2DOgkjSS0CBZT7qlWyep4OdIl+r85WKrluQKt5qdd/OX8K2WaObbol9 SIlOvMScwPTzjvidAdepagzCrhF9Qkv6bbhlOcSkjm2vl5pN80LGpDUSIbvCp6J+ rOpUNph0lMSljdVDEBi9WBYCs= Received: from zhb.. (unknown []) by gzsmtp3 (Coremail) with SMTP id PigvCgA3t7MPhPNpY8phBw--.45309S4; Fri, 01 May 2026 00:32:20 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: ray.huang@amd.com, mario.limonciello@amd.com, rafael@kernel.org, viresh.kumar@linaro.org, sven@kernel.org, j@jannau.net Cc: perry.yuan@amd.com, kprateek.nayak@amd.com, neal@gompa.dev, linux-pm@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH 2/2] cpufreq: apple-soc: Use FIELD_MODIFY() Date: Fri, 1 May 2026 00:32:13 +0800 Message-Id: <20260430163213.44695-3-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260430163213.44695-1-18255117159@163.com> References: <20260430163213.44695-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PigvCgA3t7MPhPNpY8phBw--.45309S4 X-Coremail-Antispam: 1Uf129KBjvdXoWrur17tw43JrW7Ary7Ww1kGrg_yoWDJrX_ur 1fCr4Iyr4DCan5ta43CF1vvF98tw1xZrnYvFy0g39xtFn8AryF93ykZr4ku3yDAayxCFZ2 qw129FyruF4xAjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7sRMPEf7UUUUU== X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCwxR9IWnzhBScdgAA3r Content-Type: text/plain; charset="utf-8" Use FIELD_MODIFY() to remove open-coded bit manipulation. No functional change intended. Signed-off-by: Hans Zhang <18255117159@163.com> Reviewed-by: Joshua Peisach --- drivers/cpufreq/apple-soc-cpufreq.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/cpufreq/apple-soc-cpufreq.c b/drivers/cpufreq/apple-so= c-cpufreq.c index 9396034167e5..638e5bf72185 100644 --- a/drivers/cpufreq/apple-soc-cpufreq.c +++ b/drivers/cpufreq/apple-soc-cpufreq.c @@ -187,10 +187,8 @@ static int apple_soc_cpufreq_set_target(struct cpufreq= _policy *policy, =20 reg &=3D ~priv->info->ps1_mask; reg |=3D pstate << priv->info->ps1_shift; - if (priv->info->has_ps2) { - reg &=3D ~APPLE_DVFS_CMD_PS2; - reg |=3D FIELD_PREP(APPLE_DVFS_CMD_PS2, pstate); - } + if (priv->info->has_ps2) + FIELD_MODIFY(APPLE_DVFS_CMD_PS2, ®, pstate); reg |=3D APPLE_DVFS_CMD_SET; =20 writeq_relaxed(reg, priv->reg_base + APPLE_DVFS_CMD); --=20 2.34.1