From nobody Tue Jun 16 15:58:50 2026 Received: from smtpout.sipearl.com (smtpout.sipearl.com [178.170.11.57]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C62840628F for ; Thu, 30 Apr 2026 14:28:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.170.11.57 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777559315; cv=none; b=bw1oXeJBl1R723qnhNtLTGV2ZCDB8t74L0AmHu1MDMG6Oztjx7Ccyq+fQbzLZwZxQSyQe+u+0eQiUPgFuHsKr5ElqwQEBeSwZUAK0+xcvbjmwEfFlbEvxDBAiATaPG1DOILhzDJMMui/w6C/gBhvWOsyoOtDwmoymmbo0qaNrz0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777559315; c=relaxed/simple; bh=SPcqNJQot0yJ8SIs9PhXhBtyEZpHdGUjm2IIKeY+gr0=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=F7yDZEjkWdqvieVHuOZPkAOF43srwW7NGKo+Pm2rlCOEVzxb2Xc39OV6OFUagMzk4a6a3s3CWl9jUEWj4GkLGAupInRlrVYva5L23nlVH4nCVc9M+XJ4fNaf/IqIb8gHQo8d6qux1sT+zSmCWMYTH3/QFoMWSR2Crz96KBCJmjc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sipearl.com; spf=pass smtp.mailfrom=sipearl.com; dkim=pass (2048-bit key) header.d=sipearl.com header.i=@sipearl.com header.b=FD1z4c13; arc=none smtp.client-ip=178.170.11.57 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sipearl.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sipearl.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sipearl.com header.i=@sipearl.com header.b="FD1z4c13" Received: from smtpout.sipearl.com ([172.31.29.1]) by smtpin.sipearl.com with ESMTPS id 63UED6AG009117-63UED6AI009117 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 30 Apr 2026 16:13:06 +0200 Received: from dc2pvlnosz002.pub.int.sipearl.com (172.31.65.18) by dc2pvwexcz001.sipearl.corp (172.31.29.1) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.36; Thu, 30 Apr 2026 16:13:06 +0200 From: Andrea Tomassetti To: Peter Rosin CC: , Andrea Tomassetti , Johan Hovold , Krzysztof Kozlowski , Srinivas Kandagatla , Subject: [PATCH RESEND] mux: gpio-mux: add support for 4:1 2-channels mux Date: Thu, 30 Apr 2026 16:11:54 +0200 Message-ID: <20260430141201.1105285-1-andrea.tomassetti@sipearl.com> X-Mailer: git-send-email 2.51.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dc2pvwexcz002.sipearl.corp (172.31.29.2) To dc2pvwexcz001.sipearl.corp (172.31.29.1) X-FEAS-BEC-Info: WlpIGw0aAQkEARIJHAEHBlJSCRoLAAEeDUhZUEhYSFhIWUhZXkguLT4lWFo8JVpcWFhZW1xcSFpRSAkGDBoNCUYcBwUJGxsNHBwBKBsBGA0JGgRGCwcFSFlIWV1IGA0MCSgJEA0GHAEJRhsNSFhIWkhZWUhZX1pGW1lGWlFGWUhQSFhIWEhbSFhIWEhYSFpbSAIHAAkGQwQBBgkaBygDDRoGDQRGBxoPSFhIWlBIBAEGHRBFAw0aBg0EKB4PDRpGAw0aBg0ERgcaD0hYSFldSBgNDAkoCRANBhwBCUYbDUhY X-FEAS-Client-IP: 172.31.29.1 X-FE-Policy-ID: 2:2:2:SYSTEM DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; d=sipearl.com; s=sipearl2024; c=relaxed/relaxed; h=from:to:cc:subject:date:message-id:mime-version:content-type; bh=Bo20XJW94j3oeM9VKNJpCiXRiOk4qtx3BStw4WttyNk=; b=FD1z4c13gPS/QaMfZSBp66gMx84RMGJa50SKOPnH7oqdbqu3118xELDrC4lRJWPSW0MFHdhPysOd MFcwdf7X/z0fWE1XfA1R7Sr/St4TYR99w8BrhmNsIaI8WYlFZ1dLzLggyAQzpCtPOhFV3YLmp/gt Jt76HfyTYLth3PRvDg3ingMOQ2ZBy1QWgaZYDHYcEThCF7j7UEFKxSBo77KQb4jQ+PuFSULlavp7 sNvX2ELrdUfOUhLmFqd3cmTljLN+xtWFnwE0zaTOeaZ61YJxVCriaWhH8yQcJlOFPENuo+jWug8D GSmQRP3S5DrTTCeThYfyaWqqAK8hp6nNnfCB/A== Content-Type: text/plain; charset="utf-8" Some gpio multiplexers, like TMUX1209, offer differential 4:1 or dual 4:1 single-ended channels. Similarly to what already done by the adg792a driver, the gpio-mux driver has to take into account the #mux-control-cells property and allocate as many controllers as advised by it. So, in the DTS you can now define: tmux1209: mux-controller { compatible =3D "gpio-mux"; #mux-control-cells =3D <1>; mux-gpios =3D <&gpio_expander 01 GPIO_ACTIVE_HIGH>, <&gpio_expander 02 GPIO_ACTIVE_HIGH>; }; adcmux30: adcmux30 { compatible =3D "io-channel-mux"; io-channels =3D <&adc1 4>; io-channel-names =3D "parent"; #io-channel-cells =3D <1>; mux-controls =3D <&tmux1209 0>; channels =3D "S1A", "S2A", "S3A", "S4A"; }; adcmux31: adcmux31 { compatible =3D "io-channel-mux"; io-channels =3D <&adc1 5>; io-channel-names =3D "parent"; #io-channel-cells =3D <1>; mux-controls =3D <&tmux1209 1>; channels =3D "S1B", "S2B", "S3B", "S4B"; }; Signed-off-by: Andrea Tomassetti Reviewed-by: Linus Walleij --- drivers/mux/gpio.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/mux/gpio.c b/drivers/mux/gpio.c index 4cc3202c58f3..01ce3f878b9e 100644 --- a/drivers/mux/gpio.c +++ b/drivers/mux/gpio.c @@ -52,12 +52,23 @@ static int mux_gpio_probe(struct platform_device *pdev) int pins; s32 idle_state; int ret; + u32 cells; + int i; pins =3D gpiod_count(dev, "mux"); if (pins < 0) return pins; - mux_chip =3D devm_mux_chip_alloc(dev, 1, sizeof(*mux_gpio)); + ret =3D device_property_read_u32(dev, "#mux-control-cells", &cells); + if (ret < 0) + cells =3D 0; + + if (cells >=3D 2) { + dev_err(dev, "invalid control-cells %u\n", cells); + return -EINVAL; + } + + mux_chip =3D devm_mux_chip_alloc(dev, cells + 1, sizeof(*mux_gpio)); if (IS_ERR(mux_chip)) return PTR_ERR(mux_chip); @@ -69,7 +80,9 @@ static int mux_gpio_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(mux_gpio->gpios), "failed to get gpios\n"); WARN_ON(pins !=3D mux_gpio->gpios->ndescs); - mux_chip->mux->states =3D BIT(pins); + + for (i =3D 0; i < mux_chip->controllers; ++i) + mux_chip->mux[i].states =3D BIT(pins); ret =3D device_property_read_u32(dev, "idle-state", (u32 *)&idle_state); if (ret >=3D 0 && idle_state !=3D MUX_IDLE_AS_IS) { base-commit: 80234b5ab240f52fa45d201e899e207b9265ef91 -- 2.51.2