From nobody Tue Jun 16 18:00:14 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42B7119DF62; Thu, 30 Apr 2026 00:30:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777509054; cv=none; b=kniuxv6KWqE/Kro51jaLln5jORPrvexMqZNk/czxHkGaJwcYwSR4LeX6oR/2pEBPK0GGJhFAOhDIVDF5uC56FQsWMu8XSSy6oOpxJFSex21yGpaM1YfDoYh+KEvlj7P7UYeoH+DvVjAeEuo67/P1kM959KJJPBMmYoa3zD+TLxc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777509054; c=relaxed/simple; bh=BB4qWrczuxBdpRMQvOH7NHT8ySrVHIlxNOcUm8gwJN8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=kesbsRgrme94jYGsh1V2ndWnAhyzP5Bwgq2tITrqHDkz05hA3DU+R8baYfrEdYAYJ8QOJ1HAmkdPA8kn2jly1wWpOW/w24pehTHNPe8c6Dda4dVuJJmpQgv2WvdlNU6gpY3sg7vYFoB8z35LDfvZoNNKgWxIybURS0hRNo7AIrI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=kq7ITEHo; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="kq7ITEHo" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777509053; x=1809045053; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BB4qWrczuxBdpRMQvOH7NHT8ySrVHIlxNOcUm8gwJN8=; b=kq7ITEHoI6u8sHC6fMRPl0hqcdPTEI+D46PlLMuY/ywjJkHHT7K/NQ6o UGcmXgMkP6DBP2KZlSfCF2BXBbit20BMjw3oBt4ymLFFJhlnrwAdVsenU urew1TEtvLGejIUKjLnHeQoqo4ZjDKOHfHHm3q9Hz1WwA0diu3maKWL5O NsvPVYkn/Uv0tNxIW5HdE6erqwKipowKFQC6s9q5kyT81rtFCGV46FiiP rwO6mk8IchYURXjfufFBKWOU6r9RppQ46i3Cy3lf78tKx4cSzuxhyDCRz RUr3SUd5XEeECr09c0393yhEHeg2EkqxvsfyVjTxLS/s4IWdZywKD6ncn g==; X-CSE-ConnectionGUID: M7meXerLT0eaMcibHrhQXQ== X-CSE-MsgGUID: COWp+PRgTY6+xumqi6CMTA== X-IronPort-AV: E=McAfee;i="6800,10657,11771"; a="95873641" X-IronPort-AV: E=Sophos;i="6.23,207,1770624000"; d="scan'208";a="95873641" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 17:30:53 -0700 X-CSE-ConnectionGUID: qbM9CZcNQzy0726/hU4Gtg== X-CSE-MsgGUID: 1pS2YygjRoC0UK/v6P4kcA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,207,1770624000"; d="scan'208";a="234455199" Received: from spr.sh.intel.com ([10.112.229.196]) by orviesa009.jf.intel.com with ESMTP; 29 Apr 2026 17:30:50 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , Dapeng Mi , stable@vger.kernel.org Subject: [Patch v4 1/5] perf/x86/intel: Improve validation and configuration of ACR masks Date: Thu, 30 Apr 2026 08:25:54 +0800 Message-Id: <20260430002558.712334-2-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260430002558.712334-1-dapeng1.mi@linux.intel.com> References: <20260430002558.712334-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently there are several issues on the user space ACR mask validation and configuration. - The validation for user space ACR mask (attr.config2) is incomplete, e.g., the ACR mask could include the index which belongs to another ACR events group, but it's not validated. - An early return on an invalid ACR mask caused all subsequent ACR groups to be skipped. - The stale hardware ACR mask (hw.config1) is not cleared before setting new hardware ACR mask. The following changes address all of the above issues. - Figure out the event index group of an ACR group. Any bits in the user-space mask not present in the index group are now dropped. - Instead of an early return on invalid bits, drop only the invalid portions and continue iterating through all ACR events to ensure full configuration. - Explicitly clear the stale hardware ACR mask for each event prior to writing the new configuration. Besides, a non-leader event member of ACR group could be disabled in theory. This could cause bit-shifting errors in the acr_mask of remaining group members. But since ACR sampling requires all events to be active, this should not be a big concern in real use case. Add a "FIXME" comment to notice this risk. Cc: stable@vger.kernel.org Fixes: ec980e4facef ("perf/x86/intel: Support auto counter reload") Signed-off-by: Dapeng Mi --- V4: 1) Simplify ACR group indices validation. 2) Add FIXME to notify the bit-shifting risk of ACR mask if event numbers of ACR group are diabled. arch/x86/events/intel/core.c | 32 +++++++++++++++++++++++++------- 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 4768236c054b..ca910e6bfc77 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3332,23 +3332,41 @@ static void intel_pmu_enable_event(struct perf_even= t *event) static void intel_pmu_acr_late_setup(struct cpu_hw_events *cpuc) { struct perf_event *event, *leader; - int i, j, idx; + int i, j, k, bit, idx; =20 + /* + * FIXME: ACR mask parsing relies on cpuc->event_list[] (active events on= ly). + * Disabling an ACR event causes bit-shifting errors in the acr_mask of + * remaining group members. As ACR sampling requires all events to be act= ive, + * this limitation is acceptable for now. Revisit if independent event to= ggling + * is required. + */ for (i =3D 0; i < cpuc->n_events; i++) { leader =3D cpuc->event_list[i]; if (!is_acr_event_group(leader)) continue; =20 - /* The ACR events must be contiguous. */ + /* Find the last event of the ACR group. */ for (j =3D i; j < cpuc->n_events; j++) { event =3D cpuc->event_list[j]; if (event->group_leader !=3D leader->group_leader) break; - for_each_set_bit(idx, (unsigned long *)&event->attr.config2, X86_PMC_ID= X_MAX) { - if (i + idx >=3D cpuc->n_events || - !is_acr_event_group(cpuc->event_list[i + idx])) - return; - __set_bit(cpuc->assign[i + idx], (unsigned long *)&event->hw.config1); + } + + /* + * Translate the user-space ACR mask (attr.config2) into the physical + * counter bitmask (hw.config1) for each ACR event in the group. + * NOTE: ACR event contiguity is guaranteed by intel_pmu_hw_config(). + */ + for (k =3D i; k < j; k++) { + event =3D cpuc->event_list[k]; + event->hw.config1 =3D 0; + for_each_set_bit(bit, (unsigned long *)&event->attr.config2, X86_PMC_ID= X_MAX) { + idx =3D i + bit; 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d="scan'208";a="234455202" Received: from spr.sh.intel.com ([10.112.229.196]) by orviesa009.jf.intel.com with ESMTP; 29 Apr 2026 17:30:54 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , Dapeng Mi , stable@vger.kernel.org Subject: [Patch v4 2/5] perf/x86/intel: Always reprogram ACR events to prevent stale masks Date: Thu, 30 Apr 2026 08:25:55 +0800 Message-Id: <20260430002558.712334-3-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260430002558.712334-1-dapeng1.mi@linux.intel.com> References: <20260430002558.712334-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Members of an ACR group are logically linked via a bitmask of their hardware counter indices. If some members of the group are assigned new hardware counters during rescheduling, even events that keep their original counter index must be updated with a new mask. Without this, an event will continue to use a stale acr_mask that references the old indices of its group peers. Ensure all ACR events are reprogrammed during the scheduling path to maintain consistency across the group. Cc: stable@vger.kernel.org Fixes: ec980e4facef ("perf/x86/intel: Support auto counter reload") Signed-off-by: Dapeng Mi --- V4: new patch. arch/x86/events/core.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 03ce1bc7ef2e..e766621f9449 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -1294,13 +1294,16 @@ int x86_perf_rdpmc_index(struct perf_event *event) return event->hw.event_base_rdpmc; } =20 -static inline int match_prev_assignment(struct hw_perf_event *hwc, +static inline int match_prev_assignment(struct perf_event *event, struct cpu_hw_events *cpuc, int i) { + struct hw_perf_event *hwc =3D &event->hw; + return hwc->idx =3D=3D cpuc->assign[i] && - hwc->last_cpu =3D=3D smp_processor_id() && - hwc->last_tag =3D=3D cpuc->tags[i]; + hwc->last_cpu =3D=3D smp_processor_id() && + hwc->last_tag =3D=3D cpuc->tags[i] && + !is_acr_event_group(event); } =20 static void x86_pmu_start(struct perf_event *event, int flags); @@ -1346,7 +1349,7 @@ static void x86_pmu_enable(struct pmu *pmu) * - no other event has used the counter since */ if (hwc->idx =3D=3D -1 || - match_prev_assignment(hwc, cpuc, i)) + match_prev_assignment(event, cpuc, i)) continue; =20 /* @@ -1367,7 +1370,7 @@ static void x86_pmu_enable(struct pmu *pmu) event =3D cpuc->event_list[i]; hwc =3D &event->hw; =20 - if (!match_prev_assignment(hwc, cpuc, i)) + if (!match_prev_assignment(event, cpuc, i)) x86_assign_hw_event(event, cpuc, i); else if (i < n_running) continue; --=20 2.34.1 From nobody Tue Jun 16 18:00:14 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF2321CAA68; Thu, 30 Apr 2026 00:31:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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d="scan'208";a="95873659" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 17:31:01 -0700 X-CSE-ConnectionGUID: iNfWsfHyQfuf9OgKrE0bAA== X-CSE-MsgGUID: Xlp0gTyOQ821XoC+KfV00Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,207,1770624000"; d="scan'208";a="234455208" Received: from spr.sh.intel.com ([10.112.229.196]) by orviesa009.jf.intel.com with ESMTP; 29 Apr 2026 17:30:58 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , Dapeng Mi , stable@vger.kernel.org Subject: [Patch v4 3/5] perf/x86/intel: Disable PMI for self-reloaded ACR events Date: Thu, 30 Apr 2026 08:25:56 +0800 Message-Id: <20260430002558.712334-4-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260430002558.712334-1-dapeng1.mi@linux.intel.com> References: <20260430002558.712334-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On platforms with Auto Counter Reload (ACR) support, such as NVL, a "NMI received for unknown reason 30" warning is observed when running multiple events in a group with ACR enabled: $ perf record -e '{instructions/period=3D20000,acr_mask=3D0x2/u,\ cycles/period=3D40000,acr_mask=3D0x3/u}' ./test The warning occurs because the Performance Monitoring Interrupt (PMI) is enabled for the self-reloaded event (the cycles event in this case). According to the Intel SDM, the overflow bit (IA32_PERF_GLOBAL_STATUS.PMCn_OVF) is never set for self-reloaded events. Since the bit is not set, the perf NMI handler cannot identify the source of the interrupt, leading to the "unknown reason" message. Furthermore, enabling PMI for self-reloaded events is unnecessary and can lead to extraneous records that pollute the user's requested data. Disable the interrupt bit for all events configured with ACR self-reload. Reported-by: Andi Kleen Cc: stable@vger.kernel.org Fixes: ec980e4facef ("perf/x86/intel: Support auto counter reload") Signed-off-by: Dapeng Mi --- arch/x86/events/intel/core.c | 17 +++++++++++++---- arch/x86/events/perf_event.h | 10 ++++++++++ 2 files changed, 23 insertions(+), 4 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index ca910e6bfc77..9e77d836b878 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3118,11 +3118,11 @@ static void intel_pmu_enable_fixed(struct perf_even= t *event) intel_set_masks(event, idx); =20 /* - * Enable IRQ generation (0x8), if not PEBS, - * and enable ring-3 counting (0x2) and ring-0 counting (0x1) - * if requested: + * Enable IRQ generation (0x8), if not PEBS or self-reloaded + * ACR event, and enable ring-3 counting (0x2) and ring-0 + * counting (0x1) if requested: */ - if (!event->attr.precise_ip) + if (!event->attr.precise_ip && !is_acr_self_reload_event(event)) bits |=3D INTEL_FIXED_0_ENABLE_PMI; if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) bits |=3D INTEL_FIXED_0_USER; @@ -3306,6 +3306,15 @@ static void intel_pmu_enable_event(struct perf_event= *event) intel_set_masks(event, idx); static_call_cond(intel_pmu_enable_acr_event)(event); static_call_cond(intel_pmu_enable_event_ext)(event); + /* + * For self-reloaded ACR event, don't enable PMI since + * HW won't set overflow bit in GLOBAL_STATUS. Otherwise, + * the PMI would be recognized as a suspicious NMI. + */ + if (is_acr_self_reload_event(event)) + hwc->config &=3D ~ARCH_PERFMON_EVENTSEL_INT; + else if (!event->attr.precise_ip) + hwc->config |=3D ARCH_PERFMON_EVENTSEL_INT; __x86_pmu_enable_event(hwc, enable_mask); break; case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index fad87d3c8b2c..524668dcf4cc 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -137,6 +137,16 @@ static inline bool is_acr_event_group(struct perf_even= t *event) return check_leader_group(event->group_leader, PERF_X86_EVENT_ACR); } =20 +static inline bool is_acr_self_reload_event(struct perf_event *event) +{ + struct hw_perf_event *hwc =3D &event->hw; + + if (hwc->idx < 0) + return false; + + return test_bit(hwc->idx, (unsigned long *)&hwc->config1); +} + struct amd_nb { int nb_id; /* NorthBridge id */ int refcnt; /* reference count */ --=20 2.34.1 From nobody Tue Jun 16 18:00:14 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B22661A682F; Thu, 30 Apr 2026 00:31:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777509065; cv=none; b=fMur9HnKnSGGM+2nVQPUCIevPMAJ9sR9SpUimM2pHd20Pc5MaF6u3wE3byxV+fP/L/HZjrZMDIm0aYRnM8hEHiU46whs8Fo9aZrf418xy2PqBc8hUrAmrWNKdIXU/PmDLNdKQAiLhqocjC5/M3ff85IvuVtOiLpQ3iB+eu4TBJ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777509065; c=relaxed/simple; bh=qwSIvUAIHquGWy/otod5pyn/mc/Z6mxdBqjoaK+pMr8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=DLRaK2oLUPPVSd/5TEI4+Fadqo4MGDBmiw0inuX78ZddopoKdJ3rBrsIdqt8kJlEKbWPHWNSaVXp0ylUauQfcRrDnvh+FmC1J03WUQV53lu/U78Pjp5WSrVfWJ0Eetq1fMQf3rmgETJatH9aLkF3CrMfExyNC2paCB3CyMzqW78= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=CTBVTM2M; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="CTBVTM2M" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777509065; x=1809045065; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qwSIvUAIHquGWy/otod5pyn/mc/Z6mxdBqjoaK+pMr8=; b=CTBVTM2MwT5jxB6bRUjKFW+xBuougqt1mjQoo4tGzUzRcb4DKOqPdqAW nBbUxZrK4OZGIdj/XXEdAHzRCHUEzTSptQ4oieAl9159GnQl7zImDMj68 6oDrJubz9SJGAehX/c28FN0Kfn1ye6mPwT4lK4HRTi4K1LSoqYpsnz0Ny JOBPi8M3b2fC+4/+4vzYos2OXCLszzoIYhtDuWSuiZqwOgWcMnQZuGCwB d3rMgAW3RTH0JPhXX9ei9ov7mONoKvD95tEbaODAa07uPHNir9Wky2n88 LZkPU923rU214FAp+UzNF9zW0llS+NZoznuqk9bTjQs4AXfzwAh4pbJIM w==; X-CSE-ConnectionGUID: bWjKF9vHQUSmwMFTwK1ZFg== X-CSE-MsgGUID: CWB3pJWPQF23qyrNefcWrA== X-IronPort-AV: E=McAfee;i="6800,10657,11771"; a="95873673" X-IronPort-AV: E=Sophos;i="6.23,207,1770624000"; d="scan'208";a="95873673" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 17:31:05 -0700 X-CSE-ConnectionGUID: BYLsI6v7SCOvlFBCuH+eYQ== X-CSE-MsgGUID: D9tDnfB2TF2iQnbRaGUWxA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,207,1770624000"; d="scan'208";a="234455212" Received: from spr.sh.intel.com ([10.112.229.196]) by orviesa009.jf.intel.com with ESMTP; 29 Apr 2026 17:31:01 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , Dapeng Mi , stable@vger.kernel.org Subject: [Patch v4 4/5] perf/x86/intel: Enable auto counter reload for DMR Date: Thu, 30 Apr 2026 08:25:57 +0800 Message-Id: <20260430002558.712334-5-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260430002558.712334-1-dapeng1.mi@linux.intel.com> References: <20260430002558.712334-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Panther cove =C2=B5arch starts to support auto counter reload (ACR), but the static_call intel_pmu_enable_acr_event() is not updated for the Panther Cove =C2=B5arch used by DMR. It leads to the auto counter reload is not really enabled on DMR. Update static_call intel_pmu_enable_acr_event() in intel_pmu_init_pnc(). Cc: stable@vger.kernel.org Fixes: d345b6bb8860 ("perf/x86/intel: Add core PMU support for DMR") Signed-off-by: Dapeng Mi --- arch/x86/events/intel/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 9e77d836b878..4d5c35f0df5c 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -7518,6 +7518,7 @@ static __always_inline void intel_pmu_init_pnc(struct= pmu *pmu) hybrid(pmu, event_constraints) =3D intel_pnc_event_constraints; hybrid(pmu, pebs_constraints) =3D intel_pnc_pebs_event_constraints; hybrid(pmu, extra_regs) =3D intel_pnc_extra_regs; + static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr); } =20 static __always_inline void intel_pmu_init_skt(struct pmu *pmu) --=20 2.34.1 From nobody Tue Jun 16 18:00:14 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65D911DDC28; Thu, 30 Apr 2026 00:31:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777509069; cv=none; b=Fi4WzuxkZfv84Kcs08/Wpvu7RkftKnbdS+I1jdxHWHmiadBCbsCD4LcYBbftIO5pzyJYzEMvOcWzsaC0HVJEUPR550eH7QoBjCqBvDZ+KcTUypflNl4ugZmJNzFIi2Z1hxEZsi6S8OvEIWa5kfBN6LrSBB5tfMmpDn3ckwBSS8w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777509069; c=relaxed/simple; bh=C1vm2Lj8334MDFPdH93Q3JfYi9FSc8bx0eqzAEFttMw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YH+fgvo5mhMnljoyZ8Sf58CNUQl+dv4t6ukjwEOIkuWoPic76gTHjBJPd90dup9qH+dVR7AQ14IM3udwHR/2voocI67gTfTPwEPaqp1tzScRdudJ35TIv3C/YY+ZJUFdpsBPrsdL0XNXYXVQVgJb7O780w7eByxHvQpgtPAn2QI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=DfbPrW22; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="DfbPrW22" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777509068; x=1809045068; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=C1vm2Lj8334MDFPdH93Q3JfYi9FSc8bx0eqzAEFttMw=; b=DfbPrW22lhha7Q2EN2QsTx2npp/A+aSkniWacjMGKHP/uudFclGjk+Ru yJvvAai7u71IVCr23w3x/OFPmSLCbvN32wQ2GF++jZ/XQD1mzb001voDf owItVMlrT91a5vONK5zl7pTKd//Pd2xu7aH5R87ZI7LQIoaZr4Y9OJdP6 2UNs8hX/CWdk8XysCnaLd8D66UNaJ5ARD3X1N92pURZwOGGUKtbPAAt/S DgsLVJoYLa+hHRs6whcfmYZCZzsTyBnk7DOqfCFuiVMT+MooPg0RJPTg4 zWbYdSUH8xr+6sraBPIEXVeVnpYMsqjB70lk6Wq5oMAMEu/BgR6fZPQvg w==; X-CSE-ConnectionGUID: sF3HZtl4ToO1Zse34yzA/A== X-CSE-MsgGUID: TKD/MWRoSiu93sApNgFENQ== X-IronPort-AV: E=McAfee;i="6800,10657,11771"; a="95873681" X-IronPort-AV: E=Sophos;i="6.23,207,1770624000"; d="scan'208";a="95873681" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 17:31:08 -0700 X-CSE-ConnectionGUID: jGdR1d8PTSezYmZgBqYKrw== X-CSE-MsgGUID: YC+oBq+2QDCZae3+cP0D0w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,207,1770624000"; d="scan'208";a="234455218" Received: from spr.sh.intel.com ([10.112.229.196]) by orviesa009.jf.intel.com with ESMTP; 29 Apr 2026 17:31:05 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , Dapeng Mi Subject: [Patch v4 5/5] perf/x86/intel: Consolidate MSR_IA32_PERF_CFG_C tracking Date: Thu, 30 Apr 2026 08:25:58 +0800 Message-Id: <20260430002558.712334-6-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260430002558.712334-1-dapeng1.mi@linux.intel.com> References: <20260430002558.712334-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Both Auto Counter Reload (ACR) and Architectural PEBS use the PERF_CFG_C MSRs to configure event behavior. Currently, the driver maintains two independent variables acr_cfg_c and cfg_c_val to cache the values intended for these MSRs. Using separate variables to track a single hardware register state is error-prone and can lead to configuration conflicts. Consolidate the tracking into a single cfg_c_val variable to ensure a unified and consistent view of the PERF_CFG_C MSR state. Signed-off-by: Dapeng Mi --- arch/x86/events/intel/core.c | 13 +++++++------ arch/x86/events/perf_event.h | 4 +--- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 4d5c35f0df5c..e05e1aad989e 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3169,10 +3169,10 @@ static void intel_pmu_config_acr(int idx, u64 mask,= u32 reload) wrmsrl(msr_b + msr_offset, mask); cpuc->acr_cfg_b[idx] =3D mask; } - /* Only need to update the reload value when there is a valid config valu= e. */ - if (mask && cpuc->acr_cfg_c[idx] !=3D reload) { + /* Only update CFG_C reload when ACR is actively enabled (mask !=3D 0) */ + if (mask && ((cpuc->cfg_c_val[idx] & ARCH_PEBS_RELOAD) !=3D reload)) { wrmsrl(msr_c + msr_offset, reload); - cpuc->acr_cfg_c[idx] =3D reload; + cpuc->cfg_c_val[idx] =3D reload; } } =20 @@ -3198,14 +3198,15 @@ static void intel_pmu_enable_event_ext(struct perf_= event *event) { struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); struct hw_perf_event *hwc =3D &event->hw; - union arch_pebs_index old, new; - struct arch_pebs_cap cap; u64 ext =3D 0; =20 - cap =3D hybrid(cpuc->pmu, arch_pebs_cap); + if (is_acr_event_group(event)) + ext |=3D (-hwc->sample_period) & ARCH_PEBS_RELOAD; =20 if (event->attr.precise_ip) { u64 pebs_data_cfg =3D intel_get_arch_pebs_data_config(event); + struct arch_pebs_cap cap =3D hybrid(cpuc->pmu, arch_pebs_cap); + union arch_pebs_index old, new; =20 ext |=3D ARCH_PEBS_EN; if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 524668dcf4cc..40d6fe0afc4a 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -322,10 +322,8 @@ struct cpu_hw_events { u64 fixed_ctrl_val; u64 active_fixed_ctrl_val; =20 - /* Intel ACR configuration */ + /* Intel ACR/arch-PEBS configuration */ u64 acr_cfg_b[X86_PMC_IDX_MAX]; - u64 acr_cfg_c[X86_PMC_IDX_MAX]; - /* Cached CFG_C values */ u64 cfg_c_val[X86_PMC_IDX_MAX]; =20 /* --=20 2.34.1