From nobody Sun Jun 14 07:49:21 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11C882770A; Fri, 1 May 2026 06:38:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777617513; cv=none; b=AsXRE+EMzjlKJyY3ZxiGEAA35VilKsCoXU9zZcveH/xl4MG2PwW+uVQ7xzdLInaPgcRHWqz7nM0pcKfx/W9CRTj9u1/CrWi9lvXeDra25Jha+VnBJD8JorbXyZnEQv1od0SbIxiiZ1tWoVFi420hzc8NNc6KXBMJnxnV1NMoBHA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777617513; c=relaxed/simple; bh=XSYe7jkpijRWFzoQHobj2J+nayL2ngnYFQd8umnnDPE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BLbdjnhqheADp4OIsvKwuDaoCQ4nN4ZSOog3+eO27GiKkFJZofjnldSdm0jK38rJLhecyWZY1OdNptC6FH7g/tyuOJ6fsutR80Ttvjua7kx7LKu2Q2FXQy3q5gq2xE1T8GfOcz0Q9P6Ol/E0gO9e/1lcuJK9ViHOCMZIW8zu+G0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=FKujK0Nu; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="FKujK0Nu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777617512; x=1809153512; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=XSYe7jkpijRWFzoQHobj2J+nayL2ngnYFQd8umnnDPE=; b=FKujK0NuV6MGXk5LEX5lOxlqMUg6bKwoYJ7WcatiudTwsCfb2eP4oBff ECcdVjmzq0jdnsyC/zPI1vhNHqsYPyQhnNNupYJk37SeX2wKVLqdLuBD6 ViysbssgIa+MzbeTe5CpZrTGe6fvOcpBrRmVSJmXFzKD/TuHI+TNQVNLQ WXBjQ4sNBJz7NdoJnysotyC9x07tDUjofa104lGcxcwaChf9XfH82oc+X MRqyC8xYotgAxk53I7+Kdwdk8i7pDU1egtDoSTe+fnjbve9FFD6GUNsQB Kwf8U6F9mHHBf0rOGrpcRFZPURCLI1g2B/vFgSkuVLY6Z5kUFWYeHH8B8 g==; X-CSE-ConnectionGUID: qitlHOdYSc+TBl1tHQzj9g== X-CSE-MsgGUID: 76FHRBn7SMa4MUXXptowWQ== X-IronPort-AV: E=McAfee;i="6800,10657,11772"; a="89271858" X-IronPort-AV: E=Sophos;i="6.23,209,1770624000"; d="scan'208";a="89271858" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2026 23:38:31 -0700 X-CSE-ConnectionGUID: cGAuR70URKuVIFC3mPJeAw== X-CSE-MsgGUID: 3PiMGmLdQuC8QTGONu3KzQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,209,1770624000"; d="scan'208";a="233752839" Received: from orcnseosdtjek.jf.intel.com (HELO [10.166.28.109]) ([10.166.28.109]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2026 23:38:31 -0700 From: Jacob Keller Date: Thu, 30 Apr 2026 23:37:12 -0700 Subject: [PATCH net-next 01/15] ixgbe: E610: add discovering EEE capability Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260430-jk-iwl-net-next-2026-04-30-v1-1-6f27ae1cd073@intel.com> References: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> In-Reply-To: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> To: Przemek Kitszel , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexander Lobakin , Simon Horman , Michal Swiatkowski , Jedrzej Jagielski , Aleksandr Loktionov , Grzegorz Nitka , Ivan Vecera , Arkadiusz Kubalewski , Tony Nguyen , Stefan Wegrzyn Cc: Piotr Kwapulinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Jacob Keller , Rinitha S X-Mailer: b4 0.16-dev-ea14f X-Developer-Signature: v=1; a=openpgp-sha256; l=2432; i=jacob.e.keller@intel.com; h=from:subject:message-id; bh=piRjMZsWjhPpWeIoF5aPcVpYYh7oDNAqZaQNX2L0ThE=; b=owGbwMvMwCWWNS3WLp9f4wXjabUkhswvXslbP++R3XPlcZVuiuej2aZC2SeTKmtOH9b3KD3+a dpd8x0+HaUsDGJcDLJiiiwKDiErrxtPCNN64ywHM4eVCWQIAxenAExktjLDPyuddqbHDncj+5oV Ful9eyfJdS0u/Abv5f8MkxedmN49K5SRofd9yuynBQVOcyQviXLq2AT1bsoJ1UjIDndOXPzctsy WDQA= X-Developer-Key: i=jacob.e.keller@intel.com; a=openpgp; fpr=204054A9D73390562AEC431E6A965D3E6F0F28E8 From: Jedrzej Jagielski Add detecting and parsing EEE device capability. Recently EEE functionality support has been introduced to E610 FW. Currently ixgbe driver has no possibility to detect whether NVM loaded on given adapter supports EEE. There's dedicated device capability element reflecting FW support for given EEE link speed. Reviewed-by: Aleksandr Loktionov Signed-off-by: Jedrzej Jagielski Tested-by: Rinitha S Signed-off-by: Jacob Keller --- drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h | 1 + include/linux/net/intel/libie/adminq.h | 1 + drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c | 3 +++ 3 files changed, 5 insertions(+) diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h b/drivers/n= et/ethernet/intel/ixgbe/ixgbe_type_e610.h index ff8d640a50b1..34f62a416eaa 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h @@ -891,6 +891,7 @@ struct ixgbe_hw_caps { u8 apm_wol_support; u8 acpi_prog_mthd; u8 proxy_support; + u8 eee_support; bool nvm_update_pending_nvm; bool nvm_update_pending_orom; bool nvm_update_pending_netlist; diff --git a/include/linux/net/intel/libie/adminq.h b/include/linux/net/int= el/libie/adminq.h index ab13bd777a28..839114d8975a 100644 --- a/include/linux/net/intel/libie/adminq.h +++ b/include/linux/net/intel/libie/adminq.h @@ -196,6 +196,7 @@ LIBIE_CHECK_STRUCT_LEN(16, libie_aqc_list_caps); #define LIBIE_AQC_BIT_ROCEV2_LAG BIT(0) #define LIBIE_AQC_BIT_SRIOV_LAG BIT(1) #define LIBIE_AQC_BIT_SRIOV_AA_LAG BIT(2) +#define LIBIE_AQC_CAPS_EEE 0x009B #define LIBIE_AQC_CAPS_FLEX10 0x00F1 #define LIBIE_AQC_CAPS_CEM 0x00F2 =20 diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c b/drivers/net/et= hernet/intel/ixgbe/ixgbe_e610.c index 52f73142ff75..5383f0fd55d6 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c @@ -628,6 +628,9 @@ static bool ixgbe_parse_e610_caps(struct ixgbe_hw *hw, (phys_id & IXGBE_EXT_TOPO_DEV_IMG_PROG_EN) !=3D 0; break; } + case LIBIE_AQC_CAPS_EEE: + caps->eee_support =3D (u8)number; + break; default: /* Not one of the recognized common capabilities */ return false; --=20 2.54.0.rc2.531.gaf818d63126a From nobody Sun Jun 14 07:49:21 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E89193603FC; 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a="89271865" X-IronPort-AV: E=Sophos;i="6.23,209,1770624000"; d="scan'208";a="89271865" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2026 23:38:32 -0700 X-CSE-ConnectionGUID: qAmWQXYHTx6HAvdJod5HcQ== X-CSE-MsgGUID: evdBjwuXRdmaDmNwv2OrSA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,209,1770624000"; d="scan'208";a="233752842" Received: from orcnseosdtjek.jf.intel.com (HELO [10.166.28.109]) ([10.166.28.109]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2026 23:38:31 -0700 From: Jacob Keller Date: Thu, 30 Apr 2026 23:37:13 -0700 Subject: [PATCH net-next 02/15] ixgbe: E610: update EEE supported speeds Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260430-jk-iwl-net-next-2026-04-30-v1-2-6f27ae1cd073@intel.com> References: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> In-Reply-To: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> To: Przemek Kitszel , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexander Lobakin , Simon Horman , Michal Swiatkowski , Jedrzej Jagielski , Aleksandr Loktionov , Grzegorz Nitka , Ivan Vecera , Arkadiusz Kubalewski , Tony Nguyen , Stefan Wegrzyn Cc: Piotr Kwapulinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Jacob Keller , Rinitha S X-Mailer: b4 0.16-dev-ea14f X-Developer-Signature: v=1; a=openpgp-sha256; l=2505; i=jacob.e.keller@intel.com; h=from:subject:message-id; bh=ac5X7jGfbRIkX633o+bauck12PclZCfVS7L27CYA9Sk=; b=owGbwMvMwCWWNS3WLp9f4wXjabUkhswvXsmasx49MXz4/fI315d7UmZt2HT9jnthulw8p4n0p n9XPnFN7ihlYRDjYpAVU2RRcAhZed14QpjWG2c5mDmsTCBDGLg4BWAidx0Z/ql86P3j99ZBtqpz TVjdlm/vzGL7I+Uvyof+Xn4j1YfFQovhn0Yjv8m526/qWyckqiSfmfH7h6nhFB2VVDuNrQnb/V8 o8QAA X-Developer-Key: i=jacob.e.keller@intel.com; a=openpgp; fpr=204054A9D73390562AEC431E6A965D3E6F0F28E8 From: Jedrzej Jagielski Despite there was no EEE (Energy Efficient Ethernet) feature support for E610 adapters, eee_speeds_supported variable was defined and even initialized with some EEE speeds. As E610 adapter supports EEE only for 10G, 5G and 2.5G speeds, update hw.phy.eee_speeds_supported. Remove unsupported speeds - 10M, 100M and 1G. Add also entry for 5G speed in EEE speeds mapping array used by ethtool callbacks. Reviewed-by: Aleksandr Loktionov Signed-off-by: Jedrzej Jagielski Tested-by: Rinitha S Signed-off-by: Jacob Keller --- drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c | 11 ++++++++--- drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c | 1 + 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c b/drivers/net/et= hernet/intel/ixgbe/ixgbe_e610.c index 5383f0fd55d6..097a3e1c67aa 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c @@ -1983,9 +1983,14 @@ int ixgbe_identify_phy_e610(struct ixgbe_hw *hw) /* Set PHY ID */ memcpy(&hw->phy.id, pcaps.phy_id_oui, sizeof(u32)); =20 - hw->phy.eee_speeds_supported =3D IXGBE_LINK_SPEED_10_FULL | - IXGBE_LINK_SPEED_100_FULL | - IXGBE_LINK_SPEED_1GB_FULL; + /* E610 supports EEE only for speeds above 1G */ + if (hw->device_id =3D=3D IXGBE_DEV_ID_E610_2_5G_T) + hw->phy.eee_speeds_supported =3D IXGBE_LINK_SPEED_2_5GB_FULL; + else + hw->phy.eee_speeds_supported =3D IXGBE_LINK_SPEED_2_5GB_FULL | + IXGBE_LINK_SPEED_5GB_FULL | + IXGBE_LINK_SPEED_10GB_FULL; + hw->phy.eee_speeds_advertised =3D hw->phy.eee_speeds_supported; =20 return 0; diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c b/drivers/net= /ethernet/intel/ixgbe/ixgbe_ethtool.c index ba049b3a9609..8450094a028a 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c @@ -3541,6 +3541,7 @@ static const struct { { IXGBE_LINK_SPEED_100_FULL, ETHTOOL_LINK_MODE_100baseT_Full_BIT }, { IXGBE_LINK_SPEED_1GB_FULL, ETHTOOL_LINK_MODE_1000baseT_Full_BIT }, { IXGBE_LINK_SPEED_2_5GB_FULL, ETHTOOL_LINK_MODE_2500baseX_Full_BIT }, + { IXGBE_LINK_SPEED_5GB_FULL, ETHTOOL_LINK_MODE_5000baseT_Full_BIT }, { IXGBE_LINK_SPEED_10GB_FULL, ETHTOOL_LINK_MODE_10000baseT_Full_BIT }, }; =20 --=20 2.54.0.rc2.531.gaf818d63126a From nobody Sun Jun 14 07:49:21 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 528FE3612F1; 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a="89271871" X-IronPort-AV: E=Sophos;i="6.23,209,1770624000"; d="scan'208";a="89271871" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2026 23:38:32 -0700 X-CSE-ConnectionGUID: BOgQoVRPRmW7uUcUo9HtBg== X-CSE-MsgGUID: AkbmK7AFTB20KGgmlSQC7Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,209,1770624000"; d="scan'208";a="233752845" Received: from orcnseosdtjek.jf.intel.com (HELO [10.166.28.109]) ([10.166.28.109]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2026 23:38:31 -0700 From: Jacob Keller Date: Thu, 30 Apr 2026 23:37:14 -0700 Subject: [PATCH net-next 03/15] ixgbe: E610: use new version of 0x601 ACI command buffer Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260430-jk-iwl-net-next-2026-04-30-v1-3-6f27ae1cd073@intel.com> References: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> In-Reply-To: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> To: Przemek Kitszel , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexander Lobakin , Simon Horman , Michal Swiatkowski , Jedrzej Jagielski , Aleksandr Loktionov , Grzegorz Nitka , Ivan Vecera , Arkadiusz Kubalewski , Tony Nguyen , Stefan Wegrzyn Cc: Piotr Kwapulinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Jacob Keller , Rinitha S X-Mailer: b4 0.16-dev-ea14f X-Developer-Signature: v=1; a=openpgp-sha256; l=3974; i=jacob.e.keller@intel.com; h=from:subject:message-id; bh=eT9FxPmW9pvzrJeiT+itWKYrV3DwGwVXyQO9Di1PaE4=; b=owGbwMvMwCWWNS3WLp9f4wXjabUkhswvXskFvCf4X+53dODK7JquN1lQqstl14Ga6onfoytUL t84rfa2o5SFQYyLQVZMkUXBIWTldeMJYVpvnOVg5rAygQxh4OIUgIlkHWL4Kzgz2+W/E3+67o2I 46m/n2+bw3Ar+Bf3p1XRn2/E2nSaxjP8z/1wSf7R5fX7RCt69l0Ibot82bZT69KsAAmWDOUfDsX rOQE= X-Developer-Key: i=jacob.e.keller@intel.com; a=openpgp; fpr=204054A9D73390562AEC431E6A965D3E6F0F28E8 From: Jedrzej Jagielski Since FW version 1.40, buffer size of the 0x601 cmd has been increased by 2B - from 24 to 26B. Buffer has been extended with new field which can be used to configure EEE entry delay. Pre-1.40 FW versions still expect 24B buffer and throws error when receipts 26B buffer. To keep compatibility, check whether EEE device capability flag is set and basing on it use appropriate size of the command buffer. Additionally place Set PHY Config capabilities defines out of structs definitions. Reviewed-by: Aleksandr Loktionov Reviewed-by: Przemek Kitszel Signed-off-by: Jedrzej Jagielski Tested-by: Rinitha S Signed-off-by: Jacob Keller --- drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h | 15 +++++++++------ drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c | 17 ++++++++++++++++- 2 files changed, 25 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h b/drivers/n= et/ethernet/intel/ixgbe/ixgbe_type_e610.h index 34f62a416eaa..cfaaf2fcf7ae 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h @@ -382,6 +382,15 @@ struct ixgbe_aci_cmd_set_phy_cfg_data { __le64 phy_type_low; /* Use values from IXGBE_PHY_TYPE_LOW_* */ __le64 phy_type_high; /* Use values from IXGBE_PHY_TYPE_HIGH_* */ u8 caps; + u8 low_power_ctrl_an; + __le16 eee_cap; /* Value from ixgbe_aci_get_phy_caps */ + __le16 eeer_value; /* Use defines from ixgbe_aci_get_phy_caps */ + u8 link_fec_opt; /* Use defines from ixgbe_aci_get_phy_caps */ + u8 module_compliance_enforcement; + __le16 eee_entry_delay; +} __packed; + +/* Set PHY config capabilities (@caps) defines */ #define IXGBE_ACI_PHY_ENA_VALID_MASK 0xef #define IXGBE_ACI_PHY_ENA_TX_PAUSE_ABILITY BIT(0) #define IXGBE_ACI_PHY_ENA_RX_PAUSE_ABILITY BIT(1) @@ -390,12 +399,6 @@ struct ixgbe_aci_cmd_set_phy_cfg_data { #define IXGBE_ACI_PHY_ENA_AUTO_LINK_UPDT BIT(5) #define IXGBE_ACI_PHY_ENA_LESM BIT(6) #define IXGBE_ACI_PHY_ENA_AUTO_FEC BIT(7) - u8 low_power_ctrl_an; - __le16 eee_cap; /* Value from ixgbe_aci_get_phy_caps */ - __le16 eeer_value; /* Use defines from ixgbe_aci_get_phy_caps */ - u8 link_fec_opt; /* Use defines from ixgbe_aci_get_phy_caps */ - u8 module_compliance_enforcement; -}; =20 /* Restart AN command data structure (direct 0x0605) * Also used for response, with only the lport_num field present. diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c b/drivers/net/et= hernet/intel/ixgbe/ixgbe_e610.c index 097a3e1c67aa..2703207a9efa 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c @@ -1096,11 +1096,16 @@ int ixgbe_aci_set_phy_cfg(struct ixgbe_hw *hw, { struct ixgbe_aci_cmd_set_phy_cfg *cmd; struct libie_aq_desc desc; + bool use_buff_eee_field; + u16 buf_size; int err; =20 if (!cfg) return -EINVAL; =20 + /* If FW supports EEE, we have to use buffer with EEE field. */ + use_buff_eee_field =3D hw->dev_caps.common_cap.eee_support; + cmd =3D libie_aq_raw(&desc); /* Ensure that only valid bits of cfg->caps can be turned on. */ cfg->caps &=3D IXGBE_ACI_PHY_ENA_VALID_MASK; @@ -1109,7 +1114,17 @@ int ixgbe_aci_set_phy_cfg(struct ixgbe_hw *hw, cmd->lport_num =3D hw->bus.func; desc.flags |=3D cpu_to_le16(LIBIE_AQ_FLAG_RD); =20 - err =3D ixgbe_aci_send_cmd(hw, &desc, cfg, sizeof(*cfg)); + if (use_buff_eee_field) + buf_size =3D sizeof(*cfg); + else + /* Buffer w/o eee_entry_delay field is 2B smaller. */ + buf_size =3D sizeof(*cfg) - sizeof(u16); + + err =3D ixgbe_aci_send_cmd(hw, &desc, cfg, buf_size); + + /* 1.40 config format is compatible with pre-1.40, just extends + * it at the end. + */ if (!err) hw->phy.curr_user_phy_cfg =3D *cfg; =20 --=20 2.54.0.rc2.531.gaf818d63126a From nobody Sun Jun 14 07:49:21 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7768736167B; 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a="89271880" X-IronPort-AV: E=Sophos;i="6.23,209,1770624000"; d="scan'208";a="89271880" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2026 23:38:32 -0700 X-CSE-ConnectionGUID: qvAXxiR2RaG1gA1zNFcW6g== X-CSE-MsgGUID: SO51vtIGR+efTcW0+vsFZg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,209,1770624000"; d="scan'208";a="233752848" Received: from orcnseosdtjek.jf.intel.com (HELO [10.166.28.109]) ([10.166.28.109]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2026 23:38:31 -0700 From: Jacob Keller Date: Thu, 30 Apr 2026 23:37:15 -0700 Subject: [PATCH net-next 04/15] ixgbe: E610: update ACI command structs with EEE fields Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260430-jk-iwl-net-next-2026-04-30-v1-4-6f27ae1cd073@intel.com> References: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> In-Reply-To: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> To: Przemek Kitszel , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexander Lobakin , Simon Horman , Michal Swiatkowski , Jedrzej Jagielski , Aleksandr Loktionov , Grzegorz Nitka , Ivan Vecera , Arkadiusz Kubalewski , Tony Nguyen , Stefan Wegrzyn Cc: Piotr Kwapulinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Jacob Keller , Rinitha S X-Mailer: b4 0.16-dev-ea14f X-Developer-Signature: v=1; a=openpgp-sha256; l=3625; i=jacob.e.keller@intel.com; h=from:subject:message-id; bh=xlP/+hUtsf9ohCh8KeWrPSIgij8iWN/pG/B9r5XKl08=; b=owGbwMvMwCWWNS3WLp9f4wXjabUkhswvXskSO/qaBWuUCphDCqbuuVCZv9Y7ufNG4Hq7dt1vv yYv97TvKGVhEONikBVTZFFwCFl53XhCmNYbZzmYOaxMIEMYuDgFYCKihxj+GQlXzmw8aXXf79O8 g0zW/X3V91OiA57Kf/6X73fsf57xNob/vlbz4g5vjbRgnBMkK3fvxYHv7/3mzDy8eX2C3O7vsf2 y/AA= X-Developer-Key: i=jacob.e.keller@intel.com; a=openpgp; fpr=204054A9D73390562AEC431E6A965D3E6F0F28E8 From: Jedrzej Jagielski There were recent changes in some of the ACI commands, which have been extended with EEE related fields. Set PHY Config, Get PHY Caps and Get Link Info have been affected. Align SW structs to the recent FW changes. Reviewed-by: Aleksandr Loktionov Signed-off-by: Jedrzej Jagielski Tested-by: Rinitha S Signed-off-by: Jacob Keller --- drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h | 16 +++++++++------- drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c | 2 ++ 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h b/drivers/n= et/ethernet/intel/ixgbe/ixgbe_type_e610.h index cfaaf2fcf7ae..959cacecae49 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h @@ -323,10 +323,8 @@ struct ixgbe_aci_cmd_get_phy_caps_data { #define IXGBE_ACI_PHY_EEE_EN_100BASE_TX BIT(0) #define IXGBE_ACI_PHY_EEE_EN_1000BASE_T BIT(1) #define IXGBE_ACI_PHY_EEE_EN_10GBASE_T BIT(2) -#define IXGBE_ACI_PHY_EEE_EN_1000BASE_KX BIT(3) -#define IXGBE_ACI_PHY_EEE_EN_10GBASE_KR BIT(4) -#define IXGBE_ACI_PHY_EEE_EN_25GBASE_KR BIT(5) -#define IXGBE_ACI_PHY_EEE_EN_10BASE_T BIT(11) +#define IXGBE_ACI_PHY_EEE_EN_5GBASE_T BIT(11) +#define IXGBE_ACI_PHY_EEE_EN_2_5GBASE_T BIT(12) __le16 eeer_value; u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ u8 phy_fw_ver[8]; @@ -356,7 +354,9 @@ struct ixgbe_aci_cmd_get_phy_caps_data { #define IXGBE_ACI_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 #define IXGBE_ACI_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 u8 qualified_module_count; - u8 rsvd2[7]; /* Bytes 47:41 reserved */ + u8 rsvd2; + __le16 eee_entry_delay; + u8 rsvd3[4]; #define IXGBE_ACI_QUAL_MOD_COUNT_MAX 16 struct { u8 v_oui[3]; @@ -512,8 +512,9 @@ struct ixgbe_aci_cmd_get_link_status_data { #define IXGBE_ACI_LINK_SPEED_200GB BIT(11) #define IXGBE_ACI_LINK_SPEED_UNKNOWN BIT(15) __le16 reserved3; - u8 ext_fec_status; -#define IXGBE_ACI_LINK_RS_272_FEC_EN BIT(0) /* RS 272 FEC enabled */ + u8 eee_status; +#define IXGBE_ACI_LINK_EEE_ENABLED BIT(2) +#define IXGBE_ACI_LINK_EEE_ACTIVE BIT(3) u8 reserved4; __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ @@ -815,6 +816,7 @@ struct ixgbe_link_status { * of ixgbe_aci_get_phy_caps structure */ u8 module_type[IXGBE_ACI_MODULE_TYPE_TOTAL_BYTE]; + u8 eee_status; }; =20 /* Common HW capabilities for SW use */ diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c b/drivers/net/et= hernet/intel/ixgbe/ixgbe_e610.c index 2703207a9efa..a01d991ee2e0 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c @@ -1076,6 +1076,7 @@ void ixgbe_copy_phy_caps_to_cfg(struct ixgbe_aci_cmd_= get_phy_caps_data *caps, cfg->link_fec_opt =3D caps->link_fec_options; cfg->module_compliance_enforcement =3D caps->module_compliance_enforcement; + cfg->eee_entry_delay =3D caps->eee_entry_delay; } =20 /** @@ -1404,6 +1405,7 @@ int ixgbe_aci_get_link_info(struct ixgbe_hw *hw, bool= ena_lse, li->topo_media_conflict =3D link_data.topo_media_conflict; li->pacing =3D link_data.cfg & (IXGBE_ACI_CFG_PACING_M | IXGBE_ACI_CFG_PACING_TYPE_M); + li->eee_status =3D link_data.eee_status; =20 /* Update fc info. */ tx_pause =3D !!(link_data.an_info & IXGBE_ACI_LINK_PAUSE_TX); --=20 2.54.0.rc2.531.gaf818d63126a From nobody Sun Jun 14 07:49:21 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F05C364045; 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a="89271887" X-IronPort-AV: E=Sophos;i="6.23,209,1770624000"; d="scan'208";a="89271887" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2026 23:38:32 -0700 X-CSE-ConnectionGUID: /NXGYkg1Ti6YL3hiPKVfFg== X-CSE-MsgGUID: CvQazrnjT8qQa1nTL2EHGA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,209,1770624000"; d="scan'208";a="233752852" Received: from orcnseosdtjek.jf.intel.com (HELO [10.166.28.109]) ([10.166.28.109]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2026 23:38:31 -0700 From: Jacob Keller Date: Thu, 30 Apr 2026 23:37:16 -0700 Subject: [PATCH net-next 05/15] ixgbe: move EEE config validation out of ixgbe_set_eee() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260430-jk-iwl-net-next-2026-04-30-v1-5-6f27ae1cd073@intel.com> References: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> In-Reply-To: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> To: Przemek Kitszel , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexander Lobakin , Simon Horman , Michal Swiatkowski , Jedrzej Jagielski , Aleksandr Loktionov , Grzegorz Nitka , Ivan Vecera , Arkadiusz Kubalewski , Tony Nguyen , Stefan Wegrzyn Cc: Piotr Kwapulinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Jacob Keller , Rinitha S X-Mailer: b4 0.16-dev-ea14f X-Developer-Signature: v=1; a=openpgp-sha256; l=4123; i=jacob.e.keller@intel.com; h=from:subject:message-id; bh=+UYOBw1om1HhT8Rq1KbBklwfxBv/e5K+mQfxVIFcl9I=; b=owGbwMvMwCWWNS3WLp9f4wXjabUkhswvXikS/8Ty7+6smcPo57puc5liS5LSDhshlQ2LnqdsF uwy0ebpKGVhEONikBVTZFFwCFl53XhCmNYbZzmYOaxMIEMYuDgFYCJvLzH8j0lovn+XSe+qWstU w+obu6P25TUEs0y8NkWin42jKXx9PyND+z2Z+GJuLfn4zY5nK+WTmgwnWiXfYmR47yBYv+askiA LAA== X-Developer-Key: i=jacob.e.keller@intel.com; a=openpgp; fpr=204054A9D73390562AEC431E6A965D3E6F0F28E8 From: Jedrzej Jagielski To make this part of the code mode reusable move all EEE input checks out of ixgbe_set_eee(). Reviewed-by: Aleksandr Loktionov Signed-off-by: Jedrzej Jagielski Tested-by: Rinitha S Signed-off-by: Jacob Keller --- drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c | 98 ++++++++++++++------= ---- 1 file changed, 57 insertions(+), 41 deletions(-) diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c b/drivers/net= /ethernet/intel/ixgbe/ixgbe_ethtool.c index 8450094a028a..186345933f3f 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c @@ -3557,6 +3557,47 @@ static const struct { { FW_PHY_ACT_UD_2_10G_KR_EEE, ETHTOOL_LINK_MODE_10000baseKR_Full_BIT}, }; =20 +static int ixgbe_validate_keee(struct net_device *netdev, + struct ethtool_keee *keee_requested) +{ + struct ixgbe_adapter *adapter =3D ixgbe_from_netdev(netdev); + struct ethtool_keee keee_stored =3D {}; + int err; + + if (!(adapter->flags2 & IXGBE_FLAG2_EEE_CAPABLE)) + return -EOPNOTSUPP; + + err =3D netdev->ethtool_ops->get_eee(netdev, &keee_stored); + if (err) + return err; + + if (keee_stored.tx_lpi_enabled !=3D keee_requested->tx_lpi_enabled) { + e_err(drv, "Setting EEE tx-lpi is not supported\n"); + return -EINVAL; + } + + if (keee_stored.tx_lpi_timer !=3D keee_requested->tx_lpi_timer) { + e_err(drv, + "Setting EEE Tx LPI timer is not supported\n"); + return -EINVAL; + } + + if (!linkmode_equal(keee_stored.advertised, + keee_requested->advertised)) { + e_err(drv, + "Setting EEE advertised speeds is not supported\n"); + return -EINVAL; + } + + /* -EALREADY here is for internal use only, must be converted into + * early bail out with 0 by caller + */ + if (keee_stored.eee_enabled =3D=3D keee_requested->eee_enabled) + return -EALREADY; + + return 0; +} + static int ixgbe_get_eee_fw(struct ixgbe_adapter *adapter, struct ethtool_keee *edata) { @@ -3615,53 +3656,28 @@ static int ixgbe_set_eee(struct net_device *netdev,= struct ethtool_keee *edata) { struct ixgbe_adapter *adapter =3D ixgbe_from_netdev(netdev); struct ixgbe_hw *hw =3D &adapter->hw; - struct ethtool_keee eee_data; int ret_val; =20 - if (!(adapter->flags2 & IXGBE_FLAG2_EEE_CAPABLE)) - return -EOPNOTSUPP; - - memset(&eee_data, 0, sizeof(struct ethtool_keee)); - - ret_val =3D ixgbe_get_eee(netdev, &eee_data); - if (ret_val) + ret_val =3D ixgbe_validate_keee(netdev, edata); + if (ret_val =3D=3D -EALREADY) + return 0; + else if (ret_val) return ret_val; =20 - if (eee_data.eee_enabled && !edata->eee_enabled) { - if (eee_data.tx_lpi_enabled !=3D edata->tx_lpi_enabled) { - e_err(drv, "Setting EEE tx-lpi is not supported\n"); - return -EINVAL; - } - - if (eee_data.tx_lpi_timer !=3D edata->tx_lpi_timer) { - e_err(drv, - "Setting EEE Tx LPI timer is not supported\n"); - return -EINVAL; - } - - if (!linkmode_equal(eee_data.advertised, edata->advertised)) { - e_err(drv, - "Setting EEE advertised speeds is not supported\n"); - return -EINVAL; - } + if (edata->eee_enabled) { + adapter->flags2 |=3D IXGBE_FLAG2_EEE_ENABLED; + hw->phy.eee_speeds_advertised =3D + hw->phy.eee_speeds_supported; + } else { + adapter->flags2 &=3D ~IXGBE_FLAG2_EEE_ENABLED; + hw->phy.eee_speeds_advertised =3D 0; } =20 - if (eee_data.eee_enabled !=3D edata->eee_enabled) { - if (edata->eee_enabled) { - adapter->flags2 |=3D IXGBE_FLAG2_EEE_ENABLED; - hw->phy.eee_speeds_advertised =3D - hw->phy.eee_speeds_supported; - } else { - adapter->flags2 &=3D ~IXGBE_FLAG2_EEE_ENABLED; - hw->phy.eee_speeds_advertised =3D 0; - } - - /* reset link */ - if (netif_running(netdev)) - ixgbe_reinit_locked(adapter); - else - ixgbe_reset(adapter); - } + /* reset link */ + if (netif_running(netdev)) + ixgbe_reinit_locked(adapter); + else + ixgbe_reset(adapter); =20 return 0; } --=20 2.54.0.rc2.531.gaf818d63126a From nobody Sun Jun 14 07:49:21 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BF6E366057; Fri, 1 May 2026 06:38:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; 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30 Apr 2026 23:38:32 -0700 X-CSE-ConnectionGUID: S5dleScdQpaT2g6meLpyjA== X-CSE-MsgGUID: jgMYbmcVSlmC0MF4zOrYig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,209,1770624000"; d="scan'208";a="233752855" Received: from orcnseosdtjek.jf.intel.com (HELO [10.166.28.109]) ([10.166.28.109]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2026 23:38:31 -0700 From: Jacob Keller Date: Thu, 30 Apr 2026 23:37:17 -0700 Subject: [PATCH net-next 06/15] ixgbe: E610: add EEE support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260430-jk-iwl-net-next-2026-04-30-v1-6-6f27ae1cd073@intel.com> References: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> In-Reply-To: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> To: Przemek Kitszel , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexander Lobakin , Simon Horman , Michal Swiatkowski , Jedrzej Jagielski , Aleksandr Loktionov , Grzegorz Nitka , Ivan Vecera , Arkadiusz Kubalewski , Tony Nguyen , Stefan Wegrzyn Cc: Piotr Kwapulinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Jacob Keller , Rinitha S X-Mailer: b4 0.16-dev-ea14f X-Developer-Signature: v=1; a=openpgp-sha256; l=13772; i=jacob.e.keller@intel.com; h=from:subject:message-id; bh=6oCNnEyq63lnz1tHYDfSGCeCEMD2dPzCwLamxw3Z24I=; b=owGbwMvMwCWWNS3WLp9f4wXjabUkhswvXinHTLKq7HWrsyL8FopsCA5sfl8m/sFVt9nk5bqZP 97Fv1ncUcrCIMbFICumyKLgELLyuvGEMK03znIwc1iZQIYwcHEKwETMTzP803kZP2u/dqpybXP5 tyWb+3efW+L/aZrn9qdzZk8S6ZhjFMrwv2SvcE2/sWPAqePMV+Y7sZ38n8jC1sBucJUnLvbkzN0 svAA= X-Developer-Key: i=jacob.e.keller@intel.com; a=openpgp; fpr=204054A9D73390562AEC431E6A965D3E6F0F28E8 From: Jedrzej Jagielski Add E610 specific implementation of .get_eee() and .set_eee() ethtool callbacks. Introduce ixgbe_setup_eee_e610() which is used to set EEE config on E610 device via ixgbe_aci_set_phy_cfg() (0x0601 ACI command). Assign it to dedicated mac operation. E610 devices support EEE feature specifically for 2.5, 5 and 10G link speeds. When user try to set EEE for unsupported speeds log it. Setting timer and setting EEE advertised speeds are not yet supported. EEE shall be enabled by default for E610 devices. Add EEE statuis logging during link watchdog run. Reviewed-by: Aleksandr Loktionov Signed-off-by: Jedrzej Jagielski Tested-by: Rinitha S Signed-off-by: Jacob Keller --- drivers/net/ethernet/intel/ixgbe/ixgbe_e610.h | 1 + drivers/net/ethernet/intel/ixgbe/ixgbe_type.h | 1 + drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c | 40 +++++++ drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c | 145 +++++++++++++++++++= +++- drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | 30 ++++- 5 files changed, 212 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.h b/drivers/net/et= hernet/intel/ixgbe/ixgbe_e610.h index 11916b979d28..2cb76a3d30ae 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.h +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.h @@ -55,6 +55,7 @@ int ixgbe_init_phy_ops_e610(struct ixgbe_hw *hw); int ixgbe_identify_phy_e610(struct ixgbe_hw *hw); int ixgbe_identify_module_e610(struct ixgbe_hw *hw); int ixgbe_setup_phy_link_e610(struct ixgbe_hw *hw); +int ixgbe_setup_eee_e610(struct ixgbe_hw *hw, bool enable_eee); int ixgbe_set_phy_power_e610(struct ixgbe_hw *hw, bool on); int ixgbe_enter_lplu_e610(struct ixgbe_hw *hw); int ixgbe_init_eeprom_params_e610(struct ixgbe_hw *hw); diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h b/drivers/net/et= hernet/intel/ixgbe/ixgbe_type.h index 61f2ef67defd..01d0aa70b2b7 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h @@ -3524,6 +3524,7 @@ struct ixgbe_mac_operations { int (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *, bool *); void (*set_rate_select_speed)(struct ixgbe_hw *, ixgbe_link_speed); + int (*setup_eee)(struct ixgbe_hw *hw, bool enable_eee); =20 /* Packet Buffer Manipulation */ void (*set_rxpba)(struct ixgbe_hw *, int, u32, int); diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c b/drivers/net/et= hernet/intel/ixgbe/ixgbe_e610.c index a01d991ee2e0..665a9813e251 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c @@ -2013,6 +2013,45 @@ int ixgbe_identify_phy_e610(struct ixgbe_hw *hw) return 0; } =20 +/** + * ixgbe_setup_eee_e610 - Enable/disable EEE support + * @hw: pointer to the HW structure + * @enable_eee: boolean flag to enable EEE + * + * Enable/disable EEE based on @enable_eee. + * + * Return: the exit code of the operation. + */ +int ixgbe_setup_eee_e610(struct ixgbe_hw *hw, bool enable_eee) +{ + struct ixgbe_aci_cmd_get_phy_caps_data phy_caps =3D {}; + struct ixgbe_aci_cmd_set_phy_cfg_data phy_cfg =3D {}; + u16 eee_cap =3D 0; + int err; + + err =3D ixgbe_aci_get_phy_caps(hw, false, + IXGBE_ACI_REPORT_ACTIVE_CFG, &phy_caps); + if (err) + return err; + + ixgbe_copy_phy_caps_to_cfg(&phy_caps, &phy_cfg); + phy_cfg.caps |=3D (IXGBE_ACI_PHY_ENA_LINK | + IXGBE_ACI_PHY_ENA_AUTO_LINK_UPDT); + + if (enable_eee) { + if (hw->phy.eee_speeds_advertised & IXGBE_LINK_SPEED_2_5GB_FULL) + eee_cap |=3D IXGBE_ACI_PHY_EEE_EN_2_5GBASE_T; + if (hw->phy.eee_speeds_advertised & IXGBE_LINK_SPEED_5GB_FULL) + eee_cap |=3D IXGBE_ACI_PHY_EEE_EN_5GBASE_T; + if (hw->phy.eee_speeds_advertised & IXGBE_LINK_SPEED_10GB_FULL) + eee_cap |=3D IXGBE_ACI_PHY_EEE_EN_10GBASE_T; + } + + phy_cfg.eee_cap =3D cpu_to_le16(eee_cap); + + return ixgbe_aci_set_phy_cfg(hw, &phy_cfg); +} + /** * ixgbe_identify_module_e610 - Identify SFP module type * @hw: pointer to hardware structure @@ -4026,6 +4065,7 @@ static const struct ixgbe_mac_operations mac_ops_e610= =3D { .fw_rollback_mode =3D ixgbe_fw_rollback_mode_e610, .get_nvm_ver =3D ixgbe_get_active_nvm_ver, .get_link_capabilities =3D ixgbe_get_link_capabilities_e610, + .setup_eee =3D ixgbe_setup_eee_e610, .get_bus_info =3D ixgbe_get_bus_info_generic, .acquire_swfw_sync =3D ixgbe_acquire_swfw_sync_X540, .release_swfw_sync =3D ixgbe_release_swfw_sync_X540, diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c b/drivers/net= /ethernet/intel/ixgbe/ixgbe_ethtool.c index 186345933f3f..6990fe53f049 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c @@ -12,6 +12,7 @@ #include #include #include +#include #include =20 #include "ixgbe.h" @@ -3540,7 +3541,7 @@ static const struct { { IXGBE_LINK_SPEED_10_FULL, ETHTOOL_LINK_MODE_10baseT_Full_BIT }, { IXGBE_LINK_SPEED_100_FULL, ETHTOOL_LINK_MODE_100baseT_Full_BIT }, { IXGBE_LINK_SPEED_1GB_FULL, ETHTOOL_LINK_MODE_1000baseT_Full_BIT }, - { IXGBE_LINK_SPEED_2_5GB_FULL, ETHTOOL_LINK_MODE_2500baseX_Full_BIT }, + { IXGBE_LINK_SPEED_2_5GB_FULL, ETHTOOL_LINK_MODE_2500baseT_Full_BIT }, { IXGBE_LINK_SPEED_5GB_FULL, ETHTOOL_LINK_MODE_5000baseT_Full_BIT }, { IXGBE_LINK_SPEED_10GB_FULL, ETHTOOL_LINK_MODE_10000baseT_Full_BIT }, }; @@ -3557,6 +3558,17 @@ static const struct { { FW_PHY_ACT_UD_2_10G_KR_EEE, ETHTOOL_LINK_MODE_10000baseKR_Full_BIT}, }; =20 +static const struct { + u16 eee_cap_bit; + u32 link_mode; +} ixgbe_eee_cap_map[] =3D { + { IXGBE_ACI_PHY_EEE_EN_100BASE_TX, ETHTOOL_LINK_MODE_100baseT_Full_BIT }, + { IXGBE_ACI_PHY_EEE_EN_1000BASE_T, ETHTOOL_LINK_MODE_1000baseT_Full_BIT }, + { IXGBE_ACI_PHY_EEE_EN_10GBASE_T, ETHTOOL_LINK_MODE_10000baseT_Full_BIT }, + { IXGBE_ACI_PHY_EEE_EN_5GBASE_T, ETHTOOL_LINK_MODE_5000baseT_Full_BIT }, + { IXGBE_ACI_PHY_EEE_EN_2_5GBASE_T, ETHTOOL_LINK_MODE_2500baseT_Full_BIT }, +}; + static int ixgbe_validate_keee(struct net_device *netdev, struct ethtool_keee *keee_requested) { @@ -3598,6 +3610,133 @@ static int ixgbe_validate_keee(struct net_device *n= etdev, return 0; } =20 +/** + * ixgbe_is_eee_link_speed_supported_e610 - Check if EEE can be enabled + * @adapter: pointer to the adapter struct + * + * Check whether current link configuration is capable of enabling EEE fea= ture. + * + * E610 specific function - for other adapters supporting EEE there might = be + * no such limitation. + * + * Return: true if EEE can be enabled, false otherwise. + */ +static bool +ixgbe_is_eee_link_speed_supported_e610(struct ixgbe_adapter *adapter) +{ + switch (adapter->link_speed) { + case IXGBE_LINK_SPEED_10GB_FULL: + case IXGBE_LINK_SPEED_2_5GB_FULL: + case IXGBE_LINK_SPEED_5GB_FULL: + return true; + case IXGBE_LINK_SPEED_100_FULL: + case IXGBE_LINK_SPEED_1GB_FULL: + e_dev_info("Energy Efficient Ethernet (EEE) feature is not supported on = link speeds equal to or below 1Gbps. EEE is supported on speeds above 1Gbps= .\n"); + fallthrough; + default: + return false; + } +} + +static int ixgbe_get_eee_e610(struct net_device *netdev, + struct ethtool_keee *kedata) +{ + struct ixgbe_adapter *adapter =3D ixgbe_from_netdev(netdev); + struct ixgbe_aci_cmd_get_phy_caps_data pcaps; + struct ixgbe_hw *hw =3D &adapter->hw; + struct ixgbe_link_status link; + u16 eee_cap; + int err; + + linkmode_zero(kedata->lp_advertised); + linkmode_zero(kedata->supported); + linkmode_zero(kedata->advertised); + + err =3D ixgbe_aci_get_link_info(hw, true, &link); + if (err) + return err; + + err =3D ixgbe_aci_get_phy_caps(hw, false, IXGBE_ACI_REPORT_ACTIVE_CFG, + &pcaps); + if (err) + return err; + + kedata->eee_active =3D link.eee_status & IXGBE_ACI_LINK_EEE_ACTIVE; + kedata->eee_enabled =3D link.eee_status & IXGBE_ACI_LINK_EEE_ENABLED; + + /* for E610 devices EEE enablement implies TX LPI enablement */ + kedata->tx_lpi_enabled =3D kedata->eee_enabled; + + if (kedata->eee_enabled) + kedata->tx_lpi_timer =3D le16_to_cpu(pcaps.eee_entry_delay); + + eee_cap =3D le16_to_cpu(pcaps.eee_cap); + + for (int i =3D 0; i < ARRAY_SIZE(ixgbe_eee_cap_map); i++) { + if (eee_cap & ixgbe_eee_cap_map[i].eee_cap_bit) + linkmode_set_bit(ixgbe_eee_cap_map[i].link_mode, + kedata->lp_advertised); + } + + for (int i =3D 0; i < ARRAY_SIZE(ixgbe_ls_map); i++) { + if (hw->phy.eee_speeds_supported & + ixgbe_ls_map[i].mac_speed) + linkmode_set_bit(ixgbe_ls_map[i].link_mode, + kedata->supported); + + if (hw->phy.eee_speeds_advertised & + ixgbe_ls_map[i].mac_speed) + linkmode_set_bit(ixgbe_ls_map[i].link_mode, + kedata->advertised); + } + + return 0; +} + +static int ixgbe_set_eee_e610(struct net_device *netdev, + struct ethtool_keee *kedata) +{ + struct ixgbe_adapter *adapter =3D ixgbe_from_netdev(netdev); + struct ixgbe_hw *hw =3D &adapter->hw; + int err; + + err =3D ixgbe_validate_keee(netdev, kedata); + + if (err =3D=3D -EALREADY) { + return 0; + } else if (err) { + if (err =3D=3D -EOPNOTSUPP) + e_dev_info("Energy Efficient Ethernet (EEE) feature is currently not su= pported on this device, please update the device NVM to the latest and try = again\n"); + return err; + } + + if (!(ixgbe_is_eee_link_speed_supported_e610(adapter)) && + kedata->eee_enabled) + return -EOPNOTSUPP; + + hw->phy.eee_speeds_advertised =3D kedata->eee_enabled ? + hw->phy.eee_speeds_supported : 0; + + err =3D hw->mac.ops.setup_eee(hw, kedata->eee_enabled); + if (err) { + e_dev_err("Setting EEE %s failed.\n", + str_on_off(kedata->eee_enabled)); + return err; + } + + if (kedata->eee_enabled) + adapter->flags2 |=3D IXGBE_FLAG2_EEE_ENABLED; + else + adapter->flags2 &=3D ~IXGBE_FLAG2_EEE_ENABLED; + + if (netif_running(netdev)) + ixgbe_reinit_locked(adapter); + else + ixgbe_reset(adapter); + + return 0; +} + static int ixgbe_get_eee_fw(struct ixgbe_adapter *adapter, struct ethtool_keee *edata) { @@ -3824,8 +3963,8 @@ static const struct ethtool_ops ixgbe_ethtool_ops_e61= 0 =3D { .set_rxfh =3D ixgbe_set_rxfh, .get_rxfh_fields =3D ixgbe_get_rxfh_fields, .set_rxfh_fields =3D ixgbe_set_rxfh_fields, - .get_eee =3D ixgbe_get_eee, - .set_eee =3D ixgbe_set_eee, + .get_eee =3D ixgbe_get_eee_e610, + .set_eee =3D ixgbe_set_eee_e610, .get_channels =3D ixgbe_get_channels, .set_channels =3D ixgbe_set_channels, .get_priv_flags =3D ixgbe_get_priv_flags, diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/et= hernet/intel/ixgbe/ixgbe_main.c index 2646ee6f295f..9e1fb7383975 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c @@ -6758,6 +6758,7 @@ void ixgbe_down(struct ixgbe_adapter *adapter) =20 /** * ixgbe_set_eee_capable - helper function to determine EEE support on X550 + * and E610 * @adapter: board private structure */ static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter) @@ -6774,6 +6775,20 @@ static void ixgbe_set_eee_capable(struct ixgbe_adapt= er *adapter) break; adapter->flags2 |=3D IXGBE_FLAG2_EEE_ENABLED; break; + case IXGBE_DEV_ID_E610_BACKPLANE: + case IXGBE_DEV_ID_E610_SFP: + case IXGBE_DEV_ID_E610_10G_T: + case IXGBE_DEV_ID_E610_2_5G_T: + if (hw->dev_caps.common_cap.eee_support && + hw->phy.eee_speeds_supported) { + adapter->flags2 |=3D IXGBE_FLAG2_EEE_CAPABLE; + /* For E610 adapters EEE should be enabled by default + * if the feature is supported by FW. + */ + adapter->flags2 |=3D IXGBE_FLAG2_EEE_ENABLED; + break; + } + fallthrough; default: adapter->flags2 &=3D ~IXGBE_FLAG2_EEE_CAPABLE; adapter->flags2 &=3D ~IXGBE_FLAG2_EEE_ENABLED; @@ -8082,6 +8097,7 @@ static void ixgbe_watchdog_link_is_up(struct ixgbe_ad= apter *adapter) struct net_device *netdev =3D adapter->netdev; struct ixgbe_hw *hw =3D &adapter->hw; u32 link_speed =3D adapter->link_speed; + struct ethtool_keee keee =3D {}; const char *speed_str; bool flow_rx, flow_tx; =20 @@ -8122,6 +8138,8 @@ static void ixgbe_watchdog_link_is_up(struct ixgbe_ad= apter *adapter) if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) ixgbe_ptp_start_cyclecounter(adapter); =20 + netdev->ethtool_ops->get_eee(netdev, &keee); + switch (link_speed) { case IXGBE_LINK_SPEED_10GB_FULL: speed_str =3D "10 Gbps"; @@ -8145,10 +8163,11 @@ static void ixgbe_watchdog_link_is_up(struct ixgbe_= adapter *adapter) speed_str =3D "unknown speed"; break; } - e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str, + e_info(drv, "NIC Link is Up %s, Flow Control: %s, EEE: %s\n", speed_str, ((flow_rx && flow_tx) ? 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"TX" : "None"))), + str_on_off(keee.eee_enabled)); =20 netif_carrier_on(netdev); ixgbe_check_vf_rate_limit(adapter); @@ -12003,6 +12022,13 @@ static int ixgbe_probe(struct pci_dev *pdev, const= struct pci_device_id *ent) if (err) goto err_netdev; =20 + if (hw->mac.type =3D=3D ixgbe_mac_e610 && + (adapter->flags2 & IXGBE_FLAG2_EEE_CAPABLE)) { + bool eee_enable =3D adapter->flags2 & IXGBE_FLAG2_EEE_ENABLED; + + hw->mac.ops.setup_eee(hw, eee_enable); + } + ixgbe_devlink_init_regions(adapter); devl_register(adapter->devlink); devl_unlock(adapter->devlink); --=20 2.54.0.rc2.531.gaf818d63126a From nobody Sun Jun 14 07:49:21 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 644D6361675; Fri, 1 May 2026 06:38:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777617519; cv=none; b=UsvfcAtY9xg2KLvZkKJ3rPd8t/BFva/9xxt7Y0WoSMoukBAAk5wybE2qysf//3QdwSxc5cGKYlgNnhcDhDbLf8/TfrnYM/c0+Adoryx0hCbKp01PmBeeC+kWhQMKjV46KVpdlPytFm40HCdhwCSBD0ytMe1MZyr6opOsyjOygFQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777617519; c=relaxed/simple; bh=FXZ5bJqI4ovhpOunxxdyUT5gfRoy399BLyBsuo38664=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OBzcmt3KzFDI3LhY9FgRFlMaM5LpfCfQF7DDbpmA59dM/845hNL5h0F0O5aRmiukp5RQ0usAKfvrRRrMqvp6C3NoAmGxJcY3Xr0Q059gt/YRkoKywJQ6e2WG2g+VqdYSk5ExsuuTeUlZzPKyzNeXfYc5AHG2veNzfkb2UM2nYMo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=RT+GJGqg; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="RT+GJGqg" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777617517; x=1809153517; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=FXZ5bJqI4ovhpOunxxdyUT5gfRoy399BLyBsuo38664=; b=RT+GJGqgUhW6lLvAAShMYs52O+m6D5HxS9Jlo9G1F/ZjY2tsu4YAUAUL C2BZt2DqIQJmf9ypYmjdgi89b14lXWJTbQ7dKjKPAgV8sI8oOf3gxZVcJ yrrwIaX6IttAI0t96ANCPjvXuelioSP5wnORQL2CDbHZEVIB1yRHCrDui qY8V/Adhv4GaESTTC5QgZa/jVrN5+A0MeWPpUxF0G+hr6S5CCm1f3gmk9 QLIf+HMgQ0p56y1SRYzsjvk1IGr49npWJb1Uzx8BVl3c+jjqoxTH4yQsy 2i0mIgVouplcMp3gGF+5DR6bV8k4W7USQlXd8qLIMTAvp6xbsmJ4sNqI0 A==; X-CSE-ConnectionGUID: Q2L13DwMR/S+KtTjBcu5iQ== X-CSE-MsgGUID: g7VXxXUpRtyQC/hx8TGH+A== X-IronPort-AV: E=McAfee;i="6800,10657,11772"; a="89271902" X-IronPort-AV: E=Sophos;i="6.23,209,1770624000"; d="scan'208";a="89271902" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2026 23:38:32 -0700 X-CSE-ConnectionGUID: kFuwsrE2R7S+8bl4GaVb+g== X-CSE-MsgGUID: S1haTBXrThKMXck60guAFg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,209,1770624000"; d="scan'208";a="233752858" Received: from orcnseosdtjek.jf.intel.com (HELO [10.166.28.109]) ([10.166.28.109]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2026 23:38:31 -0700 From: Jacob Keller Date: Thu, 30 Apr 2026 23:37:18 -0700 Subject: [PATCH net-next 07/15] ixgbe: E610: add ACI dynamic debug Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260430-jk-iwl-net-next-2026-04-30-v1-7-6f27ae1cd073@intel.com> References: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> In-Reply-To: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> To: Przemek Kitszel , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexander Lobakin , Simon Horman , Michal Swiatkowski , Jedrzej Jagielski , Aleksandr Loktionov , Grzegorz Nitka , Ivan Vecera , Arkadiusz Kubalewski , Tony Nguyen , Stefan Wegrzyn Cc: Piotr Kwapulinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Jacob Keller , Rinitha S X-Mailer: b4 0.16-dev-ea14f X-Developer-Signature: v=1; a=openpgp-sha256; l=8880; i=jacob.e.keller@intel.com; h=from:subject:message-id; bh=M3A0TGxQzef9H8v9AL1pR11dIm6zNfcjlkNEFzkda/g=; b=owGbwMvMwCWWNS3WLp9f4wXjabUkhswvXik/bWy2nzI332Mh4b3j4iR1noNXXr3fxHHMO1fxL vstDau8jlIWBjEuBlkxRRYFh5CV140nhGm9cZaDmcPKBDKEgYtTACYi78rI0Mck5qS1OOeO68qL Bn1tgsfMQu9UsX9qvL3yueV2IQbuVob/1ercjPoWiiK5i0SaM5oVqiRML+/Vtz+lvmrb9Ule9YU 8AA== X-Developer-Key: i=jacob.e.keller@intel.com; a=openpgp; fpr=204054A9D73390562AEC431E6A965D3E6F0F28E8 From: Piotr Kwapulinski Enable dynamic debug (dyndbg) of Admin Command Interface (ACI) for e610 adapter. Utilizes the standard dynamic debug interface. For example to enable dyndbg at driver load: insmod ixgbe.ko dyndbg=3D'+p' ACI debug output for e610 adapter is immediately printed into a kernel log (dmesg). Example output: ixgbe 0000:01:00.0 eth0: CQ CMD: opcode 0x0701, flags 0x3003, datalen 0x006= 0, retval 0x0000 ixgbe 0000:01:00.0 eth0: cookie (h,l) 0x00000000 0x00000000 ixgbe 0000:01:00.0 eth0: param (0,1) 0x8194E044 0x00600000 ixgbe 0000:01:00.0 eth0: addr (h,l) 0x00000000 0x00000000 ixgbe 0000:01:00.0 eth0: Buffer: ixgbe 0000:01:00.0 eth0: 00000000: 01 00 17 00 00 00 00 00 00 00 00 00 00 0= 0 00 00 ixgbe 0000:01:00.0 eth0: 00000010: 1d 00 00 00 0b d5 1e 15 5e 4b 90 63 aa 0= b 21 31 ixgbe 0000:01:00.0 eth0: 00000020: 69 eb cd ab dc f8 8a fd f4 53 e2 dc 54 e= 0 81 fa ixgbe 0000:01:00.0 eth0: 00000030: 12 dc 41 82 01 00 00 00 24 20 08 26 53 0= 8 00 00 ixgbe 0000:01:00.0 eth0: 00000040: 08 00 14 00 00 00 00 00 00 00 00 00 00 0= 0 00 00 ixgbe 0000:01:00.0 eth0: 00000050: 00 00 00 00 00 00 00 00 00 00 00 00 00 0= 0 00 00 ixgbe 0000:01:00.0 eth0: CQ CMD: opcode 0x0009, flags 0x2003, datalen 0x000= 0, retval 0x0000 ixgbe 0000:01:00.0 eth0: cookie (h,l) 0x00000000 0x00000000 ixgbe 0000:01:00.0 eth0: param (0,1) 0x00000001 0x00000000 ixgbe 0000:01:00.0 eth0: addr (h,l) 0x00000000 0x00000000 Co-developed-by: Stefan Wegrzyn Signed-off-by: Stefan Wegrzyn Reviewed-by: Aleksandr Loktionov Signed-off-by: Piotr Kwapulinski Tested-by: Rinitha S Signed-off-by: Jacob Keller --- drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c | 112 ++++++++++++++++++++++= ++-- 1 file changed, 105 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c b/drivers/net/et= hernet/intel/ixgbe/ixgbe_e610.c index 665a9813e251..b686636beb93 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c @@ -9,6 +9,78 @@ #include "ixgbe_mbx.h" #include "ixgbe_phy.h" =20 +#define IXGBE_ACI_DEBUG_ROW_SIZE 16 +#define IXGBE_ACI_DEBUG_GROUP_SIZE 1 +#define IXGBE_NETDEV_PREFIX_BUF_SIZE 64 + +/** + * ixgbe_hex_debug_dump - dump a blob of data in "hex ASCII" format + * @hw: hardware structure address + * @buf: data blob to dump + * @buf_size: number of bytes in the @buf + * + * Dump a blob of data into a kernel log. The blob is printed in lines + * consisting of 16 or 32 bytes decorated with PCI device string. Each byt= e is + * printed in a "hex ASCII" format. + * Example output: + * ixgbe 0000:01:00.1 eth14: 00000000: 01 00 17 00 00 00 00 00 00 00 00 00= 00 00 00 00 + * ixgbe 0000:01:00.1 eth14: 00000010: 1d 00 00 00 0b d5 1e 15 5e 4b 90 63= aa 0b 21 31 + * ixgbe 0000:01:00.1 eth14: 00000020: 69 eb cd ab dc f8 8a fd f4 53 e2 dc= 54 e0 81 fa + */ +static void ixgbe_hex_debug_dump(struct ixgbe_hw *hw, void *buf, + size_t buf_size) +{ + char netdev_info[IXGBE_NETDEV_PREFIX_BUF_SIZE]; + struct ixgbe_adapter *adapter =3D hw->back; + struct pci_dev *pdev =3D adapter->pdev; + + snprintf(netdev_info, IXGBE_NETDEV_PREFIX_BUF_SIZE, + "%s %s %s: ", ixgbe_driver_name, pci_name(pdev), + netdev_name(adapter->netdev)); + print_hex_dump_debug(netdev_info, DUMP_PREFIX_OFFSET, + IXGBE_ACI_DEBUG_ROW_SIZE, + IXGBE_ACI_DEBUG_GROUP_SIZE, + buf, buf_size, false); +} + +/** + * ixgbe_aci_debug - dump the ACI content + * @hw: pointer to the hardware structure + * @desc: pointer to control queue descriptor + * @buf: pointer to command buffer + * @buf_len: max length of buf + * + * Dump individual ACI commands and its descriptor details. + */ +static void ixgbe_aci_debug(struct ixgbe_hw *hw, void *desc, void *buf, + u16 buf_len) +{ + struct libie_aq_desc *aq_desc =3D desc; + u16 datalen, flags; + + datalen =3D le16_to_cpu(aq_desc->datalen); + flags =3D le16_to_cpu(aq_desc->flags); + + hw_dbg(hw, "CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0= x%04X\n", + le16_to_cpu(aq_desc->opcode), flags, datalen, + le16_to_cpu(aq_desc->retval)); + hw_dbg(hw, "\tcookie (h,l) 0x%08X 0x%08X\n", + le32_to_cpu(aq_desc->cookie_high), + le32_to_cpu(aq_desc->cookie_low)); + hw_dbg(hw, "\tparam (0,1) 0x%08X 0x%08X\n", + le32_to_cpu(aq_desc->params.generic.param0), + le32_to_cpu(aq_desc->params.generic.param1)); + hw_dbg(hw, "\taddr (h,l) 0x%08X 0x%08X\n", + le32_to_cpu(aq_desc->params.generic.addr_high), + le32_to_cpu(aq_desc->params.generic.addr_low)); + + if (buf && datalen && (flags & (LIBIE_AQ_FLAG_DD | LIBIE_AQ_FLAG_CMP | + LIBIE_AQ_FLAG_RD))) { + hw_dbg(hw, "Buffer:\n"); + ixgbe_hex_debug_dump(hw, buf, min(buf_len, datalen)); + } +} + /** * ixgbe_should_retry_aci_send_cmd_execute - decide if ACI command should * be resent @@ -69,26 +141,33 @@ static int ixgbe_aci_send_cmd_execute(struct ixgbe_hw = *hw, /* It's necessary to check if mechanism is enabled */ hicr =3D IXGBE_READ_REG(hw, IXGBE_PF_HICR); =20 - if (!(hicr & IXGBE_PF_HICR_EN)) + if (!(hicr & IXGBE_PF_HICR_EN)) { + hw_dbg(hw, "CSR mechanism is not enabled\n"); return -EIO; + } =20 if (hicr & IXGBE_PF_HICR_C) { hw->aci.last_status =3D LIBIE_AQ_RC_EBUSY; + hw_dbg(hw, "CSR mechanism is busy\n"); return -EBUSY; } =20 opcode =3D le16_to_cpu(desc->opcode); =20 - if (buf_size > IXGBE_ACI_MAX_BUFFER_SIZE) + if (buf_size > IXGBE_ACI_MAX_BUFFER_SIZE) { + hw_dbg(hw, "buf_size is too big\n"); return -EINVAL; + } =20 if (buf) desc->flags |=3D cpu_to_le16(LIBIE_AQ_FLAG_BUF); =20 if (desc->flags & cpu_to_le16(LIBIE_AQ_FLAG_BUF)) { if ((buf && !buf_size) || - (!buf && buf_size)) + (!buf && buf_size)) { + hw_dbg(hw, "error: invalid argument buf or buf_size\n"); return -EINVAL; + } if (buf && buf_size) valid_buf =3D true; } @@ -106,8 +185,12 @@ static int ixgbe_aci_send_cmd_execute(struct ixgbe_hw = *hw, if (desc->flags & cpu_to_le16(LIBIE_AQ_FLAG_RD)) { for (i =3D 0; i < buf_size / 4; i++) IXGBE_WRITE_REG(hw, IXGBE_PF_HIBA(i), ((u32 *)buf)[i]); - if (buf_tail_size) + ixgbe_aci_debug(hw, desc, buf, buf_size); + if (buf_tail_size) { IXGBE_WRITE_REG(hw, IXGBE_PF_HIBA(i), buf_tail); + ixgbe_aci_debug(hw, desc, &buf_tail, + buf_tail_size); + } } } =20 @@ -147,6 +230,7 @@ static int ixgbe_aci_send_cmd_execute(struct ixgbe_hw *= hw, raw_desc[i] =3D IXGBE_READ_REG(hw, IXGBE_PF_HIDA(i)); raw_desc[i] =3D raw_desc[i]; } + ixgbe_aci_debug(hw, raw_desc, NULL, 0); } =20 /* Read async Admin Command response */ @@ -155,14 +239,21 @@ static int ixgbe_aci_send_cmd_execute(struct ixgbe_hw= *hw, raw_desc[i] =3D IXGBE_READ_REG(hw, IXGBE_PF_HIDA_2(i)); raw_desc[i] =3D raw_desc[i]; } + ixgbe_aci_debug(hw, raw_desc, NULL, 0); } =20 /* Handle timeout and invalid state of HICR register */ - if (hicr & IXGBE_PF_HICR_C) + if (hicr & IXGBE_PF_HICR_C) { + hw_dbg(hw, "error: Admin Command 0x%X command timeout\n", + le16_to_cpu(desc->opcode)); return -ETIME; + } =20 - if (!(hicr & IXGBE_PF_HICR_SV) && !(hicr & IXGBE_PF_HICR_EV)) + if (!(hicr & IXGBE_PF_HICR_SV) && !(hicr & IXGBE_PF_HICR_EV)) { + hw_dbg(hw, "error: Admin Command 0x%X invalid state of HICR register\n", + le16_to_cpu(desc->opcode)); return -EIO; + } =20 /* For every command other than 0x0014 treat opcode mismatch * as an error. Response to 0x0014 command read from HIDA_2 @@ -170,12 +261,16 @@ static int ixgbe_aci_send_cmd_execute(struct ixgbe_hw= *hw, * different opcode than the command. */ if (desc->opcode !=3D cpu_to_le16(opcode) && - opcode !=3D ixgbe_aci_opc_get_fw_event) + opcode !=3D ixgbe_aci_opc_get_fw_event) { + hw_dbg(hw, "error: Admin Command failed, bad opcode returned\n"); return -EIO; + } =20 if (desc->retval) { hw->aci.last_status =3D (enum libie_aq_err) le16_to_cpu(desc->retval); + hw_dbg(hw, "error: Admin Command failed with error %x\n", + le16_to_cpu(desc->retval)); return -EIO; } =20 @@ -183,10 +278,13 @@ static int ixgbe_aci_send_cmd_execute(struct ixgbe_hw= *hw, if (valid_buf) { for (i =3D 0; i < buf_size / 4; i++) ((u32 *)buf)[i] =3D IXGBE_READ_REG(hw, IXGBE_PF_HIBA(i)); + ixgbe_aci_debug(hw, raw_desc, buf, buf_size); if (buf_tail_size) { buf_tail =3D IXGBE_READ_REG(hw, IXGBE_PF_HIBA(i)); memcpy(buf + buf_size - buf_tail_size, &buf_tail, buf_tail_size); + ixgbe_aci_debug(hw, raw_desc, &buf_tail, + buf_tail_size); } } =20 --=20 2.54.0.rc2.531.gaf818d63126a From nobody Sun Jun 14 07:49:21 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26E4136EA80; Fri, 1 May 2026 06:38:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777617524; cv=none; b=Q9xe1PfN3vw4Q4WC6PlkgyMojpbCPBO7OYhFgrDeG5z14v7e2B7I/+I80ajwfTUGOzNg2W8wXYuVBC60PVZ3CZlmEWXbWeM92ZPaX0QGtMEAHW1l6/GIC9RuZx6fC85kGIQvhQsC4KZ+CIe3R2uGwLNofhyyr2tbgZA275AM6S8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777617524; c=relaxed/simple; bh=QOCm2sopwgNpl+EKxsL6rGh0AzlEggXHpYnJl0//k3I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=H4A5dsk7dDmS9L8pcJMeIYOSPeEzaE2Gs8/OqqJ7oj0tLMrVAUeDrRu1hzZ67CTdkRrW4UNRDo5L8jjCxUWQu60bpC62Hk/xRbTj2mg3hosodeBpqqzn5otOaWLB9DV+PWq8YhN1IFMqTeADjbSBm8gEopTlmCMr2FLUYFT/Nr4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=hKtgxbBg; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="hKtgxbBg" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777617519; x=1809153519; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=QOCm2sopwgNpl+EKxsL6rGh0AzlEggXHpYnJl0//k3I=; b=hKtgxbBgj+aqhw1cib1Iwc7RZD7K6XMijgLrvXIh1migjvhCafRZFjDG dxdwTMXEOUhTPaNHbEefPjzWRWjgUBuKo8k6SRWjpq9LZazpqcvKTbAR/ bkeizyfd0KFUc7DcDhdE3JKBnjK2G79UzC4fVSrKzEuAHGZjJ2dYi1qHN 40JFgLvjiiccQz7/r/D+qV603i+8OwDXAZvhuYn++R+oCcla95hju62K8 C//58AkGpaJHCXNxll8iqZHQucZwjn2VbDgmH8YU/80wpZ30ZH316MXHU 2F8ydyVU/man02nnEDAKnAlp2Ku++zfcZijRQJrC/2a8EHQEHSossq6VM A==; X-CSE-ConnectionGUID: ecWPT3rhR4S45iLgn3fn3A== X-CSE-MsgGUID: jBgX2CVXThiOqG+7MB8ZVQ== X-IronPort-AV: E=McAfee;i="6800,10657,11772"; a="89271910" X-IronPort-AV: E=Sophos;i="6.23,209,1770624000"; d="scan'208";a="89271910" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2026 23:38:32 -0700 X-CSE-ConnectionGUID: pVfQznXiSr2BYVQoaq/6GQ== X-CSE-MsgGUID: /gxstvVKQiWYcH9CuEmKOg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,209,1770624000"; d="scan'208";a="233752861" Received: from orcnseosdtjek.jf.intel.com (HELO [10.166.28.109]) ([10.166.28.109]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2026 23:38:32 -0700 From: Jacob Keller Date: Thu, 30 Apr 2026 23:37:19 -0700 Subject: [PATCH net-next 08/15] ixgbe: E610: remove redundant assignment Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260430-jk-iwl-net-next-2026-04-30-v1-8-6f27ae1cd073@intel.com> References: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> In-Reply-To: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> To: Przemek Kitszel , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexander Lobakin , Simon Horman , Michal Swiatkowski , Jedrzej Jagielski , Aleksandr Loktionov , Grzegorz Nitka , Ivan Vecera , Arkadiusz Kubalewski , Tony Nguyen , Stefan Wegrzyn Cc: Piotr Kwapulinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Jacob Keller X-Mailer: b4 0.16-dev-ea14f X-Developer-Signature: v=1; a=openpgp-sha256; l=1521; i=jacob.e.keller@intel.com; h=from:subject:message-id; bh=W/40c8BFZkNJ6uVOUp9nRUCH9K3Lx1uOG5OO7H/Jis0=; b=owGbwMvMwCWWNS3WLp9f4wXjabUkhswvXil7GA7xrZ548MXCsBhBuaL4uXs8LU9wLvh69mK9/ ZorsryxHaUsDGJcDLJiiiwKDiErrxtPCNN64ywHM4eVCWQIAxenAEyEfRIjw+4ODflzdumfSiJ/ fQ89/3J+nlTLD/dELmXmoJKjO8WdfBn+V582b3qXvWH1/KwlcXo1yh3C1l7aNmt2WpSXsM6Qdf7 NCQA= X-Developer-Key: i=jacob.e.keller@intel.com; a=openpgp; fpr=204054A9D73390562AEC431E6A965D3E6F0F28E8 From: Piotr Kwapulinski Remove unnecessary code. No functional impact. Fixes: 46761fd52a88 ("ixgbe: Add support for E610 FW Admin Command Interfac= e") Signed-off-by: Piotr Kwapulinski Reviewed-by: Aleksandr Loktionov Signed-off-by: Jacob Keller --- drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c b/drivers/net/et= hernet/intel/ixgbe/ixgbe_e610.c index b686636beb93..831cfe9a4697 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c @@ -226,19 +226,15 @@ static int ixgbe_aci_send_cmd_execute(struct ixgbe_hw= *hw, =20 /* Read sync Admin Command response */ if ((hicr & IXGBE_PF_HICR_SV)) { - for (i =3D 0; i < IXGBE_ACI_DESC_SIZE_IN_DWORDS; i++) { + for (i =3D 0; i < IXGBE_ACI_DESC_SIZE_IN_DWORDS; i++) raw_desc[i] =3D IXGBE_READ_REG(hw, IXGBE_PF_HIDA(i)); - raw_desc[i] =3D raw_desc[i]; - } ixgbe_aci_debug(hw, raw_desc, NULL, 0); } =20 /* Read async Admin Command response */ if ((hicr & IXGBE_PF_HICR_EV) && !(hicr & IXGBE_PF_HICR_C)) { - for (i =3D 0; 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d="scan'208";a="233752865" Received: from orcnseosdtjek.jf.intel.com (HELO [10.166.28.109]) ([10.166.28.109]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2026 23:38:32 -0700 From: Jacob Keller Date: Thu, 30 Apr 2026 23:37:20 -0700 Subject: [PATCH net-next 09/15] ixgbe: fix unaligned u32 access in ixgbe_update_flash_X550() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260430-jk-iwl-net-next-2026-04-30-v1-9-6f27ae1cd073@intel.com> References: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> In-Reply-To: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> To: Przemek Kitszel , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexander Lobakin , Simon Horman , Michal Swiatkowski , Jedrzej Jagielski , Aleksandr Loktionov , Grzegorz Nitka , Ivan Vecera , Arkadiusz Kubalewski , Tony Nguyen , Stefan Wegrzyn Cc: Piotr Kwapulinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Jacob Keller , Paul Menzel , Rinitha S X-Mailer: b4 0.16-dev-ea14f X-Developer-Signature: v=1; a=openpgp-sha256; l=2201; i=jacob.e.keller@intel.com; h=from:subject:message-id; bh=Aqtc3PLkUgsFHWa28RCMB+oLSMNUQQxnwKMbK9Zb72I=; b=owGbwMvMwCWWNS3WLp9f4wXjabUkhswvXql2F9X/Kf7n2VMSzlf/fYUYA/uq3TZ73tYWscZ4O p1OT3LrKGVhEONikBVTZFFwCFl53XhCmNYbZzmYOaxMIEMYuDgFYCJ3cxgZOiY57T3B3qDqH37z gUp8w9blyREWJd3TLL4vluWvcOK3Y2To+R/8KvrbAn2G4r296en3VB4sLvbe/eIPM+vq+I+bomL YAA== X-Developer-Key: i=jacob.e.keller@intel.com; a=openpgp; fpr=204054A9D73390562AEC431E6A965D3E6F0F28E8 From: Aleksandr Loktionov ixgbe_host_interface_command() treats its buffer as a u32 array. The local buffer we pass in was a union of byte-sized fields, which gives it 1-byte alignment on the stack. On strict-align architectures this can cause unaligned 32-bit accesses. Add a u32 member to union ixgbe_hic_hdr2 so the object is 4-byte aligned, and pass the u32 member when calling ixgbe_host_interface_command(). No functional change on x86; prevents unaligned accesses on architectures that enforce natural alignment. Fixes: 49425dfc7451 ("ixgbe: Add support for x550em_a 10G MAC type") Signed-off-by: Aleksandr Loktionov Reviewed-by: Jedrzej Jagielski Reviewed-by: Paul Menzel Fixes: 6a14ee0cfb19 ("ixgbe: Add X550 support function pointers") Tested-by: Rinitha S Signed-off-by: Jacob Keller --- drivers/net/ethernet/intel/ixgbe/ixgbe_type.h | 1 + drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h b/drivers/net/et= hernet/intel/ixgbe/ixgbe_type.h index 01d0aa70b2b7..a461b6542f96 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h @@ -2798,6 +2798,7 @@ struct ixgbe_hic_hdr2_rsp { }; =20 union ixgbe_hic_hdr2 { + u32 buf[1]; struct ixgbe_hic_hdr2_req req; struct ixgbe_hic_hdr2_rsp rsp; }; diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c b/drivers/net/et= hernet/intel/ixgbe/ixgbe_x550.c index 76d2fa3ef518..4a0ccbf448a2 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c @@ -1228,7 +1228,7 @@ static int ixgbe_update_flash_X550(struct ixgbe_hw *h= w) buffer.req.buf_lenl =3D FW_SHADOW_RAM_DUMP_LEN; buffer.req.checksum =3D FW_DEFAULT_CHECKSUM; =20 - status =3D ixgbe_host_interface_command(hw, &buffer, sizeof(buffer), + status =3D ixgbe_host_interface_command(hw, buffer.buf, sizeof(buffer), IXGBE_HI_COMMAND_TIMEOUT, false); return status; } --=20 2.54.0.rc2.531.gaf818d63126a From nobody Sun Jun 14 07:49:21 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E48CE364053; Fri, 1 May 2026 06:38:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777617520; cv=none; b=n5V/Z2xqj1Bpa2wrZTOGcWv7NtKRtNL7nxL7N+a+cxzUfpXyQAVoBcBjCU5RWygJHaLUrfauFeKpjtwKJz8RH017rXY4FmsRTDkiXKh9O8Pq9FU2o1rF2NBQwybEYp+nDTx0aaQ3fHYivbUsRGBA+ocGPBqsIafSrtMKTrKPBts= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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d="scan'208";a="233752868" Received: from orcnseosdtjek.jf.intel.com (HELO [10.166.28.109]) ([10.166.28.109]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2026 23:38:32 -0700 From: Jacob Keller Date: Thu, 30 Apr 2026 23:37:21 -0700 Subject: [PATCH net-next 10/15] i40e: only timestamp PTP event packets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260430-jk-iwl-net-next-2026-04-30-v1-10-6f27ae1cd073@intel.com> References: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> In-Reply-To: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> To: Przemek Kitszel , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexander Lobakin , Simon Horman , Michal Swiatkowski , Jedrzej Jagielski , Aleksandr Loktionov , Grzegorz Nitka , Ivan Vecera , Arkadiusz Kubalewski , Tony Nguyen , Stefan Wegrzyn Cc: Piotr Kwapulinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Jacob Keller , Rinitha S X-Mailer: b4 0.16-dev-ea14f X-Developer-Signature: v=1; a=openpgp-sha256; l=5472; i=jacob.e.keller@intel.com; h=from:subject:message-id; bh=RjzD3QV0Pc7FQKiPpdSySz683TeMOk4ms6dduW8uUiY=; b=owGbwMvMwCWWNS3WLp9f4wXjabUkhswvXqkPftw3+PbzwMvtH2QSbr0KbtnVX7yg6KKDZtK/M oNM8+fqHaUsDGJcDLJiiiwKDiErrxtPCNN64ywHM4eVCWQIAxenAExkxXNGhlOT+zINkpd89f52 60Cg3RJ12b9RuzapLG1+MOHw+ZpnWRyMDHtcL/LfND3nvbwxN9Jt24+rstsW7lsrHbhoj5H2z1X ugewA X-Developer-Key: i=jacob.e.keller@intel.com; a=openpgp; fpr=204054A9D73390562AEC431E6A965D3E6F0F28E8 The i40e_ptp_set_timestamp_mode() function is responsible for configuring hardware timestamping. When programming receive timestamping, the logic must determine how to configure the PRTTSYN_CTL1 register for receive timestamping. The i40e hardware does not support timestamping all frames. Instead, timestamps are captured into one of the four PRTTSYN_RXTIME registers. Currently, the driver configures hardware to timestamp all V2 packets on ports 319 and 320, including all message types. This timestamps significantly more packets than is actually requested by the HWTSTAMP_FILTER_PTP_V2_EVENT filter type. The documentation for HWTSTAMP_FILTER_PTP_V2_EVENT indicates that it should timestamp PTP v2 messages on any layer, including any kind of event packets. Timestamping other packets is acceptable, but not required by the filter. Doing so wastes valuable slots in the Rx timestamp registers. For most applications this doesn't cause a problem. However, for extremely high rates of messages, it becomes possible that one of the critical event packets is not timestamped. The PTP protocol only requires timestamps for event messages on port 319, but hardware is timestamping on both 319 and 320, and timestamping message types which do not need a timestamp value. The i40e hardware actually has a more strict filtering option. First, only timestamp layer 4 messages on port 319 instead of both 319 and 320. Second, note that hardware has a specific mode to timestamp only event packets (those with message type < 8). Update the configuration to use the strict mode that only timestamps event messages, switching the TSYNTYPE field from 10b to 11b which limits the timestamping only to eventpackets with a Message Type of < 8. Note that the X700 series datasheet seems to indicate that the V2MSESTYPE field is no longer relevant. However, we only tested and validated with leaving the V2MESSTYPE field set to 0xF for the "wildcard" behavior it documents. This might not be required but it in that case setting it appears harmless, so leave it as is. This avoids wasting the valuable Rx timestamp register slots on non-event frames, and may reduce faults when operating under high event rates. Reviewed-by: Aleksandr Loktionov Tested-by: Rinitha S Signed-off-by: Jacob Keller --- drivers/net/ethernet/intel/i40e/i40e_register.h | 10 ++++++++++ drivers/net/ethernet/intel/i40e/i40e_ptp.c | 9 +++------ 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/intel/i40e/i40e_register.h b/drivers/net/= ethernet/intel/i40e/i40e_register.h index 432afbb64201..d426d83e0214 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_register.h +++ b/drivers/net/ethernet/intel/i40e/i40e_register.h @@ -788,8 +788,18 @@ #define I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT 16 #define I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL= 1_V2MESSTYPE0_SHIFT) #define I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT 24 +#define I40E_PRTTSYN_CTL1_TSYNTYPE_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL1_T= SYNTYPE_SHIFT) +/* Timestamp UDP v1 packets */ +#define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 \ + FIELD_PREP(I40E_PRTTSYN_CTL1_TSYNTYPE_MASK, 1) +/* Timestamp L2 and UDP v2 packets with message type < 8 */ +#define I40E_PRTTSYN_CTL1_TSYNTYPE_V2_EVENT \ + FIELD_PREP(I40E_PRTTSYN_CTL1_TSYNTYPE_MASK, 3) #define I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT 26 #define I40E_PRTTSYN_CTL1_UDP_ENA_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL1_UD= P_ENA_SHIFT) +/* Timestamp UDP packets on port 319 */ +#define I40E_PRTTSYN_CTL1_UDP_ENA_319 \ + FIELD_PREP(I40E_PRTTSYN_CTL1_UDP_ENA_MASK, 1) #define I40E_PRTTSYN_CTL1_TSYNENA_SHIFT 31 #define I40E_PRTTSYN_CTL1_TSYNENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL1_TS= YNENA_SHIFT) #define I40E_PRTTSYN_INC_H 0x001E4060 /* Reset: GLOBR */ diff --git a/drivers/net/ethernet/intel/i40e/i40e_ptp.c b/drivers/net/ether= net/intel/i40e/i40e_ptp.c index 404a716db8da..7bcea7d9720f 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_ptp.c +++ b/drivers/net/ethernet/intel/i40e/i40e_ptp.c @@ -24,9 +24,6 @@ #define I40E_PTP_1GB_INCVAL_MULT 20 #define I40E_ISGN 0x80000000 =20 -#define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 BIT(I40E_PRTTSYN_CTL1_TSYNTYPE_SHIF= T) -#define I40E_PRTTSYN_CTL1_TSYNTYPE_V2 (2 << \ - I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) #define I40E_SUBDEV_ID_25G_PTP_PIN 0xB =20 enum i40e_ptp_pin { @@ -1219,7 +1216,7 @@ static int i40e_ptp_set_timestamp_mode(struct i40e_pf= *pf, pf->ptp_rx =3D true; tsyntype =3D I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK | I40E_PRTTSYN_CTL1_TSYNTYPE_V1 | - I40E_PRTTSYN_CTL1_UDP_ENA_MASK; + I40E_PRTTSYN_CTL1_UDP_ENA_319; config->rx_filter =3D HWTSTAMP_FILTER_PTP_V1_L4_EVENT; break; case HWTSTAMP_FILTER_PTP_V2_EVENT: @@ -1236,9 +1233,9 @@ static int i40e_ptp_set_timestamp_mode(struct i40e_pf= *pf, case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: pf->ptp_rx =3D true; tsyntype =3D I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK | - I40E_PRTTSYN_CTL1_TSYNTYPE_V2; + I40E_PRTTSYN_CTL1_TSYNTYPE_V2_EVENT; if (test_bit(I40E_HW_CAP_PTP_L4, pf->hw.caps)) { - tsyntype |=3D I40E_PRTTSYN_CTL1_UDP_ENA_MASK; + tsyntype |=3D I40E_PRTTSYN_CTL1_UDP_ENA_319; config->rx_filter =3D HWTSTAMP_FILTER_PTP_V2_EVENT; } else { config->rx_filter =3D HWTSTAMP_FILTER_PTP_V2_L2_EVENT; --=20 2.54.0.rc2.531.gaf818d63126a From nobody Sun Jun 14 07:49:21 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ECB90367F21; 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a="89271925" X-IronPort-AV: E=Sophos;i="6.23,209,1770624000"; d="scan'208";a="89271925" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2026 23:38:33 -0700 X-CSE-ConnectionGUID: v4WENUiMRjaf1eMRA68JXQ== X-CSE-MsgGUID: CeNn1GWdRVejcGthQMADbQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,209,1770624000"; d="scan'208";a="233752871" Received: from orcnseosdtjek.jf.intel.com (HELO [10.166.28.109]) ([10.166.28.109]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2026 23:38:32 -0700 From: Jacob Keller Date: Thu, 30 Apr 2026 23:37:22 -0700 Subject: [PATCH net-next 11/15] ice: mention fw_activate action along with devlink reload Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260430-jk-iwl-net-next-2026-04-30-v1-11-6f27ae1cd073@intel.com> References: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> In-Reply-To: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> To: Przemek Kitszel , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexander Lobakin , Simon Horman , Michal Swiatkowski , Jedrzej Jagielski , Aleksandr Loktionov , Grzegorz Nitka , Ivan Vecera , Arkadiusz Kubalewski , Tony Nguyen , Stefan Wegrzyn Cc: Piotr Kwapulinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Jacob Keller X-Mailer: b4 0.16-dev-ea14f X-Developer-Signature: v=1; a=openpgp-sha256; l=1805; i=jacob.e.keller@intel.com; h=from:subject:message-id; bh=XXZI7pQh1J2x8jCwKraX2UOMZwG+RSwyWryaNcpYiOk=; b=owGbwMvMwCWWNS3WLp9f4wXjabUkhswvXqm8sSLnqh1fnpzTeui+RHrP7a9yZ9+3H2Gb91Zr0 69Pm1JXd5SyMIhxMciKKbIoOISsvG48IUzrjbMczBxWJpAhDFycAnARNob/RVecJPa9tz39hd1q /1nL2WzqCW95fuUfCH4sss7/zgeZY4wMxxq/3vhw9MmZwFLp8OgWpUP+QktO9l9Msl7eaynvbpH KCgA= X-Developer-Key: i=jacob.e.keller@intel.com; a=openpgp; fpr=204054A9D73390562AEC431E6A965D3E6F0F28E8 The ice driver reports a helpful status message when updating firmware indicating what action is necessary to enable the new firmware. This is done because some updates require power cycling or rebooting the machine but some can be activated via devlink. The ice driver only supports activating firmware with the specific action of "fw_activate" a bare "devlink dev reload" will *not* update the firmware, and will only perform driver reinitialization. Update the status message to explicitly reflect that the reload must use the fw_activate action. I considered modifying the text to spell out the full command, but felt that was both overkill and something that would belong better as part of the user space program and not hard coded into the kernel driver output. Reviewed-by: Aleksandr Loktionov Reviewed-by: Przemek Kitszel Reviewed-by: Simon Horman Signed-off-by: Jacob Keller --- drivers/net/ethernet/intel/ice/ice_fw_update.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/ice/ice_fw_update.c b/drivers/net/e= thernet/intel/ice/ice_fw_update.c index c143e546dd8c..36314610927b 100644 --- a/drivers/net/ethernet/intel/ice/ice_fw_update.c +++ b/drivers/net/ethernet/intel/ice/ice_fw_update.c @@ -726,7 +726,7 @@ static int ice_finalize_update(struct pldmfw *context) switch (priv->reset_level) { case ICE_AQC_NVM_EMPR_FLAG: devlink_flash_update_status_notify(devlink, - "Activate new firmware by devlink reload", + "Activate new firmware by devlink reload action fw_activate", NULL, 0, 0); break; case ICE_AQC_NVM_PERST_FLAG: --=20 2.54.0.rc2.531.gaf818d63126a From nobody Sun Jun 14 07:49:21 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFD30364053; Fri, 1 May 2026 06:38:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777617537; cv=none; b=rmgbYOZHx2jxo/TuLaDiZS5ZBbelHlaM/riSvvBQSShpC30qEoMHsHBSjyQFW8ZXJYmTug/Nl41ZhUuT5wWCKTvt/IM7QM8zNpO3RMpHdJDybbsfkGQb+IKCF6gqxHfdZt2nL5OjvkC2FamqDYfkvxJpIkgp8E+KyIzcvncrA88= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777617537; c=relaxed/simple; bh=vEB0fiJj7H/xD8ySXsvckM6+AhfWsB18bO96+ihTxBg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KfDWRUwRJfyJCkguDfEnHZLiJjUFq4sfHMYhFBtQfgpKjKGj8x0aRNyjEKPphOR13LX6OM8HI7kcW22Y+xLehyPPbF39Q1R9bqJHZ9u3s7Ew9/KEEEwicJFVBhIfKrb7Y8153IS4o7v5lvk5/hx/fj9rUwhQCL2PELX8XvCOPRI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YxEeSlEW; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YxEeSlEW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777617525; x=1809153525; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=vEB0fiJj7H/xD8ySXsvckM6+AhfWsB18bO96+ihTxBg=; b=YxEeSlEW3JSiIUnaGK7Tv7K+qNF1Vug1blaLTD+ldD0UVOTSozEOyRdy /cLJLowHSU4OuHTJnFyAcunvkP7N4GcNYNojvXqf50PGYx55My1BevYqx YUGfSda2eNqQL8RUsgBo9VucI1G0pyjiypzY0MieglKMX1QOt7mug2ASj 7/4UPcR8KdW9O6iNxF5mSXAzvDwPX2FYOugWOGSQfDAzOdIt+N8msYg0p qNFn+ggWN5clyJsTZI8sqUce1WT6XOvUk+hqO7Q/52ErEUnoy2ggsvpIi tnMWfj6DnxT0NSDqNkt5PFrlBld7moXzPCiggDHvGS+90BueC/XBhBT72 A==; X-CSE-ConnectionGUID: qkXaWgywTOyHJ6PF6p82JA== X-CSE-MsgGUID: U67moQPYRH6vEgtEOC5IrA== X-IronPort-AV: E=McAfee;i="6800,10657,11772"; a="89271937" X-IronPort-AV: E=Sophos;i="6.23,209,1770624000"; d="scan'208";a="89271937" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2026 23:38:33 -0700 X-CSE-ConnectionGUID: uHGX/IAURPa7mJG6VQWo/Q== X-CSE-MsgGUID: Jualyz7yRfmTNY2Ceiy1Rg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,209,1770624000"; d="scan'208";a="233752874" Received: from orcnseosdtjek.jf.intel.com (HELO [10.166.28.109]) ([10.166.28.109]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2026 23:38:32 -0700 From: Jacob Keller Date: Thu, 30 Apr 2026 23:37:23 -0700 Subject: [PATCH net-next 12/15] ice: access @pp through netmem_desc instead of page Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260430-jk-iwl-net-next-2026-04-30-v1-12-6f27ae1cd073@intel.com> References: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> In-Reply-To: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> To: Przemek Kitszel , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexander Lobakin , Simon Horman , Michal Swiatkowski , Jedrzej Jagielski , Aleksandr Loktionov , Grzegorz Nitka , Ivan Vecera , Arkadiusz Kubalewski , Tony Nguyen , Stefan Wegrzyn Cc: Piotr Kwapulinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Jacob Keller , Byungchul Park , Alexander Nowlin , Rinitha S , "David Hildenbrand (Arm)" X-Mailer: b4 0.16-dev-ea14f X-Developer-Signature: v=1; a=openpgp-sha256; l=1230; i=jacob.e.keller@intel.com; h=from:subject:message-id; bh=TGwZV0NmJnw+cmQ/tSq26oujWdnFsUW5u892Ld/O3g4=; b=owGbwMvMwCWWNS3WLp9f4wXjabUkhswvXmk6AR9qpipW9M9obLM/0zr/wi7Pkr9hqhW3zty6z vzpM6tORykLgxgXg6yYIouCQ8jK68YTwrTeOMvBzGFlAhnCwMUpABNJcGf4H35MOXDrV11ld4cj Vot4Wpu9Fz/+W97UdJXjbbXi5B+LeBkZTm765GiyZsu26Rz5W/pi4ze/ZPpjIPH00X/L/arc14N mMQIA X-Developer-Key: i=jacob.e.keller@intel.com; a=openpgp; fpr=204054A9D73390562AEC431E6A965D3E6F0F28E8 From: Byungchul Park To eliminate the use of struct page in page pool, the page pool users should use netmem descriptor and APIs instead. Make ice driver access @pp through netmem_desc instead of page. Signed-off-by: Byungchul Park Tested-by: Alexander Nowlin Tested-by: Rinitha S Reviewed-by: David Hildenbrand (Arm) Signed-off-by: Jacob Keller --- drivers/net/ethernet/intel/ice/ice_ethtool.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/ice/ice_ethtool.c b/drivers/net/eth= ernet/intel/ice/ice_ethtool.c index f28416a707d7..236d293aba98 100644 --- a/drivers/net/ethernet/intel/ice/ice_ethtool.c +++ b/drivers/net/ethernet/intel/ice/ice_ethtool.c @@ -1251,7 +1251,7 @@ static int ice_lbtest_receive_frames(struct ice_rx_ri= ng *rx_ring) rx_buf =3D &rx_ring->rx_fqes[i]; page =3D __netmem_to_page(rx_buf->netmem); received_buf =3D page_address(page) + rx_buf->offset + - page->pp->p.offset; + pp_page_to_nmdesc(page)->pp->p.offset; =20 if (ice_lbtest_check_frame(received_buf)) valid_frames++; --=20 2.54.0.rc2.531.gaf818d63126a From nobody Sun Jun 14 07:49:21 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C97B0373C0B; Fri, 1 May 2026 06:38:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777617531; cv=none; b=mXhtiRf2azV+YrbcJdAHCrvHVDaAeVWxKbSFr8OKH2mH9SRL1dnItcoR5T0fc5xMZtO5Ohks1JWPLhL1+BsUFnkcn0nL2BN8Z8Ib6JcEAMIXC0oxii6HqqoND9iUw8FdZ+oOqcckbNNSTcsCCqiKBlNhEDCSA3lSzYlNvH/r2rc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777617531; c=relaxed/simple; bh=hZEmZMTWms93iScRWFWbXFUbeAQnRsLmufvsHgKBvR8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JACEFhabLhBZGMKux2aS7NgNTlf7Lq8/AATfeIjGmd28I4PsEWE92TdCk51Ppmcf4smIwOn/rV/n/+6gplwlzPkYvqRoRKDucdfotl2r4FC4UgFYznc/M8QakWrlHTC6y3BczC53zYL0Zs4GKHhag33E5+10oB/QKRwUY6ZyPhA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=cyu3DyZg; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="cyu3DyZg" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777617525; x=1809153525; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=hZEmZMTWms93iScRWFWbXFUbeAQnRsLmufvsHgKBvR8=; b=cyu3DyZguTEfhZrHoloQ55Tp6uhuG09v70Yav8P0tnfFCUYPTSszbpCo MuxllZm8DNpgPJSPCxGnd79px7XLEVY9JhB6X4pldj8r/kV06XTJorNtt wSVRRnfa/1zrFPQeSoZFYpHgo4aQsHQ01JwrC6LrjJdyYil1wY1LX6JGF XFQFNQHqQotsCV1kEA5UrPJKsYNaaqwRjqcL+vPOBKUlkQeotI1yipQ+k eAdi/bqduUQoB+SrHUNKxFFnJ0nopQ3yasTsyawGYYeVtDLj4GkcU4toB +QLc4INckq3FNAKj1Y03Z6Ov3SVa8GcQucGx/v0lB1VWqKZgHEAjbZsGh w==; X-CSE-ConnectionGUID: e5PZwpG9TIisa9iD3BviCA== X-CSE-MsgGUID: 4o54v0DnQbe1STWsiG5wNw== X-IronPort-AV: E=McAfee;i="6800,10657,11772"; a="89271941" X-IronPort-AV: E=Sophos;i="6.23,209,1770624000"; d="scan'208";a="89271941" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2026 23:38:33 -0700 X-CSE-ConnectionGUID: vfifRqAFSMeffQQZCUC4kA== X-CSE-MsgGUID: NW34wUKjSFiCI7MR+7U+Ng== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,209,1770624000"; d="scan'208";a="233752877" Received: from orcnseosdtjek.jf.intel.com (HELO [10.166.28.109]) ([10.166.28.109]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2026 23:38:32 -0700 From: Jacob Keller Date: Thu, 30 Apr 2026 23:37:24 -0700 Subject: [PATCH net-next 13/15] ice: dpll: Fix compilation warning Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260430-jk-iwl-net-next-2026-04-30-v1-13-6f27ae1cd073@intel.com> References: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> In-Reply-To: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> To: Przemek Kitszel , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexander Lobakin , Simon Horman , Michal Swiatkowski , Jedrzej Jagielski , Aleksandr Loktionov , Grzegorz Nitka , Ivan Vecera , Arkadiusz Kubalewski , Tony Nguyen , Stefan Wegrzyn Cc: Piotr Kwapulinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Jacob Keller , Przemyslaw Korba X-Mailer: b4 0.16-dev-ea14f X-Developer-Signature: v=1; a=openpgp-sha256; l=1244; i=jacob.e.keller@intel.com; h=from:subject:message-id; bh=e03GxYUPA/S1DBBMfmY+CJB2v7PFQcAFMRVgEvhGnGk=; b=owGbwMvMwCWWNS3WLp9f4wXjabUkhswvXmnxSoEhQZyfLoUazVObuXrF6Vvz3YM+bjO+8lv8+ 4QFOQf4O0pZGMS4GGTFFFkUHEJWXjeeEKb1xlkOZg4rE8gQBi5OAZhIyEJGhm8Fn0JqNO+9++0S 5rCiqJvz8pNpj3Uu/IuqabkeP+3VDn5Ghi8fuJSzFyZ8EVhz5VOy0dwJrw25mz8snHuWZ3NXP8d EfVYA X-Developer-Key: i=jacob.e.keller@intel.com; a=openpgp; fpr=204054A9D73390562AEC431E6A965D3E6F0F28E8 From: Przemyslaw Korba Introduced by commit ad1df4f2d591 ("ice: dpll: Support E825-C SyncE and dynamic pin discovery"): ice_dpll.c: In function =E2=80=98ice_dpll_init=E2=80=99: ice_dpll.c:3588:59: error: =E2=80=98%u=E2=80=99 directive output may be tru= ncated writing between 1 and 10 bytes into a region of size 4 [-Werror=3Dformat-truncation=3D] snprintf(pin_name, sizeof(pin_name), "rclk%u", i); Reviewed-by: Przemek Kitszel Signed-off-by: Przemyslaw Korba Reviewed-by: Aleksandr Loktionov Signed-off-by: Jacob Keller --- drivers/net/ethernet/intel/ice/ice_dpll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethern= et/intel/ice/ice_dpll.c index 62f75701d652..054a2c05f163 100644 --- a/drivers/net/ethernet/intel/ice/ice_dpll.c +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c @@ -3527,7 +3527,7 @@ static int ice_dpll_init_fwnode_pins(struct ice_pf *pf, struct ice_dpll_pin *pins, int start_idx) { - char pin_name[8]; + char pin_name[16]; int i, ret; =20 pf->dplls.wq =3D create_singlethread_workqueue("ice_dpll_wq"); --=20 2.54.0.rc2.531.gaf818d63126a From nobody Sun Jun 14 07:49:21 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFDCA36B04E; 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a="89271943" X-IronPort-AV: E=Sophos;i="6.23,209,1770624000"; d="scan'208";a="89271943" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2026 23:38:33 -0700 X-CSE-ConnectionGUID: JCEW06nTRuiY2ABmy7PXOA== X-CSE-MsgGUID: RZB1mL3iRyKyvHeQeY2zdA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,209,1770624000"; d="scan'208";a="233752880" Received: from orcnseosdtjek.jf.intel.com (HELO [10.166.28.109]) ([10.166.28.109]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2026 23:38:32 -0700 From: Jacob Keller Date: Thu, 30 Apr 2026 23:37:25 -0700 Subject: [PATCH net-next 14/15] ice: dpll: fix rclk pin state get and misplaced header macros Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260430-jk-iwl-net-next-2026-04-30-v1-14-6f27ae1cd073@intel.com> References: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> In-Reply-To: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> To: Przemek Kitszel , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexander Lobakin , Simon Horman , Michal Swiatkowski , Jedrzej Jagielski , Aleksandr Loktionov , Grzegorz Nitka , Ivan Vecera , Arkadiusz Kubalewski , Tony Nguyen , Stefan Wegrzyn Cc: Piotr Kwapulinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Jacob Keller X-Mailer: b4 0.16-dev-ea14f X-Developer-Signature: v=1; a=openpgp-sha256; l=4237; i=jacob.e.keller@intel.com; h=from:subject:message-id; bh=siSulnAIoSIGkhsuHQarR6BgLpyYP0IIK6K/d8Qf1MM=; b=owGbwMvMwCWWNS3WLp9f4wXjabUkhswvXmnRl4uE/QP6eXdldl+Ji631vLOOoz7+mkQHs7Pu2 78+pzo7SlkYxLgYZMUUWRQcQlZeN54QpvXGWQ5mDisTyBAGLk4BmMhaG4b/uY8nLjQo6LWcoh5u YnDuyd+bxvJ+zT/f/mbTOXlczsA/iZHhMPu/D3NPl/BnaNRaHX/idOBEm6lE05Xn/F9T3JRPXvF lBQA= X-Developer-Key: i=jacob.e.keller@intel.com; a=openpgp; fpr=204054A9D73390562AEC431E6A965D3E6F0F28E8 From: Ivan Vecera Fix two issues introduced in commit ad1df4f2d591 ("ice: dpll: Support E825-C SyncE and dynamic pin discovery"): * The refactoring of ice_dpll_rclk_state_on_pin_get() to use ice_dpll_pin_get_parent_idx() omitted the base_rclk_idx adjustment that was correctly added in the ice_dpll_rclk_state_on_pin_set() path. This breaks E810 devices where base_rclk_idx is non-zero, causing the wrong hardware index to be used for pin state lookup and incorrect recovered clock state to be reported via the DPLL subsystem. E825C is unaffected as its base_rclk_idx is 0. * Add bounds check against ICE_DPLL_RCLK_NUM_MAX on hw_idx after the base_rclk_idx subtraction in both ice_dpll_rclk_state_on_pin_{get,set}() to prevent out-of-bounds access on the pin state array. * The CGU register definitions (ICE_CGU_R10, ICE_CGU_R11 and related field masks) were placed after the #endif of the _ICE_DPLL_H_ include guard, leaving them unprotected. Move them inside the guard. Fixes: ad1df4f2d591 ("ice: dpll: Support E825-C SyncE and dynamic pin disco= very") Signed-off-by: Ivan Vecera Reviewed-by: Aleksandr Loktionov Signed-off-by: Jacob Keller --- drivers/net/ethernet/intel/ice/ice_dpll.h | 32 +++++++++++++++------------= ---- drivers/net/ethernet/intel/ice/ice_dpll.c | 5 +++++ 2 files changed, 21 insertions(+), 16 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.h b/drivers/net/ethern= et/intel/ice/ice_dpll.h index ae42cdea0ee1..8678575359b9 100644 --- a/drivers/net/ethernet/intel/ice/ice_dpll.h +++ b/drivers/net/ethernet/intel/ice/ice_dpll.h @@ -8,6 +8,22 @@ =20 #define ICE_DPLL_RCLK_NUM_MAX 4 =20 +#define ICE_CGU_R10 0x28 +#define ICE_CGU_R10_SYNCE_CLKO_SEL GENMASK(8, 5) +#define ICE_CGU_R10_SYNCE_CLKODIV_M1 GENMASK(13, 9) +#define ICE_CGU_R10_SYNCE_CLKODIV_LOAD BIT(14) +#define ICE_CGU_R10_SYNCE_DCK_RST BIT(15) +#define ICE_CGU_R10_SYNCE_ETHCLKO_SEL GENMASK(18, 16) +#define ICE_CGU_R10_SYNCE_ETHDIV_M1 GENMASK(23, 19) +#define ICE_CGU_R10_SYNCE_ETHDIV_LOAD BIT(24) +#define ICE_CGU_R10_SYNCE_DCK2_RST BIT(25) +#define ICE_CGU_R10_SYNCE_S_REF_CLK GENMASK(31, 27) + +#define ICE_CGU_R11 0x2C +#define ICE_CGU_R11_SYNCE_S_BYP_CLK GENMASK(6, 1) + +#define ICE_CGU_BYPASS_MUX_OFFSET_E825C 3 + /** * enum ice_dpll_pin_sw - enumerate ice software pin indices: * @ICE_DPLL_PIN_SW_1_IDX: index of first SW pin @@ -157,19 +173,3 @@ static inline void ice_dpll_deinit(struct ice_pf *pf) = { } #endif =20 #endif - -#define ICE_CGU_R10 0x28 -#define ICE_CGU_R10_SYNCE_CLKO_SEL GENMASK(8, 5) -#define ICE_CGU_R10_SYNCE_CLKODIV_M1 GENMASK(13, 9) -#define ICE_CGU_R10_SYNCE_CLKODIV_LOAD BIT(14) -#define ICE_CGU_R10_SYNCE_DCK_RST BIT(15) -#define ICE_CGU_R10_SYNCE_ETHCLKO_SEL GENMASK(18, 16) -#define ICE_CGU_R10_SYNCE_ETHDIV_M1 GENMASK(23, 19) -#define ICE_CGU_R10_SYNCE_ETHDIV_LOAD BIT(24) -#define ICE_CGU_R10_SYNCE_DCK2_RST BIT(25) -#define ICE_CGU_R10_SYNCE_S_REF_CLK GENMASK(31, 27) - -#define ICE_CGU_R11 0x2C -#define ICE_CGU_R11_SYNCE_S_BYP_CLK GENMASK(6, 1) - -#define ICE_CGU_BYPASS_MUX_OFFSET_E825C 3 diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethern= et/intel/ice/ice_dpll.c index 054a2c05f163..3eea83b0cdc9 100644 --- a/drivers/net/ethernet/intel/ice/ice_dpll.c +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c @@ -2440,6 +2440,8 @@ ice_dpll_rclk_state_on_pin_set(const struct dpll_pin = *pin, void *pin_priv, if (hw_idx < 0) goto unlock; hw_idx -=3D pf->dplls.base_rclk_idx; + if (hw_idx >=3D ICE_DPLL_RCLK_NUM_MAX) + goto unlock; =20 if ((enable && p->state[hw_idx] =3D=3D DPLL_PIN_STATE_CONNECTED) || (!enable && p->state[hw_idx] =3D=3D DPLL_PIN_STATE_DISCONNECTED)) { @@ -2503,6 +2505,9 @@ ice_dpll_rclk_state_on_pin_get(const struct dpll_pin = *pin, void *pin_priv, hw_idx =3D ice_dpll_pin_get_parent_idx(p, parent_pin); if (hw_idx < 0) goto unlock; + hw_idx -=3D pf->dplls.base_rclk_idx; + if (hw_idx >=3D ICE_DPLL_RCLK_NUM_MAX) + goto unlock; =20 ret =3D ice_dpll_pin_state_update(pf, p, ICE_DPLL_PIN_TYPE_RCLK_INPUT, extack); --=20 2.54.0.rc2.531.gaf818d63126a From nobody Sun Jun 14 07:49:21 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CEB7336405F; Fri, 1 May 2026 06:38:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; 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spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="bEV02Peb" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777617532; x=1809153532; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=3KVaW1N1XX/xgaRaZj5INMTnrb8wRJc5NS6nDMoLpxc=; b=bEV02PebXkOKyZDRK0e6v8DvAMaAXA9IysmGOqgJF9oSS+T7VXDWA4ye mGHUcaEWaV9PAnE1jZT8s1vJRhJLaziGeE7AiPcHZ7xZT5vemzahurKWz 7LGFJqw1BkXLxQymcmI297stfGV8E77b99W/MxCiqs3/0lwKucMrTJu0F Bc6FzoxHgQrSLy+7ZSCwX7O7/vzutXhnAQnvYav5HAx5rn8AHOPktBG/r HYB36EC5G6TXW8C0F+rSlp+LEWkmBtvAgeWSXqdkt/mEVUt1dSUCkkPtZ Zn/wgvvl3Bykk4wjUdI2UhfiSoB4xgN09nR48vn0VVtWI1Ca0XfsvwB1X Q==; X-CSE-ConnectionGUID: OfmXs3ixS3uFNglGlYD8Jg== X-CSE-MsgGUID: gVyYg9blTMOHGrS/V+9LKw== X-IronPort-AV: E=McAfee;i="6800,10657,11772"; a="89271947" X-IronPort-AV: E=Sophos;i="6.23,209,1770624000"; d="scan'208";a="89271947" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2026 23:38:33 -0700 X-CSE-ConnectionGUID: pnAPVuxjROeo7FlIJ9n6Aw== X-CSE-MsgGUID: xiy3jZA9Thu9mkP2A0rgcA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,209,1770624000"; d="scan'208";a="233752882" Received: from orcnseosdtjek.jf.intel.com (HELO [10.166.28.109]) ([10.166.28.109]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2026 23:38:32 -0700 From: Jacob Keller Date: Thu, 30 Apr 2026 23:37:26 -0700 Subject: [PATCH net-next 15/15] ice: add support for unmanaged DPLL on E830 NIC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260430-jk-iwl-net-next-2026-04-30-v1-15-6f27ae1cd073@intel.com> References: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> In-Reply-To: <20260430-jk-iwl-net-next-2026-04-30-v1-0-6f27ae1cd073@intel.com> To: Przemek Kitszel , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexander Lobakin , Simon Horman , Michal Swiatkowski , Jedrzej Jagielski , Aleksandr Loktionov , Grzegorz Nitka , Ivan Vecera , Arkadiusz Kubalewski , Tony Nguyen , Stefan Wegrzyn Cc: Piotr Kwapulinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Jacob Keller , Paul Menzel , Sunitha Mekala X-Mailer: b4 0.16-dev-ea14f X-Developer-Signature: v=1; a=openpgp-sha256; l=35475; i=jacob.e.keller@intel.com; h=from:subject:message-id; bh=TBgPhJokTmZKjriclC4RIr3nZATSQhRMOtLbt8Yipmc=; b=owGbwMvMwCWWNS3WLp9f4wXjabUkhswvXmnpZ6ZJvt/lu+NN/h0W1XMZShUu1/Uf31m/esped Zcd4fN9O0pZGMS4GGTFFFkUHEJWXjeeEKb1xlkOZg4rE8gQBi5OAZjIqTaG/8lLXn5Z/WLF+XOs GuatUstSVuu9crGxXl1uOv3BugOGcZwM/332Nsp/EMkTOV5RZpB+W2fNIylOrVNy3Me8Mw6F/f+ ZzgoA X-Developer-Key: i=jacob.e.keller@intel.com; a=openpgp; fpr=204054A9D73390562AEC431E6A965D3E6F0F28E8 From: Arkadiusz Kubalewski Hardware variants of E830 may support an unmanaged DPLL where the configuration is hardcoded within the hardware and firmware, meaning users cannot modify settings. However, users are able to check the DPLL lock status and obtain configuration information through the Linux DPLL and devlink health subsystem. Availability of 'loss of lock' health status code determines if such support is available, if true, register single DPLL device with 1 input and 1 output and provide hardcoded/read only properties of a pin and DPLL device. User is only allowed to check DPLL device status and receive notifications on DPLL lock status change. When present, the DPLL device locks to an external signal provided through the PCIe/OCP pin. The expected input signal is 1PPS (1 Pulse Per Second) embedded on a 10MHz reference clock. The DPLL produces output: - for MAC (Media Access Control) & PHY (Physical Layer) clocks, - 1PPS for synchronization of onboard PHC (Precision Hardware Clock) timer. Reviewed-by: Aleksandr Loktionov Reviewed-by: Paul Menzel Signed-off-by: Grzegorz Nitka Signed-off-by: Arkadiusz Kubalewski Tested-by: Sunitha Mekala Signed-off-by: Jacob Keller --- drivers/net/ethernet/intel/ice/ice_adminq_cmd.h | 12 + drivers/net/ethernet/intel/ice/ice_common.h | 8 + drivers/net/ethernet/intel/ice/ice_dpll.h | 11 + drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 1 + drivers/net/ethernet/intel/ice/devlink/health.c | 4 + drivers/net/ethernet/intel/ice/ice_common.c | 136 ++++++++++ drivers/net/ethernet/intel/ice/ice_dpll.c | 300 +++++++++++++++++= ++-- drivers/net/ethernet/intel/ice/ice_main.c | 11 +- drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 46 ++++ .../device_drivers/ethernet/intel/ice.rst | 83 ++++++ 10 files changed, 592 insertions(+), 20 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h b/drivers/net/= ethernet/intel/ice/ice_adminq_cmd.h index 3cbb1b0582e3..a4e37e01435d 100644 --- a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h +++ b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h @@ -1498,6 +1498,7 @@ struct ice_aqc_get_link_topo { #define ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575 0x21 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032 0x24 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384 0x25 +#define ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL80640 0x27 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY 0x30 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_C827 0x31 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX 0x47 @@ -2481,11 +2482,14 @@ enum ice_aqc_health_status { ICE_AQC_HEALTH_STATUS_ERR_BMC_RESET =3D 0x50B, ICE_AQC_HEALTH_STATUS_ERR_LAST_MNG_FAIL =3D 0x50C, ICE_AQC_HEALTH_STATUS_ERR_RESOURCE_ALLOC_FAIL =3D 0x50D, + ICE_AQC_HEALTH_STATUS_INFO_LOSS_OF_LOCK =3D 0x601, ICE_AQC_HEALTH_STATUS_ERR_FW_LOOP =3D 0x1000, ICE_AQC_HEALTH_STATUS_ERR_FW_PFR_FAIL =3D 0x1001, ICE_AQC_HEALTH_STATUS_ERR_LAST_FAIL_AQ =3D 0x1002, }; =20 +#define ICE_AQC_HEALTH_STATUS_CODE_NUM 64 + /* Get Health Status (indirect 0xFF22) */ struct ice_aqc_get_health_status { __le16 health_status_count; @@ -2512,6 +2516,13 @@ struct ice_aqc_health_status_elem { __le32 internal_data2; }; =20 +/* Get Health Status response buffer entry, (0xFF21) + * repeated per reported health status + */ +struct ice_aqc_health_status_supp_elem { + __le16 health_status_code; +}; + /* Admin Queue command opcodes */ enum ice_adminq_opc { /* AQ commands */ @@ -2675,6 +2686,7 @@ enum ice_adminq_opc { =20 /* System Diagnostic commands */ ice_aqc_opc_set_health_status_cfg =3D 0xFF20, + ice_aqc_opc_get_supported_health_status_codes =3D 0xFF21, ice_aqc_opc_get_health_status =3D 0xFF22, =20 /* FW Logging Commands */ diff --git a/drivers/net/ethernet/intel/ice/ice_common.h b/drivers/net/ethe= rnet/intel/ice/ice_common.h index e700ac0dc347..cbecee66e2a7 100644 --- a/drivers/net/ethernet/intel/ice/ice_common.h +++ b/drivers/net/ethernet/intel/ice/ice_common.h @@ -162,6 +162,7 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual= _mods, u8 report_mode, bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw); bool ice_is_clock_mux_in_netlist(struct ice_hw *hw); bool ice_is_cgu_in_netlist(struct ice_hw *hw); +bool ice_is_unmanaged_cgu_in_netlist(struct ice_hw *hw); bool ice_is_gps_in_netlist(struct ice_hw *hw); int ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *c= md, @@ -188,6 +189,13 @@ ice_get_link_default_override(struct ice_link_default_= override_tlv *ldo, struct ice_port_info *pi); bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps); bool ice_is_fw_health_report_supported(struct ice_hw *hw); +int ice_aq_get_health_status(struct ice_hw *hw, + struct ice_aqc_health_status_elem *buff, int num); +int ice_is_health_status_code_supported(struct ice_hw *hw, u16 code, + bool *supported); +int ice_get_last_health_status_code(struct ice_hw *hw, + struct ice_aqc_health_status_elem *out, + u16 code); int ice_aq_set_health_status_cfg(struct ice_hw *hw, u8 event_source); int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_cod= e, u8 serdes_num, int *output); diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.h b/drivers/net/ethern= et/intel/ice/ice_dpll.h index 8678575359b9..eda8743f3a79 100644 --- a/drivers/net/ethernet/intel/ice/ice_dpll.h +++ b/drivers/net/ethernet/intel/ice/ice_dpll.h @@ -24,6 +24,9 @@ =20 #define ICE_CGU_BYPASS_MUX_OFFSET_E825C 3 =20 +#define ICE_DPLL_UNMANAGED_PIN_NUM 4 +#define ICE_DPLL_IN_ESYNC_ENABLED ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN + /** * enum ice_dpll_pin_sw - enumerate ice software pin indices: * @ICE_DPLL_PIN_SW_1_IDX: index of first SW pin @@ -162,14 +165,22 @@ struct ice_dplls { s32 output_phase_adj_max; u32 periodic_counter; bool generic; + bool unmanaged; }; =20 #if IS_ENABLED(CONFIG_PTP_1588_CLOCK) void ice_dpll_init(struct ice_pf *pf); void ice_dpll_deinit(struct ice_pf *pf); +void ice_dpll_lock_state_set_unmanaged(struct ice_pf *pf, + const struct ice_aqc_health_status_elem *buff, + bool notify); #else static inline void ice_dpll_init(struct ice_pf *pf) { } static inline void ice_dpll_deinit(struct ice_pf *pf) { } +static inline void +ice_dpll_lock_state_set_unmanaged(struct ice_pf *pf, + const struct ice_aqc_health_status_elem *buff, + bool notify) { } #endif =20 #endif diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethe= rnet/intel/ice/ice_ptp_hw.h index 1c9e77dbc770..98bca7cae88d 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h @@ -357,6 +357,7 @@ int ice_read_sma_ctrl(struct ice_hw *hw, u8 *data); int ice_write_sma_ctrl(struct ice_hw *hw, u8 data); int ice_ptp_read_sdp_ac(struct ice_hw *hw, __le16 *entries, uint *num_entr= ies); int ice_cgu_get_num_pins(struct ice_hw *hw, bool input); +int ice_cgu_get_pin_num(struct ice_hw *hw, bool input); enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool in= put); struct dpll_pin_frequency * ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num); diff --git a/drivers/net/ethernet/intel/ice/devlink/health.c b/drivers/net/= ethernet/intel/ice/devlink/health.c index 8e9a8a8178d4..31e6c5107c97 100644 --- a/drivers/net/ethernet/intel/ice/devlink/health.c +++ b/drivers/net/ethernet/intel/ice/devlink/health.c @@ -101,6 +101,8 @@ static const struct ice_health_status ice_health_status= _lookup[] =3D { "Supplied MIB file is invalid. DCB reverted to default configuration.", "Disable FW-LLDP and check DCBx system configuration.", {ice_port_number_label, "MIB ID"}}, + {ICE_AQC_HEALTH_STATUS_INFO_LOSS_OF_LOCK, "Local DPLL lock status", + NULL,}, }; =20 static int ice_health_status_lookup_compare(const void *a, const void *b) @@ -242,6 +244,8 @@ void ice_process_health_status_event(struct ice_pf *pf,= struct ice_rq_event_info pf->health_reporters.fw_status =3D *health_info; devlink_health_report(pf->health_reporters.fw, "FW syndrome reported", NULL); + if (status_code =3D=3D ICE_AQC_HEALTH_STATUS_INFO_LOSS_OF_LOCK) + ice_dpll_lock_state_set_unmanaged(pf, health_info, true); break; case ICE_AQC_HEALTH_STATUS_PF: case ICE_AQC_HEALTH_STATUS_PORT: diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethe= rnet/intel/ice/ice_common.c index ce11fea122d0..5bf4bda74e4c 100644 --- a/drivers/net/ethernet/intel/ice/ice_common.c +++ b/drivers/net/ethernet/intel/ice/ice_common.c @@ -3050,6 +3050,29 @@ bool ice_is_cgu_in_netlist(struct ice_hw *hw) return false; } =20 +/** + * ice_is_unmanaged_cgu_in_netlist - check for unmanaged CGU presence + * @hw: pointer to the hw struct + * + * Check if the unmanaged Clock Generation Unit (CGU) device is present in= the netlist. + * Save the CGU part number in the hw structure for later use. + * Return: + * * true - unmanaged cgu is present + * * false - unmanaged cgu is not present + */ +bool ice_is_unmanaged_cgu_in_netlist(struct ice_hw *hw) +{ + if (!ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, + ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, + ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL80640, + NULL)) { + hw->cgu_part_number =3D ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL80640; + return true; + } + + return false; +} + /** * ice_is_gps_in_netlist * @hw: pointer to the hw struct @@ -6312,6 +6335,119 @@ bool ice_is_fw_health_report_supported(struct ice_h= w *hw) ICE_FW_API_HEALTH_REPORT_PATCH); } =20 +/** + * ice_aq_get_health_status_supported - get supported health status codes + * @hw: pointer to the HW struct + * @buff: pointer to buffer where health status elements will be stored + * @num: number of health status elements buffer can hold + * + * Return: + * * 0 - success, + * * negative - AQ error code. + */ +static int +ice_aq_get_health_status_supported(struct ice_hw *hw, + struct ice_aqc_health_status_supp_elem *buff, + int num) +{ + u16 code =3D ice_aqc_opc_get_supported_health_status_codes; + struct libie_aq_desc desc; + + ice_fill_dflt_direct_cmd_desc(&desc, code); + + return ice_aq_send_cmd(hw, &desc, buff, num * sizeof(*buff), NULL); +} + +/** + * ice_aq_get_health_status - get current health status array from the fir= mware + * @hw: pointer to the HW struct + * @buff: pointer to buffer where health status elements will be stored + * @num: number of health status elements buffer can hold + * + * Return: + * * 0 - success, + * * negative - AQ error code. + */ +int ice_aq_get_health_status(struct ice_hw *hw, + struct ice_aqc_health_status_elem *buff, int num) +{ + struct libie_aq_desc desc; + + ice_fill_dflt_direct_cmd_desc(&desc, + ice_aqc_opc_get_health_status); + + return ice_aq_send_cmd(hw, &desc, buff, num * sizeof(*buff), NULL); +} + +/** + * ice_is_health_status_code_supported - check if health status code is su= pported + * @hw: pointer to the hardware structure + * @code: health status code to check + * @supported: pointer to boolean result + * + * Return: 0 on success, negative error code otherwise + */ +int ice_is_health_status_code_supported(struct ice_hw *hw, u16 code, + bool *supported) +{ + const int BUFF_SIZE =3D ICE_AQC_HEALTH_STATUS_CODE_NUM; + struct ice_aqc_health_status_supp_elem *buff; + int ret; + + *supported =3D false; + buff =3D kcalloc(BUFF_SIZE, sizeof(*buff), GFP_KERNEL); + if (!buff) + return -ENOMEM; + ret =3D ice_aq_get_health_status_supported(hw, buff, BUFF_SIZE); + if (ret) + goto free_buff; + for (int i =3D 0; i < BUFF_SIZE && buff[i].health_status_code; i++) + if (le16_to_cpu(buff[i].health_status_code) =3D=3D code) { + *supported =3D true; + break; + } + +free_buff: + kfree(buff); + return ret; +} + +/** + * ice_get_last_health_status_code - get last health status for given code + * @hw: pointer to the hardware structure + * @out: pointer to the health status struct to be filled + * @code: health status code to check + * + * Return: 0 on success, negative error code otherwise + */ +int ice_get_last_health_status_code(struct ice_hw *hw, + struct ice_aqc_health_status_elem *out, + u16 code) +{ + const int BUFF_SIZE =3D ICE_AQC_HEALTH_STATUS_CODE_NUM; + struct ice_aqc_health_status_elem *buff; + int ret, last_status =3D -1; + + buff =3D kcalloc(BUFF_SIZE, sizeof(*buff), GFP_KERNEL); + if (!buff) + return -ENOMEM; + ret =3D ice_aq_get_health_status(hw, buff, BUFF_SIZE); + if (ret) + goto free_buff; + for (int i =3D 0; i < BUFF_SIZE && buff[i].health_status_code; i++) + if (le16_to_cpu(buff[i].health_status_code) =3D=3D code) + last_status =3D i; + + if (last_status >=3D 0) + memcpy(out, &buff[last_status], sizeof(*out)); + else + memset(out, 0, sizeof(*out)); + +free_buff: + kfree(buff); + return ret; +} + /** * ice_aq_set_health_status_cfg - Configure FW health events * @hw: pointer to the HW struct diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethern= et/intel/ice/ice_dpll.c index 3eea83b0cdc9..00704dfeb3b2 100644 --- a/drivers/net/ethernet/intel/ice/ice_dpll.c +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c @@ -18,6 +18,8 @@ #define ICE_DPLL_SW_PIN_INPUT_BASE_SFP 4 #define ICE_DPLL_SW_PIN_INPUT_BASE_QSFP 6 #define ICE_DPLL_SW_PIN_OUTPUT_BASE 0 +#define ICE_DPLL_HEALTH_STATUS_LOCKED 1 +#define ICE_DPLL_HEALTH_STATUS_UNLOCKED 0 =20 #define ICE_DPLL_PIN_SW_INPUT_ABS(in_idx) \ (ICE_DPLL_SW_PIN_INPUT_BASE_SFP + (in_idx)) @@ -80,6 +82,10 @@ static const struct dpll_pin_frequency ice_esync_range[]= =3D { DPLL_PIN_FREQUENCY_RANGE(0, DPLL_PIN_FREQUENCY_1_HZ), }; =20 +static const struct dpll_pin_frequency ice_esync_range_unmanaged[] =3D { + DPLL_PIN_FREQUENCY_1PPS, +}; + /** * ice_dpll_is_sw_pin - check if given pin shall be controlled by SW * @pf: private board structure @@ -1089,9 +1095,11 @@ ice_dpll_pin_state_get(const struct dpll_pin *pin, v= oid *pin_priv, return -EBUSY; =20 mutex_lock(&pf->dplls.lock); - ret =3D ice_dpll_pin_state_update(pf, p, pin_type, extack); - if (ret) - goto unlock; + if (!pf->dplls.unmanaged) { + ret =3D ice_dpll_pin_state_update(pf, p, pin_type, extack); + if (ret) + goto unlock; + } if (pin_type =3D=3D ICE_DPLL_PIN_TYPE_INPUT || pin_type =3D=3D ICE_DPLL_PIN_TYPE_OUTPUT) *state =3D p->state[d->dpll_idx]; @@ -2151,9 +2159,14 @@ ice_dpll_input_esync_get(const struct dpll_pin *pin,= void *pin_priv, mutex_unlock(&pf->dplls.lock); return -EOPNOTSUPP; } - esync->range =3D ice_esync_range; - esync->range_num =3D ARRAY_SIZE(ice_esync_range); - if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN) { + if (pf->dplls.unmanaged) { + esync->range =3D ice_esync_range_unmanaged; + esync->range_num =3D ARRAY_SIZE(ice_esync_range_unmanaged); + } else { + esync->range =3D ice_esync_range; + esync->range_num =3D ARRAY_SIZE(ice_esync_range); + } + if (p->flags[0] & ICE_DPLL_IN_ESYNC_ENABLED) { esync->freq =3D DPLL_PIN_FREQUENCY_1_HZ; esync->pulse =3D ICE_DPLL_PIN_ESYNC_PULSE_HIGH_PERCENT; } else { @@ -2588,6 +2601,21 @@ static const struct dpll_pin_ops ice_dpll_output_ops= =3D { .esync_get =3D ice_dpll_output_esync_get, }; =20 +static const struct dpll_pin_ops ice_dpll_input_unmanaged_ops =3D { + .frequency_get =3D ice_dpll_input_frequency_get, + .direction_get =3D ice_dpll_input_direction, + .state_on_dpll_get =3D ice_dpll_input_state_get, +#if defined(HAVE_DPLL_ESYNC) + .esync_get =3D ice_dpll_input_esync_get, +#endif /* HAVE_DPLL_ESYNC */ +}; + +static const struct dpll_pin_ops ice_dpll_output_unmanaged_ops =3D { + .frequency_get =3D ice_dpll_output_frequency_get, + .direction_get =3D ice_dpll_output_direction, + .state_on_dpll_get =3D ice_dpll_output_state_get, +}; + static const struct dpll_device_ops ice_dpll_ops =3D { .lock_status_get =3D ice_dpll_lock_status_get, .mode_get =3D ice_dpll_mode_get, @@ -3153,12 +3181,15 @@ ice_dpll_init_direct_pins(struct ice_pf *pf, bool c= gu, int ret; =20 ret =3D ice_dpll_get_pins(pf, pins, start_idx, count, pf->dplls.clock_id); - if (ret) + if (!cgu || ret) return ret; - if (cgu) { + + if (first) { ret =3D ice_dpll_register_pins(first, pins, ops, count); if (ret) goto release_pins; + } + if (second) { ret =3D ice_dpll_register_pins(second, pins, ops, count); if (ret) goto unregister_first; @@ -3167,7 +3198,8 @@ ice_dpll_init_direct_pins(struct ice_pf *pf, bool cgu, return 0; =20 unregister_first: - ice_dpll_unregister_pins(first, pins, ops, count); + if (first) + ice_dpll_unregister_pins(first, pins, ops, count); release_pins: ice_dpll_release_pins(pins, count); return ret; @@ -3424,6 +3456,18 @@ static void ice_dpll_deinit_pins(struct ice_pf *pf, = bool cgu) struct ice_dpll *de =3D &d->eec; struct ice_dpll *dp =3D &d->pps; =20 + if (d->unmanaged) { + ice_dpll_unregister_pins(dp->dpll, inputs, + &ice_dpll_input_unmanaged_ops, + num_inputs); + ice_dpll_unregister_pins(dp->dpll, outputs, + &ice_dpll_output_unmanaged_ops, + num_outputs); + ice_dpll_release_pins(inputs, num_inputs); + ice_dpll_release_pins(outputs, num_outputs); + return; + } + ice_dpll_deinit_rclk_pin(pf); if (pf->hw.mac_type =3D=3D ICE_MAC_GENERIC_3K_E825) ice_dpll_deinit_fwnode_pins(pf, pf->dplls.inputs, 0); @@ -3608,23 +3652,29 @@ static int ice_dpll_init_pins(struct ice_pf *pf, bo= ol cgu) const struct dpll_pin_ops *input_ops; int ret, count; =20 - input_ops =3D &ice_dpll_input_ops; - output_ops =3D &ice_dpll_output_ops; + if (!pf->dplls.unmanaged) { + input_ops =3D &ice_dpll_input_ops; + output_ops =3D &ice_dpll_output_ops; + } else { + input_ops =3D &ice_dpll_input_unmanaged_ops; + output_ops =3D &ice_dpll_output_unmanaged_ops; + } =20 ret =3D ice_dpll_init_direct_pins(pf, cgu, pf->dplls.inputs, 0, pf->dplls.num_inputs, input_ops, - pf->dplls.eec.dpll, - pf->dplls.pps.dpll); + pf->dplls.eec.dpll, pf->dplls.pps.dpll); if (ret) return ret; count =3D pf->dplls.num_inputs; - if (cgu) { + if (cgu || pf->dplls.unmanaged) { ret =3D ice_dpll_init_direct_pins(pf, cgu, pf->dplls.outputs, count, pf->dplls.num_outputs, output_ops, pf->dplls.eec.dpll, pf->dplls.pps.dpll); if (ret) goto deinit_inputs; + if (pf->dplls.unmanaged) + return 0; count +=3D pf->dplls.num_outputs; if (!pf->dplls.generic) { ret =3D ice_dpll_init_direct_pins(pf, cgu, pf->dplls.sma, @@ -3737,7 +3787,8 @@ ice_dpll_init_dpll(struct ice_pf *pf, struct ice_dpll= *d, bool cgu, =20 if (type =3D=3D DPLL_TYPE_PPS && ice_dpll_is_pps_phase_monitor(pf)) ops =3D &ice_dpll_pom_ops; - ice_dpll_update_state(pf, d, true); + if (!pf->dplls.unmanaged) + ice_dpll_update_state(pf, d, true); ret =3D dpll_device_register(d->dpll, type, ops, d); if (ret) { dpll_device_put(d->dpll, &d->tracker); @@ -3764,6 +3815,33 @@ static void ice_dpll_deinit_worker(struct ice_pf *pf) kthread_destroy_worker(d->kworker); } =20 +/** + * ice_dpll_pin_freq_info - find pin frequency from supported ones + * @hw: pointer to the hardware structure + * @pin_idx: pin index + * @input: if input pin + * + * This function searches through the array of supported frequencies for a + * DPLL pin and returns single frequency pin is capable, if pin support on= ly + * one frequency. Shall be used only for dpll with driver hardcoded freque= ncy. + * + * Return: + * * 0 - failure, pin uses multiple frequencies, + * * frequency - success. + */ +static u64 ice_dpll_pin_freq_info(struct ice_hw *hw, u8 pin_idx, bool inpu= t) +{ + struct dpll_pin_frequency *freqs; + u8 freq_num; + + /* Get supported frequencies for this pin */ + freqs =3D ice_cgu_get_pin_freq_supp(hw, pin_idx, input, &freq_num); + if (!freqs || freq_num !=3D 1 || freqs[0].min !=3D freqs[0].max) + return 0; + + return freqs[0].min; +} + /** * ice_dpll_init_worker - Initialize DPLLs periodic worker * @pf: board private structure @@ -3923,6 +4001,15 @@ ice_dpll_init_info_direct_pins(struct ice_pf *pf, pins[i].prop.board_label =3D ice_cgu_get_pin_name(hw, i, input); pins[i].prop.type =3D ice_cgu_get_pin_type(hw, i, input); if (input) { + if (pf->dplls.unmanaged) { + pins[i].freq =3D ice_dpll_pin_freq_info(hw, i, + input); + pins[i].state[0] =3D DPLL_PIN_STATE_CONNECTED; + pins[i].status =3D + ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_CAP; + pins[i].flags[0] =3D ICE_DPLL_IN_ESYNC_ENABLED; + continue; + } ret =3D ice_aq_get_cgu_ref_prio(hw, de->dpll_idx, i, &de->input_prio[i]); if (ret) @@ -3936,6 +4023,12 @@ ice_dpll_init_info_direct_pins(struct ice_pf *pf, if (ice_dpll_is_sw_pin(pf, i, true)) pins[i].hidden =3D true; } else { + if (pf->dplls.unmanaged) { + pins[i].freq =3D ice_dpll_pin_freq_info(hw, i, + input); + pins[i].state[0] =3D DPLL_PIN_STATE_CONNECTED; + continue; + } ret =3D ice_cgu_get_output_pin_state_caps(hw, i, &caps); if (ret) return ret; @@ -3953,10 +4046,13 @@ ice_dpll_init_info_direct_pins(struct ice_pf *pf, pins[i].prop.freq_supported_num =3D freq_supp_num; pins[i].pf =3D pf; } - if (input) + if (input && !pf->dplls.unmanaged) { ret =3D ice_dpll_init_ref_sync_inputs(pf); + if (ret) + return ret; + } =20 - return ret; + return 0; } =20 /** @@ -4174,6 +4270,81 @@ static int ice_dpll_init_info_e825c(struct ice_pf *p= f) return ret; } =20 +/* ice_dpll_lock_state_init_unmanaged - initialize lock state for unmanage= d dpll + * @pf: board private structure + * + * Initialize the lock state for unmanaged DPLL by checking health status. + * For unmanaged DPLL, we rely on hardware autonomous operation. + * + * Return: + * * 0 - success + * * negative - init failure reason + */ +static int ice_dpll_lock_state_init_unmanaged(struct ice_pf *pf) +{ + u16 code =3D ICE_AQC_HEALTH_STATUS_INFO_LOSS_OF_LOCK; + struct ice_aqc_health_status_elem buff; + int ret; + + ret =3D ice_get_last_health_status_code(&pf->hw, &buff, code); + if (ret) + return ret; + ice_dpll_lock_state_set_unmanaged(pf, &buff, false); + + return ret; +} + +/** + * ice_dpll_init_info_unmanaged - init dpll information for unmanaged dpll + * @pf: board private structure + * + * Acquire (from HW) and set basic dpll information (on pf->dplls struct). + * For unmanaged dpll mode. + * + * Return: + * * 0 - success + * * negative - init failure reason + */ +static int ice_dpll_init_info_unmanaged(struct ice_pf *pf) +{ + struct ice_dplls *d =3D &pf->dplls; + int ret; + + d->clock_id =3D ice_generate_clock_id(pf); + d->num_inputs =3D ice_cgu_get_pin_num(&pf->hw, true); + d->num_outputs =3D ice_cgu_get_pin_num(&pf->hw, false); + ret =3D ice_dpll_lock_state_init_unmanaged(pf); + if (ret) + return ret; + d->inputs =3D kcalloc(d->num_inputs, sizeof(*d->inputs), GFP_KERNEL); + if (!d->inputs) + return -ENOMEM; + + ret =3D ice_dpll_init_pins_info(pf, ICE_DPLL_PIN_TYPE_INPUT); + if (ret) + goto deinit_info; + + d->outputs =3D kcalloc(d->num_outputs, sizeof(*d->outputs), GFP_KERNEL); + if (!d->outputs) { + ret =3D -ENOMEM; + goto deinit_info; + } + + ret =3D ice_dpll_init_pins_info(pf, ICE_DPLL_PIN_TYPE_OUTPUT); + if (ret) + goto deinit_info; + + d->pps.mode =3D DPLL_MODE_MANUAL; + dev_dbg(ice_pf_to_dev(pf), "%s - success, inputs:%u, outputs:%u\n", + __func__, d->num_inputs, d->num_outputs); + return 0; +deinit_info: + dev_err(ice_pf_to_dev(pf), "%s - fail: d->inputs:%p, d->outputs:%p\n", + __func__, d->inputs, d->outputs); + ice_dpll_deinit_info(pf); + return ret; +} + /** * ice_dpll_init_info - prepare pf's dpll information structure * @pf: board private structure @@ -4273,6 +4444,42 @@ static int ice_dpll_init_info(struct ice_pf *pf, boo= l cgu) return ret; } =20 +/** + * ice_dpll_lock_state_set_unmanaged - determine lock state from health st= atus + * @pf: board private structure + * @buff: health status buffer + * @notify: if true, notify dpll device + * + * Set unmanaged dpll lock state based on health status code and internal = data. + * Context: Acquires and releases pf->dplls.lock (must release before noti= fy + * if called). + */ +void ice_dpll_lock_state_set_unmanaged(struct ice_pf *pf, + const struct ice_aqc_health_status_elem *buff, + bool notify) +{ + u32 internal_data =3D le32_to_cpu(buff->internal_data1); + struct ice_dpll *d =3D &pf->dplls.pps; + + if (!ice_pf_src_tmr_owned(pf)) + return; + + mutex_lock(&pf->dplls.lock); + if (buff->health_status_code =3D=3D 0 || + internal_data =3D=3D ICE_DPLL_HEALTH_STATUS_LOCKED) + d->dpll_state =3D DPLL_LOCK_STATUS_LOCKED; + else + d->dpll_state =3D DPLL_LOCK_STATUS_UNLOCKED; + + if (d->prev_dpll_state =3D=3D d->dpll_state) + notify =3D false; + else + d->prev_dpll_state =3D d->dpll_state; + mutex_unlock(&pf->dplls.lock); + if (notify && d->dpll) + dpll_device_change_ntf(d->dpll); +} + /** * ice_dpll_deinit - Disable the driver/HW support for dpll subsystem * the dpll device. @@ -4292,15 +4499,55 @@ void ice_dpll_deinit(struct ice_pf *pf) if (cgu) ice_dpll_deinit_worker(pf); =20 - ice_dpll_deinit_pins(pf, cgu); + ice_dpll_deinit_pins(pf, cgu || pf->dplls.unmanaged); if (!IS_ERR_OR_NULL(pf->dplls.pps.dpll)) - ice_dpll_deinit_dpll(pf, &pf->dplls.pps, cgu); + ice_dpll_deinit_dpll(pf, &pf->dplls.pps, + cgu || pf->dplls.unmanaged); if (!IS_ERR_OR_NULL(pf->dplls.eec.dpll)) ice_dpll_deinit_dpll(pf, &pf->dplls.eec, cgu); ice_dpll_deinit_info(pf); mutex_destroy(&pf->dplls.lock); } =20 +/** + * ice_dpll_init_unmanaged - initialize support for unmanaged dpll subsyst= em + * @pf: board private structure + * + * Set up the device dplls for unmanaged mode, register them and pins conn= ected + * within Linux dpll subsystem. Allow userspace to obtain state of DPLL. + * + * Context: Initializes pf->dplls.lock mutex. + */ +static void ice_dpll_init_unmanaged(struct ice_pf *pf) +{ + struct ice_dplls *d =3D &pf->dplls; + int err; + + if (!ice_pf_src_tmr_owned(pf)) + return; + mutex_init(&d->lock); + err =3D ice_dpll_init_info_unmanaged(pf); + if (err) + goto err_exit; + err =3D ice_dpll_init_dpll(pf, &pf->dplls.pps, true, DPLL_TYPE_PPS); + if (err) + goto deinit_info; + err =3D ice_dpll_init_pins(pf, true); + if (err) + goto deinit_pps; + set_bit(ICE_FLAG_DPLL, pf->flags); + + return; + +deinit_pps: + ice_dpll_deinit_dpll(pf, &pf->dplls.pps, true); +deinit_info: + ice_dpll_deinit_info(pf); +err_exit: + mutex_destroy(&d->lock); + dev_warn(ice_pf_to_dev(pf), "DPLLs init failure err:%d\n", err); +} + /** * ice_dpll_init_e825 - initialize support for dpll subsystem * @pf: board private structure @@ -4388,8 +4635,23 @@ static void ice_dpll_init_e810(struct ice_pf *pf) dev_warn(ice_pf_to_dev(pf), "DPLLs init failure err:%d\n", err); } =20 +/** + * ice_dpll_init - initialize support for dpll subsystem + * @pf: board private structure + * + * Set up the device dplls, register them and pins connected within Linux = dpll + * subsystem. Allow userspace to obtain state of DPLL and handling of DPLL + * configuration requests. + * + * Context: Initializes pf->dplls.lock mutex. + */ void ice_dpll_init(struct ice_pf *pf) { + if (pf->dplls.unmanaged) { + ice_dpll_init_unmanaged(pf); + return; + } + switch (pf->hw.mac_type) { case ICE_MAC_GENERIC_3K_E825: ice_dpll_init_e825(pf); diff --git a/drivers/net/ethernet/intel/ice/ice_main.c b/drivers/net/ethern= et/intel/ice/ice_main.c index 5f92377d4dfc..de2b8dd52824 100644 --- a/drivers/net/ethernet/intel/ice/ice_main.c +++ b/drivers/net/ethernet/intel/ice/ice_main.c @@ -4714,7 +4714,9 @@ void ice_deinit_dev(struct ice_pf *pf) =20 static void ice_init_features(struct ice_pf *pf) { + u16 code =3D ICE_AQC_HEALTH_STATUS_INFO_LOSS_OF_LOCK; struct device *dev =3D ice_pf_to_dev(pf); + int err; =20 if (ice_is_safe_mode(pf)) return; @@ -4726,8 +4728,15 @@ static void ice_init_features(struct ice_pf *pf) if (ice_is_feature_supported(pf, ICE_F_GNSS)) ice_gnss_init(pf); =20 + /* Initialize unmanaged DPLL detection */ + err =3D ice_is_health_status_code_supported(&pf->hw, code, + &pf->dplls.unmanaged); + if (err || !ice_is_unmanaged_cgu_in_netlist(&pf->hw)) + pf->dplls.unmanaged =3D false; + if (ice_is_feature_supported(pf, ICE_F_CGU) || - ice_is_feature_supported(pf, ICE_F_PHY_RCLK)) + ice_is_feature_supported(pf, ICE_F_PHY_RCLK) || + pf->dplls.unmanaged) ice_dpll_init(pf); =20 /* Note: Flow director init failure is non-fatal to load */ diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethe= rnet/intel/ice/ice_ptp_hw.c index 24fb7a3e14d6..d8d20b1ef209 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c @@ -20,6 +20,10 @@ static struct dpll_pin_frequency ice_cgu_pin_freq_10_mhz= [] =3D { DPLL_PIN_FREQUENCY_10MHZ, }; =20 +static struct dpll_pin_frequency ice_cgu_pin_freq_156_25mhz[] =3D { + DPLL_PIN_FREQUENCY_RANGE(156250000, 156250000), +}; + static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_inputs[] =3D { { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR, ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, @@ -131,6 +135,18 @@ static const struct ice_cgu_pin_desc ice_e823_zl_cgu_o= utputs[] =3D { { "NONE", ZL_OUT5, 0, 0 }, }; =20 +static const struct ice_cgu_pin_desc ice_e830_unmanaged_inputs[] =3D { + { "1588-TIME_SYNC", 0, DPLL_PIN_TYPE_EXT, + ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz }, +}; + +static const struct ice_cgu_pin_desc ice_e830_unmanaged_outputs[] =3D { + { "MAC-PHY-CLK", 0, DPLL_PIN_TYPE_SYNCE_ETH_PORT, + ARRAY_SIZE(ice_cgu_pin_freq_156_25mhz), ice_cgu_pin_freq_156_25mhz }, + { "1588-TIME_REF", 1, DPLL_PIN_TYPE_INT_OSCILLATOR, + ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz}, +}; + /* Low level functions for interacting with and managing the device clock = used * for the Precision Time Protocol. * @@ -5923,6 +5939,24 @@ ice_cgu_get_pin_desc(struct ice_hw *hw, bool input, = int *size) case ICE_DEV_ID_E823C_SGMII: t =3D ice_cgu_get_pin_desc_e823(hw, input, size); break; + case ICE_DEV_ID_E830CC_BACKPLANE: + case ICE_DEV_ID_E830CC_QSFP56: + case ICE_DEV_ID_E830CC_SFP: + case ICE_DEV_ID_E830CC_SFP_DD: + case ICE_DEV_ID_E830C_BACKPLANE: + case ICE_DEV_ID_E830C_QSFP: + case ICE_DEV_ID_E830C_SFP: + case ICE_DEV_ID_E830_XXV_BACKPLANE: + case ICE_DEV_ID_E830_XXV_QSFP: + case ICE_DEV_ID_E830_XXV_SFP: + if (input) { + t =3D ice_e830_unmanaged_inputs; + *size =3D ARRAY_SIZE(ice_e830_unmanaged_inputs); + } else { + t =3D ice_e830_unmanaged_outputs; + *size =3D ARRAY_SIZE(ice_e830_unmanaged_outputs); + } + break; default: break; } @@ -5949,6 +5983,18 @@ int ice_cgu_get_num_pins(struct ice_hw *hw, bool inp= ut) return 0; } =20 +/** + * ice_cgu_get_pin_num - get pin description array size + * @hw: pointer to the hw struct + * @input: if request is done against input or output pins + * + * Return: size of pin description array for given hw. + */ +int ice_cgu_get_pin_num(struct ice_hw *hw, bool input) +{ + return ice_cgu_get_num_pins(hw, input); +} + /** * ice_cgu_get_pin_type - get pin's type * @hw: pointer to the hw struct diff --git a/Documentation/networking/device_drivers/ethernet/intel/ice.rst= b/Documentation/networking/device_drivers/ethernet/intel/ice.rst index 0bca293cf9cb..7c24761d1008 100644 --- a/Documentation/networking/device_drivers/ethernet/intel/ice.rst +++ b/Documentation/networking/device_drivers/ethernet/intel/ice.rst @@ -941,6 +941,89 @@ To see input signal on those PTP pins, you need to con= figure DPLL properly. Output signal is only visible on DPLL and to send it to the board SMA/U.FL= pins, DPLL output pins have to be manually configured. =20 +Unmanaged DPLL Support +---------------------- +Hardware variants of E830 may support an unmanaged DPLL: + +- Intel=C2=AE Ethernet Network Adapter E830-XXVDA8F for OCP 3.0, + +- Intel=C2=AE Ethernet Network Adapter E830-XXVDA4F. + +In the case of the unmanaged DPLL, the configuration is hardcoded within t= he +hardware and firmware, meaning users cannot modify settings. However, +users can check the DPLL lock status and obtain configuration information +through the Linux DPLL subsystem. + +When present, the DPLL device locks to an external signal provided through= the +PCIe/OCP pin. The expected input signal is 1PPS (1 Pulse Per Second) embed= ded +on a 10MHz reference clock. +The DPLL produces output: + +- for MAC (Media Access Control) & PHY (Physical Layer) clocks, + +- 1PPS for synchronization of onboard PHC (Precision Hardware Clock) timer. + +Requirements: The Linux kernel must have support for both the DPLL Subsyst= em +and the Embedded Sync patch series. + +Example output of querying the Linux DPLL subsystem can be found below. + +.. code-block:: console + :caption: Dumping the DPLL pins + + $ --spec Documentation/netlink/specs/dpll.yaml --dump pin-get + [{'board-label': '1588-TIME_SYNC', + 'capabilities': set(), + 'clock-id': 282574471561216, + 'esync-frequency': 1, + 'esync-frequency-supported': [{'frequency-max': 1, 'frequency-min': 1}= ], + 'esync-pulse': 25, + 'frequency': 10000000, + 'id': 13, + 'module-name': 'ice', + 'parent-device': [{'direction': 'input', + 'parent-id': 6, + 'state': 'connected'}], + 'phase-adjust-max': 0, + 'phase-adjust-min': 0, + 'type': 'ext'}, + {'board-label': 'MAC-PHY-CLK', + 'capabilities': set(), + 'clock-id': 282574471561216, + 'frequency': 156250000, + 'id': 14, + 'module-name': 'ice', + 'parent-device': [{'direction': 'output', + 'parent-id': 6, + 'state': 'connected'}], + 'phase-adjust-max': 0, + 'phase-adjust-min': 0, + 'type': 'synce-eth-port'}, + {'board-label': '1588-TIME_REF', + 'capabilities': set(), + 'clock-id': 282574471561216, + 'frequency': 1, + 'id': 15, + 'module-name': 'ice', + 'parent-device': [{'direction': 'output', + 'parent-id': 6, + 'state': 'connected'}], + 'phase-adjust-max': 0, + 'phase-adjust-min': 0, + 'type': 'int-oscillator'}] + +.. code-block:: console + :caption: Dumping the DPLL devices + + $ --spec Documentation/netlink/specs/dpll.yaml --dump device-get + [{'clock-id': 282574471561216, + 'id': 6, + 'lock-status': 'locked', + 'mode': 'manual', + 'mode-supported': ['manual'], + 'module-name': 'ice', + 'type': 'pps'}] + GNSS module ----------- Requires kernel compiled with CONFIG_GNSS=3Dy or CONFIG_GNSS=3Dm. --=20 2.54.0.rc2.531.gaf818d63126a