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Thu, 30 Apr 2026 02:20:21 -0700 (PDT) Received: from hu-smankad-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c7fd5e6cf20sm4614782a12.3.2026.04.30.02.20.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2026 02:20:21 -0700 (PDT) From: Sneh Mankad Date: Thu, 30 Apr 2026 14:50:07 +0530 Subject: [PATCH v2] pinctrl: qcom: Unconditionally mark gpio as wakeup enable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260430-enable_wakeup_capable_gpios-v2-1-8c26ac795318@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIAMYe82kC/43NQQ6CMBCF4auQri0pBcGy8h6GkFIGmAi0dgQ1h LtbOYGbSb5Z/G9jBB6BWBltzMOKhHYOkKeImUHPPXBsg5kUMhdZKjjMuhmhfuk7LK422h3sHVr iplFZqjRcikKyUHAeOnwf9VsVPCA9rf8cY2vy+/7XXROe8HMLqWo6kQuVXS1R/Fj0aOw0xeGwa t/3L937jynNAAAA X-Change-ID: 20260430-enable_wakeup_capable_gpios-cb9439ae8772 To: Bjorn Andersson , Linus Walleij , Neil Armstrong , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Sneh Mankad , Maulik Shah X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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This is set only for PDC irqchip using additional check skip_wake_irqs making it impossible for MPM irqchip to detect the GPIO interrupt during SoC low power mode since for MPM irqchip the skip_wake_irqs is always false. Remove skip_wake_irqs condition when setting wakeup enable bit to allow forwarding GPIO interrupts for SoCs using MPM irqchip too. Fixes: 76b446f5b86e ("pinctrl: qcom: handle intr_target_reg wakeup_present/= enable bits") Signed-off-by: Sneh Mankad Reviewed-by: Maulik Shah --- Changes in v2: - Modified comment to specify MPM HW as well. - Spelling correction. - Link to v1: https://lore.kernel.org/r/20260430-enable_wakeup_capable_gpio= s-v1-1-5de39bf06094@oss.qualcomm.com --- drivers/pinctrl/qcom/pinctrl-msm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinc= trl-msm.c index 45b3a2763eb85405fecdd4770ba3d4ab684563f0..6a24f9b5e4a979528ba6b5b87fd= 297c2783ec765 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -1242,12 +1242,12 @@ static int msm_gpio_irq_reqres(struct irq_data *d) /* * If the wakeup_enable bit is present and marked as available for the * requested GPIO, it should be enabled when the GPIO is marked as - * wake irq in order to allow the interrupt event to be transfered to - * the PDC HW. + * wake irq in order to allow the interrupt event to be transferred to + * the PDC/MPM HW. * While the name implies only the wakeup event, it's also required for * the interrupt event. */ - if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_b= it) { + if (g->intr_wakeup_present_bit) { u32 intr_cfg; =20 raw_spin_lock_irqsave(&pctrl->lock, flags); @@ -1275,7 +1275,7 @@ static void msm_gpio_irq_relres(struct irq_data *d) unsigned long flags; =20 /* Disable the wakeup_enable bit if it has been set in msm_gpio_irq_reqre= s() */ - if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_b= it) { + if (g->intr_wakeup_present_bit) { u32 intr_cfg; =20 raw_spin_lock_irqsave(&pctrl->lock, flags); --- base-commit: b4e07588e743c989499ca24d49e752c074924a9a change-id: 20260430-enable_wakeup_capable_gpios-cb9439ae8772 Best regards, --=20 Sneh Mankad