From nobody Tue Jun 16 17:02:08 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55D3013B7AE; Thu, 30 Apr 2026 10:31:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777545065; cv=none; b=hRFMqCj9Bn8sFEytlMddhkEFluycOrJvpZxe9greMFxaCqM27YgcbqadXhR9yEObCUNk35zdcP0yZyV+OU1WgtfgHzqsbh0Kc+kO5WppYYVRvuivREwnR4LYv18hSnteuaHVM6TJZfSeJxyFOSc4X95TGtYuB4IjBbN5pvVzcYk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777545065; c=relaxed/simple; bh=QJ3l9s3WRH0yxHRx/NIafnOMgM2A7S6+psCcSgpfN6I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EY0PJpRWj3QmyVSQaskBBxoRxTPrSH1eJRLM3FtbC2PKP8IlRDs18oHWb283R8LDBGWVgOwlGIfXhJhBoZ1qE5r3FwrqI5NCwxm0vE26LJkL3Am24cfzGt0N4gGu8EBr+zD4sNRRfUmDCZvvTTp/w/DrgghVxy9pS3TYTnazocU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NnqFYq25; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NnqFYq25" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9E1CFC2BCB4; Thu, 30 Apr 2026 10:30:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777545065; bh=QJ3l9s3WRH0yxHRx/NIafnOMgM2A7S6+psCcSgpfN6I=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=NnqFYq25pGo/VPzFfdpzHdzYlZeqEzFG2P1obsx6PyWS6zGWijOpXPwFJAIwl2cP9 tbECcUYRuHW5FhBbPwYc19hYSMmzRY3TgdNdXwbhm5ILN613etBRLZJab+mS8PWxDD TuXP2PMhVc9Qa8R9Xvq6VSYiamcOOyYDfa8Vmssc6yKp0RBshZG0HYNJtxnPKjuX/2 QH5a/rvz73TgSQRkwZ3wTt2dtxvwLTMATVeBaGiCdMB/FKSE9JSi8wZ1XIVDfC6Ncn OmZyZ1HSwja6jPm3a0Ndnt3kQoHyfkh0OU/WQctoiqLlDcE4M4hcTG6hedkQ8AG6FT ti+eeEkLWJahQ== From: Yixun Lan Date: Thu, 30 Apr 2026 10:30:26 +0000 Subject: [PATCH 1/4] dt-bindings: soc: spacemit: k3: Add PCIe DBI clock IDs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260430-06-pci-clk-fix-v1-1-32fdc77c02ab@kernel.org> References: <20260430-06-pci-clk-fix-v1-0-32fdc77c02ab@kernel.org> In-Reply-To: <20260430-06-pci-clk-fix-v1-0-32fdc77c02ab@kernel.org> To: Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Inochi Amaoto , Krzysztof Kozlowski , linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, Yixun Lan X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=936; i=dlan@kernel.org; h=from:subject:message-id; bh=QJ3l9s3WRH0yxHRx/NIafnOMgM2A7S6+psCcSgpfN6I=; b=owEB6QIW/ZANAwAKATGq6kdZTbvtAcsmYgBp8y9SSIqzEuSPbtUyWFait1k7Ip757U8OyVpzG t+X0JrAYvqJAq8EAAEKAJkWIQS1urjJwxtxFWcCI9wxqupHWU277QUCafMvUhsUgAAAAAAEAA5t YW51MiwyLjUrMS4xMiwyLDJfFIAAAAAALgAoaXNzdWVyLWZwckBub3RhdGlvbnMub3BlbnBncC5 maWZ0aGhvcnNlbWFuLm5ldEI1QkFCOEM5QzMxQjcxMTU2NzAyMjNEQzMxQUFFQTQ3NTk0REJCRU QACgkQMarqR1lNu+2Mpg/7B4iSJo/BrSyeWdPkixvHCMSvye2WX+yY/meFPbYJ0W8qrlsGwMCke EMj+Rrhiz1tHULVm6H+S7jPCFvCDMd3Ryp8oad/An4BEBrECfpqTjl9UKLpFoX9GbU7SbiYh6Hi 1sNZ807E3wDXP+W5+i4DSX83qH7pRflD41wm9g4rzmCA7msr8dSjJLbVFDWGuYrYiOd0y5m3uMb bDokkeQonPIexstW9cQ37IIBi2qt2y9bkiUerUMOUl+QvNhWctU26m0TljWka42tjyMyKTVpCR5 RdUA6CwzvhVNhphZJy+ktYDNwesoFDnqN/Gub2R/1Wjr8ONQ2cH9MxHBxjboCHGXmIIyZqR0u2s ssZc+wO8KjfqTQxc+yDBC604BSWuj1akNTZhntx64pPt2FUQsKZj5+ScLrpNIxzbxzIIZ4E5smp 8oM5nqNMKBIHU70iURQ8Y1gtgc8RB7hgmPXNxrtktGPhCMTv4CrYg6b/9fnPvdl8pBwEwr3bI/U MaPekx9ZrFh4JlzPvo/fd0V2y2jhiRwQcCPfncaMy3GiAhoHDcTdaJL+T/DPo6Zq4DO53Bpf0SH YviBuQJ+8UVCAcuGlSL/ZpNebMx60C6VnV1x7VYKTRKbhiWxdD4pTPSSnxOaJYRfH6qAG8Kve7v t9kOOonzcx+Zkz2RK5dPR11B6IVJtc= X-Developer-Key: i=dlan@kernel.org; a=openpgp; fpr=50B03A1A5CBCD33576EF8CD7920C0DBCAABEFD55 Add clock IDs of PCIe DBI (Data Bus Interface) clock. Fixes: efe897b557e2 ("dt-bindings: soc: spacemit: k3: add clock support") Signed-off-by: Yixun Lan --- include/dt-bindings/clock/spacemit,k3-clocks.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/dt-bindings/clock/spacemit,k3-clocks.h b/include/dt-bi= ndings/clock/spacemit,k3-clocks.h index b22336f3ae40..dfae52547cda 100644 --- a/include/dt-bindings/clock/spacemit,k3-clocks.h +++ b/include/dt-bindings/clock/spacemit,k3-clocks.h @@ -380,6 +380,11 @@ #define CLK_APMU_ISIM_VCLK1 86 #define CLK_APMU_ISIM_VCLK2 87 #define CLK_APMU_ISIM_VCLK3 88 +#define CLK_APMU_PCIE_PORTA_DBI 89 +#define CLK_APMU_PCIE_PORTB_DBI 90 +#define CLK_APMU_PCIE_PORTC_DBI 91 +#define CLK_APMU_PCIE_PORTD_DBI 92 +#define CLK_APMU_PCIE_PORTE_DBI 93 =20 /* DCIU clocks */ #define CLK_DCIU_HDMA 0 --=20 2.53.0 From nobody Tue Jun 16 17:02:08 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E94B18C2C; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KEKdrlDG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D5D73C2BCC4; Thu, 30 Apr 2026 10:31:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777545072; bh=IpiL+RBz1lSzMr/JnmJS8SeVm2TVfTS8BYtTohl5w98=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=KEKdrlDGtaguhU3e9fRgZySaUtO6E6il83MyyA3lCmKKQ+CgDeSn0xB1W35/OyTxA Jj4lJE2j1zyqgkvVqxd69avVGK0QLwKcbxHy3LLoH2LF4cuDKauhXa8PFDH/XJN/P+ 6O44Yr78vHsseSOsUHZvAilRbOhA5NYbzFpa6jHx8nQiDNWQVw0zOa99063wjTrARK t4XPqZtGx6yJT/U/5er83kVLGr2jODtLfkAvVbQjQGI6XmJDOTQq+W0+RfegJZY1Yq 1r8sY6PpQyBzNnT87kTVRIZuvlnbB2ck4/3bOH0a10R9QRhsln3K29c9q4ZVIOGtXW LklVkBj8Gcpvg== From: Yixun Lan Date: Thu, 30 Apr 2026 10:30:27 +0000 Subject: [PATCH 2/4] clk: spacemit: k3: Add PCIe DBI clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260430-06-pci-clk-fix-v1-2-32fdc77c02ab@kernel.org> References: <20260430-06-pci-clk-fix-v1-0-32fdc77c02ab@kernel.org> In-Reply-To: <20260430-06-pci-clk-fix-v1-0-32fdc77c02ab@kernel.org> To: Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Inochi Amaoto , Krzysztof Kozlowski , linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, Yixun Lan X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3245; i=dlan@kernel.org; h=from:subject:message-id; bh=IpiL+RBz1lSzMr/JnmJS8SeVm2TVfTS8BYtTohl5w98=; b=owEB6AIX/ZANAwAKATGq6kdZTbvtAcsmYgBp8y9W4tjslaqQWKo0VLk22lTFGGPnVzG4a1Kbr XrkhnSSpvGJAq4EAAEKAJkWIQS1urjJwxtxFWcCI9wxqupHWU277QUCafMvVhsUgAAAAAAEAA5t YW51MiwyLjUrMS4xMiwyLDJfFIAAAAAALgAoaXNzdWVyLWZwckBub3RhdGlvbnMub3BlbnBncC5 maWZ0aGhvcnNlbWFuLm5ldEI1QkFCOEM5QzMxQjcxMTU2NzAyMjNEQzMxQUFFQTQ3NTk0REJCRU QACgkQMarqR1lNu+2cww/410ftVHlIPv/3hC8bUZOVC+fddhyL9Jjqfckpoh1x59BOYjNyFvHOU qUXDfoKPXvmnAIHtHT+MrX8o7RfX1mF85cNEhiW5R3WnLquVNSrJ6R7DCX1/8zdykwDp+xT+6E+ YNJT6f5+6wnldI107HLVi1PCCgRw+W7CoXyk97O99O72QHArBC/oxcg4lJOyJlXBYA4WNvLRpHr C2ZRiKMURX660AjyHIoAIMYwkCMCas7vbEyN3IeFN5kzmzPTP5mFyUkk6JOS6NekyUvAZyo1pIR Sapmlgka4/MPk7bIXqEDUFcN3Cu58OQV2k+Ea971SHTSNnboVoAQIl8OaTsrI6UnJlCk15v1U4U s97JS+tpzeHBrOnAgQLei83p+kkcxrIWO2mtPLHJmZKrMEEEHgq1ysLGB8vvBNzC7zR25+5goxg I9cXp5MpuI+ymtHJZp4r7+5F0sk18/L3cV5uecMblBe7DLNm1SmRzDzeu61uy3dIEzrM0us9ego ejWm4cgbIqiNvZqngTspnWwXHrsAAnQBHOKty9V0xY5B+zkJ1VQ/YOlKcZGV5bS+fa5v4m5yqZS fLUy9Qtjx+ex1oK5tAQiCsWtC22FuFdAtgjZakDoTGCuOrpyItYDN3oyN0hA1EnGpyv3ENO9opi CQfmg9T8esiZjk1kAul2D4xVNlSOQ== X-Developer-Key: i=dlan@kernel.org; a=openpgp; fpr=50B03A1A5CBCD33576EF8CD7920C0DBCAABEFD55 Add PCIe DBI (Data Bus Interface) clock which was missing. Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") Signed-off-by: Yixun Lan --- drivers/clk/spacemit/ccu-k3.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c index e98afd59f05c..bd60c0d776b4 100644 --- a/drivers/clk/spacemit/ccu-k3.c +++ b/drivers/clk/spacemit/ccu-k3.c @@ -949,14 +949,19 @@ CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, AP= MU_LCD_EDP_CTRL, 18, 1, BIT =20 CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_= CTRL_A, BIT(2), 0); CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_A, BIT(1), 0); +CCU_GATE_DEFINE(pciea_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_A, BIT(0), 0); CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_= CTRL_B, BIT(2), 0); CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_B, BIT(1), 0); +CCU_GATE_DEFINE(pcieb_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_B, BIT(0), 0); CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_= CTRL_C, BIT(2), 0); CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_C, BIT(1), 0); +CCU_GATE_DEFINE(pciec_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_C, BIT(0), 0); CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_= CTRL_D, BIT(2), 0); CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_D, BIT(1), 0); +CCU_GATE_DEFINE(pcied_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_D, BIT(0), 0); CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_= CTRL_E, BIT(2), 0); CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_E, BIT(1), 0); +CCU_GATE_DEFINE(pciee_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_E, BIT(0), 0); =20 static const struct clk_parent_data emac_1588_parents[] =3D { CCU_PARENT_NAME(vctcxo_24m), @@ -1391,14 +1396,19 @@ static struct clk_hw *k3_ccu_apmu_hws[] =3D { [CLK_APMU_EDP1_PXCLK] =3D &edp1_pxclk.common.hw, [CLK_APMU_PCIE_PORTA_MSTE] =3D &pciea_mstr_clk.common.hw, [CLK_APMU_PCIE_PORTA_SLV] =3D &pciea_slv_clk.common.hw, + [CLK_APMU_PCIE_PORTA_DBI] =3D &pciea_dbi_clk.common.hw, [CLK_APMU_PCIE_PORTB_MSTE] =3D &pcieb_mstr_clk.common.hw, [CLK_APMU_PCIE_PORTB_SLV] =3D &pcieb_slv_clk.common.hw, + [CLK_APMU_PCIE_PORTB_DBI] =3D &pcieb_dbi_clk.common.hw, [CLK_APMU_PCIE_PORTC_MSTE] =3D &pciec_mstr_clk.common.hw, [CLK_APMU_PCIE_PORTC_SLV] =3D &pciec_slv_clk.common.hw, + [CLK_APMU_PCIE_PORTC_DBI] =3D &pciec_dbi_clk.common.hw, [CLK_APMU_PCIE_PORTD_MSTE] =3D &pcied_mstr_clk.common.hw, [CLK_APMU_PCIE_PORTD_SLV] =3D &pcied_slv_clk.common.hw, + [CLK_APMU_PCIE_PORTD_DBI] =3D &pcied_dbi_clk.common.hw, [CLK_APMU_PCIE_PORTE_MSTE] =3D &pciee_mstr_clk.common.hw, [CLK_APMU_PCIE_PORTE_SLV] =3D &pciee_slv_clk.common.hw, + [CLK_APMU_PCIE_PORTE_DBI] =3D &pciee_dbi_clk.common.hw, [CLK_APMU_EMAC0_BUS] =3D &emac0_bus_clk.common.hw, [CLK_APMU_EMAC0_REF] =3D &emac0_ref_clk.common.hw, [CLK_APMU_EMAC0_1588] =3D &emac0_1588_clk.common.hw, --=20 2.53.0 From nobody Tue Jun 16 17:02:08 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C2A3285072; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KRd3tdRa" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7933EC2BCB3; Thu, 30 Apr 2026 10:31:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777545077; bh=0hL8QmJznMFL7fjhjp0jS5VvDwviOUJ8jc36396/SQM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=KRd3tdRalN0wvzVqkdTxcN68y724lsVZ6msGTkoqj9fg955iv86PS120Rte7lLcmx XBo8F3KKOrvzdt+niuP2NALCnw+BrlQWnrxol75t1vwiuj0ggPPpVbxzT6FtyPBhJw FxnMkUBx2fl7E2F8hyhk+31QbikrYUOR6p9MHaJIGQUY70S0u59kmxn2iL/y/a+vrU kowpZBXj77ILXddOO/XEWTpXvJgv+MD3Sy8SsRJMvTSfnH4iwZYgTRZQoUH+I3oqgq xHOSyrh+tkOK/11KNfynTStVSXglioI34U9E0dlqahFjg7hpNmqQy/B886KalE+ng2 LtE/pueZE9O3w== From: Yixun Lan Date: Thu, 30 Apr 2026 10:30:28 +0000 Subject: [PATCH 3/4] clk: spacemit: k3: Switch to pll2_d6 as parent for PCIe clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260430-06-pci-clk-fix-v1-3-32fdc77c02ab@kernel.org> References: <20260430-06-pci-clk-fix-v1-0-32fdc77c02ab@kernel.org> In-Reply-To: <20260430-06-pci-clk-fix-v1-0-32fdc77c02ab@kernel.org> To: Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Inochi Amaoto , Krzysztof Kozlowski , linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, Yixun Lan X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3177; i=dlan@kernel.org; h=from:subject:message-id; bh=0hL8QmJznMFL7fjhjp0jS5VvDwviOUJ8jc36396/SQM=; b=owEB6QIW/ZANAwAKATGq6kdZTbvtAcsmYgBp8y9ZNVwEggvuhhjAjcA+7744Uek7q8h5cIG00 zCqqYMo43+JAq8EAAEKAJkWIQS1urjJwxtxFWcCI9wxqupHWU277QUCafMvWRsUgAAAAAAEAA5t YW51MiwyLjUrMS4xMiwyLDJfFIAAAAAALgAoaXNzdWVyLWZwckBub3RhdGlvbnMub3BlbnBncC5 maWZ0aGhvcnNlbWFuLm5ldEI1QkFCOEM5QzMxQjcxMTU2NzAyMjNEQzMxQUFFQTQ3NTk0REJCRU QACgkQMarqR1lNu+2nWw/+KGor7vBHizlsZkVuvectfrs5ZQdGJqxyECFf1DCN05f4C052E0ayn vxt8jkVBzmCLNq0NEWBsODmvywYfmQH56xZANZBqmR57VRS1LIxzlnu/cvLuFnTjybp65wBAvnE PqWuGlnZwzlbTgifrY8Qkgnh3p3SknXZtWgaQDaoGQ+zijO70aBZLHdbWRsAHhpGPxtVd/wHuvM YenocpUyMZtlcE9Wsj7t7GzPfJDqKrrBI2Xj/MLFWnEmHMvTi3uLvuh4/JKQoXXx4B1d8W/7H13 7CyX9dT1nafcshh6Kzve1IF8fehmXxjt0qaCHDgb1aNUWL8fHT2beiuJNO+EdIaY6zfZYIwWkX/ TmvDkh7doL/y8HZsLNO42gqeLLiZA2in7C4NRX4fPWkVrqjO6auOx2dI/WLbmNqa8+mvcKFDsHA O63/V+PRWTUleE3e87q0dt/NqPoE8isxS9xadOYqt9TiqrSaUZvKx+0m5vnXDm7AZ82M47L2v6r bjt8n2+b7P4SsI3OCG8e9/SPYVRZIaYoRxH4LU0nBnE+Cc6+fHvPxte6kOJZjlTUESJsEKpY8bb BR4zQRfQ/UAtdKcN4UJTxVb5gQM4QYr2UBVJV7xo+GeFts8/GVO1KRHS7WolZtP7wUqI3tW4cWW igwRnSf5G3ep0EMX/POSX62esp2WJA= X-Developer-Key: i=dlan@kernel.org; a=openpgp; fpr=50B03A1A5CBCD33576EF8CD7920C0DBCAABEFD55 According to SpacemiT updated docs, the PCIe master and slave clock's parent is the pll2_d6 clock, so fix it. Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") Signed-off-by: Yixun Lan --- drivers/clk/spacemit/ccu-k3.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c index bd60c0d776b4..196d32194125 100644 --- a/drivers/clk/spacemit/ccu-k3.c +++ b/drivers/clk/spacemit/ccu-k3.c @@ -947,20 +947,20 @@ static const struct clk_parent_data edp1_pclk_parents= [] =3D { }; CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, = 1, BIT(17), 0); =20 -CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_= CTRL_A, BIT(2), 0); -CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_A, BIT(1), 0); +CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_= CTRL_A, BIT(2), 0); +CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_C= TRL_A, BIT(1), 0); CCU_GATE_DEFINE(pciea_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_A, BIT(0), 0); -CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_= CTRL_B, BIT(2), 0); -CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_B, BIT(1), 0); +CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_= CTRL_B, BIT(2), 0); +CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_C= TRL_B, BIT(1), 0); CCU_GATE_DEFINE(pcieb_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_B, BIT(0), 0); -CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_= CTRL_C, BIT(2), 0); -CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_C, BIT(1), 0); +CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_= CTRL_C, BIT(2), 0); +CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_C= TRL_C, BIT(1), 0); CCU_GATE_DEFINE(pciec_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_C, BIT(0), 0); -CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_= CTRL_D, BIT(2), 0); -CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_D, BIT(1), 0); +CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_= CTRL_D, BIT(2), 0); +CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_C= TRL_D, BIT(1), 0); CCU_GATE_DEFINE(pcied_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_D, BIT(0), 0); -CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_= CTRL_E, BIT(2), 0); -CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_E, BIT(1), 0); +CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_= CTRL_E, BIT(2), 0); +CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_C= TRL_E, BIT(1), 0); CCU_GATE_DEFINE(pciee_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_E, BIT(0), 0); =20 static const struct clk_parent_data emac_1588_parents[] =3D { --=20 2.53.0 From nobody Tue Jun 16 17:02:08 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3D552F9C37; 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a=openpgp; fpr=50B03A1A5CBCD33576EF8CD7920C0DBCAABEFD55 The offset of PCIe Clock CTRL register for port B and C controller was wrongle swapped, correct it here. Fixes: 091d19cc2401 ("clk: spacemit: k3: extract common header") Signed-off-by: Yixun Lan --- include/soc/spacemit/k3-syscon.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/soc/spacemit/k3-syscon.h b/include/soc/spacemit/k3-sys= con.h index 0299bea065a0..a68255dd641f 100644 --- a/include/soc/spacemit/k3-syscon.h +++ b/include/soc/spacemit/k3-syscon.h @@ -168,8 +168,8 @@ #define APMU_CPU_C2_CLK_CTRL 0x394 #define APMU_CPU_C3_CLK_CTRL 0x208 #define APMU_PCIE_CLK_RES_CTRL_A 0x1f0 -#define APMU_PCIE_CLK_RES_CTRL_B 0x1c8 -#define APMU_PCIE_CLK_RES_CTRL_C 0x1d0 +#define APMU_PCIE_CLK_RES_CTRL_B 0x1d0 +#define APMU_PCIE_CLK_RES_CTRL_C 0x1c8 #define APMU_PCIE_CLK_RES_CTRL_D 0x1e0 #define APMU_PCIE_CLK_RES_CTRL_E 0x1e8 #define APMU_EMAC0_CLK_RES_CTRL 0x3e4 --=20 2.53.0