From nobody Fri Jun 12 07:28:12 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DDEA421A12 for ; Wed, 29 Apr 2026 18:45:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777488327; cv=none; b=chMLFkx1jY+6nFbuVPgyxMzJkaoL8sFz5e0nvyD2Pr69NR9Iw8h/rH5k1CMhiqmC+EmdyzCX6qGv5pB4pNspu2KJ8zEQNa1JEfjD4ioUFaLz9BgkFpbR5QxXOVw3Tf2j5pGWd1eublVfzzKjU5hgsYzU0suJt10xhIXuvaGUFUo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777488327; c=relaxed/simple; bh=Y0aKY+A8WnMWRYzlnK79objhgdxMemgKOX80eTq4/K4=; h=Subject:To:Cc:From:Date:References:In-Reply-To:Message-Id; b=uFQhFfELzQRenaa1x4geVW7JbTl0Xq3ncVUmdClvSmrlpKd2DWxPntKNK57Zi0H2YjMivP/+JZ2KkE/vEk70ul6B8lYNbkGfYvLLxERTylQj/EzNDfzplmDKANAQQnR0eB/9SUHkuFU5dHn2AO8IOn9CFdrsPN3CKSlHy1XR5xs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=hTGy6AoM; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="hTGy6AoM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777488324; x=1809024324; h=subject:to:cc:from:date:references:in-reply-to: message-id; bh=Y0aKY+A8WnMWRYzlnK79objhgdxMemgKOX80eTq4/K4=; b=hTGy6AoMeSZ2RXjmFr3mFhKPIu/BKWtrQ428QPhAa1UqBDaXg0qI0QMv uF1NvXxszFHz6co+OS6st3KIxeA8UwB8raFBRq3rDUIqHnKywbVcvrHS+ FPDuv5Y/sGsPZaDnXidHmv/4pWwm19ttgjlTMTwxi4PPI2MLlHIcXJhB3 C+vvWe5W30MEfP/gZdZhhV6Zg1CfV0FjB1GnJVkWMzgOzEs/yBaDYrWcJ GbGUPuHxw6tiGGY35yMXEdqmN07IQXme8gpw1xzMtFDiHre/3PuYnOikB TEuS5zEHKKcCmRatiBGBLTZadLLGaeQgttpljRFyuyV10zO85NmKZOFDN A==; X-CSE-ConnectionGUID: Mv5SHfn6RpCvfjvfu5Lrfg== X-CSE-MsgGUID: Iw7Ort0jT36srUWwqelMgw== X-IronPort-AV: E=McAfee;i="6800,10657,11771"; a="78322256" X-IronPort-AV: E=Sophos;i="6.23,206,1770624000"; d="scan'208";a="78322256" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 11:45:20 -0700 X-CSE-ConnectionGUID: i5jP2DffS9ie4IReWIVQKg== X-CSE-MsgGUID: /GjBj8AxTpCyuAGA9Kn77Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,206,1770624000"; d="scan'208";a="229749570" Received: from davehans-spike.ostc.intel.com (HELO localhost.localdomain) ([10.165.164.11]) by fmviesa006.fm.intel.com with ESMTP; 29 Apr 2026 11:45:20 -0700 Subject: [PATCH v2 1/8] x86/msr: Use paravirt "calls" in common code To: linux-kernel@vger.kernel.org Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , x86@kernel.org, Juergen Gross , virtualization@lists.linux.dev, Dave Hansen From: Dave Hansen Date: Wed, 29 Apr 2026 11:45:19 -0700 References: <20260429184517.7E078510@davehans-spike.ostc.intel.com> In-Reply-To: <20260429184517.7E078510@davehans-spike.ostc.intel.com> Message-Id: <20260429184519.A701C74E@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen Currently, the paravirt and native code define a common set of MSR functions. But, some of the code is duplicated between the two. For instance, the packing and unpacking of the 64-bit MSR value into two 32-bit values is done in both. Prepare to consolidate the two copies. Have common code use the paravirt_{rd,wr}msr*() naming and short-circuit the paravirt infrastructure with the preprocessor to do paravirt=3D>native without any paravirt overhead. Signed-off-by: Dave Hansen Reviewed-by: Juergen Gross --- b/arch/x86/include/asm/msr.h | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff -puN arch/x86/include/asm/msr.h~raw_msr_names arch/x86/include/asm/msr= .h --- a/arch/x86/include/asm/msr.h~raw_msr_names 2026-04-01 14:32:55.57241598= 4 -0700 +++ b/arch/x86/include/asm/msr.h 2026-04-01 14:32:55.575416096 -0700 @@ -173,6 +173,13 @@ static inline u64 native_read_pmc(int co #include #else #include + +/* Short-circuit the paravirt MSR infrastructure when it is disabled: */ +#define paravirt_read_msr native_read_msr +#define paravirt_read_msr_safe native_read_msr_safe +#define paravirt_write_msr native_write_msr +#define paravirt_write_msr_safe native_write_msr_safe + /* * Access to machine-specific registers (available on 586 and better only) * Note: the rd* operations modify the parameters directly (without using @@ -181,35 +188,35 @@ static inline u64 native_read_pmc(int co =20 #define rdmsr(msr, low, high) \ do { \ - u64 __val =3D native_read_msr((msr)); \ + u64 __val =3D paravirt_read_msr((msr)); \ (void)((low) =3D (u32)__val); \ (void)((high) =3D (u32)(__val >> 32)); \ } while (0) =20 static inline void wrmsr(u32 msr, u32 low, u32 high) { - native_write_msr(msr, (u64)high << 32 | low); + paravirt_write_msr(msr, (u64)high << 32 | low); } =20 #define rdmsrq(msr, val) \ - ((val) =3D native_read_msr((msr))) + ((val) =3D paravirt_read_msr((msr))) =20 static inline void wrmsrq(u32 msr, u64 val) { - native_write_msr(msr, val); + paravirt_write_msr(msr, val); } =20 /* wrmsr with exception handling */ static inline int wrmsrq_safe(u32 msr, u64 val) { - return native_write_msr_safe(msr, val); + return paravirt_write_msr_safe(msr, val); } =20 /* rdmsr with exception handling */ #define rdmsr_safe(msr, low, high) \ ({ \ u64 __val; \ - int __err =3D native_read_msr_safe((msr), &__val); \ + int __err =3D paravirt_read_msr_safe((msr), &__val); \ (*low) =3D (u32)__val; \ (*high) =3D (u32)(__val >> 32); \ __err; \ @@ -217,7 +224,7 @@ static inline int wrmsrq_safe(u32 msr, u =20 static inline int rdmsrq_safe(u32 msr, u64 *p) { - return native_read_msr_safe(msr, p); + return paravirt_read_msr_safe(msr, p); } =20 static __always_inline u64 rdpmc(int counter) _ From nobody Fri Jun 12 07:28:12 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8A4B3FE372 for ; Wed, 29 Apr 2026 18:45:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777488328; cv=none; b=qSqdF51wL3fe10FVpRLo39yVRFaQntJvoC8gfalc4ht8l22GsvD/NwxIP37pzQmUSpUEBjIj8IZG1+yRkc3A3GeTUPins/+mi9yeO2yPsiJ3pPthOeFRl0toDKexkOWRdqbV/qmMrQGmYrdFQ7GCeVRJQOvESFfP0Tu97uKcvP8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777488328; c=relaxed/simple; bh=MiD2O5l5b6bczKAjI37QxnoqTeJZdSks8jGHE8IekPU=; h=Subject:To:Cc:From:Date:References:In-Reply-To:Message-Id; b=pjc5EQL0PGss2z6b7Hg/3FkE8NRK3z6VGZjNsLAzszIIVupf81ruWK14DUArtDIihCkd7K5Ut1/oyhxACTD7uh/+In9grb+Ox3uPK27dVtHBo+dtwnQWT11dQVFIEL/YxGZ9aTltO1C35CPzSSlkVF3hNDKulz8n7pk4o2ASkps= ARC-Authentication-Results: i=1; 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charset="utf-8" From: Dave Hansen The paravirt and native code define very similar rdmsr() implementations. Move the non-paravirt one out to common code where both the "native" and "paravirt" implementations can use it. Remove the now duplicate paravirt rdmsr(). Signed-off-by: Dave Hansen Reviewed-by: Juergen Gross --- b/arch/x86/include/asm/msr.h | 17 ++++++++++------- b/arch/x86/include/asm/paravirt.h | 7 ------- 2 files changed, 10 insertions(+), 14 deletions(-) diff -puN arch/x86/include/asm/msr.h~rdmsr-dups-2 arch/x86/include/asm/msr.h --- a/arch/x86/include/asm/msr.h~rdmsr-dups-2 2026-04-01 14:32:56.105435948= -0700 +++ b/arch/x86/include/asm/msr.h 2026-04-01 14:32:56.112436210 -0700 @@ -186,13 +186,6 @@ static inline u64 native_read_pmc(int co * pointer indirection), this allows gcc to optimize better */ =20 -#define rdmsr(msr, low, high) \ -do { \ - u64 __val =3D paravirt_read_msr((msr)); \ - (void)((low) =3D (u32)__val); \ - (void)((high) =3D (u32)(__val >> 32)); \ -} while (0) - static inline void wrmsr(u32 msr, u32 low, u32 high) { paravirt_write_msr(msr, (u64)high << 32 | low); @@ -234,6 +227,16 @@ static __always_inline u64 rdpmc(int cou =20 #endif /* !CONFIG_PARAVIRT_XXL */ =20 +/* + * Common paravirt and native helpers: + */ +#define rdmsr(msr, low, high) \ +do { \ + u64 __val =3D paravirt_read_msr((msr)); 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charset="utf-8" From: Dave Hansen Move the existing "native" rdmsr_safe() implementation out to common code. Consolidate the two rdmsr_safe() implementations down to one by removing the paravirt.h version. Signed-off-by: Dave Hansen Acked-by: Maciej Wieczor-Retman Reviewed-by: Juergen Gross Tested-by: Maciej Wieczor-Retman --- b/arch/x86/include/asm/msr.h | 20 ++++++++++---------- b/arch/x86/include/asm/paravirt.h | 10 ---------- 2 files changed, 10 insertions(+), 20 deletions(-) diff -puN arch/x86/include/asm/msr.h~rdmsr-dups-4 arch/x86/include/asm/msr.h --- a/arch/x86/include/asm/msr.h~rdmsr-dups-4 2026-04-01 14:32:56.670457110= -0700 +++ b/arch/x86/include/asm/msr.h 2026-04-01 14:32:56.676457335 -0700 @@ -205,16 +205,6 @@ static inline int wrmsrq_safe(u32 msr, u return paravirt_write_msr_safe(msr, val); } =20 -/* rdmsr with exception handling */ -#define rdmsr_safe(msr, low, high) \ -({ \ - u64 __val; \ - int __err =3D paravirt_read_msr_safe((msr), &__val); \ - (*low) =3D (u32)__val; \ - (*high) =3D (u32)(__val >> 32); \ - __err; \ -}) - static inline int rdmsrq_safe(u32 msr, u64 *p) { return paravirt_read_msr_safe(msr, p); @@ -237,6 +227,16 @@ do { \ (void)((high) =3D (u32)(__val >> 32)); \ } while (0) =20 +/* rdmsr with exception handling */ +#define rdmsr_safe(msr, low, high) \ +({ \ + u64 __val; \ + int __err =3D paravirt_read_msr_safe((msr), &__val); \ + (*low) =3D (u32)__val; \ + (*high) =3D (u32)(__val >> 32); \ + __err; \ +}) + /* Instruction opcode for WRMSRNS supported in binutils >=3D 2.40 */ #define ASM_WRMSRNS _ASM_BYTES(0x0f,0x01,0xc6) =20 diff -puN arch/x86/include/asm/paravirt.h~rdmsr-dups-4 arch/x86/include/asm= /paravirt.h --- a/arch/x86/include/asm/paravirt.h~rdmsr-dups-4 2026-04-01 14:32:56.6734= 57222 -0700 +++ b/arch/x86/include/asm/paravirt.h 2026-04-01 14:32:56.676457335 -0700 @@ -181,16 +181,6 @@ static inline int wrmsrq_safe(u32 msr, u return paravirt_write_msr_safe(msr, val); } =20 -/* rdmsr with exception handling */ -#define rdmsr_safe(msr, a, b) \ -({ \ - u64 _l; \ - int _err =3D paravirt_read_msr_safe((msr), &_l); \ - (*a) =3D (u32)_l; \ - (*b) =3D (u32)(_l >> 32); \ - _err; \ -}) - static __always_inline int rdmsrq_safe(u32 msr, u64 *p) { return paravirt_read_msr_safe(msr, p); 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charset="utf-8" From: Dave Hansen Consolidate the two rdmsrq() implementations down to one. The paravirt.h implementation was probably better, but just stick with the native one here for consistency. Signed-off-by: Dave Hansen Reviewed-by: Juergen Gross --- b/arch/x86/include/asm/msr.h | 6 +++--- b/arch/x86/include/asm/paravirt.h | 5 ----- 2 files changed, 3 insertions(+), 8 deletions(-) diff -puN arch/x86/include/asm/msr.h~rdmsr-dups-5 arch/x86/include/asm/msr.h --- a/arch/x86/include/asm/msr.h~rdmsr-dups-5 2026-04-01 14:32:57.236478310= -0700 +++ b/arch/x86/include/asm/msr.h 2026-04-01 14:32:57.242478534 -0700 @@ -191,9 +191,6 @@ static inline void wrmsr(u32 msr, u32 lo paravirt_write_msr(msr, (u64)high << 32 | low); } =20 -#define rdmsrq(msr, val) \ - ((val) =3D paravirt_read_msr((msr))) - static inline void wrmsrq(u32 msr, u64 val) { paravirt_write_msr(msr, val); @@ -237,6 +234,9 @@ do { \ __err; \ }) =20 +#define rdmsrq(msr, val) \ + ((val) =3D paravirt_read_msr((msr))) + /* Instruction opcode for WRMSRNS supported in binutils >=3D 2.40 */ #define ASM_WRMSRNS _ASM_BYTES(0x0f,0x01,0xc6) =20 diff -puN arch/x86/include/asm/paravirt.h~rdmsr-dups-5 arch/x86/include/asm= /paravirt.h --- a/arch/x86/include/asm/paravirt.h~rdmsr-dups-5 2026-04-01 14:32:57.2394= 78422 -0700 +++ b/arch/x86/include/asm/paravirt.h 2026-04-01 14:32:57.242478534 -0700 @@ -166,11 +166,6 @@ static __always_inline void wrmsr(u32 ms paravirt_write_msr(msr, (u64)high << 32 | low); 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29 Apr 2026 11:45:26 -0700 Subject: [PATCH v2 5/8] x86/msr: Consolidate {rd,wr}msr[q]_safe() implementations To: linux-kernel@vger.kernel.org Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , x86@kernel.org, Juergen Gross , virtualization@lists.linux.dev, Dave Hansen From: Dave Hansen Date: Wed, 29 Apr 2026 11:45:25 -0700 References: <20260429184517.7E078510@davehans-spike.ostc.intel.com> In-Reply-To: <20260429184517.7E078510@davehans-spike.ostc.intel.com> Message-Id: <20260429184525.F1123DA9@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen These should be very familiar by now. Move the native implementations of the "safe" MSR functions out to common code and zap the paravirt.h version. Do four at once now because these are quite straightforward. Signed-off-by: Dave Hansen Reviewed-by: Juergen Gross --- b/arch/x86/include/asm/msr.h | 42 +++++++++++++++++++--------------= ----- b/arch/x86/include/asm/paravirt.h | 20 ------------------ 2 files changed, 21 insertions(+), 41 deletions(-) diff -puN arch/x86/include/asm/msr.h~rdmsr-dups-6 arch/x86/include/asm/msr.h --- a/arch/x86/include/asm/msr.h~rdmsr-dups-6 2026-04-01 14:32:57.802499509= -0700 +++ b/arch/x86/include/asm/msr.h 2026-04-01 14:32:57.809499772 -0700 @@ -186,27 +186,6 @@ static inline u64 native_read_pmc(int co * pointer indirection), this allows gcc to optimize better */ =20 -static inline void wrmsr(u32 msr, u32 low, u32 high) -{ - paravirt_write_msr(msr, (u64)high << 32 | low); -} - -static inline void wrmsrq(u32 msr, u64 val) -{ - paravirt_write_msr(msr, val); -} - -/* wrmsr with exception handling */ -static inline int wrmsrq_safe(u32 msr, u64 val) -{ - return paravirt_write_msr_safe(msr, val); -} - -static inline int rdmsrq_safe(u32 msr, u64 *p) -{ - return paravirt_read_msr_safe(msr, p); -} - static __always_inline u64 rdpmc(int counter) { return native_read_pmc(counter); @@ -237,6 +216,27 @@ do { \ #define rdmsrq(msr, val) \ ((val) =3D paravirt_read_msr((msr))) =20 +static inline int rdmsrq_safe(u32 msr, u64 *p) +{ + return paravirt_read_msr_safe(msr, p); +} + +/* wrmsr with exception handling */ +static inline int wrmsrq_safe(u32 msr, u64 val) +{ + return paravirt_write_msr_safe(msr, val); +} + +static inline void wrmsr(u32 msr, u32 low, u32 high) +{ + paravirt_write_msr(msr, (u64)high << 32 | low); +} + +static inline void wrmsrq(u32 msr, u64 val) +{ + paravirt_write_msr(msr, val); +} + /* Instruction opcode for WRMSRNS supported in binutils >=3D 2.40 */ #define ASM_WRMSRNS _ASM_BYTES(0x0f,0x01,0xc6) =20 diff -puN arch/x86/include/asm/paravirt.h~rdmsr-dups-6 arch/x86/include/asm= /paravirt.h --- a/arch/x86/include/asm/paravirt.h~rdmsr-dups-6 2026-04-01 14:32:57.8064= 99659 -0700 +++ b/arch/x86/include/asm/paravirt.h 2026-04-01 14:32:57.809499772 -0700 @@ -161,26 +161,6 @@ static inline int paravirt_write_msr_saf return PVOP_CALL2(int, pv_ops, cpu.write_msr_safe, msr, val); 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charset="utf-8" From: Dave Hansen Doing this is debatable. It does not actually remove any code. But, this makes rdpmc() follow the same pattern as all of the MSR functions where paravirt.h defines a paravirt_foo() function and then msr.h uses that function in common code. Signed-off-by: Dave Hansen Reviewed-by: Juergen Gross --- b/arch/x86/include/asm/msr.h | 11 ++++++----- b/arch/x86/include/asm/paravirt.h | 2 +- 2 files changed, 7 insertions(+), 6 deletions(-) diff -puN arch/x86/include/asm/msr.h~rdmsr-dups-9 arch/x86/include/asm/msr.h --- a/arch/x86/include/asm/msr.h~rdmsr-dups-9 2026-04-01 14:32:58.366520634= -0700 +++ b/arch/x86/include/asm/msr.h 2026-04-01 14:32:58.373520897 -0700 @@ -179,6 +179,7 @@ static inline u64 native_read_pmc(int co #define paravirt_read_msr_safe native_read_msr_safe #define paravirt_write_msr native_write_msr #define paravirt_write_msr_safe native_write_msr_safe +#define paravirt_read_pmc native_read_pmc =20 /* * Access to machine-specific registers (available on 586 and better only) @@ -186,11 +187,6 @@ static inline u64 native_read_pmc(int co * pointer indirection), this allows gcc to optimize better */ =20 -static __always_inline u64 rdpmc(int counter) -{ - return native_read_pmc(counter); -} - #endif /* !CONFIG_PARAVIRT_XXL */ =20 /* @@ -237,6 +233,11 @@ static inline void wrmsrq(u32 msr, u64 v paravirt_write_msr(msr, val); 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charset="utf-8" From: Dave Hansen I'm not sure any of this makes sense any more. The kernel only runs on "586 and better". The comment about gcc optimization is hopefully decades out of date too. Really, the only reason to keep the wonky semantics where the parameters get modified is to avoid all the churn to make them sane. Not gcc. gcc was probably a bad reason, even back in the day because MSRs are mostly very slow and have always been very slow. A few extra bytes of register shuffling was probably never measurable. Signed-off-by: Dave Hansen Reviewed-by: Juergen Gross --- b/arch/x86/include/asm/msr.h | 6 ------ 1 file changed, 6 deletions(-) diff -puN arch/x86/include/asm/msr.h~rdmsr-dups-10 arch/x86/include/asm/msr= .h --- a/arch/x86/include/asm/msr.h~rdmsr-dups-10 2026-04-01 14:32:58.97154329= 5 -0700 +++ b/arch/x86/include/asm/msr.h 2026-04-01 14:32:58.974543407 -0700 @@ -181,12 +181,6 @@ static inline u64 native_read_pmc(int co #define paravirt_write_msr_safe native_write_msr_safe #define paravirt_read_pmc native_read_pmc =20 -/* - * Access to machine-specific registers (available on 586 and better only) - * Note: the rd* operations modify the parameters directly (without using - * pointer indirection), this allows gcc to optimize better - */ - #endif /* !CONFIG_PARAVIRT_XXL */ =20 /* _ From nobody Fri Jun 12 07:28:12 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF4042F617C for ; Wed, 29 Apr 2026 18:45:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777488334; cv=none; b=YvKAK49jIXhgSENHsc8vLD5TODMfF2ehEveB3RFXBuHwe0Nw1/a/iK4ijo2YTlY1ISV+8cZAjvSjr729ZZmpKYnLJ1mn87TZttmhwBlzbrMdpU113yjO2UeHPIyaVOvCWZDD7rGlJqh5cOJ1uptPDxYzGPc83zrVsCqSeAJETEw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777488334; c=relaxed/simple; bh=dhcNJDDi3zQS9Nk/E4umfgiUZ3RFntrTQSozkeTfCIs=; h=Subject:To:Cc:From:Date:References:In-Reply-To:Message-Id; b=lJGdFQDu5e7mz8fC8mmQw21b9QUgst5/ZxEamL442fxoikQB7IBz4AHNQ3riLLWcZ+EwN01g65+7PCvapKbajh3DTKoY9KtvWnERQ8Qo7LTF4XmViA9zB0qeO/EfOXPEHeVC86dgyIlc7Sv3qRKovdiH831miFDxnkN93JSaQHE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=HuxxFfrE; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="HuxxFfrE" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777488331; x=1809024331; h=subject:to:cc:from:date:references:in-reply-to: message-id; bh=dhcNJDDi3zQS9Nk/E4umfgiUZ3RFntrTQSozkeTfCIs=; b=HuxxFfrEikC8BLKaTjeMOc6wfz1Sj3ow2gQ2RRoTGUhmLaW1xsrYo28U /m2xV8CXkOH3CnA5N5G1mLKEsFr3+trOzy2s1Ys7tDd+0APXarJihIpkD x5HPXu4Sf89lYHQVt+/CYaukzezTktjyph8PTjDg+S5HuZJvBmWh2k2wS 3UQseFb9bJjtTpsfWR845eKiZOhWPoobcQcXIF5wekrBm/tXlTlyDjXO7 UuJDO0TfWL0cvlUEE2pMl4PAoAHKfJQisozU040Q2AM7KnfeL5uDiKw0P 7r0O7yk3kJp8UmNcOE9SCk682HDRnJQbC9p3JGhbePPAvbeGH8o0Pfqad A==; X-CSE-ConnectionGUID: w5UxwpVFSyOSXWnljeqN/A== X-CSE-MsgGUID: myVzqDJ4QVSo3JoayN96tQ== X-IronPort-AV: E=McAfee;i="6800,10657,11771"; a="78322306" X-IronPort-AV: E=Sophos;i="6.23,206,1770624000"; d="scan'208";a="78322306" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 11:45:31 -0700 X-CSE-ConnectionGUID: jDYROiRVRFS1dReNxcCN5w== X-CSE-MsgGUID: +liPkOrQRZe+A4sdhMUsfQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,206,1770624000"; d="scan'208";a="229749686" Received: from davehans-spike.ostc.intel.com (HELO localhost.localdomain) ([10.165.164.11]) by fmviesa006.fm.intel.com with ESMTP; 29 Apr 2026 11:45:31 -0700 Subject: [PATCH v2 8/8] x86/msr: Remove duplicate #include To: linux-kernel@vger.kernel.org Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , x86@kernel.org, Juergen Gross , virtualization@lists.linux.dev, Dave Hansen From: Dave Hansen Date: Wed, 29 Apr 2026 11:45:30 -0700 References: <20260429184517.7E078510@davehans-spike.ostc.intel.com> In-Reply-To: <20260429184517.7E078510@davehans-spike.ostc.intel.com> Message-Id: <20260429184530.9FE585E8@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen errno.h is already included for C code at the top of the header. Zap the duplicate. Signed-off-by: Dave Hansen Reviewed-by: Juergen Gross --- b/arch/x86/include/asm/msr.h | 1 - 1 file changed, 1 deletion(-) diff -puN arch/x86/include/asm/msr.h~rdmsr-dups-11 arch/x86/include/asm/msr= .h --- a/arch/x86/include/asm/msr.h~rdmsr-dups-11 2026-04-29 11:38:57.83873240= 5 -0700 +++ b/arch/x86/include/asm/msr.h 2026-04-29 11:38:57.841732519 -0700 @@ -172,7 +172,6 @@ static inline u64 native_read_pmc(int co #ifdef CONFIG_PARAVIRT_XXL #include #else -#include =20 /* Short-circuit the paravirt MSR infrastructure when it is disabled: */ #define paravirt_read_msr native_read_msr _