From nobody Tue Jun 16 19:33:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9886C3CE495; Wed, 29 Apr 2026 18:06:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777486020; cv=none; b=RDryy15t1fta6vq0+fs6JIL+h1DMDKHdkWUjQDnyDq5v1iMNgyCUU9Uec9dmwntzBf6IcoPQndFASpeUFdHzyMYjX/cHihrrBLqoS7t8hDWeKBTvIrmkm98laOrZ+MLrurc6bpx1O/UC8sOgW0AK/Oz/LqCzNr28eWuT/Dudeuk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777486020; c=relaxed/simple; bh=R3M1Wd/Iys/ZSh84oAQZ8j5ob1LKTDhbBg/wAEZStYU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HPHNo3ad8wFB4wgzQdN1KZ/5j1cI05XqA0GF9sLgpPKQs/1tabnem2Iou/V51fum7WF/Fu0JlTXEsd+vCao2Tior8cZ3zXTdxpRw87SPdJeOosqR37vai3MmbQ4fuP7hws9scCj0NLGHpPj+ujS+MTEo83C3n7KxUmgNlsIqK98= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=FcEfI34o; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="FcEfI34o" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777486017; x=1809022017; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=R3M1Wd/Iys/ZSh84oAQZ8j5ob1LKTDhbBg/wAEZStYU=; b=FcEfI34oAewrquGu/atRxUKOTyxfPOY1evkliLbtErSH1nRLIN0y6u6V vBQkoTtt26TFRV51MXYI+M/IDjueodIjwrjF4I2yjkE1BMOjOkHq862Y8 aJrlB1DVX8gtvlaHJvE6GPdes3ZWTX2LFVnDjMDIT9+evGSsjiuILfuH6 owTUk+Imp9BJn73iOytzEYLCpx3GUFVnIESt46Ma08YpROkDW6IKk5lpG T/9VDlfbNPB9XU0OKrvKiPPI8T8R3yTcWOaPipNBHfRmkP+C9f6kEkoaF ja+NMiZ8eM0ggIzFrTqXKme1Vyyx6T4oLRwOS3fFwO9T/GeRnStomNe03 g==; X-CSE-ConnectionGUID: U+CjtDMNTsuQ7UXH47hLVQ== X-CSE-MsgGUID: 3p4y/EbGQRuWuYmD/WglcA== X-IronPort-AV: E=McAfee;i="6800,10657,11771"; a="78532274" X-IronPort-AV: E=Sophos;i="6.23,206,1770624000"; d="scan'208";a="78532274" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 11:06:55 -0700 X-CSE-ConnectionGUID: mR8rcttgQ56FZ9VCwOI0gw== X-CSE-MsgGUID: ng0XwoOFRSCNLdXC0cwaMw== X-ExtLoop1: 1 Received: from iherna2-mobl4.amr.corp.intel.com (HELO tfalcon-desk.intel.com) ([10.124.221.251]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 11:06:53 -0700 From: Thomas Falcon To: Bjorn Helgaas , "Rafael J . Wysocki" Cc: "David E . Box" , Lukas Wunner , Manivannan Sadhasivam , Len Brown , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Falcon Subject: [RFC PATCH 1/4] pcie/aspm: Add debug logging for aspm policy config Date: Wed, 29 Apr 2026 13:06:43 -0500 Message-ID: <20260429180647.197072-2-thomas.falcon@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260429180647.197072-1-thomas.falcon@intel.com> References: <20260429180647.197072-1-thomas.falcon@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Include additional logging for ASPM and Clock PM state changes keeping track of code flow and enabled power saving states. Example output after enabling powersupersave policy: [ 130.179249] pcieport 0000:80:1b.0: Updating ASPM state [ 130.179256] igc 0000:81:00.0: ASPM: Disabling ASPM on this device before= disabling parent [ 130.179368] pcieport 0000:80:1b.0: ASPM: Disabling ASPM before applying = configuration [ 130.179373] pcieport 0000:80:1b.0: ASPM: Configure L1 substates [ 130.179391] pcieport 0000:80:1b.0: ASPM: Configure ASPM state on upstrea= m device [ 130.179395] igc 0000:81:00.0: ASPM: Configure ASPM state on downstream d= evice [ 130.179401] pcieport 0000:80:1b.0: ASPM: enabled states: L1 ASPM-L1.1 PC= I-PM-L1.1 PCI-PM-L1.2 [ 130.179416] pcieport 0000:00:06.0: Updating ASPM state [ 130.179418] nvme 0000:01:00.0: ASPM: Disabling ASPM on this device befor= e disabling parent [ 130.179422] pcieport 0000:00:06.0: ASPM: Disabling ASPM before applying = configuration [ 130.179425] pcieport 0000:00:06.0: ASPM: Configure L1 substates [ 130.179435] pcieport 0000:00:06.0: ASPM: Configure ASPM state on upstrea= m device [ 130.179438] nvme 0000:01:00.0: ASPM: Configure ASPM state on downstream = device [ 130.179442] pcieport 0000:00:06.0: ASPM: enabled states: L1 ASPM-L1.1 AS= PM-L1.2 PCI-PM-L1.1 PCI-PM-L1.2 Suggested-by: David E. Box Signed-off-by: Thomas Falcon --- drivers/pci/pcie/aspm.c | 34 ++++++++++++++++++++++++++++++---- 1 file changed, 30 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 925373b98dff..cd23c1462502 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -372,6 +372,9 @@ static void pcie_set_clkpm(struct pcie_link_state *link= , int enable) /* Need nothing if the specified equals to current state */ if (link->clkpm_enabled =3D=3D enable) return; + + pci_dbg(link->pdev, "%s Clock PM\n", + enable ? "Enabling" : "Disabling"); pcie_set_clkpm_nocheck(link, enable); } =20 @@ -961,11 +964,14 @@ static void pcie_config_aspm_link(struct pcie_link_st= ate *link, u32 state) state &=3D (link->aspm_capable & ~link->aspm_disable); =20 /* Can't enable any substates if L1 is not enabled */ - if (!(state & PCIE_LINK_STATE_L1)) + if (!(state & PCIE_LINK_STATE_L1)) { + pci_dbg(parent, "ASPM: L1 not enabled, disabling L1 substates\n"); state &=3D ~PCIE_LINK_STATE_L1SS; + } =20 /* Spec says both ports must be in D0 before enabling PCI PM substates*/ if (parent->current_state !=3D PCI_D0 || child->current_state !=3D PCI_D0= ) { + pci_dbg(parent, "ASPM: Both ports are not in D0, disable PCI PM L1 subst= ates unless explicitly enabled\n"); state &=3D ~PCIE_LINK_STATE_L1_SS_PCIPM; state |=3D (link->aspm_enabled & PCIE_LINK_STATE_L1_SS_PCIPM); } @@ -973,6 +979,8 @@ static void pcie_config_aspm_link(struct pcie_link_stat= e *link, u32 state) /* Nothing to do if the link is already in the requested state */ if (link->aspm_enabled =3D=3D state) return; + pci_dbg(parent, "Updating ASPM state\n"); + /* Convert ASPM state to upstream/downstream ASPM register state */ if (state & PCIE_LINK_STATE_L0S_UP) dwstream |=3D PCI_EXP_LNKCTL_ASPM_L0S; @@ -997,16 +1005,34 @@ static void pcie_config_aspm_link(struct pcie_link_s= tate *link, u32 state) * Sec 7.5.3.7 also recommends programming the same ASPM Control * value for all functions of a multi-function device. */ - list_for_each_entry(child, &linkbus->devices, bus_list) + list_for_each_entry(child, &linkbus->devices, bus_list) { + pci_dbg(child, "ASPM: Disabling ASPM on this device before disabling par= ent\n"); pcie_config_aspm_dev(child, 0); + } + pci_dbg(parent, "ASPM: Disabling ASPM before applying configuration\n"); pcie_config_aspm_dev(parent, 0); =20 - if (link->aspm_capable & PCIE_LINK_STATE_L1SS) + if (link->aspm_capable & PCIE_LINK_STATE_L1SS) { + pci_dbg(parent, "ASPM: Configure L1 substates\n"); pcie_config_aspm_l1ss(link, state); + } =20 + pci_dbg(parent, "ASPM: Configure ASPM state on upstream device\n"); pcie_config_aspm_dev(parent, upstream); - list_for_each_entry(child, &linkbus->devices, bus_list) + list_for_each_entry(child, &linkbus->devices, bus_list) { + pci_dbg(child, "ASPM: Configure ASPM state on downstream device\n"); pcie_config_aspm_dev(child, dwstream); + } + + pci_dbg(parent, "ASPM: enabled states:%s%s%s%s%s%s%s%s\n", + FLAG(state, L0S_UP, " L0s-Upstream"), + FLAG(state, L0S_DW, " L0s-Downstream"), + FLAG(state, L1, " L1"), + FLAG(state, L1_1, " ASPM-L1.1"), + FLAG(state, L1_2, " ASPM-L1.2"), + FLAG(state, L1_1_PCIPM, " PCI-PM-L1.1"), + FLAG(state, L1_2_PCIPM, " PCI-PM-L1.2"), + FLAG(state, CLKPM, " ClockPM")); =20 link->aspm_enabled =3D state; =20 --=20 2.43.0 From nobody Tue Jun 16 19:33:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EAE1841B342; Wed, 29 Apr 2026 18:07:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a="78532279" X-IronPort-AV: E=Sophos;i="6.23,206,1770624000"; d="scan'208";a="78532279" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 11:06:55 -0700 X-CSE-ConnectionGUID: 0l/u9bIgQEKXPMYLrAqsww== X-CSE-MsgGUID: UasF+sk9QB2H/NXH9bhDcw== X-ExtLoop1: 1 Received: from iherna2-mobl4.amr.corp.intel.com (HELO tfalcon-desk.intel.com) ([10.124.221.251]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 11:06:54 -0700 From: Thomas Falcon To: Bjorn Helgaas , "Rafael J . Wysocki" Cc: "David E . Box" , Lukas Wunner , Manivannan Sadhasivam , Len Brown , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Falcon Subject: [RFC PATCH 2/4] pcie/aspm: Enable all power-saving states during link state initialization Date: Wed, 29 Apr 2026 13:06:44 -0500 Message-ID: <20260429180647.197072-3-thomas.falcon@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260429180647.197072-1-thomas.falcon@intel.com> References: <20260429180647.197072-1-thomas.falcon@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Setting powersave and powersupersave states at ASPM link state initialization allows for a simpler and more maintainable enabling flow that presumes all advertised power states work. Restrict this behavior to systems with a BIOS release during or after 2025. Suggested-by: David E. Box Signed-off-by: Thomas Falcon --- drivers/pci/pcie/aspm.c | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index cd23c1462502..84d49aa8a5ba 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -24,6 +24,7 @@ #include #include #include +#include =20 #include "../pci.h" =20 @@ -1057,6 +1058,23 @@ static void free_link_state(struct pcie_link_state *= link) kfree(link); } =20 +static int pcie_aspm_legacy_config_check(void) +{ + static bool legacy_aspm_config; + static bool checked; + + if (checked) + return legacy_aspm_config; + if (dmi_get_bios_year() < 2025) + legacy_aspm_config =3D true; + + pr_info("ASPM configuration is determined at %s time\n", + legacy_aspm_config ? "build" : "boot"); + checked =3D true; + + return legacy_aspm_config; +} + static int pcie_aspm_sanity_check(struct pci_dev *pdev) { struct pci_dev *child; @@ -1196,8 +1214,9 @@ void pcie_aspm_init_link_state(struct pci_dev *pdev) * the BIOS's expectation, we'll do so once pci_enable_device() is * called. */ - if (aspm_policy !=3D POLICY_POWERSAVE && - aspm_policy !=3D POLICY_POWER_SUPERSAVE) { + if (!pcie_aspm_legacy_config_check() || + (aspm_policy !=3D POLICY_POWERSAVE && + aspm_policy !=3D POLICY_POWER_SUPERSAVE)) { pcie_config_aspm_path(link); pcie_set_clkpm(link, policy_to_clkpm_state(link)); } @@ -1379,8 +1398,9 @@ void pcie_aspm_powersave_config_link(struct pci_dev *= pdev) if (aspm_disabled || !link) return; =20 - if (aspm_policy !=3D POLICY_POWERSAVE && - aspm_policy !=3D POLICY_POWER_SUPERSAVE) + if (!pcie_aspm_legacy_config_check() || + (aspm_policy !=3D POLICY_POWERSAVE && + aspm_policy !=3D POLICY_POWER_SUPERSAVE)) return; =20 down_read(&pci_bus_sem); --=20 2.43.0 From nobody Tue Jun 16 19:33:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51047402BAC; Wed, 29 Apr 2026 18:07:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777486026; cv=none; b=UOgDHpA61BaYzbRvzCzuljToPx+y67IQnB6/8cxrOjcbAHNCLr4MXl8lD73nL2M9oVgNy4DgJbbVofBT4Jk+tn0WpSkMBx4w1XI/fu4aO+GOPPbgPi0+gdFSiBWV8yCzzdtCzz3XH2PSs+/bVXM+4CYLMhV4yvfPVMHc+eNGMhg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777486026; c=relaxed/simple; bh=I7KLo2BSP/NmxfPhvBY24w3mWqQHMkCVhmxUuigSc34=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FDkWv77cEmH8/1f8MOlWEbh5WJOwZmQanQbHRyR6XLO6/XZ2Y3n/9Zf/KgOezm1NGCMrLGSqmt21eJCFHCbOVS7wtBEMUzKUolK6ZbWedVMqtOCOwJvA2k4feNMaiVbxO9PuRLEVkLopp4R8BE058uAAHwnDzMS/fFP4aNFdk9A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=RxAfiXc2; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="RxAfiXc2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777486024; x=1809022024; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=I7KLo2BSP/NmxfPhvBY24w3mWqQHMkCVhmxUuigSc34=; b=RxAfiXc252OLzkihqnB16CvAfGV8WBYEEtgYjwgeHHg9kzdne+AsP6Ur T6GhR9FcrpN2za/bWoan2Gpncc8/Tc+MSLndm2fk7x9phcAsU3s5PF36j zBlPZFl3nlLxwxRfGTb2BSO9su6JN0EQuIrBqxji/rO27QyRDrNDjwdCY t3t1CP1oRtPssAftoxlTVMAEphQu0aM8R5nZkeb3TMZs8sAJzIBOmCMdd xrQDPfwRJj3mThBDoTDbudj7N2CO5B55N+BDDBuVMftwLp6m1L9kowqCI lqHO+ZUtvswbtTs/EQl56IV8V1MGt+4O/N01UQF4Ksfg+ZlkmZhDT3O95 Q==; X-CSE-ConnectionGUID: FFJ2sVoZRFqCfE4ByOWCZQ== X-CSE-MsgGUID: O1wDWRM0S36dqo3LedTH1w== X-IronPort-AV: E=McAfee;i="6800,10657,11771"; a="78532284" X-IronPort-AV: E=Sophos;i="6.23,206,1770624000"; d="scan'208";a="78532284" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 11:06:56 -0700 X-CSE-ConnectionGUID: BTx9jMfHRpe7XRmhbK+aXA== X-CSE-MsgGUID: HmB0qf4xQmCz2anyQdoshA== X-ExtLoop1: 1 Received: from iherna2-mobl4.amr.corp.intel.com (HELO tfalcon-desk.intel.com) ([10.124.221.251]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 11:06:55 -0700 From: Thomas Falcon To: Bjorn Helgaas , "Rafael J . Wysocki" Cc: "David E . Box" , Lukas Wunner , Manivannan Sadhasivam , Len Brown , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Falcon Subject: [RFC PATCH 3/4] pcie/aspm: Enable all hardware power-saving states by default Date: Wed, 29 Apr 2026 13:06:45 -0500 Message-ID: <20260429180647.197072-4-thomas.falcon@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260429180647.197072-1-thomas.falcon@intel.com> References: <20260429180647.197072-1-thomas.falcon@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For systems with a BIOS release date starting in 2025, default ASPM policy to powersupersave if supported in the ACPI FADT. Provide a flag, aspm_user_policy, tracking whether a user has requested a specific power state to give those precedence. Do not enable all states if user has chosen a specific policy or disabled ASPM using the pcie_aspm module parameter. Suggested-by: David E. Box Signed-off-by: Thomas Falcon --- drivers/pci/pci-acpi.c | 4 +++- drivers/pci/pcie/aspm.c | 17 +++++++++++++++++ include/linux/pci.h | 1 + 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 4d0f2cb6c695..d849bc6d0c0c 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -1523,7 +1523,9 @@ static int __init acpi_pci_init(void) if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) { pr_info("ACPI FADT declares the system doesn't support PCIe ASPM, so dis= able it\n"); pcie_no_aspm(); - } + } else + /* If ASPM is supported, configure the default policy here. */ + pcie_aspm_policy_config_init(); =20 if (acpi_pci_disabled) return 0; diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 84d49aa8a5ba..1c81e2f2e589 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -267,6 +267,8 @@ static int aspm_policy =3D POLICY_POWER_SUPERSAVE; #else static int aspm_policy; #endif +static int aspm_default_policy =3D POLICY_POWER_SUPERSAVE; +static bool aspm_user_policy; =20 static const char *policy_str[] =3D { [POLICY_DEFAULT] =3D "default", @@ -1609,6 +1611,7 @@ static int pcie_aspm_set_policy(const char *val, down_read(&pci_bus_sem); mutex_lock(&aspm_lock); aspm_policy =3D i; + aspm_user_policy =3D true; list_for_each_entry(link, &link_list, sibling) { pcie_config_aspm_link(link, policy_to_aspm_state(link)); pcie_set_clkpm(link, policy_to_clkpm_state(link)); @@ -1810,6 +1813,20 @@ static int __init pcie_aspm_disable(char *str) =20 __setup("pcie_aspm=3D", pcie_aspm_disable); =20 + + +void __init pcie_aspm_policy_config_init(void) +{ + /* + * Set ASPM policy here, enabling all power-saving states + * unless ASPM has been disabled or the user has already + * requested a policy or the systems BIOS release date + * is before the year 2025. Otherwise use BIOS defaults. + */ + if (!aspm_disabled && !aspm_user_policy && dmi_get_bios_year() >=3D 2025) + aspm_policy =3D aspm_default_policy; +} + void pcie_no_aspm(void) { /* diff --git a/include/linux/pci.h b/include/linux/pci.h index 2c4454583c11..36fa5579709c 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1915,6 +1915,7 @@ int pci_disable_link_state_locked(struct pci_dev *pde= v, int state); int pci_enable_link_state(struct pci_dev *pdev, int state); int pci_enable_link_state_locked(struct pci_dev *pdev, int state); void pcie_no_aspm(void); +void pcie_aspm_policy_config_init(void); bool pcie_aspm_support_enabled(void); bool pcie_aspm_enabled(struct pci_dev *pdev); #else --=20 2.43.0 From nobody Tue Jun 16 19:33:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7671941B36A; Wed, 29 Apr 2026 18:07:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777486027; cv=none; b=SznxlTywf/6R/FU5qXtoJ+m9mUJEkfTs9r3Y29FrZqa+h+DQuNb9Hdxs9huBbFSfKhAL3YR3QzLK/7Ft+kG0FXHDbqTIJ2dZfmm31emPB43HDDwat+AK73UZsegD3K0LrVsu/pdgFr68pXweoWAg2bOahwZPgV4xXQHXmAlgeYY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777486027; c=relaxed/simple; bh=8uRRJsQyi1OO48XlDkSkvbTHBNR4NC4KE68xK6PgRao=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DqEVdqUrK0h7Qu7r3bGO88uNHAMgn5JeUbAe0N3RWyH4HFXiLub9lVmgUAzCOKKwXu5WdE/WN8fX/sH6k06yj5DXJrc94I7alFRqXCT4mz/gvakDqOI1n/2fhoFabEXambJXKMdfGmCiGdNJLzadMAIRfgxdgowoBmFI378FOi8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=AYRLeY3w; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="AYRLeY3w" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777486025; x=1809022025; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8uRRJsQyi1OO48XlDkSkvbTHBNR4NC4KE68xK6PgRao=; b=AYRLeY3whfx7R55LuOnLjHfXoct5iRHjTY0VX1QFsuZBdp5L67Ux5jJ0 1ufxnaYqrQ1BXqXrjMR2E7loRIfQ4g+8pbAuwZckpDFufTBcI+QF8t1G1 v+MXuqrkyl248KL9/F9wmvhOv2ejxAM1ORpM0kxocfa7vet6SGwA+8e+K 5G37M+4EwSmLcsCFq/Yu/NP+eMXiSnX+s6O2t2rHlsvPlQtUgiejlBeGh MZfv0FCetzaRpb6LfzfL5kWl4esHGQakffLk2A0gEEl2EPkPPcr88AZr2 MKLYYepYC7j3uoynkpvL3DB7A6kxtG6/H5g7BDmyMoJ1A3hNO3F4OG3ZM A==; X-CSE-ConnectionGUID: VpHu2iC6S/6IbQObwOkcCQ== X-CSE-MsgGUID: GSvkjBIrSt6EwaWGlfG+6g== X-IronPort-AV: E=McAfee;i="6800,10657,11771"; a="78532289" X-IronPort-AV: E=Sophos;i="6.23,206,1770624000"; d="scan'208";a="78532289" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 11:06:57 -0700 X-CSE-ConnectionGUID: p1i6a/13QHCI0NYooubA0g== X-CSE-MsgGUID: SjOFropJT16lb8FhHn2hzg== X-ExtLoop1: 1 Received: from iherna2-mobl4.amr.corp.intel.com (HELO tfalcon-desk.intel.com) ([10.124.221.251]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 11:06:55 -0700 From: Thomas Falcon To: Bjorn Helgaas , "Rafael J . Wysocki" Cc: "David E . Box" , Lukas Wunner , Manivannan Sadhasivam , Len Brown , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Falcon Subject: [RFC PATCH 4/4] pcie/aspm: Remove CONFIG_PCIEASPM_* policy definitions Date: Wed, 29 Apr 2026 13:06:46 -0500 Message-ID: <20260429180647.197072-5-thomas.falcon@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260429180647.197072-1-thomas.falcon@intel.com> References: <20260429180647.197072-1-thomas.falcon@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" ASPM policy now defaults to POLICY_POWER_SUPERSAVE for new systems and POLICY_DEFAULT for others while allowing the user to change policy using the existing pcie_aspm module parameter. Safely remove CONFIG_PCIEASPM_* policy settings. Suggested-by: David E. Box Signed-off-by: Thomas Falcon --- Documentation/arch/x86/amd-debugging.rst | 5 ++-- arch/mips/configs/bmips_stb_defconfig | 1 - arch/mips/configs/loongson2k_defconfig | 1 - drivers/pci/pcie/Kconfig | 33 ------------------------ drivers/pci/pcie/aspm.c | 8 ------ 5 files changed, 2 insertions(+), 46 deletions(-) diff --git a/Documentation/arch/x86/amd-debugging.rst b/Documentation/arch/= x86/amd-debugging.rst index d92bf59d62c7..3f346a46357a 100644 --- a/Documentation/arch/x86/amd-debugging.rst +++ b/Documentation/arch/x86/amd-debugging.rst @@ -260,9 +260,8 @@ of the devices. ASPM ---- For the best runtime power consumption, ASPM should be programmed as inten= ded -by the BIOS from the hardware vendor. To accomplish this the Linux kernel -should be compiled with ``CONFIG_PCIEASPM_DEFAULT`` set to ``y`` and the -sysfs file ``/sys/module/pcie_aspm/parameters/policy`` should not be modif= ied. +by the BIOS from the hardware vendor. To accomplish this the sysfs file +``/sys/module/pcie_aspm/parameters/policy`` should not be modified. =20 Most notably, if L1.2 is not configured properly for any devices, the SoC will not be able to enter the deepest idle state. diff --git a/arch/mips/configs/bmips_stb_defconfig b/arch/mips/configs/bmip= s_stb_defconfig index ecfa7f777efa..bb19073986a8 100644 --- a/arch/mips/configs/bmips_stb_defconfig +++ b/arch/mips/configs/bmips_stb_defconfig @@ -22,7 +22,6 @@ CONFIG_RD_XZ=3Dy # CONFIG_RD_LZ4 is not set CONFIG_PCI=3Dy CONFIG_PCI_MSI=3Dy -CONFIG_PCIEASPM_POWERSAVE=3Dy CONFIG_PCIEPORTBUS=3Dy CONFIG_PCIE_BRCMSTB=3Dy CONFIG_CPU_FREQ=3Dy diff --git a/arch/mips/configs/loongson2k_defconfig b/arch/mips/configs/loo= ngson2k_defconfig index ca534a6b66de..0a2c123eee69 100644 --- a/arch/mips/configs/loongson2k_defconfig +++ b/arch/mips/configs/loongson2k_defconfig @@ -88,7 +88,6 @@ CONFIG_RFKILL=3Dm CONFIG_RFKILL_INPUT=3Dy CONFIG_PCIEPORTBUS=3Dy CONFIG_HOTPLUG_PCI_PCIE=3Dy -CONFIG_PCIEASPM_PERFORMANCE=3Dy CONFIG_HOTPLUG_PCI=3Dy CONFIG_DEVTMPFS=3Dy CONFIG_DEVTMPFS_MOUNT=3Dy diff --git a/drivers/pci/pcie/Kconfig b/drivers/pci/pcie/Kconfig index 207c2deae35f..069058870506 100644 --- a/drivers/pci/pcie/Kconfig +++ b/drivers/pci/pcie/Kconfig @@ -81,39 +81,6 @@ config PCIEASPM =20 When in doubt, say Y. =20 -choice - prompt "Default ASPM policy" - default PCIEASPM_DEFAULT - depends on PCIEASPM - -config PCIEASPM_DEFAULT - bool "BIOS default" - depends on PCIEASPM - help - Use the BIOS defaults for PCI Express ASPM. - -config PCIEASPM_POWERSAVE - bool "Powersave" - depends on PCIEASPM - help - Enable PCI Express ASPM L0s and L1 where possible, even if the - BIOS did not. - -config PCIEASPM_POWER_SUPERSAVE - bool "Power Supersave" - depends on PCIEASPM - help - Same as PCIEASPM_POWERSAVE, except it also enables L1 substates where - possible. This would result in higher power savings while staying in L1 - where the components support it. - -config PCIEASPM_PERFORMANCE - bool "Performance" - depends on PCIEASPM - help - Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them. -endchoice - config PCIE_PME def_bool y depends on PCIEPORTBUS && PM diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 1c81e2f2e589..112904a75a4c 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -258,15 +258,7 @@ static LIST_HEAD(link_list); #define POLICY_POWERSAVE 2 /* high power saving */ #define POLICY_POWER_SUPERSAVE 3 /* possibly even more power saving */ =20 -#ifdef CONFIG_PCIEASPM_PERFORMANCE -static int aspm_policy =3D POLICY_PERFORMANCE; -#elif defined CONFIG_PCIEASPM_POWERSAVE -static int aspm_policy =3D POLICY_POWERSAVE; -#elif defined CONFIG_PCIEASPM_POWER_SUPERSAVE -static int aspm_policy =3D POLICY_POWER_SUPERSAVE; -#else static int aspm_policy; -#endif static int aspm_default_policy =3D POLICY_POWER_SUPERSAVE; static bool aspm_user_policy; =20 --=20 2.43.0