From nobody Tue Jun 16 19:38:32 2026 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 367B940756D for ; Wed, 29 Apr 2026 17:00:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777482023; cv=none; b=nWnMlAJhK1K9Mo2hSVNjv8jVlNJMlEmTxXY+HFpd6NU0eRCiVxucmtZSwWUDQ/ULGqznf91vOQDBJeIkZTTxQYqMNjQoE8HZ4FqZiXsY62lJiv1/3jIsCTpjia0YfEfhWPb1lJfiBRxE5XD4atO30iWUYWcm4JwIc563o75k+BQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777482023; c=relaxed/simple; bh=bLNTtKp/CVda7Cb/aKSAn7N01NwscsKfgXsH38fKinM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BPPkawgA4aGNuVfhkZRmAuTjK/ibYkKmd7XssRbCiB4vVIjWENA+RaPrM7g/m5Q17yy5mYpUqy9ficgBZhr4BS9sh49R2wU8a9Gdzgqnl46yxcePfOrJ72Wt90Bu45mrLQnq8/Z01S1DaMqrD95Y/qs9YZYkbsJjNeNV0YK8E1A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=iDAcqbeU; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="iDAcqbeU" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-483487335c2so127093265e9.2 for ; Wed, 29 Apr 2026 10:00:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1777482021; x=1778086821; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ikSPOGR4XXwx0JwMlnraIx1B5HOIyelZFy6MXUSY+IY=; b=iDAcqbeUiZp+yqy63C3pV7kcXiTBNCxawfja7sk/TkZXr9AVhFF5oNqZLJgRvjiYrI f+/GmU4jmR4jJuEpWiJ3YDEML5mxIJDSjxq5wfOiU0f+zWWtSqYwtlBdh2zcWZPG1szt W57Ab9IHcucI+0A8+L1/SrihcWp9Osr4sZsb7VpmJ9pfVTYp/yhP7CAECG13ZgH6Eikx +TsBo76+7KlNKOoYsXqfLde4YZtETYqvtrudT6B83cMoJLBNe4IBFqDcP+ezIsHw43F3 Lu3/IkZszuiCIYKz05Ru/lECE0vKSY0LmT0df77c/cWMTyMawvoXMkjPsGeA9SxpKlAp P1kA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777482021; x=1778086821; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=ikSPOGR4XXwx0JwMlnraIx1B5HOIyelZFy6MXUSY+IY=; b=F1VeGre9OZv5T1s7gFdMOo659SEw8C+9M4ahGI9hTNSRSt4r3RYCtBQ57H164d0SEY 0226SHGEil3NadkintWdgPWNAKHR3J6/6e0lzGNsZfzW83gznYCtRACM3Cl/zr2qR18F euMsnXoZG0ePvQUtdoLzrPPEYhawPOLj9qlyHZ97fEjmfGz4RAP/kZdA4rN6SRBqYo0T Q8utbewxp3ph6c15WPt5GFRDfLHckRuxpUIKA2A2yQJVv0hhNWUMRJL7FwVosAHdpDbF sxmtvLD/Z1YLRYp/IRWEg6rFFPkEI2y4Fw2iDJ8atEKp0Tg8pi5vHZda3byxOhZn6Vjj aLdg== X-Forwarded-Encrypted: i=1; AFNElJ9PNh4W5qr8yQhOC4hGBminssq1iGCjkZ4Q/3nU9DQ4V67jaq4PWM79jPEhimHz9P71Jq+MaZIcMYWxrwc=@vger.kernel.org X-Gm-Message-State: AOJu0YyrkI/n1UhgTnTKNvb2J5VTdar5eBIE+zu9kvRg3k6zeLmMhM2B IEl6EBZPzbG7aPGRL416mTnllTKyl9xaeIcjVjOARYkA+X+/qp2DJx9f X-Gm-Gg: AeBDievvSsSPQ/U1aMnZZ3ASLwMXMbIywutB0hQsqNqT8dSc03t4xvXv8Nx61WtCX7p y+/pKxAQOZB/qKObqKyENWAQ+GJq7kqLqA/CppBTqXgicL0Ly5FLHSvFno+3h8t/A1f20mPVBod 9JHsit/kluSIC+QIVoKackAzR2cBlbNm/OnSTCu4Pqrc4isM7Il4wl7QL2I2VUQFVnFwCiFEGec RLiPDELiPOQf0yLw5Q3G7MJClcmcoJhOVF1gwTRufpa7iOSFSSSP24WiJIF0SZBlUpkcuPMnB56 LnvPQ2Wtv0GQ423JWnpQWZrsERypV4D0+x9BHGPveM9eDKXpXDrkJR0M9CnlcskOJPxpHKkbbFh LQQThz6dIOgs1yZkT4Ty5CxPxktxhTwKjOFfajMwyvTjtbUWiegR4Pq4+fEuI9xeD3t6To4P87R Qt0U9QOYWyd23amS6kMYnG3iBMBBGop3NIaZ8UPxamVgeD/pOhtzVBlXwKONJKEZvUhNlk7FjeA SNbmT/Z0rpbrTuwkTyOXqwYr0u67Sz4Z5DwWI38+4BykGFn X-Received: by 2002:a05:600c:3b0f:b0:48a:52ce:a4b1 with SMTP id 5b1f17b1804b1-48a77b177aamr133031915e9.15.1777482020092; Wed, 29 Apr 2026 10:00:20 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:212b:3a69:4f2c:3897]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48a820c856dsm4809755e9.6.2026.04.29.10.00.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Apr 2026 10:00:19 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Biju Das , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Laurent Pinchart , dri-devel@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Tommaso Merciai , Lad Prabhakar Subject: [PATCH 1/4] dt-bindings: display: renesas,rzg2l-du: Add RZ/T2H and RZ/N2H support Date: Wed, 29 Apr 2026 18:00:09 +0100 Message-ID: <20260429170012.366537-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260429170012.366537-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260429170012.366537-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Document the Display Unit (DU) support for the RZ/T2H and RZ/N2H SoCs. The DU block on RZ/T2H is functionally equivalent to the RZ/G2UL DU and supports the DPI interface, but includes SoC-specific register differences. Add a dedicated compatible string to represent this variant. As the DU implementation on RZ/N2H matches RZ/T2H, describe it using an RZ/N2H specific compatible string with the RZ/T2H compatible as fallback. Unlike other DU variants which use a multi-port model, the RZ/T2H and RZ/N2H DU has a single output and is modelled using a single port node with one endpoint. Add a port property to support this and update the allOf constraints accordingly. Signed-off-by: Lad Prabhakar Reviewed-by: Rob Herring (Arm) --- .../bindings/display/renesas,rzg2l-du.yaml | 24 +++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yam= l b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml index 2cc66dcef870..45678d536a75 100644 --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml @@ -21,6 +21,7 @@ properties: - renesas,r9a07g043u-du # RZ/G2UL - renesas,r9a07g044-du # RZ/G2{L,LC} - renesas,r9a09g057-du # RZ/V2H(P) + - renesas,r9a09g077-du # RZ/T2H - items: - enum: - renesas,r9a07g054-du # RZ/V2L @@ -28,6 +29,9 @@ properties: - items: - const: renesas,r9a09g056-du # RZ/V2N - const: renesas,r9a09g057-du # RZ/V2H(P) fallback + - items: + - const: renesas,r9a09g087-du # RZ/N2H + - const: renesas,r9a09g077-du # RZ/T2H fallback =20 reg: maxItems: 1 @@ -53,6 +57,10 @@ properties: power-domains: maxItems: 1 =20 + port: + $ref: /schemas/graph.yaml#/properties/port + description: Single output port for single-output DU variants. + ports: $ref: /schemas/graph.yaml#/properties/ports description: | @@ -83,9 +91,7 @@ required: - interrupts - clocks - clock-names - - resets - power-domains - - ports - renesas,vsps =20 additionalProperties: false @@ -137,6 +143,20 @@ allOf: =20 required: - port@0 + - if: + properties: + compatible: + contains: + const: renesas,r9a09g077-du + then: + properties: + resets: false + required: + - port + else: + required: + - resets + - ports =20 examples: # RZ/G2L DU --=20 2.54.0 From nobody Tue Jun 16 19:38:32 2026 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD399388E69 for ; Wed, 29 Apr 2026 17:00:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777482025; cv=none; b=VSok8p5whrBEz5T5UvJ3ClGezVzcxg2c8BW9epn3+fXBzf1Rihf3xtkFed2cCuIyVQNS/c5P4wiK+fUttLrLEtDRK4y2aoJ0fIrA015/pSHaiIYa1u8usHRtMoxmPMhcZgQtUGBW06eFIT66gZszjPF1ty5EaY2Oxv3Y2y2kR+8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777482025; c=relaxed/simple; bh=+SN/B0HL5voOgs8H1z2+q5XkZCu6QjgCLQ7MpeWtcac=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SjBMDOo2yZFkNLuYXfPKiEtLfufj64rO+9XmQLJVQvMjF0uz/ENSRAnnRrKVAa8tzam0uD4HSpYUr4QrLOY/nN1D5nsAEEWx+GjRHahgOqkMdruHLX7L6dcKBZ6FiutaHVQBbtDSn9iHN85Yz7HrdjbSvCeCpLe9XsqfmOZqmQI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=E3fl2gm5; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="E3fl2gm5" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-4891f625344so490465e9.0 for ; Wed, 29 Apr 2026 10:00:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1777482021; x=1778086821; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fuDLjeXf2+QKCuCo/9df2ZiinICm/jlzSdG09cp5d58=; b=E3fl2gm5sYF3X6DxFMkicnZWywPsEjFJWPITZ7qQQSKqcfKMQJkzmjyVcKd2hImZ+3 ZSAlJ7yJbcsE+27VUOK3YKO4wL76fIhOboKKy7NZFFC0iFYUw4GGfV2rfnOYGMirOgA1 LA2SBYf+fg5hdkdLRtFgKFzTqvJEX+KTa+Md67ufG/ye9lKQ0VVJsntFEKgq/GenKwtj nb8Cl+6KQDMBmLHR1jJCPgApL9AeDxvRecEDJtQFC0wuqVmygNjhLKZ3p1M0w6cherCL ccadohMOONTpfWhnOznUTAPftG2WD27u3T3Dx9iZ6IARi0lM0gtkyMmCLzFzUNPYwadw XQvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777482021; x=1778086821; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=fuDLjeXf2+QKCuCo/9df2ZiinICm/jlzSdG09cp5d58=; b=RXr58gDV26ohfhmngHN3zQCsoyvMqmiS6i/RMfQxbJScg8Cw0Oy3zG01w9RPMxcnyl t1KnTbKWtDB0rW5UEOADw1bdM8r1IKEY0Z+8cFDb5PKRJDnDe3EQNDgvAznoT+KGglEx 1CX0Ql0mlbTcUKu1nACSq3v/dUYkQ9hbp2SHUYu7mJtOdw7Q9FpZ5M/bszNlqADfmC3U +qHIj4SbTLHIJ119gPGuHK1IxFXQ+M4Yc3CWV6rShV8lCPyWE8eurfx003XOq1Aw5wij sGhoDR+xi9CX3GpOeG2dy1DAELnsiJ2HPDLVTcCyz9ET5yuTE8LlRxNrAZwssTcVfHd+ 7Z3g== X-Forwarded-Encrypted: i=1; AFNElJ+TrBntnoOWlu9BTne5xk0fbNJYiOPZ2I/zg0KE7wyiXizWJqg4KSQxmG7PglHxcIFDuFVcBtGfk/M2x3A=@vger.kernel.org X-Gm-Message-State: AOJu0YyLcHOLdF2euNYZDAQrCmY/Ol5nzVdB4fb6vXkyWJL4WL9VzK9Y FmaUYXgE7sBFzknTgOom4VnWnByp+qworBSEp2MIP3b1F3zfKMwCVqtQ X-Gm-Gg: AeBDieuSiaaWMlt7NIOoJZdorQa6Kj9n5rJnP5aoTiO+/0T6xqpOUoEVnZ/29YvW1kA 2a/NXXKYT/X+lLGiGNJOE6CdCpPCtKME3mXYWDC/bIeBahWC0cS/sd6k/GA4RiwyHhNXQbpDlo+ Eda2F7ZGMHl2Fv0mX4NL2GuoGeCWgCZONoRwZqzZ6s7bnx8DvA2gmf8RTnHVSQa7BOnBS5KV2Sd dcpF5Lym+4MBktQWwEb6wzE4hfKRmVlc+iQx8kEtQSZ8Nas5nO9jplXQ7liMH1oLBVO9sC0TCA/ CvDYbBNCVuvus+kLfA4gbW0b/GoqQcpsGDg8cG6asdsEZHxVp/hSDgrLuMy5MZCGTWYkjBmLrAR Qjwqgg1aUb5nnQAFcRKMYb/0zsxkqCljoqfCOHXlB1oHap2L6uKpbhvFY02f+/U9V5hA+NC3jZI XB5iK1oHTaKwcas4/AAXOM9a02nAVudbBvPSrW/qg6NYAelBRkYSxSy7me3FwxjMtqQBfoaCwhj ykoEHoQ6lhx4O5ZZIe5I+HjbqUqREqF6tkmhnSL35cAmgT4 X-Received: by 2002:a05:600c:a404:b0:48a:79d8:a8d6 with SMTP id 5b1f17b1804b1-48a7bfa1982mr56450465e9.7.1777482021011; Wed, 29 Apr 2026 10:00:21 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:212b:3a69:4f2c:3897]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48a820c856dsm4809755e9.6.2026.04.29.10.00.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Apr 2026 10:00:20 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Biju Das , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Laurent Pinchart , dri-devel@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Tommaso Merciai , Lad Prabhakar Subject: [PATCH 2/4] drm: renesas: rz-du: Make DU reset control optional for RZ/T2H support Date: Wed, 29 Apr 2026 18:00:10 +0100 Message-ID: <20260429170012.366537-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260429170012.366537-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260429170012.366537-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Update the DU CRTC initialisation to request the reset control using devm_reset_control_get_optional_shared(). On RZ/T2H SoCs the DU block does not expose a reset line, and treating the reset as mandatory prevents the driver from probing on those platforms. Signed-off-by: Lad Prabhakar Reviewed-by: Laurent Pinchart --- drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c b/drivers/gpu/dr= m/renesas/rz-du/rzg2l_du_crtc.c index 18e2b981b691..2b772a11c7ee 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c @@ -380,7 +380,7 @@ int rzg2l_du_crtc_create(struct rzg2l_du_device *rcdu) struct drm_plane *primary; int ret; =20 - rcrtc->rstc =3D devm_reset_control_get_shared(rcdu->dev, NULL); + rcrtc->rstc =3D devm_reset_control_get_optional_shared(rcdu->dev, NULL); if (IS_ERR(rcrtc->rstc)) { dev_err(rcdu->dev, "can't get cpg reset\n"); return PTR_ERR(rcrtc->rstc); --=20 2.54.0 From nobody Tue Jun 16 19:38:32 2026 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3B75410D08 for ; Wed, 29 Apr 2026 17:00:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777482026; cv=none; b=bcVBqybaK/WsAe2B2QTXKAzHWg5hsx5TFLT0yXUTUTlNwgzbYtCgt0KZQ6xhzik0X2vCs6bKeAH+3M4lQGVzQ7rQhxsCWLb19riJGyX/u6NH5Wr5CM+YyfDlBEmdevRSMVag9ZsH6BBgwzEhcHpJGElruHYN5W31uVqymxk8isw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777482026; c=relaxed/simple; bh=yIk8w/6ovoyQObDFMXFGLfwUhPrGI/MFA3yvbYHUlog=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iVLUA20hQ/kvsV3q8iwN71058NJgN7txYeJaM+mWAZ9iDx8MLsOFtvCs4Lg13hXP0pGfCxqF6hCYsUQzwJFz4B72YXyhJbi18ZZcrnyUMkGWEJqFbwRHmerbduikPjRMPgQ55JfLpTKLynjWOjESgWt6PBgLUEOzWYqQG8kUSrE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=rJNmMTCI; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="rJNmMTCI" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-48a7fe4f40bso3260655e9.0 for ; Wed, 29 Apr 2026 10:00:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1777482022; x=1778086822; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OPI/IWDY5AjEaKDZ824ZagzMhOb02JbM6Y93TiTFTTk=; b=rJNmMTCIlWFV5KcjKIIohZ8/u6WLS+TaRYXxSSnjwbs3SHWxIH53L0V2QGBizffXeQ RemIvA++QaxGcUd9zpSvFLQqhwzf68rb/V77T1eWS3mgDb7c/nmEcFiZXKUA93e7IF1w BVq4ANyd8BLzqth38YhpxAZVRCOgFUdw0rZoeqysjDjO5AjMGeNu4x9vUq1mCZyRH/Ie olMqbYkep7Wx6uQBoxZREiXhLazUboFs/+9Vf30XvNxk5KjZznhOdVW40XW4s2ER3siE VkKHTOHA2VZH3icPbUq9U9sBZfkFPN/YfPejJRylP+k83qf6NorY1/niWyhl381H/9zs QwZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777482022; x=1778086822; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=OPI/IWDY5AjEaKDZ824ZagzMhOb02JbM6Y93TiTFTTk=; b=Ns3E/Rf/CKsrX3sEzyN2pUQpiIa8RpNAkilWyNkPec2bqscXiwHjk8wZNSp8lb7gsa nXLLg7g/P50kCj7HpkpjuCKJ4cM6/CAhYHXwgSoN++gH2K0LkUy/p71jSXXDXjYscqiv cj6zrd0Rugi/6ZNZViF98RxovZcD4iiC3P35aQrQF/aBGInKCkeDv0v5UN5BRkQIAssq 7pigp4K6nc4IkkrXcX5/ue3bgtMpp0U3cC/IHzL6wFuCrI+3OEjHEIsIRZLyDfWIG8dp eAXraFgnHo5U10GGvlWukwJ3RxyOfCqtnYAs7Avk3MdgxqVery9tSeh/UVj1KhHvoD8r /HDg== X-Forwarded-Encrypted: i=1; AFNElJ/Q8WsPzKgGGa5WQZ3o/cFtAkY86iwICipimG0X2tXmb5NWDki//JdUdnlJq6k6SZ/EzUIiJ3iEm0AAb8c=@vger.kernel.org X-Gm-Message-State: AOJu0YyAYe7WJ+czMjzK+FqeU9NnPx9hlGaPJBGavI05WM2vmI9rivAM Ktrq80rwLvE9MusjyFBqL1peuq+meycDMNezeRU/XNsFvOh/2dY6epBs X-Gm-Gg: AeBDieuGLlXG0ez9SxKWATRSc+l5diI8UUMvTthtK+fmtUfGJ95745q87eqK0qGUdDY GmL/Lm10l0cKj5iaWwJmYh/zQlDkX7saiy1QLr0bFRgQjl87ugfDProMOrNXMseBNtd8wpPrnxh Y4T9q8G9SbflHRdyDKJvqxVKtXJqsA7BxUt4OLDCyUjOXzeBNwZV8n4HWWnrhSLhg4K4D1WWS1a Ty4NJMJjVTm2rgGvCi43g8f669Sk/azTN3VWfsqTNjezCdyfymRq6tTwUImxDFSrhCTRZeN8nJm ze1llO+GzlFtXHdWeCDWK7y8h/vM0CAwiUcWPBQUH3W/2tVpqaNCNzuHTcnmdg/DaDkqs03O7MA lq+/LvrQSEakKIFcZfsv2h5c3r6NQHq8aqdegEKMr3yXGlPr6kMUuJErR7JtguZJ5c4LJ+ZNMH3 3MfYp2+c0f7pnFGxXRPkWKiZrdwuEMI1YRe6q1g8O3Undh8ZYSq6CpvipIE0flg07TjVJRjcoJM q6o1z/DXQgvEhDjPl8mTeLwHGKhZEUBk1E2iXMIZMjB/AMA X-Received: by 2002:a05:600c:b90:b0:489:1e8a:90b4 with SMTP id 5b1f17b1804b1-48a7b53ca8fmr80064815e9.21.1777482021927; Wed, 29 Apr 2026 10:00:21 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:212b:3a69:4f2c:3897]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48a820c856dsm4809755e9.6.2026.04.29.10.00.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Apr 2026 10:00:21 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Biju Das , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Laurent Pinchart , dri-devel@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Tommaso Merciai , Lad Prabhakar Subject: [PATCH 3/4] drm: renesas: rz-du: Move mode_valid logic to per-SoC clock limits Date: Wed, 29 Apr 2026 18:00:11 +0100 Message-ID: <20260429170012.366537-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260429170012.366537-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260429170012.366537-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Move pixel clock validation from a fixed encoder check to per SoC constraints stored in rzg2l_du_device_info. Pixel clock limits differ across SoCs in the RZ DU family and cannot be expressed by a single shared rule. For example, RZ/G2UL (R9A07G043U) limits the DPAD0 pixel clock to 83.5 MHz, while other SoCs such as RZ/T2H require a wider operating range. Add mode_clock_min and mode_clock_max fields to rzg2l_du_device_info to describe the supported pixel clock range for each SoC. Update rzg2l_du_encoder_mode_valid() to return MODE_CLOCK_LOW when the pixel clock falls below mode_clock_min and MODE_CLOCK_HIGH when it exceeds mode_clock_max. Set the pixel clock limits for RZ/G2UL(R9A07G043U) to 20.875MHz minimum and 83.5MHz maximum. Signed-off-by: Lad Prabhakar --- drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 2 ++ drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h | 4 ++++ drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c | 6 +++++- drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.h | 2 ++ 4 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c b/drivers/gpu/drm= /renesas/rz-du/rzg2l_du_drv.c index 0fef33a5a089..3b7162c6e1f4 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c @@ -35,6 +35,8 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g0= 43u_info =3D { .port =3D 0, }, }, + .mode_clock_min =3D 20875, + .mode_clock_max =3D 83500, }; =20 static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info =3D { diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h b/drivers/gpu/drm= /renesas/rz-du/rzg2l_du_drv.h index 58806c2a8f2b..885558eb9547 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h @@ -44,10 +44,14 @@ struct rzg2l_du_output_routing { * struct rzg2l_du_device_info - DU model-specific information * @channels_mask: bit mask of available DU channels * @routes: array of CRTC to output routes, indexed by output (RZG2L_DU_OU= TPUT_*) + * @mode_clock_min: minimum pixel clock in kHz + * @mode_clock_max: maximum pixel clock in kHz */ struct rzg2l_du_device_info { unsigned int channels_mask; struct rzg2l_du_output_routing routes[RZG2L_DU_OUTPUT_MAX]; + u32 mode_clock_min; + u32 mode_clock_max; }; =20 #define RZG2L_DU_MAX_CRTCS 1 diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c b/drivers/gpu= /drm/renesas/rz-du/rzg2l_du_encoder.c index d53068733c66..ad02efec1c23 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c @@ -50,8 +50,11 @@ rzg2l_du_encoder_mode_valid(struct drm_encoder *encoder, const struct drm_display_mode *mode) { struct rzg2l_du_encoder *renc =3D to_rzg2l_encoder(encoder); + const struct rzg2l_du_device_info *info =3D renc->info; =20 - if (renc->output =3D=3D RZG2L_DU_OUTPUT_DPAD0 && mode->clock > 83500) + if (info->mode_clock_min && mode->clock < info->mode_clock_min) + return MODE_CLOCK_LOW; + if (info->mode_clock_max && mode->clock > info->mode_clock_max) return MODE_CLOCK_HIGH; =20 return MODE_OK; @@ -107,6 +110,7 @@ int rzg2l_du_encoder_init(struct rzg2l_du_device *rcdu, if (IS_ERR(renc)) return PTR_ERR(renc); =20 + renc->info =3D rcdu->info; renc->output =3D output; drm_encoder_helper_add(&renc->base, &rzg2l_du_encoder_helper_funcs); =20 diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.h b/drivers/gpu= /drm/renesas/rz-du/rzg2l_du_encoder.h index 3e430c1f6132..39a1d178b856 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.h +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.h @@ -14,10 +14,12 @@ #include =20 struct rzg2l_du_device; +struct rzg2l_du_device_info; =20 struct rzg2l_du_encoder { struct drm_encoder base; enum rzg2l_du_output output; + const struct rzg2l_du_device_info *info; }; =20 static inline struct rzg2l_du_encoder *to_rzg2l_encoder(struct drm_encoder= *e) --=20 2.54.0 From nobody Tue Jun 16 19:38:32 2026 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2AA02410D21 for ; Wed, 29 Apr 2026 17:00:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777482027; cv=none; b=bOnR7EUXzUnZGUU6McrCoyax5EpAA5yho7URc6XgvjGBRPBVVKSe6+25D2UW/2cGBSH4HuNOYxN6HaUqyP7bDAOg7pP3ElxlYfk8uv8yCZ/6j/+MfCceLWxotXUZOe4GuQneT4LYjtNXaBA/Fm2QSP3aOcAx0Z2v7YO8RA2ArTE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777482027; c=relaxed/simple; bh=5KJb4pUz9ISCWuOFq3mdW6ldExid2fnbaeYjkHbT2Ng=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qa8oGiWPE/XBFyJTVwJf++ZZPzYsXzlwNcXaM5hcmtkMhCecy5A8i9jWWUW69nWTk7XYhjotM8C+lFiOFbTNyI9SQwej5X+LiJkR64dS8tgGsZoX/fjIOC41CpdlBpdTHXqgqO4Bw2UPuPOULTlCB4v7I6M6RD/h3nEfrbgZC7U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=L9v6t60E; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="L9v6t60E" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-4852b81c73aso106596235e9.3 for ; Wed, 29 Apr 2026 10:00:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1777482023; x=1778086823; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vkSm8ny43p543u10ucazCdZPdCMdlkGl7rYD8obUTQI=; b=L9v6t60EVwJS0l40I9Wxs7ixw3yT/RqlkQPjdsj8+jsEfZRhSBV5wCqavh5b+xkkIh cu/uSbyRPbXzLL0GlxeETvfbG0Rso5UlJ3ar1XeypEvWrvZVrP1nQkvva68BVCFR91RD Vt+/tMXh82o00vbnliNomQjABvJ0TUz4b+EepgwTRR6NUnCRIre2LWmiB46z6B2vQqHM Rmehb5/cHcBkV3N0+pRsFT4B9JYxBmZEB1mHpn7FLqWdr5RnoWBeanUG3peYcHHFdFUK 3HoWWJH2wW3r3lTsLkXKY5sxq5gIhUeXjgWDJ49+p+9d+KWRQKASam0L7xAMrsqhSq9i Bg3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777482023; x=1778086823; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=vkSm8ny43p543u10ucazCdZPdCMdlkGl7rYD8obUTQI=; b=IUzABIm7Fnq+JMfZFg3eE+C35TJOxImkWWtJZG7w7m1zHvYVK+pD/mOxjeuOQmRjBB bQzt7gWstXBmADojSucjri0lzJaVSFlOZj7tHbfc4CxW1S3Z16v4B0ElqoJPQcO61l+u vZ+L07hRtRmPKkwisZgVHtzyFVpeykVOTB37iy8M8JTREzN0TqzcaCicqy3XQ8+1ebDD jPKR/3WgX+XVqbnPyHS36WDpUuBGkMPbtyZE0WTmd8yefyG52QDPqbs1NqSezedi8LEn g4az1GcqqvM17SmZfQ+tKS8+AOX9K1oSALgnjbKliKKB1UVgsqnRhthQZ67kBCR0S7zE SWtA== X-Forwarded-Encrypted: i=1; AFNElJ+31PLCsBGrmYEfuQEho9lxwTafcBIfYiriHG3OA7op7Qek2a3wWRuJZ0JMC1TAdXbvB3kBkeLvHzBhKIM=@vger.kernel.org X-Gm-Message-State: AOJu0YwFqIEwXqQicol8oOKsR1yjOXFV6PCS37lYHgWc3ztD+8WEKflQ BBxJhXVMuizoZZhDD7K5vQGnM7YP+m0Scd6sLoNX7wB7Oi6wbmztCt2R X-Gm-Gg: AeBDievkgnZ/9SQWtWiWNY3TNJ9O7q6Pd1wmVtNIOV7JKLTZQdJvJ0gU1Y/w2PuweU5 RzcWGPZ0ddWSj4CZQjRJIrTMgMFfZVZ2ycSzEetDfGEj9eV7+AEn0MYWnTRtyuAo7Z6xxIBp5op E7ngta21xmKtCzNnm7b1f69zud/5czlMS81u3OpFiIYGevs576cm4PZh5ldMHi+2p6h6DcL2Y8/ AH6dzFn6dVtGmaPPZQSV713EyYYU1zySsa8W5ENlP+wzMbQuFJn17PgcyvH6BG6Qap6INIKjqCn tdwgPh65QcPkj3i03QcbOcjfZFI9v0YwpxCRZGi7gt+ymXP/oBA8tqF6JzALJplDNWUCGcqv0NT wI6IY0XXQl9uI/oacZuJY3yCnsiI68zt12Fc+cp0oYLDNE/AJgAfopZ6FXq1HAlraOLDnP+q8hk jLmnXMlsW/U6XkbhhiauQsP5W7svRS/H1HZkv57lsxHNpS4bFixLicDvdlZZQ2quC+BWZohUqkZ JK1ebhCm7zP7pDCqm+IFIkMMPOtZ29IjTI9bNpawwdkyN+8 X-Received: by 2002:a05:600c:609a:b0:48a:54a6:b29f with SMTP id 5b1f17b1804b1-48a77b1da9dmr131662065e9.17.1777482022872; Wed, 29 Apr 2026 10:00:22 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:212b:3a69:4f2c:3897]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48a820c856dsm4809755e9.6.2026.04.29.10.00.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Apr 2026 10:00:22 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Biju Das , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Laurent Pinchart , dri-devel@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Tommaso Merciai , Lad Prabhakar Subject: [PATCH 4/4] drm: renesas: rz-du: Add support for RZ/T2H SoC Date: Wed, 29 Apr 2026 18:00:12 +0100 Message-ID: <20260429170012.366537-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260429170012.366537-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260429170012.366537-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar The RZ/T2H (R9A09G077) SoC includes a DU with a DPI interface, supporting resolutions up to WXGA with two RPFs for layer blending. Unlike earlier RZ/G2L SoCs, RZ/T2H requires explicit assertion of a DPI output-enable signal (DU_MCR0_DPI_EN) during CRTC startup. Signed-off-by: Lad Prabhakar Reviewed-by: Laurent Pinchart --- drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c | 7 ++++++- drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 14 ++++++++++++++ drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h | 10 ++++++++++ 3 files changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c b/drivers/gpu/dr= m/renesas/rz-du/rzg2l_du_crtc.c index 2b772a11c7ee..017d5f26bc96 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c @@ -28,6 +28,7 @@ #include "rzg2l_du_vsp.h" =20 #define DU_MCR0 0x00 +#define DU_MCR0_DPI_EN BIT(0) #define DU_MCR0_DI_EN BIT(8) =20 #define DU_DITR0 0x10 @@ -217,8 +218,12 @@ static void rzg2l_du_crtc_put(struct rzg2l_du_crtc *rc= rtc) static void rzg2l_du_start_stop(struct rzg2l_du_crtc *rcrtc, bool start) { struct rzg2l_du_device *rcdu =3D rcrtc->dev; + u32 val =3D DU_MCR0_DI_EN; =20 - writel(start ? DU_MCR0_DI_EN : 0, rcdu->mmio + DU_MCR0); + if (start && rzg2l_du_has(rcdu, RZG2L_DU_FEATURE_DPIO_OE)) + val |=3D DU_MCR0_DPI_EN; + + writel(start ? val : 0, rcdu->mmio + DU_MCR0); } =20 static void rzg2l_du_crtc_start(struct rzg2l_du_crtc *rcrtc) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c b/drivers/gpu/drm= /renesas/rz-du/rzg2l_du_drv.c index 3b7162c6e1f4..fc55dfffebaf 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c @@ -63,10 +63,24 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a09= g057_info =3D { }, }; =20 +static const struct rzg2l_du_device_info rzg2l_du_r9a09g077_info =3D { + .channels_mask =3D BIT(0), + .routes =3D { + [RZG2L_DU_OUTPUT_DPAD0] =3D { + .possible_outputs =3D BIT(0), + .port =3D 0, + }, + }, + .features =3D RZG2L_DU_FEATURE_DPIO_OE, + .mode_clock_min =3D 5000, + .mode_clock_max =3D 100000, +}; + static const struct of_device_id rzg2l_du_of_table[] =3D { { .compatible =3D "renesas,r9a07g043u-du", .data =3D &rzg2l_du_r9a07g043u= _info }, { .compatible =3D "renesas,r9a07g044-du", .data =3D &rzg2l_du_r9a07g044_i= nfo }, { .compatible =3D "renesas,r9a09g057-du", .data =3D &rzg2l_du_r9a09g057_i= nfo }, + { .compatible =3D "renesas,r9a09g077-du", .data =3D &rzg2l_du_r9a09g077_i= nfo }, { /* sentinel */ } }; =20 diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h b/drivers/gpu/drm= /renesas/rz-du/rzg2l_du_drv.h index 885558eb9547..baf076d69cda 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h @@ -20,6 +20,8 @@ struct device; struct drm_property; =20 +#define RZG2L_DU_FEATURE_DPIO_OE BIT(0) /* Has DPIO output enable control = */ + enum rzg2l_du_output { RZG2L_DU_OUTPUT_DSI0, RZG2L_DU_OUTPUT_DPAD0, @@ -46,12 +48,14 @@ struct rzg2l_du_output_routing { * @routes: array of CRTC to output routes, indexed by output (RZG2L_DU_OU= TPUT_*) * @mode_clock_min: minimum pixel clock in kHz * @mode_clock_max: maximum pixel clock in kHz + * @features: device features (RZG2L_DU_FEATURE_*) */ struct rzg2l_du_device_info { unsigned int channels_mask; struct rzg2l_du_output_routing routes[RZG2L_DU_OUTPUT_MAX]; u32 mode_clock_min; u32 mode_clock_max; + unsigned int features; }; =20 #define RZG2L_DU_MAX_CRTCS 1 @@ -77,6 +81,12 @@ static inline struct rzg2l_du_device *to_rzg2l_du_device= (struct drm_device *dev) return container_of(dev, struct rzg2l_du_device, ddev); } =20 +static inline bool rzg2l_du_has(struct rzg2l_du_device *rcdu, + unsigned int feature) +{ + return rcdu->info->features & feature; +} + const char *rzg2l_du_output_name(enum rzg2l_du_output output); =20 #endif /* __RZG2L_DU_DRV_H__ */ --=20 2.54.0