From nobody Tue Jun 16 19:41:11 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A846035F180; Wed, 29 Apr 2026 12:26:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777465602; cv=none; b=BPMal6LS9qQTVt5cotgwCqg6AS68k6jruWMcA+ybUhGcz0BOGox2zn+tdhAcoTziZ602Jz6nzXjgvy1QWj9enNXVr4qJJw5ARFqBQ67jNsNI4gGQqJaFgk/ewLNWTmoIj4lo74G8hvdl6yEbT/mJ7vGzFzQMXPFWfwXYPhjq6LY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777465602; c=relaxed/simple; bh=ZcnbBrCLet6KhQv9ffMklrkXZtBqvBKwCzYgPyMPV4M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=Fo2zHozsDWBBRBcS8hg5bLHd675ufZAiu41zt3s3mnE04bJYn3Iw0F/BDmIPyqHfLv7XufTeniVxoCMkeYWk3P4Kg/+SKd3cBfE9T5d+WsZbnz0ZvBQU6f2Dp8rY2cCfPPLJ6cINjma+cr9NS8DqjR/StCqQK55ruhRFLE0vxhE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=BFqSbIVz; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="BFqSbIVz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777465600; x=1809001600; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZcnbBrCLet6KhQv9ffMklrkXZtBqvBKwCzYgPyMPV4M=; b=BFqSbIVzN8SWsagTP5Sr2jZ1H+R6Yy8EWcFbd3lpTnShl5mkznn3wZdS 9EAPDenhGY+x8N6izGQvNtTLerSp2XCJAJR6hrVzWP+5jXhYakXyzIctD WFU6JCosidbsC015T92FhMdMbdqZRkQ8l0gqCqnaqHDwm1jkDxa6VLbLA v7Yo/DjZDW39FJ77pthBuKqCh2qwZqmDvte9JIKhLw9DB+zv/uv3BOGX2 g0BfDZHuJsMdi15tZEUtMtIpQhznOfChzXltsNB6z/ivVqnPHxVVszHoe XHVHt+NffWznio/nRxtpCFb8xCtHjmdyfMBStuEfgkGTPorH1ZwrMmJMY g==; X-CSE-ConnectionGUID: S7wpNlApSHKe74AafvwF5g== X-CSE-MsgGUID: 0a3BNc2cRnOKWU08G35V/Q== X-IronPort-AV: E=McAfee;i="6800,10657,11770"; a="77557668" X-IronPort-AV: E=Sophos;i="6.23,206,1770624000"; d="scan'208";a="77557668" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 05:26:40 -0700 X-CSE-ConnectionGUID: eJ2+zU6sTeuUgdPAP8eYLg== X-CSE-MsgGUID: H7blClL+SSOTRT9AmhNfxA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,206,1770624000"; d="scan'208";a="229669679" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.212]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 05:26:36 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Shawn Jin , linuxppc-dev@lists.ozlabs.org, Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 01/11] PCI: Log all resource claims Date: Wed, 29 Apr 2026 15:26:07 +0300 Message-Id: <20260429122617.7324-2-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260429122617.7324-1-ilpo.jarvinen@linux.intel.com> References: <20260429122617.7324-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable There are two ways to graft resource into resource tree in PCI, pci_assign_resource() and pci_claim_resource(). Only the former logs the action which complicated troubleshooting the cases where resources are assigned by pci_claim_resource() which mostly assigns the addresses inherited from the FW. Add logging into pci_claim_resource() to make troubleshooting easier. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-res.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index fbc05cda96ee..0d203325562b 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -167,6 +167,8 @@ int pci_claim_resource(struct pci_dev *dev, int resourc= e) return -EBUSY; } =20 + pci_dbg(dev, "%s %pR: claiming\n", res_name, res); + return 0; } EXPORT_SYMBOL(pci_claim_resource); --=20 2.39.5 From nobody Tue Jun 16 19:41:11 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA20939C002; Wed, 29 Apr 2026 12:26:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777465613; cv=none; b=XSItwaTuoqKqFKb7G3ZnvA8j2cIxgt82c13qukBoS/b1eS1nB+LoTiVsk1Y2AjOckIANJO736PT/UWT/CYk9aCH3eaeQSwMyvcjUIrc0QHTfFXT0YdSgdjG6oInqqy+ttsrw3KCJ0TDNCaiHCuzDJxwOVZ3QZxmBO4VChi30vqs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777465613; c=relaxed/simple; bh=NlSw3DKYOjHOeHYh/0go2vSw53u8u6nznavTwXNw3m0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=FgHpQRXnFQFwROPeSDCCpszSSpxvnvGm1epKYICuZx1SmmM+fn52fpf3ZeP9QNeQN1zV4LrnRYN+9vrCKw4/aqmGgY+IqRN40n0VaZQQ/PAwvA8mijgRN0CkD4MlULt278Rgyb8cTkxTVU8Twkpl3d7CinJye2paJK0JV+mBe/U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=T8Dmh9QN; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="T8Dmh9QN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777465611; x=1809001611; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NlSw3DKYOjHOeHYh/0go2vSw53u8u6nznavTwXNw3m0=; b=T8Dmh9QN7vTMXo+7Abx8weaCfVRCUWL7gMRn9Jvzs7MMSWr98+uB2yB6 IEIgKCNMs4QiU2KM3JhjxWgSR+F+yIzSU68iePkk9/3IdJKmxrDDOQ4Iz /E7hPLG87GHDBf7X3O25ElxfoszCtBzSFOFMt5KK51ZoeRxWYFGqDCpew QOX1QPFWvVv4VFBnDdcwv7rJ+Q+9oyeLWbAGsd7YYBu9fDToSYE8+U7Bh hvTOC5ByVcKm4JjzYXSrsV+gPCBkZAC+9v24t9qefed0TLMsZNFXog3v1 USI23fBRVdBnumMLRWZy56ErLdMHnFvn33duudkuK8b2z21RSsaWsfR0J g==; X-CSE-ConnectionGUID: N22MFhwsQG+DbcgUpkMQiQ== X-CSE-MsgGUID: AKDB1Du/RmGXknErETuYew== X-IronPort-AV: E=McAfee;i="6800,10657,11770"; a="77557694" X-IronPort-AV: E=Sophos;i="6.23,206,1770624000"; d="scan'208";a="77557694" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 05:26:51 -0700 X-CSE-ConnectionGUID: rb2ZCEBZRhq5Nh1Tx+QRvA== X-CSE-MsgGUID: XJYr1JnTROCPcbw42Lz3bw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,206,1770624000"; d="scan'208";a="229669702" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.212]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 05:26:47 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Shawn Jin , linuxppc-dev@lists.ozlabs.org, Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 02/11] PCI: Rename added to add_list Date: Wed, 29 Apr 2026 15:26:08 +0300 Message-Id: <20260429122617.7324-3-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260429122617.7324-1-ilpo.jarvinen@linux.intel.com> References: <20260429122617.7324-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The resource fitting algorithm uses different names from the list holding the optional sizes: added, add_head, add_list, and realloc_head. 'add_list' sounds the most natural and some of the related variables also use 'add' such as 'add_size'. To reduce variation, rename 'added' and 'add_head' to 'add_list'. Also rename some 'realloc_head' cases selectively to 'add_list'. While it would be nice to rename every 'realloc_head' to 'add_list' for consistency, it might create a backport headache with all to work going into this algorithm that may need to be eventually backported. Thus, it's better to leave 'realloc_head' as is for now. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/pci.h | 2 +- drivers/pci/setup-bus.c | 26 +++++++++++++------------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 4a14f88e543a..4fcf5a25ad9e 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -515,7 +515,7 @@ int pci_dev_res_add_to_list(struct list_head *head, str= uct pci_dev *dev, void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head); void __pci_bus_assign_resources(const struct pci_bus *bus, - struct list_head *realloc_head, + struct list_head *add_list, struct list_head *fail_head); bool pci_bus_clip_resource(struct pci_dev *dev, int idx); void pci_walk_bus_locked(struct pci_bus *top, diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 4cf120ebe5ad..3765693e95f0 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -756,13 +756,13 @@ static void __assign_resources_sorted(struct list_hea= d *head, } =20 static void pdev_assign_resources_sorted(struct pci_dev *dev, - struct list_head *add_head, + struct list_head *add_list, struct list_head *fail_head) { LIST_HEAD(head); =20 pdev_sort_resources(dev, &head); - __assign_resources_sorted(&head, add_head, fail_head); + __assign_resources_sorted(&head, add_list, fail_head); =20 } =20 @@ -1502,13 +1502,13 @@ static void pdev_assign_fixed_resources(struct pci_= dev *dev) } =20 void __pci_bus_assign_resources(const struct pci_bus *bus, - struct list_head *realloc_head, + struct list_head *add_list, struct list_head *fail_head) { struct pci_bus *b; struct pci_dev *dev; =20 - pbus_assign_resources_sorted(bus, realloc_head, fail_head); + pbus_assign_resources_sorted(bus, add_list, fail_head); =20 list_for_each_entry(dev, &bus->devices, bus_list) { pdev_assign_fixed_resources(dev); @@ -1517,7 +1517,7 @@ void __pci_bus_assign_resources(const struct pci_bus = *bus, if (!b) continue; =20 - __pci_bus_assign_resources(b, realloc_head, fail_head); + __pci_bus_assign_resources(b, add_list, fail_head); =20 switch (dev->hdr_type) { case PCI_HEADER_TYPE_BRIDGE: @@ -1613,19 +1613,19 @@ void pci_bus_claim_resources(struct pci_bus *b) EXPORT_SYMBOL(pci_bus_claim_resources); =20 static void __pci_bridge_assign_resources(const struct pci_dev *bridge, - struct list_head *add_head, + struct list_head *add_list, struct list_head *fail_head) { struct pci_bus *b; =20 pdev_assign_resources_sorted((struct pci_dev *)bridge, - add_head, fail_head); + add_list, fail_head); =20 b =3D bridge->subordinate; if (!b) return; =20 - __pci_bus_assign_resources(b, add_head, fail_head); + __pci_bus_assign_resources(b, add_list, fail_head); =20 switch (bridge->class >> 8) { case PCI_CLASS_BRIDGE_PCI: @@ -2303,7 +2303,7 @@ static int pbus_reassign_bridge_resources(struct pci_= bus *bus, struct resource * unsigned long type =3D res->flags; struct pci_dev_resource *dev_res; struct pci_dev *bridge =3D NULL; - LIST_HEAD(added); + LIST_HEAD(add_list); LIST_HEAD(failed); unsigned int i; int ret =3D 0; @@ -2337,10 +2337,10 @@ static int pbus_reassign_bridge_resources(struct pc= i_bus *bus, struct resource * if (!bridge) return -ENOENT; =20 - __pci_bus_size_bridges(bridge->subordinate, &added); - __pci_bridge_assign_resources(bridge, &added, &failed); - if (WARN_ON_ONCE(!list_empty(&added))) - pci_dev_res_free_list(&added); + __pci_bus_size_bridges(bridge->subordinate, &add_list); + __pci_bridge_assign_resources(bridge, &add_list, &failed); + if (WARN_ON_ONCE(!list_empty(&add_list))) + pci_dev_res_free_list(&add_list); =20 if (!list_empty(&failed)) { if (pci_required_resource_failed(&failed, type)) --=20 2.39.5 From nobody Tue Jun 16 19:41:11 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 105B839BFF4; Wed, 29 Apr 2026 12:27:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777465623; cv=none; b=uhWCyxiFpDz2fIMooXxlhz7sd1u5DMHv/RSTqiTfcYxYArOLVxLAA7E2wu6uZHcQUTDxsxEKi1msDSTxD8WCQr0GNgxD0QaKKUt2CBvFewSUw56/3CyS8bwNLQkwfJq9to70IWDsoktRG3fl5tyIhybYAEQRVnMQt/Lgynnyh70= ARC-Message-Signature: i=1; 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d="scan'208";a="229669749" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.212]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 05:26:58 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Shawn Jin , linuxppc-dev@lists.ozlabs.org, Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 03/11] PCI: Consolidate add_list (aka realloc_head) empty sanity checks Date: Wed, 29 Apr 2026 15:26:09 +0300 Message-Id: <20260429122617.7324-4-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260429122617.7324-1-ilpo.jarvinen@linux.intel.com> References: <20260429122617.7324-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Callers of __pci_bridge_assign_resources() and __pci_bus_assign_resources() perform WARN_ON_ONCE(list_empty(add_list))) checks to sanity check that all optional sizes were processed (and removed) from the list. The empty list sanity check is duplicated code so the more appropriate place for it would be inside the called function. Placing the empty list check into __pci_bus_assign_resources() also ensures all callsites do perform the sanity check which currently is not the case when being called from enable_slot(). This inconsistency was noted by Sashiko though only inside its in depth log but not flagged as a real problem, possibly because this is only a sanity check that should never fire. Nonetheless, this sanity check has been very useful to catch problems early in the past so it's good to do it consistenty everywhere. As __pci_bus_assign_resources() is recursive function, it needs to be renamed to __pci_bus_assign_resources_one() to only perform the empty list check at the end of processing the entire hierarchy in __pci_bus_assign_resources(). Suggested-by: sashiko.dev # Sanity check missing from enable_slot() Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-bus.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 3765693e95f0..1e0e28efe8b8 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1501,9 +1501,9 @@ static void pdev_assign_fixed_resources(struct pci_de= v *dev) } } =20 -void __pci_bus_assign_resources(const struct pci_bus *bus, - struct list_head *add_list, - struct list_head *fail_head) +static void __pci_bus_assign_resources_one(const struct pci_bus *bus, + struct list_head *add_list, + struct list_head *fail_head) { struct pci_bus *b; struct pci_dev *dev; @@ -1517,7 +1517,7 @@ void __pci_bus_assign_resources(const struct pci_bus = *bus, if (!b) continue; =20 - __pci_bus_assign_resources(b, add_list, fail_head); + __pci_bus_assign_resources_one(b, add_list, fail_head); =20 switch (dev->hdr_type) { case PCI_HEADER_TYPE_BRIDGE: @@ -1537,6 +1537,16 @@ void __pci_bus_assign_resources(const struct pci_bus= *bus, } } =20 +void __pci_bus_assign_resources(const struct pci_bus *bus, + struct list_head *add_list, + struct list_head *fail_head) +{ + __pci_bus_assign_resources_one(bus, add_list, fail_head); + + if (WARN_ON_ONCE(add_list && !list_empty(add_list))) + pci_dev_res_free_list(add_list); +} + void pci_bus_assign_resources(const struct pci_bus *bus) { __pci_bus_assign_resources(bus, NULL, NULL); @@ -1641,6 +1651,9 @@ static void __pci_bridge_assign_resources(const struc= t pci_dev *bridge, pci_domain_nr(b), b->number); break; } + + if (WARN_ON_ONCE(add_list && !list_empty(add_list))) + pci_dev_res_free_list(add_list); } =20 static void pci_bridge_release_resources(struct pci_bus *bus, @@ -2205,8 +2218,6 @@ void pci_assign_unassigned_root_bus_resources(struct = pci_bus *bus) =20 /* Depth last, allocate resources and update the hardware. */ __pci_bus_assign_resources(bus, add_list, &fail_head); - if (WARN_ON_ONCE(add_list && !list_empty(add_list))) - pci_dev_res_free_list(add_list); tried_times++; =20 /* Any device complain? */ @@ -2268,8 +2279,6 @@ void pci_assign_unassigned_bridge_resources(struct pc= i_dev *bridge) pci_bridge_distribute_available_resources(bridge, &add_list); =20 __pci_bridge_assign_resources(bridge, &add_list, &fail_head); - if (WARN_ON_ONCE(!list_empty(&add_list))) - pci_dev_res_free_list(&add_list); tried_times++; =20 if (list_empty(&fail_head)) @@ -2339,8 +2348,6 @@ static int pbus_reassign_bridge_resources(struct pci_= bus *bus, struct resource * =20 __pci_bus_size_bridges(bridge->subordinate, &add_list); __pci_bridge_assign_resources(bridge, &add_list, &failed); - if (WARN_ON_ONCE(!list_empty(&add_list))) - pci_dev_res_free_list(&add_list); =20 if (!list_empty(&failed)) { if (pci_required_resource_failed(&failed, type)) @@ -2473,7 +2480,5 @@ void pci_assign_unassigned_bus_resources(struct pci_b= us *bus) __pci_bus_size_bridges(dev->subordinate, &add_list); up_read(&pci_bus_sem); __pci_bus_assign_resources(bus, &add_list, NULL); - if (WARN_ON_ONCE(!list_empty(&add_list))) - pci_dev_res_free_list(&add_list); } EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources); --=20 2.39.5 From nobody Tue Jun 16 19:41:11 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1482399023; 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X-CSE-ConnectionGUID: La2GhVC4R2CxXyvnSpJSZw== X-CSE-MsgGUID: vCXAag7FQe207a+ZGIWTxw== X-IronPort-AV: E=McAfee;i="6800,10657,11770"; a="78101785" X-IronPort-AV: E=Sophos;i="6.23,206,1770624000"; d="scan'208";a="78101785" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 05:27:13 -0700 X-CSE-ConnectionGUID: 5Wxn3kxaSMiU9A0qp47Zcg== X-CSE-MsgGUID: SE6lrUwIRuKuzbGOxcD7Qg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,206,1770624000"; d="scan'208";a="234512137" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.212]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 05:27:09 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Shawn Jin , linuxppc-dev@lists.ozlabs.org, Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 04/11] PCI: Remove const removal cast Date: Wed, 29 Apr 2026 15:26:10 +0300 Message-Id: <20260429122617.7324-5-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260429122617.7324-1-ilpo.jarvinen@linux.intel.com> References: <20260429122617.7324-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable __pci_bridge_assign_resources() inputs const pci_dev *bridge, but then immediately casts const away to pass the bridge to pdev_assign_resources_sorted(). As pdev_assign_resources_sorted() performs assignment of resources, it is not possible to make its input parameter to const. Neither of the __pci_bridge_assign_resources() callers requires the bridge parameter to be const. Thus, simply remove the out of place cast and convert the input parameter to non-const. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-bus.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 1e0e28efe8b8..c0a949f2c995 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1622,14 +1622,13 @@ void pci_bus_claim_resources(struct pci_bus *b) } EXPORT_SYMBOL(pci_bus_claim_resources); =20 -static void __pci_bridge_assign_resources(const struct pci_dev *bridge, +static void __pci_bridge_assign_resources(struct pci_dev *bridge, struct list_head *add_list, struct list_head *fail_head) { struct pci_bus *b; =20 - pdev_assign_resources_sorted((struct pci_dev *)bridge, - add_list, fail_head); + pdev_assign_resources_sorted(bridge, add_list, fail_head); =20 b =3D bridge->subordinate; if (!b) --=20 2.39.5 From nobody Tue Jun 16 19:41:11 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4879399023; Wed, 29 Apr 2026 12:27:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777465645; cv=none; b=VbXAZt42bCKNL4jbTpGiQAkx5914Ho5y9nUuUit78y7OlfjRck1kTQHAsvcXkULk3QU9BIm2wQ35SNkYmc3crJangRXzcarNk4Z/Ie5L5BnrxA7Vn89P9lwiewkZTBcmfRYZ7+3eWQ2rn1woJQJvy9YjbRN5GOQ/SofuNGVBMD8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777465645; c=relaxed/simple; bh=8VXJ5q9tWKaV2T92TCmAxPMeclranQN4ydQ0uXeo4AY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=XMvblRTZVDGMQk1S1qemBxeZJpyCAxmJDvTfxKn4QvDJjSETvxA4yqH5scY9DNKaGxaJ+lGdyA88GblVbIQYR3teJj7IkLzWiim6PAAJ7VUkQ3GIaLgXaoqTuuELUszUOmmFhJNdz8avJQM93ZGTViX9/9h3IWqIakuyNmSRzf4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=gTH/zqHM; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="gTH/zqHM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777465645; x=1809001645; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8VXJ5q9tWKaV2T92TCmAxPMeclranQN4ydQ0uXeo4AY=; b=gTH/zqHM0CQH/QjUuj6zUxRbXUlTnuNcit7QGSSqFzIRCckS5YDsP4Bo l5msHNbEa6gFXzrTAyVPZ7HISwSsldJ4SLCaXR37ZEqKo+J0ujo+bIffX YwoqezD+Artr5I/az89BedvnKhV7Urd7BKy09ncV90F4zqiSbdJmewenq YFruvdJopoxWJ6jpAKn+esQc9TnsK9CAvrAdTWw3sxT2ajs+28KwN2t38 zp0rzU6KC8Id534AbpFgAzJOBPCintj647Irp5TnO8fRMYVKXrXV9PvmU gznt2gH/7cGv+Dd2EGGx8lB1suSGOWyMyG/T1GXeiGfdy1Rq5bXVch7Aq w==; X-CSE-ConnectionGUID: n2hr5JWSQmO+ht37pyTZtA== X-CSE-MsgGUID: kwHYQsGpT3SLBRQ4Yi2UkA== X-IronPort-AV: E=McAfee;i="6800,10657,11770"; a="78101799" X-IronPort-AV: E=Sophos;i="6.23,206,1770624000"; d="scan'208";a="78101799" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 05:27:24 -0700 X-CSE-ConnectionGUID: Jgvu4VG+RDuYkRSRGmchNQ== X-CSE-MsgGUID: ccCDbeE2TSqj2vquDJN+4g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,206,1770624000"; d="scan'208";a="234512170" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.212]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 05:27:20 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Shawn Jin , linuxppc-dev@lists.ozlabs.org, Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 05/11] resource: Make resource_alignment() input const resource Date: Wed, 29 Apr 2026 15:26:11 +0300 Message-Id: <20260429122617.7324-6-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260429122617.7324-1-ilpo.jarvinen@linux.intel.com> References: <20260429122617.7324-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable resource_alignment() does not need to change resource so it can be made const. Signed-off-by: Ilpo J=C3=A4rvinen --- include/linux/ioport.h | 2 +- kernel/resource.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/linux/ioport.h b/include/linux/ioport.h index 3c73c9c0d4f7..f7930b3dfd0a 100644 --- a/include/linux/ioport.h +++ b/include/linux/ioport.h @@ -261,7 +261,7 @@ extern int allocate_resource(struct resource *root, str= uct resource *new, struct resource *lookup_resource(struct resource *root, resource_size_t st= art); int adjust_resource(struct resource *res, resource_size_t start, resource_size_t size); -resource_size_t resource_alignment(struct resource *res); +resource_size_t resource_alignment(const struct resource *res); =20 /** * resource_set_size - Calculate resource end address from size and start diff --git a/kernel/resource.c b/kernel/resource.c index d02a53fb95d8..3d17e3196a3e 100644 --- a/kernel/resource.c +++ b/kernel/resource.c @@ -1238,7 +1238,7 @@ reserve_region_with_split(struct resource *root, reso= urce_size_t start, * * Returns alignment on success, 0 (invalid alignment) on failure. */ -resource_size_t resource_alignment(struct resource *res) +resource_size_t resource_alignment(const struct resource *res) { switch (res->flags & (IORESOURCE_SIZEALIGN | IORESOURCE_STARTALIGN)) { case IORESOURCE_SIZEALIGN: --=20 2.39.5 From nobody Tue Jun 16 19:41:11 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7940E39BFF4; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Convert input pci_dev for pseries_get_iov_fw_value() and pnv_iov_get() to const to be able to convert pcibios_iov_resource_alignment() as well in an upcoming change. Signed-off-by: Ilpo J=C3=A4rvinen --- arch/powerpc/platforms/powernv/pci.h | 2 +- arch/powerpc/platforms/pseries/setup.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/= powernv/pci.h index 42075501663b..032b2081aedb 100644 --- a/arch/powerpc/platforms/powernv/pci.h +++ b/arch/powerpc/platforms/powernv/pci.h @@ -251,7 +251,7 @@ struct pnv_iov_data { struct resource holes[PCI_SRIOV_NUM_BARS]; }; =20 -static inline struct pnv_iov_data *pnv_iov_get(struct pci_dev *pdev) +static inline struct pnv_iov_data *pnv_iov_get(const struct pci_dev *pdev) { return pdev->dev.archdata.iov_data; } diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platform= s/pseries/setup.c index 50b26ed8432d..b670c6fdfcea 100644 --- a/arch/powerpc/platforms/pseries/setup.c +++ b/arch/powerpc/platforms/pseries/setup.c @@ -658,7 +658,8 @@ enum get_iov_fw_value_index { WDW_SIZE =3D 3 /* Get Window Size */ }; =20 -static resource_size_t pseries_get_iov_fw_value(struct pci_dev *dev, int r= esno, +static resource_size_t pseries_get_iov_fw_value(const struct pci_dev *dev, + int resno, enum get_iov_fw_value_index value) { const int *indexes; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable pci_sriov_resource_alignment() inputs struct pci_dev which it should not need to alter to calculate alignment. Make pci_dev pci_sriov_resource_alignment() inputs const. It requires making pci_iov_resource_size() input const as well. Signed-off-by: Ilpo J=C3=A4rvinen --- arch/powerpc/include/asm/machdep.h | 2 +- arch/powerpc/kernel/pci-common.c | 2 +- arch/powerpc/platforms/powernv/pci-sriov.c | 4 ++-- arch/powerpc/platforms/powernv/pci.h | 3 ++- arch/powerpc/platforms/pseries/setup.c | 2 +- drivers/pci/iov.c | 7 ++++--- drivers/pci/pci.h | 5 +++-- include/linux/pci.h | 8 +++++--- 8 files changed, 19 insertions(+), 14 deletions(-) diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/= machdep.h index 3298eec123a3..256f9309bf4f 100644 --- a/arch/powerpc/include/asm/machdep.h +++ b/arch/powerpc/include/asm/machdep.h @@ -169,7 +169,7 @@ struct machdep_calls { =20 #ifdef CONFIG_PCI_IOV void (*pcibios_fixup_sriov)(struct pci_dev *pdev); - resource_size_t (*pcibios_iov_resource_alignment)(struct pci_dev *, int r= esno); + resource_size_t (*pcibios_iov_resource_alignment)(const struct pci_dev *,= int resno); int (*pcibios_sriov_enable)(struct pci_dev *pdev, u16 num_vfs); int (*pcibios_sriov_disable)(struct pci_dev *pdev); #endif /* CONFIG_PCI_IOV */ diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-com= mon.c index 8efe95a0c4ff..3c4ca90e2ab7 100644 --- a/arch/powerpc/kernel/pci-common.c +++ b/arch/powerpc/kernel/pci-common.c @@ -254,7 +254,7 @@ resource_size_t pcibios_default_alignment(void) } =20 #ifdef CONFIG_PCI_IOV -resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int r= esno) +resource_size_t pcibios_iov_resource_alignment(const struct pci_dev *pdev,= int resno) { if (ppc_md.pcibios_iov_resource_alignment) return ppc_md.pcibios_iov_resource_alignment(pdev, resno); diff --git a/arch/powerpc/platforms/powernv/pci-sriov.c b/arch/powerpc/plat= forms/powernv/pci-sriov.c index 7105a573aec4..8652078801f2 100644 --- a/arch/powerpc/platforms/powernv/pci-sriov.c +++ b/arch/powerpc/platforms/powernv/pci-sriov.c @@ -244,8 +244,8 @@ void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev) } } =20 -resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, - int resno) +resource_size_t pnv_pci_iov_resource_alignment(const struct pci_dev *pdev, + int resno) { resource_size_t align =3D pci_iov_resource_size(pdev, resno); struct pnv_phb *phb =3D pci_bus_to_pnvhb(pdev->bus); diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/= powernv/pci.h index 032b2081aedb..3ac718d471c2 100644 --- a/arch/powerpc/platforms/powernv/pci.h +++ b/arch/powerpc/platforms/powernv/pci.h @@ -257,7 +257,8 @@ static inline struct pnv_iov_data *pnv_iov_get(const st= ruct pci_dev *pdev) } =20 void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev); -resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, int r= esno); +resource_size_t pnv_pci_iov_resource_alignment(const struct pci_dev *pdev, + int resno); =20 int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); int pnv_pcibios_sriov_disable(struct pci_dev *pdev); diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platform= s/pseries/setup.c index b670c6fdfcea..1223dc961242 100644 --- a/arch/powerpc/platforms/pseries/setup.c +++ b/arch/powerpc/platforms/pseries/setup.c @@ -789,7 +789,7 @@ static void pseries_pci_fixup_iov_resources(struct pci_= dev *pdev) pseries_disable_sriov_resources(pdev); } =20 -static resource_size_t pseries_pci_iov_resource_alignment(struct pci_dev *= pdev, +static resource_size_t pseries_pci_iov_resource_alignment(const struct pci= _dev *pdev, int resno) { const __be32 *reg; diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index 91ac4e37ecb9..c86409835f73 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -150,7 +150,7 @@ static void virtfn_remove_bus(struct pci_bus *physbus, = struct pci_bus *virtbus) pci_remove_bus(virtbus); } =20 -resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) +resource_size_t pci_iov_resource_size(const struct pci_dev *dev, int resno) { if (!dev->is_physfn) return 0; @@ -1084,7 +1084,7 @@ void pci_iov_update_resource(struct pci_dev *dev, int= resno) } } =20 -resource_size_t __weak pcibios_iov_resource_alignment(struct pci_dev *dev, +resource_size_t __weak pcibios_iov_resource_alignment(const struct pci_dev= *dev, int resno) { return pci_iov_resource_size(dev, resno); @@ -1100,7 +1100,8 @@ resource_size_t __weak pcibios_iov_resource_alignment= (struct pci_dev *dev, * the VF BAR size multiplied by the number of VFs. The alignment * is just the VF BAR size. */ -resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resn= o) +resource_size_t pci_sriov_resource_alignment(const struct pci_dev *dev, + int resno) { return pcibios_iov_resource_alignment(dev, resno); } diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 4fcf5a25ad9e..710803be3a79 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -947,7 +947,8 @@ int pci_iov_init(struct pci_dev *dev); void pci_iov_release(struct pci_dev *dev); void pci_iov_remove(struct pci_dev *dev); void pci_iov_update_resource(struct pci_dev *dev, int resno); -resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resn= o); +resource_size_t pci_sriov_resource_alignment(const struct pci_dev *dev, + int resno); void pci_restore_iov_state(struct pci_dev *dev); int pci_iov_bus_range(struct pci_bus *bus); void pci_iov_resource_set_size(struct pci_dev *dev, int resno, int size); @@ -981,7 +982,7 @@ static inline int pci_iov_init(struct pci_dev *dev) static inline void pci_iov_release(struct pci_dev *dev) { } static inline void pci_iov_remove(struct pci_dev *dev) { } static inline void pci_iov_update_resource(struct pci_dev *dev, int resno)= { } -static inline resource_size_t pci_sriov_resource_alignment(struct pci_dev = *dev, +static inline resource_size_t pci_sriov_resource_alignment(const struct pc= i_dev *dev, int resno) { return 0; diff --git a/include/linux/pci.h b/include/linux/pci.h index 2c4454583c11..0ced3bbd08c0 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -2540,7 +2540,7 @@ int pci_vfs_assigned(struct pci_dev *dev); int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); int pci_sriov_get_totalvfs(struct pci_dev *dev); int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); -resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); +resource_size_t pci_iov_resource_size(const struct pci_dev *dev, int resno= ); int pci_iov_vf_bar_set_size(struct pci_dev *dev, int resno, int size); u32 pci_iov_vf_bar_get_sizes(struct pci_dev *dev, int resno, int num_vfs); void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); @@ -2548,7 +2548,8 @@ void pci_vf_drivers_autoprobe(struct pci_dev *dev, bo= ol probe); /* Arch may override these (weak) */ int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); int pcibios_sriov_disable(struct pci_dev *pdev); -resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int re= sno); +resource_size_t pcibios_iov_resource_alignment(const struct pci_dev *dev, + int resno); #else static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) { @@ -2593,7 +2594,8 @@ static inline int pci_sriov_set_totalvfs(struct pci_d= ev *dev, u16 numvfs) static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) { return 0; } #define pci_sriov_configure_simple NULL -static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, i= nt resno) +static inline resource_size_t pci_iov_resource_size(const struct pci_dev *= dev, + int resno) { return 0; } static inline int pci_iov_vf_bar_set_size(struct pci_dev *dev, int resno, = int size) { return -ENODEV; } --=20 2.39.5 From nobody Tue Jun 16 19:41:11 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29B613A7F7E; Wed, 29 Apr 2026 12:28:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable pci_resource_alignment() calculates resource alignment and should not alter its input structs. Make its input parameters const. It requires making also pci_cardbus_resource_alignment() input const. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/pci.h | 8 ++++---- drivers/pci/setup-cardbus.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 710803be3a79..e0fcc33dfef6 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -419,7 +419,7 @@ static inline bool pci_is_cardbus_bridge(struct pci_dev= *dev) return dev->hdr_type =3D=3D PCI_HEADER_TYPE_CARDBUS; } #ifdef CONFIG_CARDBUS -unsigned long pci_cardbus_resource_alignment(struct resource *res); +unsigned long pci_cardbus_resource_alignment(const struct resource *res); int pci_bus_size_cardbus_bridge(struct pci_bus *bus, struct list_head *realloc_head); int pci_cardbus_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *de= v, @@ -428,7 +428,7 @@ int pci_cardbus_scan_bridge_extend(struct pci_bus *bus,= struct pci_dev *dev, int pci_setup_cardbus(char *str); =20 #else -static inline unsigned long pci_cardbus_resource_alignment(struct resource= *res) +static inline unsigned long pci_cardbus_resource_alignment(const struct re= source *res) { return 0; } @@ -1044,8 +1044,8 @@ static inline void pci_suspend_ptm(struct pci_dev *de= v) { } static inline void pci_resume_ptm(struct pci_dev *dev) { } #endif =20 -static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, - struct resource *res) +static inline resource_size_t pci_resource_alignment(const struct pci_dev = *dev, + const struct resource *res) { int resno =3D pci_resource_num(dev, res); =20 diff --git a/drivers/pci/setup-cardbus.c b/drivers/pci/setup-cardbus.c index 1ebd13a1f730..0cba404080ad 100644 --- a/drivers/pci/setup-cardbus.c +++ b/drivers/pci/setup-cardbus.c @@ -22,7 +22,7 @@ static unsigned long pci_cardbus_io_size =3D DEFAULT_CARDBUS_IO_SIZE; static unsigned long pci_cardbus_mem_size =3D DEFAULT_CARDBUS_MEM_SIZE; =20 -unsigned long pci_cardbus_resource_alignment(struct resource *res) +unsigned long pci_cardbus_resource_alignment(const struct resource *res) { if (res->flags & IORESOURCE_IO) return pci_cardbus_io_size; --=20 2.39.5 From nobody Tue Jun 16 19:41:11 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6344F35F180; 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X-CSE-ConnectionGUID: V1fbMe5zQumZVVSOjB4OdQ== X-CSE-MsgGUID: 5WT/aL4hSrWk7fMcPROtDQ== X-IronPort-AV: E=McAfee;i="6800,10657,11770"; a="78101863" X-IronPort-AV: E=Sophos;i="6.23,206,1770624000"; d="scan'208";a="78101863" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 05:28:14 -0700 X-CSE-ConnectionGUID: M7JSCq3WQimiDepsf6U6sQ== X-CSE-MsgGUID: /7sDIPHHQWeOjNW11AQIwA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,206,1770624000"; d="scan'208";a="257573749" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.212]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 05:28:11 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Shawn Jin , linuxppc-dev@lists.ozlabs.org, Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 09/11] PCI: Move pci_resource_alignment() to setup-res.c file Date: Wed, 29 Apr 2026 15:26:15 +0300 Message-Id: <20260429122617.7324-10-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260429122617.7324-1-ilpo.jarvinen@linux.intel.com> References: <20260429122617.7324-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable pci_resource_alignment() is a bit one the complex side to have in a header so put it into setup-res.c. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/pci.h | 13 ++----------- drivers/pci/setup-res.c | 12 ++++++++++++ 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index e0fcc33dfef6..472b6c2f7c4d 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -1044,17 +1044,8 @@ static inline void pci_suspend_ptm(struct pci_dev *d= ev) { } static inline void pci_resume_ptm(struct pci_dev *dev) { } #endif =20 -static inline resource_size_t pci_resource_alignment(const struct pci_dev = *dev, - const struct resource *res) -{ - int resno =3D pci_resource_num(dev, res); - - if (pci_resource_is_iov(resno)) - return pci_sriov_resource_alignment(dev, resno); - if (dev->class >> 8 =3D=3D PCI_CLASS_BRIDGE_CARDBUS) - return pci_cardbus_resource_alignment(res); - return resource_alignment(res); -} +resource_size_t pci_resource_alignment(const struct pci_dev *dev, + const struct resource *res); =20 resource_size_t pci_min_window_alignment(struct pci_bus *bus, unsigned long type); diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index 0d203325562b..18e8775ea848 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -246,6 +246,18 @@ static int pci_revert_fw_address(struct resource *res,= struct pci_dev *dev, return 0; } =20 +resource_size_t pci_resource_alignment(const struct pci_dev *dev, + const struct resource *res) +{ + int resno =3D pci_resource_num(dev, res); + + if (pci_resource_is_iov(resno)) + return pci_sriov_resource_alignment(dev, resno); + if (dev->class >> 8 =3D=3D PCI_CLASS_BRIDGE_CARDBUS) + return pci_cardbus_resource_alignment(res); + return resource_alignment(res); +} + /* * For mem bridge windows, try to relocate tail remainder space to space * before res->start if there's enough free space there. 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Add lower bound to bridge window alignment to help callers out to always have large enough alignment. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-res.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index 18e8775ea848..c15bce20815d 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -19,7 +19,10 @@ #include #include #include +#include #include +#include + #include "pci.h" =20 static void pci_std_update_resource(struct pci_dev *dev, int resno) @@ -250,12 +253,19 @@ resource_size_t pci_resource_alignment(const struct p= ci_dev *dev, const struct resource *res) { int resno =3D pci_resource_num(dev, res); + resource_size_t min_align =3D 0; =20 if (pci_resource_is_iov(resno)) return pci_sriov_resource_alignment(dev, resno); + if (dev->class >> 8 =3D=3D PCI_CLASS_BRIDGE_CARDBUS) return pci_cardbus_resource_alignment(res); - return resource_alignment(res); + + if (pci_resource_is_bridge_win(resno) && + (res->flags & (IORESOURCE_IO|IORESOURCE_MEM))) + min_align =3D pci_min_window_alignment(dev->bus, res->flags); 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X-CSE-ConnectionGUID: zlIUYeOETpKXizbNKS+LYQ== X-CSE-MsgGUID: R/l30yNDSfaBB/5q4eR3qw== X-IronPort-AV: E=McAfee;i="6800,10657,11770"; a="89853556" X-IronPort-AV: E=Sophos;i="6.23,206,1770624000"; d="scan'208";a="89853556" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 05:28:36 -0700 X-CSE-ConnectionGUID: wGp35jvkToyaC0AQ8zhvVw== X-CSE-MsgGUID: vJjmMR20RrCYutR71IFsrQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,206,1770624000"; d="scan'208";a="264639579" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.212]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 05:28:33 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Shawn Jin , linuxppc-dev@lists.ozlabs.org, Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 11/11] PCI: Return valid alignment for assigned resources Date: Wed, 29 Apr 2026 15:26:17 +0300 Message-Id: <20260429122617.7324-12-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260429122617.7324-1-ilpo.jarvinen@linux.intel.com> References: <20260429122617.7324-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable When a resource is assigned, IORESOURCE_STARTALIGN flag is cleared, resulting in pci_resource_alignment() returning 0 in some situations (at least for bridge windows). Add heuristic to pci_resource_alignment() which mimics start and size alignment by taking minimum of those for an assigned resource. It may overestimate alignment when start has large alignment but the exact alignment information is not available and regenerating it by sizing the bridge again is costly. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-res.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index c15bce20815d..03098f159ec9 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -13,6 +13,7 @@ * Resource sorting */ =20 +#include #include #include #include @@ -265,6 +266,18 @@ resource_size_t pci_resource_alignment(const struct pc= i_dev *dev, (res->flags & (IORESOURCE_IO|IORESOURCE_MEM))) min_align =3D pci_min_window_alignment(dev->bus, res->flags); =20 + if (resource_assigned(res)) { + resource_size_t start_align =3D 1, size_align; + + size_align =3D roundup_pow_of_two(resource_size(res)); + if (res->start) + start_align <<=3D __ffs(res->start); + else + start_align =3D size_align; + + return max(min(start_align, size_align), min_align); + } + return max(resource_alignment(res), min_align); } =20 --=20 2.39.5