From nobody Tue Jun 16 19:36:52 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F58A378D74 for ; Wed, 29 Apr 2026 15:24:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777476286; cv=none; b=lwsJbKIxIggtQlZ+DUPkzEdLn8JtIy9nYdex1D5P/5jXWOl65AhOCrXx1BQZ2vvwmfwU/HEY6tUKa42N87JtCvRtnG6t/nSun0vtAOEudD8g3ODUhS4DhYIOXtvaJombCubBdOkiITd5vjUDv/X2oGSIewX18ib1tbvXmH5RnIY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777476286; c=relaxed/simple; bh=M98SHhJnejP9q8zgsyyblC/G92OTfC4PpM0GHqsfiYY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=imY1QqzrhqTUl9NZBmtb407AUDnEqqhrHWfmCu6EUGRjJKNoSXmHBgw2b8cvRW+ypReQz1YknNy7XxGIbL+uaqy8lUnxG4Y+UFtofmn3pGlR6uhckY/eICjyb/g477/HwvFAn2k2i7Bi3AX0duP0FgDJITAS9gnvm0tlWyi8zZM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=eTtvo04z; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=AX5Nj/ID; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="eTtvo04z"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="AX5Nj/ID" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 63T8ppXR3752420 for ; Wed, 29 Apr 2026 15:24:43 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= JYXgnsmjvXmWmarkuX5XpN6kOos9p6cT1Y93fzH2iuc=; b=eTtvo04ze8gc5G2Z 3BZVZeCYV54wO75aZU1ub5Vtl2Wb4ThtXFVrAGGvaMmUrrr8OeQexaak2d7Tlfsc Xk4sg80VJSeVYZJJv72B7zxrE+5GCsZX3JqV4vGxHSwPCIcqZRtdC43lP6RjljX5 uicmWuzuzA+96nfynu5THL6d8yC6iVtwrUlV/YiO6Rg9ULR2p8GY4xhzBBm3T5Ha B71ZB7yYKZ+Xb97kjtZpNKuQNzfy1DTPPxDzeiAYfgwQtxUdfeZ8beq0mixnXPcg eJnweYY0EgFWRDF5SB97pkAwJMUb50n08xycH99It4mzJL3CDMFAalet+Nk6aUZ3 X7eq2g== Received: from mail-pj1-f72.google.com (mail-pj1-f72.google.com [209.85.216.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4duch1j63f-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 29 Apr 2026 15:24:42 +0000 (GMT) Received: by mail-pj1-f72.google.com with SMTP id 98e67ed59e1d1-35641c14663so14920396a91.2 for ; Wed, 29 Apr 2026 08:24:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1777476282; x=1778081082; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=JYXgnsmjvXmWmarkuX5XpN6kOos9p6cT1Y93fzH2iuc=; b=AX5Nj/ID3/LLU57DNR25eL5HBXVPmS+SMLqbYfC7XHJT5+zRnTfn7pj+Pk2s+lZJKF FSHIl/+WVQ5NhTdI99Fa+ugPuZB4C9MjsqaJGIlCwZorwg2eRGjJjQC56wT9pwqlp2P/ rawqkg/yAJTwoYjrTL5qutFK0Ur6QAaR2XJv0izVw455CMwayKiOJuZgayXH1vOKs+4j CWr4ZPMvYmCbzd0fJ+bOboDHApRw2wqvWr/v3HXZIeNYLiXCo+asMPYfq4HM8PHP0gFz SgrgDjq5LMWwyZHC4y8I8SxxjVBTWIk4sPJY8khhhP/+lvB1rox6e8b9tJIk5ag7IPqU +2Xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777476282; x=1778081082; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=JYXgnsmjvXmWmarkuX5XpN6kOos9p6cT1Y93fzH2iuc=; b=EFuZiYeJoeDXfFBG9Fs7cQQtwXqnRU86oyUf3H5ofb+lhYlp7nFcfGV1F7gBXE71hr Gyc2wa5AV0iPjr/hNm4GZ6vgSXREGEsSesbJNdu38LyDWOMJEFEX5CR5zLk5p2+pTj02 b9hrimnHNVvddPDKayIgE6Uk8NBnnl8QPDiVeZ8JgGw5byAYU3F5Vt+2dd+1vGMi06JA eDw12xSg5KqLzQL81z4Q05fWXrw5AhfJ74SfwyzPV5TD+hhsJp86fAmO3rjFHYTe+9zU BkhosIRMqBHBIpF4imnQze2A+5cLGpP76E+b0AZFEsd6NmhF2qW2atW77gkdkqzG2Weo D+eg== X-Forwarded-Encrypted: i=1; AFNElJ/5fzGq89ChULTvUWTBxRqSOirlHP+mWXaoKe1DWZGrxTElv4xInmUQHRjp3WcTU7PjyXc6JMFE0LgC5sc=@vger.kernel.org X-Gm-Message-State: AOJu0Yxt6yxfd8E6sYWV6BHKfW+leNw6znTKMRXDTc8m9dtnzyE/Rrlc sUT3hle7XJgQcWHIUzGGRSJlYGXydfTJTFwisXXU6sIIiOqtQ0oOwlK2Q1Z7VzVITx1XAF2YBFl btOsJsSl7Ps+tniu0ntnwv5JiF6xy0z0AaQF8k3zdDVY3sBs1OiZ2VNp2wSH3bOdQeEs= X-Gm-Gg: AeBDiet4O/KYAn6e4WnZBIfM7oa5C+4T3WxnZox12wlHsKtDcFnocgo7lUuYxMlcUYj v/RiBGYTj0EKyuTkAPsEhFjuIZtgJKrTGiWK4p4yJ580+NT/EpH6aYsSh1Y6MUph2GfdTlAZBk5 4G4FWQvevqq98IF9VZW/0Mi0BMKiSPcZqgq/3KlR+c18PmFmkONFjafH7f3GEwZesABEUu1YmlN LbmGx1rVT3nyClYJG8Cd0XICXO72TzBqn4yHKTw+hgi+O2ZAk+UkS287ODsAasG9nAFVByB9lI4 51+HRUkX7VyrBHUB+3gI9CJZhUflQ11HRnHevHIGx1WS1R9OkRlKyh+EPVcnPbXZzu8z4NHHafH b48mospQlSCgU7RmrSIUpkIZtDjggr5YTI+3OgISl9Ev+1rcciHsP5TM4T+oPwZeh1aM1BA8NMd qVdGhQQfcQdQ+YfwmiyIq1FpO1URSppj1b9yFhS+Ql91x0CFgf4hJEtvSY6KVb65i+T2Q= X-Received: by 2002:a17:90b:5808:b0:35b:e5ce:73bb with SMTP id 98e67ed59e1d1-36491fbf11dmr8422628a91.1.1777476281738; Wed, 29 Apr 2026 08:24:41 -0700 (PDT) X-Received: by 2002:a17:90b:5808:b0:35b:e5ce:73bb with SMTP id 98e67ed59e1d1-36491fbf11dmr8422604a91.1.1777476281136; Wed, 29 Apr 2026 08:24:41 -0700 (PDT) Received: from hu-kathirav-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-364bd588ad5sm66732a91.3.2026.04.29.08.24.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Apr 2026 08:24:39 -0700 (PDT) From: Kathiravan Thirumoorthy Date: Wed, 29 Apr 2026 20:54:22 +0530 Subject: [PATCH v2 1/4] dt-bindings: clock: add Qualcomm IPQ9650 GCC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260429-ipq9650_boot_to_shell-v2-1-9b0dc3d1f3a8@oss.qualcomm.com> References: <20260429-ipq9650_boot_to_shell-v2-0-9b0dc3d1f3a8@oss.qualcomm.com> In-Reply-To: <20260429-ipq9650_boot_to_shell-v2-0-9b0dc3d1f3a8@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kathiravan Thirumoorthy , Krzysztof Kozlowski X-Mailer: b4 0.15.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1777476269; l=19689; i=kathiravan.thirumoorthy@oss.qualcomm.com; s=20230906; h=from:subject:message-id; bh=M98SHhJnejP9q8zgsyyblC/G92OTfC4PpM0GHqsfiYY=; b=90UPQO2vKyz2TNehoCQoQeNfnFceQE0c/CDnDOWZhybBqklM3+Xu3FQKl6unUBuZJhcrAcxhD cNtVQbKty0QD1i0aaTezWzpo0+5qaI2TjUlSLQDf8dj7JYkpuOSG24A X-Developer-Key: i=kathiravan.thirumoorthy@oss.qualcomm.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Authority-Analysis: v=2.4 cv=arGCzyZV c=1 sm=1 tr=0 ts=69f222ba cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=WFUcH46kpRkaEDnmzbAA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI5MDE1NSBTYWx0ZWRfXzHSOLWNIXa/g L0QPrO9t1ygwSPznMisdJWmxC6eQVkX/0O8VozBX8fOSRWLTFtLmIuasnu8m5Gu8aa9RPhgV5rK jmn7Bvycp2HoDML0p11XoQfivlYeXNaPvFXA6Iha1rqjwu35Xr+cf+w0cOR8gnaALV7vaYV8T5L n2KG0Pfe+R0MRAgwgLM5/jZdOol2LjbewIoKPLC5I288o8Qej3Xo7h6gbgmXN8ynnGugvlM/czB 6UtCVcSg+6Q4jEmB6tNflX4YFe1J/DNzB4c3o4cJZeFA86ncP6e8mPzlQPPRdDaI4W+e3RfBZln palC2jXKYAHVTcVHsx+s47AUr23uLIPRdgFIQSP/H6bx9Zvb+R0IAxP0PtRO1NoemuLkAQDUs8y dCy08fj4TZyalRukbci9SN50nINIjn6PBrcvmt2Et6vGxoe2+uGKvlZjFCmQP8ZP2SbboQG5fkj N2WaWRX1w1lKMYUqRHg== X-Proofpoint-GUID: 0TfMBA7ZevZFZbDHwW08u0Y05BOjAeRB X-Proofpoint-ORIG-GUID: 0TfMBA7ZevZFZbDHwW08u0Y05BOjAeRB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-29_01,2026-04-28_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 clxscore=1015 adultscore=0 impostorscore=0 spamscore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604290155 Add binding for the Qualcomm IPQ9650 Global Clock Controller. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kathiravan Thirumoorthy --- .../bindings/clock/qcom,ipq9650-gcc.yaml | 68 ++++++ include/dt-bindings/clock/qcom,ipq9650-gcc.h | 190 +++++++++++++++++ include/dt-bindings/reset/qcom,ipq9650-gcc.h | 228 +++++++++++++++++= ++++ 3 files changed, 486 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9650-gcc.yaml = b/Documentation/devicetree/bindings/clock/qcom,ipq9650-gcc.yaml new file mode 100644 index 000000000000..f33105217a06 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9650-gcc.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq9650-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on IPQ9650 + +maintainers: + - Bjorn Andersson + - Kathiravan Thirumoorthy + +description: | + Qualcomm global clock control module provides the clocks, resets and pow= er + domains on IPQ9650 + + See also: + include/dt-bindings/clock/qcom,ipq9650-gcc.h + include/dt-bindings/reset/qcom,ipq9650-gcc.h + +properties: + compatible: + const: qcom,ipq9650-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE30 PHY0 pipe clock source + - description: PCIE30 PHY1 pipe clock source + - description: PCIE30 PHY2 pipe clock source + - description: PCIE30 PHY3 pipe clock source + - description: PCIE30 PHY4 pipe clock source + - description: USB PCIE wrapper pipe clock source + - description: NSS common clock source + + '#power-domain-cells': false + + '#interconnect-cells': + const: 1 + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + clock-controller@1800000 { + compatible =3D "qcom,ipq9650-gcc"; + reg =3D <0x01800000 0x40000>; + clocks =3D <&xo_board_clk>, + <&sleep_clk>, + <&pcie30_phy0_pipe_clk>, + <&pcie30_phy1_pipe_clk>, + <&pcie30_phy2_pipe_clk>, + <&pcie30_phy3_pipe_clk>, + <&pcie30_phy4_pipe_clk>, + <&usb3phy_0_cc_pipe_clk>, + <&nss_cmn_clk>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,ipq9650-gcc.h b/include/dt-bind= ings/clock/qcom,ipq9650-gcc.h new file mode 100644 index 000000000000..600240227c3d --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq9650-gcc.h @@ -0,0 +1,190 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ9650_H +#define _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ9650_H + +#define GCC_ADSS_PWM_CLK 0 +#define GCC_ADSS_PWM_CLK_SRC 1 +#define GCC_ANOC_PCIE0_1LANE_M_CLK 2 +#define GCC_ANOC_PCIE0_1LANE_S_CLK 3 +#define GCC_ANOC_PCIE1_2LANE_M_CLK 4 +#define GCC_ANOC_PCIE1_2LANE_S_CLK 5 +#define GCC_ANOC_PCIE2_2LANE_M_CLK 6 +#define GCC_ANOC_PCIE2_2LANE_S_CLK 7 +#define GCC_ANOC_PCIE3_2LANE_M_CLK 8 +#define GCC_ANOC_PCIE3_2LANE_S_CLK 9 +#define GCC_ANOC_PCIE4_1LANE_M_CLK 10 +#define GCC_ANOC_PCIE4_1LANE_S_CLK 11 +#define GCC_CMN_12GPLL_AHB_CLK 12 +#define GCC_CMN_12GPLL_APU_CLK 13 +#define GCC_CMN_12GPLL_SYS_CLK 14 +#define GCC_CMN_LDO_CLK 15 +#define GCC_MDIO_AHB_CLK 16 +#define GCC_NSSCC_CLK 17 +#define GCC_NSSCFG_CLK 18 +#define GCC_NSSNOC_ATB_CLK 19 +#define GCC_NSSNOC_MEMNOC_1_CLK 20 +#define GCC_NSSNOC_MEMNOC_BFDCD_CLK_SRC 21 +#define GCC_NSSNOC_MEMNOC_CLK 22 +#define GCC_NSSNOC_MEMNOC_DIV_CLK_SRC 23 +#define GCC_NSSNOC_NSSCC_CLK 24 +#define GCC_NSSNOC_PCNOC_1_CLK 25 +#define GCC_NSSNOC_QOSGEN_REF_CLK 26 +#define GCC_NSSNOC_SNOC_1_CLK 27 +#define GCC_NSSNOC_SNOC_CLK 28 +#define GCC_NSSNOC_TIMEOUT_REF_CLK 29 +#define GCC_NSSNOC_XO_DCD_CLK 30 +#define GCC_NSS_TS_CLK 31 +#define GCC_NSS_TS_CLK_SRC 32 +#define GCC_PCIE0_AHB_CLK 33 +#define GCC_PCIE0_AUX_CLK 34 +#define GCC_PCIE0_AXI_M_CLK 35 +#define GCC_PCIE0_AXI_M_CLK_SRC 36 +#define GCC_PCIE0_AXI_S_BRIDGE_CLK 37 +#define GCC_PCIE0_AXI_S_CLK 38 +#define GCC_PCIE0_AXI_S_CLK_SRC 39 +#define GCC_PCIE0_PIPE_CLK 40 +#define GCC_PCIE0_PIPE_CLK_SRC 41 +#define GCC_PCIE0_RCHNG_CLK 42 +#define GCC_PCIE0_RCHNG_CLK_SRC 43 +#define GCC_PCIE1_AHB_CLK 44 +#define GCC_PCIE1_AUX_CLK 45 +#define GCC_PCIE1_AXI_M_CLK 46 +#define GCC_PCIE1_AXI_M_CLK_SRC 47 +#define GCC_PCIE1_AXI_S_BRIDGE_CLK 48 +#define GCC_PCIE1_AXI_S_CLK 49 +#define GCC_PCIE1_AXI_S_CLK_SRC 50 +#define GCC_PCIE1_PIPE_CLK 51 +#define GCC_PCIE1_PIPE_CLK_SRC 52 +#define GCC_PCIE1_RCHNG_CLK 53 +#define GCC_PCIE1_RCHNG_CLK_SRC 54 +#define GCC_PCIE2_AHB_CLK 55 +#define GCC_PCIE2_AUX_CLK 56 +#define GCC_PCIE2_AXI_M_CLK 57 +#define GCC_PCIE2_AXI_M_CLK_SRC 58 +#define GCC_PCIE2_AXI_S_BRIDGE_CLK 59 +#define GCC_PCIE2_AXI_S_CLK 60 +#define GCC_PCIE2_AXI_S_CLK_SRC 61 +#define GCC_PCIE2_PIPE_CLK 62 +#define GCC_PCIE2_PIPE_CLK_SRC 63 +#define GCC_PCIE2_RCHNG_CLK 64 +#define GCC_PCIE2_RCHNG_CLK_SRC 65 +#define GCC_PCIE3_AHB_CLK 66 +#define GCC_PCIE3_AUX_CLK 67 +#define GCC_PCIE3_AXI_M_CLK 68 +#define GCC_PCIE3_AXI_M_CLK_SRC 69 +#define GCC_PCIE3_AXI_S_BRIDGE_CLK 70 +#define GCC_PCIE3_AXI_S_CLK 71 +#define GCC_PCIE3_AXI_S_CLK_SRC 72 +#define GCC_PCIE3_PIPE_CLK 73 +#define GCC_PCIE3_PIPE_CLK_SRC 74 +#define GCC_PCIE3_RCHNG_CLK 75 +#define GCC_PCIE3_RCHNG_CLK_SRC 76 +#define GCC_PCIE4_AHB_CLK 77 +#define GCC_PCIE4_AUX_CLK 78 +#define GCC_PCIE4_AXI_M_CLK 79 +#define GCC_PCIE4_AXI_M_CLK_SRC 80 +#define GCC_PCIE4_AXI_S_BRIDGE_CLK 81 +#define GCC_PCIE4_AXI_S_CLK 82 +#define GCC_PCIE4_AXI_S_CLK_SRC 83 +#define GCC_PCIE4_PIPE_CLK 84 +#define GCC_PCIE4_PIPE_CLK_SRC 85 +#define GCC_PCIE4_RCHNG_CLK 86 +#define GCC_PCIE4_RCHNG_CLK_SRC 87 +#define GCC_PCIE_AUX_CLK_SRC 88 +#define GCC_PCIE_CMN_HCLK 89 +#define GCC_PCIE_CMN_LDO_CLK 90 +#define GCC_PCNOC_BFDCD_CLK_SRC 91 +#define GCC_PRIMESS_AHBM_CLK 92 +#define GCC_PRIMESS_AHBM_CLK_SRC 93 +#define GCC_PRIMESS_AHBM_PARTIAL_CLK 94 +#define GCC_PRIMESS_AHBS_CLK 95 +#define GCC_PRIMESS_ATB_CLK 96 +#define GCC_PRIMESS_AXIM_CLK 97 +#define GCC_PRIMESS_AXIM_CLK_SRC 98 +#define GCC_PRIMESS_AXIM_PARTIAL_CLK 99 +#define GCC_PRIMESS_CLK 100 +#define GCC_PRIMESS_CLK_SRC 101 +#define GCC_PRIMESS_XO_CLK 102 +#define GCC_QDSS_AT_CLK 103 +#define GCC_QDSS_AT_CLK_SRC 104 +#define GCC_QDSS_DAP_CLK 105 +#define GCC_QDSS_TSCTR_CLK_SRC 106 +#define GCC_QPIC_AHB_CLK 107 +#define GCC_QPIC_CLK 108 +#define GCC_QPIC_CLK_SRC 109 +#define GCC_QPIC_IO_MACRO_CLK 110 +#define GCC_QPIC_IO_MACRO_CLK_SRC 111 +#define GCC_QPIC_SLEEP_CLK 112 +#define GCC_QUPV3_2X_CORE_CLK 113 +#define GCC_QUPV3_2X_CORE_CLK_SRC 114 +#define GCC_QUPV3_AHB_MST_CLK 115 +#define GCC_QUPV3_AHB_SLV_CLK 116 +#define GCC_QUPV3_CORE_CLK 117 +#define GCC_QUPV3_SLEEP_CLK 118 +#define GCC_QUPV3_WRAP_SE0_CLK 119 +#define GCC_QUPV3_WRAP_SE0_CLK_SRC 120 +#define GCC_QUPV3_WRAP_SE1_CLK 121 +#define GCC_QUPV3_WRAP_SE1_CLK_SRC 122 +#define GCC_QUPV3_WRAP_SE2_CLK 123 +#define GCC_QUPV3_WRAP_SE2_CLK_SRC 124 +#define GCC_QUPV3_WRAP_SE3_CLK 125 +#define GCC_QUPV3_WRAP_SE3_CLK_SRC 126 +#define GCC_QUPV3_WRAP_SE4_CLK 127 +#define GCC_QUPV3_WRAP_SE4_CLK_SRC 128 +#define GCC_QUPV3_WRAP_SE5_CLK 129 +#define GCC_QUPV3_WRAP_SE5_CLK_SRC 130 +#define GCC_QUPV3_WRAP_SE6_CLK 131 +#define GCC_QUPV3_WRAP_SE6_CLK_SRC 132 +#define GCC_QUPV3_WRAP_SE7_CLK 133 +#define GCC_QUPV3_WRAP_SE7_CLK_SRC 134 +#define GCC_REFGEN_CORE_CLK_SRC 135 +#define GCC_REFGEN_PCIE_CORE_CLK 136 +#define GCC_REFGEN_PCIE_HCLK 137 +#define GCC_SDCC1_AHB_CLK 138 +#define GCC_SDCC1_APPS_CLK 139 +#define GCC_SDCC1_APPS_CLK_SRC 140 +#define GCC_SDCC1_ICE_CORE_CLK 141 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 142 +#define GCC_SLEEP_CLK_SRC 143 +#define GCC_SNOC_USB_CLK 144 +#define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 145 +#define GCC_TLMM_AHB_CLK 146 +#define GCC_TLMM_CLK 147 +#define GCC_UNIPHY0_AHB_CLK 148 +#define GCC_UNIPHY0_SYS_CLK 149 +#define GCC_UNIPHY1_AHB_CLK 150 +#define GCC_UNIPHY1_SYS_CLK 151 +#define GCC_UNIPHY2_AHB_CLK 152 +#define GCC_UNIPHY2_SYS_CLK 153 +#define GCC_UNIPHY_SYS_CLK_SRC 154 +#define GCC_USB0_AUX_CLK 155 +#define GCC_USB0_AUX_CLK_SRC 156 +#define GCC_USB0_EUD_AT_CLK 157 +#define GCC_USB0_MASTER_CLK 158 +#define GCC_USB0_MASTER_CLK_SRC 159 +#define GCC_USB0_MOCK_UTMI_CLK 160 +#define GCC_USB0_MOCK_UTMI_CLK_SRC 161 +#define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 162 +#define GCC_USB0_PHY_CFG_AHB_CLK 163 +#define GCC_USB0_PIPE_CLK 164 +#define GCC_USB0_PIPE_CLK_SRC 165 +#define GCC_USB0_SLEEP_CLK 166 +#define GCC_USB1_MASTER_CLK 167 +#define GCC_USB1_MOCK_UTMI_CLK 168 +#define GCC_USB1_MOCK_UTMI_CLK_SRC 169 +#define GCC_USB1_MOCK_UTMI_DIV_CLK_SRC 170 +#define GCC_USB1_PHY_CFG_AHB_CLK 171 +#define GCC_USB1_SLEEP_CLK 172 +#define GCC_USB_CMN_HCLK 173 +#define GCC_USB_CMN_LDO_CLK 174 +#define GCC_XO_CLK_SRC 175 +#define GPLL0 176 +#define GPLL0_MAIN 177 +#define GPLL2 178 +#define GPLL2_OUT_MAIN 179 +#define GPLL4 180 +#endif diff --git a/include/dt-bindings/reset/qcom,ipq9650-gcc.h b/include/dt-bind= ings/reset/qcom,ipq9650-gcc.h new file mode 100644 index 000000000000..0b8dd3ff4257 --- /dev/null +++ b/include/dt-bindings/reset/qcom,ipq9650-gcc.h @@ -0,0 +1,228 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_RESET_IPQ_GCC_IPQ9650_H +#define _DT_BINDINGS_RESET_IPQ_GCC_IPQ9650_H + +#define GCC_ADSS_BCR 0 +#define GCC_ADSS_PWM_CLK_ARES 1 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 2 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES 3 +#define GCC_APSS_AHB_CLK_ARES 4 +#define GCC_APSS_ATB_CLK_ARES 5 +#define GCC_APSS_AXI_CLK_ARES 6 +#define GCC_APSS_TS_CLK_ARES 7 +#define GCC_BOOT_ROM_AHB_CLK_ARES 8 +#define GCC_BOOT_ROM_BCR 9 +#define GCC_CMN_12GPLL_AHB_CLK_ARES 10 +#define GCC_CMN_12GPLL_APU_CLK_ARES 11 +#define GCC_CMN_12GPLL_SYS_CLK_ARES 12 +#define GCC_CMN_BLK_BCR 13 +#define GCC_CMN_LDO_CLK_ARES 14 +#define GCC_CPUSS_TRIG_CLK_ARES 15 +#define GCC_GP1_CLK_ARES 16 +#define GCC_GP2_CLK_ARES 17 +#define GCC_GP3_CLK_ARES 18 +#define GCC_MDIO_AHB_CLK_ARES 19 +#define GCC_MDIO_BCR 20 +#define GCC_NSSCC_CLK_ARES 21 +#define GCC_NSSCFG_CLK_ARES 22 +#define GCC_NSSNOC_ATB_CLK_ARES 23 +#define GCC_NSSNOC_MEMNOC_1_CLK_ARES 24 +#define GCC_NSSNOC_MEMNOC_CLK_ARES 25 +#define GCC_NSSNOC_NSSCC_CLK_ARES 26 +#define GCC_NSSNOC_PCNOC_1_CLK_ARES 27 +#define GCC_NSSNOC_QOSGEN_REF_CLK_ARES 28 +#define GCC_NSSNOC_SNOC_1_CLK_ARES 29 +#define GCC_NSSNOC_SNOC_CLK_ARES 30 +#define GCC_NSSNOC_TIMEOUT_REF_CLK_ARES 31 +#define GCC_NSSNOC_XO_DCD_CLK_ARES 32 +#define GCC_NSS_BCR 33 +#define GCC_NSS_TS_CLK_ARES 34 +#define GCC_PCIE0PHY_PHY_BCR 35 +#define GCC_PCIE0_AHB_CLK_ARES 36 +#define GCC_PCIE0_AHB_RESET 37 +#define GCC_PCIE0_AUX_CLK_ARES 38 +#define GCC_PCIE0_AUX_RESET 39 +#define GCC_PCIE0_AXI_M_CLK_ARES 40 +#define GCC_PCIE0_AXI_M_RESET 41 +#define GCC_PCIE0_AXI_M_STICKY_RESET 42 +#define GCC_PCIE0_AXI_S_BRIDGE_CLK_ARES 43 +#define GCC_PCIE0_AXI_S_CLK_ARES 44 +#define GCC_PCIE0_AXI_S_RESET 45 +#define GCC_PCIE0_AXI_S_STICKY_RESET 46 +#define GCC_PCIE0_BCR 47 +#define GCC_PCIE0_CORE_STICKY_RESET 48 +#define GCC_PCIE0_LINK_DOWN_BCR 49 +#define GCC_PCIE0_PHY_BCR 50 +#define GCC_PCIE0_PIPE_CLK_ARES 51 +#define GCC_PCIE0_PIPE_RESET 52 +#define GCC_PCIE1PHY_PHY_BCR 53 +#define GCC_PCIE1_AHB_CLK_ARES 54 +#define GCC_PCIE1_AHB_RESET 55 +#define GCC_PCIE1_AUX_CLK_ARES 56 +#define GCC_PCIE1_AUX_RESET 57 +#define GCC_PCIE1_AXI_M_CLK_ARES 58 +#define GCC_PCIE1_AXI_M_RESET 59 +#define GCC_PCIE1_AXI_M_STICKY_RESET 60 +#define GCC_PCIE1_AXI_S_BRIDGE_CLK_ARES 61 +#define GCC_PCIE1_AXI_S_CLK_ARES 62 +#define GCC_PCIE1_AXI_S_RESET 63 +#define GCC_PCIE1_AXI_S_STICKY_RESET 64 +#define GCC_PCIE1_BCR 65 +#define GCC_PCIE1_CORE_STICKY_RESET 66 +#define GCC_PCIE1_LINK_DOWN_BCR 67 +#define GCC_PCIE1_PHY_BCR 68 +#define GCC_PCIE1_PIPE_CLK_ARES 69 +#define GCC_PCIE1_PIPE_RESET 70 +#define GCC_PCIE2PHY_PHY_BCR 71 +#define GCC_PCIE2_AHB_CLK_ARES 72 +#define GCC_PCIE2_AHB_RESET 73 +#define GCC_PCIE2_AUX_CLK_ARES 74 +#define GCC_PCIE2_AUX_RESET 75 +#define GCC_PCIE2_AXI_M_CLK_ARES 76 +#define GCC_PCIE2_AXI_M_RESET 77 +#define GCC_PCIE2_AXI_M_STICKY_RESET 78 +#define GCC_PCIE2_AXI_S_BRIDGE_CLK_ARES 79 +#define GCC_PCIE2_AXI_S_CLK_ARES 80 +#define GCC_PCIE2_AXI_S_RESET 81 +#define GCC_PCIE2_AXI_S_STICKY_RESET 82 +#define GCC_PCIE2_BCR 83 +#define GCC_PCIE2_CORE_STICKY_RESET 84 +#define GCC_PCIE2_LINK_DOWN_BCR 85 +#define GCC_PCIE2_PHY_BCR 86 +#define GCC_PCIE2_PIPE_CLK_ARES 87 +#define GCC_PCIE2_PIPE_RESET 88 +#define GCC_PCIE3PHY_PHY_BCR 89 +#define GCC_PCIE3_AHB_CLK_ARES 90 +#define GCC_PCIE3_AHB_RESET 91 +#define GCC_PCIE3_AUX_CLK_ARES 92 +#define GCC_PCIE3_AUX_RESET 93 +#define GCC_PCIE3_AXI_M_CLK_ARES 94 +#define GCC_PCIE3_AXI_M_RESET 95 +#define GCC_PCIE3_AXI_M_STICKY_RESET 96 +#define GCC_PCIE3_AXI_S_BRIDGE_CLK_ARES 97 +#define GCC_PCIE3_AXI_S_CLK_ARES 98 +#define GCC_PCIE3_AXI_S_RESET 99 +#define GCC_PCIE3_AXI_S_STICKY_RESET 100 +#define GCC_PCIE3_BCR 101 +#define GCC_PCIE3_CORE_STICKY_RESET 102 +#define GCC_PCIE3_LINK_DOWN_BCR 103 +#define GCC_PCIE3_PHY_BCR 104 +#define GCC_PCIE3_PIPE_CLK_ARES 105 +#define GCC_PCIE3_PIPE_RESET 106 +#define GCC_PCIE4PHY_PHY_BCR 107 +#define GCC_PCIE4_AHB_CLK_ARES 108 +#define GCC_PCIE4_AHB_RESET 109 +#define GCC_PCIE4_AUX_CLK_ARES 110 +#define GCC_PCIE4_AUX_RESET 111 +#define GCC_PCIE4_AXI_M_CLK_ARES 112 +#define GCC_PCIE4_AXI_M_RESET 113 +#define GCC_PCIE4_AXI_M_STICKY_RESET 114 +#define GCC_PCIE4_AXI_S_BRIDGE_CLK_ARES 115 +#define GCC_PCIE4_AXI_S_CLK_ARES 116 +#define GCC_PCIE4_AXI_S_RESET 117 +#define GCC_PCIE4_AXI_S_STICKY_RESET 118 +#define GCC_PCIE4_BCR 119 +#define GCC_PCIE4_CORE_STICKY_RESET 120 +#define GCC_PCIE4_LINK_DOWN_BCR 121 +#define GCC_PCIE4_PHY_BCR 122 +#define GCC_PCIE4_PIPE_CLK_ARES 123 +#define GCC_PCIE4_PIPE_RESET 124 +#define GCC_PCIE_CMN_LDO_BCR 125 +#define GCC_PRIMESS_AHBM_CLK_ARES 126 +#define GCC_PRIMESS_AHBM_PARTIAL_CLK_ARES 127 +#define GCC_PRIMESS_AHBS_CLK_ARES 128 +#define GCC_PRIMESS_ATB_CLK_ARES 129 +#define GCC_PRIMESS_AXIM_CLK_ARES 130 +#define GCC_PRIMESS_AXIM_PARTIAL_CLK_ARES 131 +#define GCC_PRIMESS_CLK_ARES 132 +#define GCC_PRIMESS_XO_CLK_ARES 133 +#define GCC_PRIME_SS_BCR 134 +#define GCC_QDSS_APB2JTAG_CLK_ARES 135 +#define GCC_QDSS_AT_CLK_ARES 136 +#define GCC_QDSS_BCR 137 +#define GCC_QDSS_CFG_AHB_CLK_ARES 138 +#define GCC_QDSS_DAP_AHB_CLK_ARES 139 +#define GCC_QDSS_DAP_CLK_ARES 140 +#define GCC_QDSS_ETR_USB_CLK_ARES 141 +#define GCC_QDSS_EUD_AT_CLK_ARES 142 +#define GCC_QDSS_STM_CLK_ARES 143 +#define GCC_QDSS_TRACECLKIN_CLK_ARES 144 +#define GCC_QDSS_TSCTR_DIV16_CLK_ARES 145 +#define GCC_QDSS_TSCTR_DIV2_CLK_ARES 146 +#define GCC_QDSS_TSCTR_DIV3_CLK_ARES 147 +#define GCC_QDSS_TSCTR_DIV4_CLK_ARES 148 +#define GCC_QDSS_TSCTR_DIV8_CLK_ARES 149 +#define GCC_QDSS_TS_CLK_ARES 150 +#define GCC_QPIC_AHB_CLK_ARES 151 +#define GCC_QPIC_BCR 152 +#define GCC_QPIC_CLK_ARES 153 +#define GCC_QPIC_IO_MACRO_CLK_ARES 154 +#define GCC_QPIC_SLEEP_CLK_ARES 155 +#define GCC_QUPV3_2X_CORE_CLK_ARES 156 +#define GCC_QUPV3_AHB_MST_CLK_ARES 157 +#define GCC_QUPV3_AHB_SLV_CLK_ARES 158 +#define GCC_QUPV3_BCR 159 +#define GCC_QUPV3_CORE_CLK_ARES 160 +#define GCC_QUPV3_WRAP_SE0_BCR 161 +#define GCC_QUPV3_WRAP_SE0_CLK_ARES 162 +#define GCC_QUPV3_WRAP_SE1_BCR 163 +#define GCC_QUPV3_WRAP_SE1_CLK_ARES 164 +#define GCC_QUPV3_WRAP_SE2_BCR 165 +#define GCC_QUPV3_WRAP_SE2_CLK_ARES 166 +#define GCC_QUPV3_WRAP_SE3_BCR 167 +#define GCC_QUPV3_WRAP_SE3_CLK_ARES 168 +#define GCC_QUPV3_WRAP_SE4_BCR 169 +#define GCC_QUPV3_WRAP_SE4_CLK_ARES 170 +#define GCC_QUPV3_WRAP_SE5_BCR 171 +#define GCC_QUPV3_WRAP_SE5_CLK_ARES 172 +#define GCC_QUPV3_WRAP_SE6_BCR 173 +#define GCC_QUPV3_WRAP_SE6_CLK_ARES 174 +#define GCC_QUPV3_WRAP_SE7_BCR 175 +#define GCC_QUPV3_WRAP_SE7_CLK_ARES 176 +#define GCC_QUSB2_0_PHY_BCR 177 +#define GCC_QUSB2_1_PHY_BCR 178 +#define GCC_REFGEN_PCIE_BCR 179 +#define GCC_REFGEN_PCIE_CORE_CLK_ARES 180 +#define GCC_SDCC1_APPS_CLK_ARES 181 +#define GCC_SDCC1_ICE_CORE_CLK_ARES 182 +#define GCC_SDCC_BCR 183 +#define GCC_TLMM_AHB_CLK_ARES 184 +#define GCC_TLMM_BCR 185 +#define GCC_TLMM_CLK_ARES 186 +#define GCC_UNIPHY0_AHB_CLK_ARES 187 +#define GCC_UNIPHY0_BCR 188 +#define GCC_UNIPHY0_PMA_BCR 189 +#define GCC_UNIPHY0_SYS_CLK_ARES 190 +#define GCC_UNIPHY0_XPCS_ARES 191 +#define GCC_UNIPHY1_AHB_CLK_ARES 192 +#define GCC_UNIPHY1_BCR 193 +#define GCC_UNIPHY1_PMA_BCR 194 +#define GCC_UNIPHY1_SYS_CLK_ARES 195 +#define GCC_UNIPHY1_XPCS_ARES 196 +#define GCC_UNIPHY2_AHB_CLK_ARES 197 +#define GCC_UNIPHY2_BCR 198 +#define GCC_UNIPHY2_PMA_BCR 199 +#define GCC_UNIPHY2_SYS_CLK_ARES 200 +#define GCC_UNIPHY2_XPCS_ARES 201 +#define GCC_USB0_AUX_CLK_ARES 202 +#define GCC_USB0_MASTER_CLK_ARES 203 +#define GCC_USB0_MOCK_UTMI_CLK_ARES 204 +#define GCC_USB0_PHY_BCR 205 +#define GCC_USB0_PHY_CFG_AHB_CLK_ARES 206 +#define GCC_USB0_PIPE_CLK_ARES 207 +#define GCC_USB0_SLEEP_CLK_ARES 208 +#define GCC_USB1_BCR 209 +#define GCC_USB1_MASTER_CLK_ARES 210 +#define GCC_USB1_MOCK_UTMI_CLK_ARES 211 +#define GCC_USB1_PHY_CFG_AHB_CLK_ARES 212 +#define GCC_USB1_SLEEP_CLK_ARES 213 +#define GCC_USB3PHY_0_PHY_BCR 214 +#define GCC_USB_BCR 215 +#define GCC_USB_CMN_LDO_BCR 216 +#define GCC_UNIPHY1_XLGPCS_ARES 217 +#define GCC_UNIPHY2_XLGPCS_ARES 218 +#endif --=20 2.34.1 From nobody Tue Jun 16 19:36:52 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38730378D9F for ; Wed, 29 Apr 2026 15:24:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777476299; cv=none; b=lUSSpIOuDVimLHqED4oWI0eKgRwkmxAFKYfFuiwi1JK06J5hNYsy6RobfINtJHLddq79TuKwupFDZViL51+o09v1VTRZn5ihRneF0Tou3WE9NQvFllgnIl0wJsNr4rEyfMpgjwVGJiON28r+WZajcw1ybUXUyLKJR6k4AhkEnnc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777476299; c=relaxed/simple; bh=gtgTu5ziE8FDBBdJ7EDFaeZn7v7jrwNOh2sFPwsIRns=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=naMEXCN90yIrSLP55ivh5s6Y8neW8NNqxKR5SGnlAQtGpy0zRb2ztQPOB2BwyvrNIfEhV5hD9c58Axlmi6fFsGxMJ/n2q73gc1F2hVPGXtGAaox+9motOX7i/C2+paH8nykgPWWrAH/vh2u2Kk2aqlmxHLD3VDSuEu/V+EtVa2A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Czus03ve; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=Lci6dL7C; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Czus03ve"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="Lci6dL7C" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 63T8pmbK901591 for ; Wed, 29 Apr 2026 15:24:52 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= y6gtzRlAp/p97zpz1XghpXG1cnPHzhGrrV/Db+11b6k=; b=Czus03ver1z83CRs LMc5WJwbqpYEAGtO09iNbR3lh+3I+PGvBSbn89MgRoOfi4yCnlM79kvBgp/KXhH+ uCZN8qtzLUTqINR4zkmOtdNQflIbThzvZHguR6VRbhwCbmXivPqWpzd9RS6/RHl6 +GoBS3qcprz16RyOosNRPWz2ky21yb6WvN8ZtFJKzwPz765toxmsQ3fZLe/7hAaV 05Ilcbp4FqMARWRxNF1wMQxyh/PX6CSdQyIe/33onZpCGltTRtiSmhy8dFZs/A81 yE1wUKfyWyRGm/x3Ryq7mSsV1tQQi1iB0SdzYbN30topgzGoktn+ckisy9ik6R4S QMGprQ== Received: from mail-pj1-f69.google.com (mail-pj1-f69.google.com [209.85.216.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dubq9jatt-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 29 Apr 2026 15:24:52 +0000 (GMT) Received: by mail-pj1-f69.google.com with SMTP id 98e67ed59e1d1-35da1c703d1so15035861a91.1 for ; Wed, 29 Apr 2026 08:24:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1777476291; x=1778081091; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=y6gtzRlAp/p97zpz1XghpXG1cnPHzhGrrV/Db+11b6k=; b=Lci6dL7C85SrnlDdeoRSV2Jg5iuP5t6RWeWFhDltbeSnYTWps0c3Xe1juhNL8+gops pEt6Yi48gpKY/Lr7NJQuQcK1wp2yvXtfiZrH2grl+xnxTjFqJDznYV532oMOVAsPYq+7 T6t1XW39nprRre0OGNaaMbPujFotfsUFDQPVnmzTEk5C/4K1SCU5zcqBBStrYvkbuyI1 XP3HGgRw9+3uIZ2frCHEKz1i88VPKUNPIzXo3g9CWZiT9PkI9KKmOLZM4mm+WD8YC4+K fI1ighHb3v7co7GCzfwsUA5OMEtdfij8GRBm2qNKjoo3f6HQEIcsDEHwhZL+3rZb1TZ5 +67A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777476291; x=1778081091; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=y6gtzRlAp/p97zpz1XghpXG1cnPHzhGrrV/Db+11b6k=; b=IOTvJwtXhLPEPR7qWXCEPmd22mbIzS3w6PKBG5DfdleYv0YjNK9VZ/jaDej7eiaSLD 2kQ2/JW6NPBI2C3ZgnZrfsAova0CR3k4MRw4p9y4DubOHMJI8/eLO6DQLrZ9H4Eo4JSz kIAhNY2dMcBtirBDQjyvJSdFZg2st+dvxgzvn9ngzORHFaaFfQSTfhXcpjdzVIFCKXNq Atd3ldhlUdyeOplVQQMXtssjlFkdwh8thj+3T2txA6iAW+MV9Psf/imnmvQhHbAjEVgp s8+Ih0YAwaiZQmlD2V7JGRU3RR03bWveDVezJRxXDFUm1WaDY+BSh3eD4rJ787PgsegH gbRQ== X-Forwarded-Encrypted: i=1; AFNElJ+4qGxUdbwkcytYaxTG/b3aV84bmwqEUjaxiJAt5pP2iBUZJejdWTWu+VCFtDgpt2TnktzylB8nHEqhvKw=@vger.kernel.org X-Gm-Message-State: AOJu0YyVOJv/fh0uUxwgIJ89yyLSI3MZq7J3QVGStgCxchxdE1wRa6vY zVcL9u3WJD2xisqxQgTY10qLOLvEUUHtKoehqK1ypLlpFMDuseACuz4h++HJu/Q/zjkJz+4TNrL gUBFEkOOdmfqIMOAI5XgdRt2LNyzWpLChE5+c75J0Axt6PqJd+1IfBrRIbzOkifpVeRM= X-Gm-Gg: AeBDievYqVOuKPMEjgIBhWIEfK6y0L8Czm764jxsSP5/WfuYWUCz4jHBnQnVgQHViqO RBOqaXWs6raboqDmVAwr09VloT9WBj44dPYNG6eCJlZcZBICtOsY3fLZf/QkyWTR+fz7OJu+cm5 lDxetuMXJHk+VNvligTdMXsLdg/xkBwGRcMpOF10k4AjXp2t1c1lRHbs0ZW5+XMn7p8MzemEVUD be5E0F29/cq+QkQNWGeX4lP8KzmDXRuCk5ZesC7vBepdrzxc0qXmN0Vvi//yO/Bb3GWHsIgOyaZ IuyOnOHywIyl++VATjchluB4HwRbRPgZgDIR25yQjTNTfxjglmWRVgcr7YGq+beYBSMWcisV9OM Oeu9rlZtPyzuCswMwMRNKywf4UKekI/xg80rZYvVI0xgUENZLio9TSJRAy3r6JKDrrgPxSMmnFc z72uapGD0ATg9MG2vpp2t9lBiZzpX+J+7BgWD/OJYhENTzCraERLo1FRE5SaUSbKdb//s= X-Received: by 2002:a17:90b:380f:b0:35b:e51a:ec77 with SMTP id 98e67ed59e1d1-364920307f6mr7834540a91.16.1777476289712; Wed, 29 Apr 2026 08:24:49 -0700 (PDT) X-Received: by 2002:a17:90b:380f:b0:35b:e51a:ec77 with SMTP id 98e67ed59e1d1-364920307f6mr7834421a91.16.1777476288125; Wed, 29 Apr 2026 08:24:48 -0700 (PDT) Received: from hu-kathirav-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-364bd588ad5sm66732a91.3.2026.04.29.08.24.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Apr 2026 08:24:46 -0700 (PDT) From: Kathiravan Thirumoorthy Date: Wed, 29 Apr 2026 20:54:23 +0530 Subject: [PATCH v2 2/4] clk: qcom: add Global Clock controller (GCC) driver for IPQ9650 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260429-ipq9650_boot_to_shell-v2-2-9b0dc3d1f3a8@oss.qualcomm.com> References: <20260429-ipq9650_boot_to_shell-v2-0-9b0dc3d1f3a8@oss.qualcomm.com> In-Reply-To: <20260429-ipq9650_boot_to_shell-v2-0-9b0dc3d1f3a8@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kathiravan Thirumoorthy X-Mailer: b4 0.15.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1777476269; l=112570; i=kathiravan.thirumoorthy@oss.qualcomm.com; s=20230906; h=from:subject:message-id; bh=gtgTu5ziE8FDBBdJ7EDFaeZn7v7jrwNOh2sFPwsIRns=; b=tP2aNdBseRii6v3MECjYe0BFoRZJWQ+OSeAuxDmeeJSqn/Fs5Md9n800CmLklSquHBPOac5bW tNoHI3lS+egCb0bbv5qEiskn1bkjtJCOLh1qaUC8IiVsi9Ma+AErTko X-Developer-Key: i=kathiravan.thirumoorthy@oss.qualcomm.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Proofpoint-GUID: I0TksqKCcEczX51q0a_6hDs-8jfUr3cI X-Proofpoint-ORIG-GUID: I0TksqKCcEczX51q0a_6hDs-8jfUr3cI X-Authority-Analysis: v=2.4 cv=Wak8rUhX c=1 sm=1 tr=0 ts=69f222c4 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=wvibRb96IX8IXfwpfrsA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI5MDE1NSBTYWx0ZWRfX+qHCszD7ojP3 0AF43FB2/FXrG82ZsNDAuutxyL1tvVU6YiqDiTZ0JOaOMzXy4GHg+j1VIWYK12xDjNpRHT2p44N G30hZ8u2Z26f32nF5iAxS57TJ9o71RZ7YB2l/eu38bFyW6Av96i2mjovMPWbVJGWbbZPFX/CWYm neMJDIkVx7Ei7muSAzg6gUGuoRpQqEW8qbIRjebMbd7c3aCfpW6S4+E7QacmKhO5NgFJczxgr2S Y4PyUrku+1JtAzRrkO3AALTonJDEtN+NLW6oWJsqk9vltg6EpkYC+p5IGlzQLtzHCpUWrKvKgL/ GatNV/ENjoG2VbY3+KFAHD0KyXsLy05NOTEjEsB2byadj3nK2JSdJcAvRIBygWK7A9nNpzPJNlj 6blrn0bJGSkK85HSDQ4isUuGIrZ2oEj7x3NGzzhHpIlpnCh7CfVCBiNnzHdm76mbnKiB1xePjMd i6MB/iExXo4zX4hOYFA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-29_01,2026-04-28_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 spamscore=0 clxscore=1015 bulkscore=0 impostorscore=0 adultscore=0 phishscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604290155 Add support for the global clock controller found on IPQ9650 SoC. Signed-off-by: Kathiravan Thirumoorthy --- drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-ipq9650.c | 3795 ++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 3806 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index df21ef5ffd68..9573e88d1f25 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -434,6 +434,16 @@ config IPQ_GCC_9574 i2c, USB, SD/eMMC, etc. Select this for the root clock of ipq9574. =20 +config IPQ_GCC_9650 + tristate "IPQ9650 Global Clock Controller" + depends on ARM64 || COMPILE_TEST + default ARCH_QCOM + help + Support for global clock controller on ipq9650 devices. + Say Y if you want to use peripheral devices such as UART, SPI, + i2c, USB, SD/eMMC, etc. Select this for the root clock + of ipq9650. + config IPQ_NSSCC_5424 tristate "IPQ5424 NSS Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 89d07c35e4d9..ca04117371cf 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -57,6 +57,7 @@ obj-$(CONFIG_IPQ_GCC_6018) +=3D gcc-ipq6018.o obj-$(CONFIG_IPQ_GCC_806X) +=3D gcc-ipq806x.o obj-$(CONFIG_IPQ_GCC_8074) +=3D gcc-ipq8074.o obj-$(CONFIG_IPQ_GCC_9574) +=3D gcc-ipq9574.o +obj-$(CONFIG_IPQ_GCC_9650) +=3D gcc-ipq9650.o obj-$(CONFIG_IPQ_NSSCC_5424) +=3D nsscc-ipq5424.o obj-$(CONFIG_IPQ_NSSCC_9574) +=3D nsscc-ipq9574.o obj-$(CONFIG_IPQ_LCC_806X) +=3D lcc-ipq806x.o diff --git a/drivers/clk/qcom/gcc-ipq9650.c b/drivers/clk/qcom/gcc-ipq9650.c new file mode 100644 index 000000000000..2e6ccd2c6a09 --- /dev/null +++ b/drivers/clk/qcom/gcc-ipq9650.c @@ -0,0 +1,3795 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include + +#include +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "reset.h" + +enum { + DT_XO, + DT_SLEEP_CLK, + DT_PCIE30_PHY0_PIPE_CLK, + DT_PCIE30_PHY1_PIPE_CLK, + DT_PCIE30_PHY2_PIPE_CLK, + DT_PCIE30_PHY3_PIPE_CLK, + DT_PCIE30_PHY4_PIPE_CLK, + DT_USB3_PHY0_CC_PIPE_CLK, + DT_NSS_CMN_CLK, +}; + +enum { + P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_ODD, + P_GPLL2_OUT_AUX, + P_GPLL2_OUT_MAIN, + P_GPLL4_OUT_MAIN, + P_GPLL4_OUT_ODD, + P_NSS_CMN_CLK, + P_SLEEP_CLK, + P_XO, +}; + +static const struct clk_parent_data gcc_parent_data_xo =3D { .index =3D DT= _XO }; + +static struct clk_alpha_pll gpll0_main =3D { + .offset =3D 0x20000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr =3D { + .enable_reg =3D 0xb000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll0_main", + .parent_data =3D &gcc_parent_data_xo, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ops, + }, + }, +}; + +static struct clk_fixed_factor gpll0_div2 =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll0_div2", + .parent_hws =3D (const struct clk_hw *[]) { + &gpll0_main.clkr.hw + }, + .num_parents =3D 1, + .ops =3D &clk_fixed_factor_ops, + }, +}; + +static struct clk_alpha_pll_postdiv gpll0 =3D { + .offset =3D 0x20000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll0", + .parent_hws =3D (const struct clk_hw *[]) { + &gpll0_main.clkr.hw }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_ro_ops, + }, +}; + +static struct clk_alpha_pll gpll2 =3D { + .offset =3D 0x21000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], + .clkr =3D { + .enable_reg =3D 0xb000, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll2", + .parent_data =3D &gcc_parent_data_xo, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_zonda_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpll2_out_main[] =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpll2_out_main =3D { + .offset =3D 0x21000, + .post_div_shift =3D 8, + .post_div_table =3D post_div_table_gpll2_out_main, + .num_post_div =3D ARRAY_SIZE(post_div_table_gpll2_out_main), + .width =3D 2, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll2_out_main", + .parent_hws =3D (const struct clk_hw*[]) { + &gpll2.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_zonda_ops, + }, +}; + +static struct clk_alpha_pll gpll4 =3D { + .offset =3D 0x22000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr =3D { + .enable_reg =3D 0xb000, + .enable_mask =3D BIT(2), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll4", + .parent_data =3D &gcc_parent_data_xo, + .num_parents =3D 1, + /* + * There are no consumers for this GPLL in kernel yet, + * (will be added soon), so the clock framework + * disables this source. But some of the clocks + * initialized by boot loaders uses this source. So we + * need to keep this clock ON. Add the + * CLK_IGNORE_UNUSED flag so the clock will not be + * disabled. Once the consumer in kernel is added, we + * can get rid of this flag. + */ + .flags =3D CLK_IS_CRITICAL, + .ops =3D &clk_alpha_pll_fixed_lucid_ops, + }, + }, +}; + +static const struct parent_map gcc_parent_map_xo[] =3D { + { P_XO, 0 }, +}; + +static const struct parent_map gcc_parent_map_0[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, +}; + +static const struct clk_parent_data gcc_parent_data_0[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0_div2.hw }, +}; + +static const struct parent_map gcc_parent_map_1[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL4_OUT_MAIN, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_1[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll4.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_2[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data gcc_parent_data_2[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_3[] =3D { + { P_XO, 0 }, +}; + +static const struct clk_parent_data gcc_parent_data_3[] =3D { + { .index =3D DT_XO }, +}; + +static const struct parent_map gcc_parent_map_4[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, + { P_GPLL0_OUT_ODD, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_4[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0_div2.hw }, + { .hw =3D &gpll0.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_5[] =3D { + { P_XO, 0 }, + { P_GPLL4_OUT_MAIN, 1 }, + { P_GPLL0_OUT_ODD, 2 }, + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, +}; + +static const struct clk_parent_data gcc_parent_data_5[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll4.clkr.hw }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0_div2.hw }, +}; + +static const struct parent_map gcc_parent_map_6[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL2_OUT_AUX, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_6[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll2.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_7[] =3D { + { P_XO, 0 }, + { P_GPLL4_OUT_ODD, 1 }, + { P_GPLL0_OUT_MAIN, 3 }, + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, +}; + +static const struct clk_parent_data gcc_parent_data_7[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll4.clkr.hw }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0_div2.hw }, +}; + +static const struct parent_map gcc_parent_map_8[] =3D { + { P_XO, 0 }, + { P_NSS_CMN_CLK, 1 }, + { P_GPLL0_OUT_ODD, 2 }, + { P_GPLL2_OUT_AUX, 3 }, +}; + +static const struct clk_parent_data gcc_parent_data_8[] =3D { + { .index =3D DT_XO }, + { .index =3D DT_NSS_CMN_CLK }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll2.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_9[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_ODD, 2 }, + { P_SLEEP_CLK, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_9[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_parent_map_10[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL2_OUT_MAIN, 2 }, + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, +}; + +static const struct clk_parent_data gcc_parent_data_10[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll2_out_main.clkr.hw }, + { .hw =3D &gpll0_div2.hw }, +}; + +static const struct parent_map gcc_parent_map_11[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL4_OUT_MAIN, 2 }, + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, +}; + +static const struct clk_parent_data gcc_parent_data_11[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll4.clkr.hw }, + { .hw =3D &gpll0_div2.hw }, +}; + +static const struct parent_map gcc_parent_map_12[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_ODD, 2 }, + { P_SLEEP_CLK, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_12[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_parent_map_13[] =3D { + { P_SLEEP_CLK, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_13[] =3D { + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_parent_map_14[] =3D { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL4_OUT_MAIN, 2 }, + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 3 }, +}; + +static const struct clk_parent_data gcc_parent_data_14[] =3D { + { .index =3D DT_XO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll4.clkr.hw }, + { .hw =3D &gpll0_div2.hw }, +}; + +static const struct freq_tbl ftbl_gcc_adss_pwm_clk_src[] =3D { + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_adss_pwm_clk_src =3D { + .cmd_rcgr =3D 0x1c004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_adss_pwm_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_adss_pwm_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_apss_axi_clk_src[] =3D { + F(800000000, P_GPLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_gemnoc_anoc_pcie_clk_src[] =3D { + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_nss_ts_clk_src[] =3D { + F(24000000, P_XO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_xo_clk_src =3D { + .cmd_rcgr =3D 0x34004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_xo, + .freq_tbl =3D ftbl_gcc_nss_ts_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_xo_clk_src", + .parent_data =3D &gcc_parent_data_xo, + .num_parents =3D 1, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_fixed_factor gcc_xo_div4_clk_src =3D { + .mult =3D 1, + .div =3D 4, + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_xo_div4_clk_src", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_xo_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_fixed_factor_ops, + }, +}; + +static struct clk_rcg2 gcc_nss_ts_clk_src =3D { + .cmd_rcgr =3D 0x17088, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_nss_ts_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nss_ts_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_refgen_core_clk_src =3D { + .cmd_rcgr =3D 0x23004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_nss_ts_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_refgen_core_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_nssnoc_memnoc_bfdcd_clk_src[] =3D { + F(462000000, P_NSS_CMN_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_nssnoc_memnoc_bfdcd_clk_src =3D { + .cmd_rcgr =3D 0x17004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_8, + .freq_tbl =3D ftbl_gcc_nssnoc_memnoc_bfdcd_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_memnoc_bfdcd_clk_src", + .parent_data =3D gcc_parent_data_8, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_8), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_system_noc_bfdcd_clk_src[] =3D { + F(24000000, P_XO, 1, 0, 0), + F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src =3D { + .cmd_rcgr =3D 0x2e004, + .freq_tbl =3D ftbl_gcc_system_noc_bfdcd_clk_src, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_14, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_system_noc_bfdcd_clk_src", + .parent_data =3D gcc_parent_data_14, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_14), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcnoc_bfdcd_clk_src[] =3D { + F(24000000, P_XO, 1, 0, 0), + F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcnoc_bfdcd_clk_src =3D { + .cmd_rcgr =3D 0x31004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcnoc_bfdcd_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcnoc_bfdcd_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + /* + * There are no consumers for this source in kernel yet, + * (will be added soon), so the clock framework + * disables this source. But some of the clocks + * initialized by boot loaders uses this source. So we + * need to keep this clock ON. Add the + * CLK_IGNORE_UNUSED flag so the clock will not be + * disabled. Once the consumer in kernel is added, we + * can get rid of this flag. + */ + .flags =3D CLK_IS_CRITICAL, + .ops =3D &clk_rcg2_ops, + }, +}; +static const struct freq_tbl ftbl_gcc_pcie0_axi_m_clk_src[] =3D { + F(200000000, P_GPLL4_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcie0_axi_m_clk_src =3D { + .cmd_rcgr =3D 0x28018, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie0_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_axi_m_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie0_axi_s_clk_src =3D { + .cmd_rcgr =3D 0x28020, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie0_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_axi_s_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie0_rchng_clk_src =3D { + .cmd_rcgr =3D 0x28028, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_adss_pwm_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_rchng_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie1_axi_m_clk_src[] =3D { + F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcie1_axi_m_clk_src =3D { + .cmd_rcgr =3D 0x29018, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie1_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_axi_m_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie1_axi_s_clk_src =3D { + .cmd_rcgr =3D 0x29020, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie0_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_axi_s_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie1_rchng_clk_src =3D { + .cmd_rcgr =3D 0x29028, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_adss_pwm_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_rchng_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie2_axi_m_clk_src =3D { + .cmd_rcgr =3D 0x2a018, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie1_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie2_axi_m_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie2_axi_s_clk_src =3D { + .cmd_rcgr =3D 0x2a020, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie0_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie2_axi_s_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie2_rchng_clk_src =3D { + .cmd_rcgr =3D 0x2a028, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_adss_pwm_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie2_rchng_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie3_axi_m_clk_src =3D { + .cmd_rcgr =3D 0x2b018, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie1_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie3_axi_m_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie3_axi_s_clk_src =3D { + .cmd_rcgr =3D 0x2b020, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie0_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie3_axi_s_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie3_rchng_clk_src =3D { + .cmd_rcgr =3D 0x2b028, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_adss_pwm_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie3_rchng_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie4_axi_m_clk_src =3D { + .cmd_rcgr =3D 0x25004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie0_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie4_axi_m_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie4_axi_s_clk_src =3D { + .cmd_rcgr =3D 0x2500c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie0_axi_m_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie4_axi_s_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie4_rchng_clk_src =3D { + .cmd_rcgr =3D 0x25014, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_adss_pwm_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie4_rchng_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie_aux_clk_src[] =3D { + F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4), + { } +}; + +static struct clk_rcg2 gcc_pcie_aux_clk_src =3D { + .cmd_rcgr =3D 0x28004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_9, + .freq_tbl =3D ftbl_gcc_pcie_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_aux_clk_src", + .parent_data =3D gcc_parent_data_9, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_9), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_primess_ahbm_clk_src =3D { + .cmd_rcgr =3D 0x2601c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_adss_pwm_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_primess_ahbm_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_primess_axim_clk_src =3D { + .cmd_rcgr =3D 0x26014, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_gemnoc_anoc_pcie_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_primess_axim_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_primess_clk_src =3D { + .cmd_rcgr =3D 0x2600c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_4, + .freq_tbl =3D ftbl_gcc_apss_axi_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_primess_clk_src", + .parent_data =3D gcc_parent_data_4, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_4), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qdss_at_clk_src[] =3D { + F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_qdss_at_clk_src =3D { + .cmd_rcgr =3D 0x2d004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_5, + .freq_tbl =3D ftbl_gcc_qdss_at_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qdss_at_clk_src", + .parent_data =3D gcc_parent_data_5, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_5), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_fixed_factor gcc_eud_at_div_clk_src =3D { + .mult =3D 1, + .div =3D 6, + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_eud_at_div_clk_src", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_qdss_at_clk_src.clkr.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_fixed_factor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qdss_tsctr_clk_src[] =3D { + F(600000000, P_GPLL4_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_qdss_tsctr_clk_src =3D { + .cmd_rcgr =3D 0x2d01c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_5, + .freq_tbl =3D ftbl_gcc_qdss_tsctr_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qdss_tsctr_clk_src", + .parent_data =3D gcc_parent_data_5, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_5), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_fixed_factor gcc_qdss_dap_sync_clk_src =3D { + .mult =3D 1, + .div =3D 4, + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qdss_dap_sync_clk_src", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_qdss_tsctr_clk_src.clkr.hw + }, + .num_parents =3D 1, + .ops =3D &clk_fixed_factor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sleep_clk_src[] =3D { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sleep_clk_src =3D { + .cmd_rcgr =3D 0x3400c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_13, + .freq_tbl =3D ftbl_gcc_sleep_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sleep_clk_src", + .parent_data =3D gcc_parent_data_13, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_13), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qpic_io_macro_clk_src[] =3D { + F(24000000, P_XO, 1, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_qpic_clk_src =3D { + .cmd_rcgr =3D 0x32020, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_6, + .freq_tbl =3D ftbl_gcc_qpic_io_macro_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qpic_clk_src", + .parent_data =3D gcc_parent_data_6, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_6), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_qpic_io_macro_clk_src =3D { + .cmd_rcgr =3D 0x32004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_6, + .freq_tbl =3D ftbl_gcc_qpic_io_macro_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qpic_io_macro_clk_src", + .parent_data =3D gcc_parent_data_6, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_6), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_qupv3_2x_core_clk_src =3D { + .cmd_rcgr =3D 0x100c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_gemnoc_anoc_pcie_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_2x_core_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap_se0_clk_src[] =3D { + F(960000, P_XO, 10, 2, 5), + F(3686636, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 2, 217), + F(4800000, P_XO, 5, 0, 0), + F(7373272, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 4, 217), + F(9600000, P_XO, 2.5, 0, 0), + F(14746544, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 8, 217), + F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5), + F(24000000, P_XO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2), + F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25), + F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20), + F(46400000, P_GPLL0_OUT_MAIN, 2, 29, 250), + F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50), + F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), + F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125), + F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100), + F(58986175, P_GPLL0_OUT_MAIN, 1, 16, 217), + F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40), + F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se0_clk_src =3D { + .cmd_rcgr =3D 0x2018, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se0_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se1_clk_src =3D { + .cmd_rcgr =3D 0x3018, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se1_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se2_clk_src =3D { + .cmd_rcgr =3D 0x3034, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se3_clk_src =3D { + .cmd_rcgr =3D 0x3050, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se3_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap_se4_clk_src[] =3D { + F(960000, P_XO, 10, 2, 5), + F(3686636, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 2, 217), + F(4800000, P_XO, 5, 0, 0), + F(7373272, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 4, 217), + F(9600000, P_XO, 2.5, 0, 0), + F(14746544, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 8, 217), + F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5), + F(24000000, P_XO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2), + F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25), + F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20), + F(46400000, P_GPLL0_OUT_MAIN, 2, 29, 250), + F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50), + F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), + F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125), + F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100), + F(58986175, P_GPLL0_OUT_MAIN, 1, 16, 217), + F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40), + F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se4_clk_src =3D { + .cmd_rcgr =3D 0x306c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se4_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se4_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se5_clk_src =3D { + .cmd_rcgr =3D 0x3090, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se4_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se5_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se6_clk_src =3D { + .cmd_rcgr =3D 0x4004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se6_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap_se7_clk_src =3D { + .cmd_rcgr =3D 0x4020, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap_se0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se7_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] =3D { + F(144000, P_XO, 16, 12, 125), + F(400000, P_XO, 12, 1, 5), + F(24000000, P_GPLL2_OUT_MAIN, 12, 1, 2), + F(48000000, P_GPLL2_OUT_MAIN, 12, 0, 0), + F(96000000, P_GPLL2_OUT_MAIN, 6, 0, 0), + F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0), + F(192000000, P_GPLL2_OUT_MAIN, 3, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_apps_clk_src =3D { + .cmd_rcgr =3D 0x33004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_10, + .freq_tbl =3D ftbl_gcc_sdcc1_apps_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_apps_clk_src", + .parent_data =3D gcc_parent_data_10, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_10), + .ops =3D &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] =3D { + F(300000000, P_GPLL4_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src =3D { + .cmd_rcgr =3D 0x33018, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_11, + .freq_tbl =3D ftbl_gcc_sdcc1_ice_core_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_ice_core_clk_src", + .parent_data =3D gcc_parent_data_11, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_11), + .ops =3D &clk_rcg2_floor_ops, + }, +}; + +static struct clk_rcg2 gcc_uniphy_sys_clk_src =3D { + .cmd_rcgr =3D 0x17090, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_nss_ts_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy_sys_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb0_aux_clk_src =3D { + .cmd_rcgr =3D 0x2c018, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_12, + .freq_tbl =3D ftbl_gcc_nss_ts_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_aux_clk_src", + .parent_data =3D gcc_parent_data_12, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_12), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb0_master_clk_src =3D { + .cmd_rcgr =3D 0x2c004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_gemnoc_anoc_pcie_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_master_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb0_mock_utmi_clk_src[] =3D { + F(24000000, P_XO, 1, 0, 0), + F(60000000, P_GPLL4_OUT_ODD, 10, 1, 2), + { } +}; + +static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src =3D { + .cmd_rcgr =3D 0x2c02c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_7, + .freq_tbl =3D ftbl_gcc_usb0_mock_utmi_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_mock_utmi_clk_src", + .parent_data =3D gcc_parent_data_7, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_7), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb1_mock_utmi_clk_src =3D { + .cmd_rcgr =3D 0x3c004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_7, + .freq_tbl =3D ftbl_gcc_usb0_mock_utmi_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb1_mock_utmi_clk_src", + .parent_data =3D gcc_parent_data_7, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_7), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div gcc_nssnoc_memnoc_div_clk_src =3D { + .reg =3D 0x1700c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_memnoc_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_nssnoc_memnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_usb0_mock_utmi_div_clk_src =3D { + .reg =3D 0x2c040, + .shift =3D 0, + .width =3D 2, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_mock_utmi_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb0_mock_utmi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_usb1_mock_utmi_div_clk_src =3D { + .reg =3D 0x3c018, + .shift =3D 0, + .width =3D 2, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb1_mock_utmi_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb1_mock_utmi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gcc_adss_pwm_clk =3D { + .halt_reg =3D 0x1c00c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1c00c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_adss_pwm_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_adss_pwm_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_anoc_pcie0_1lane_m_clk =3D { + .halt_reg =3D 0x2e07c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e07c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_anoc_pcie0_1lane_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie0_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_anoc_pcie0_1lane_s_clk =3D { + .halt_reg =3D 0x2e0cc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e0cc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_anoc_pcie0_1lane_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie0_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_anoc_pcie1_2lane_m_clk =3D { + .halt_reg =3D 0x2e084, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e084, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_anoc_pcie1_2lane_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie1_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_anoc_pcie1_2lane_s_clk =3D { + .halt_reg =3D 0x2e0d0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e0d0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_anoc_pcie1_2lane_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie1_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_anoc_pcie2_2lane_m_clk =3D { + .halt_reg =3D 0x2e080, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e080, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_anoc_pcie2_2lane_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie2_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_anoc_pcie2_2lane_s_clk =3D { + .halt_reg =3D 0x2e0d4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e0d4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_anoc_pcie2_2lane_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie2_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_anoc_pcie3_2lane_m_clk =3D { + .halt_reg =3D 0x2e0bc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e0bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_anoc_pcie3_2lane_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie3_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_anoc_pcie3_2lane_s_clk =3D { + .halt_reg =3D 0x2e0d8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e0d8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_anoc_pcie3_2lane_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie3_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_anoc_pcie4_1lane_m_clk =3D { + .halt_reg =3D 0x2e0c0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e0c0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_anoc_pcie4_1lane_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie4_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_anoc_pcie4_1lane_s_clk =3D { + .halt_reg =3D 0x2e0dc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e0dc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_anoc_pcie4_1lane_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie4_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cmn_12gpll_ahb_clk =3D { + .halt_reg =3D 0x3a004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3a004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cmn_12gpll_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cmn_12gpll_sys_clk =3D { + .halt_reg =3D 0x3a008, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x3a008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cmn_12gpll_sys_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_uniphy_sys_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mdio_ahb_clk =3D { + .halt_reg =3D 0x17040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_mdio_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nss_ts_clk =3D { + .halt_reg =3D 0x17018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x17018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nss_ts_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_nss_ts_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nsscc_clk =3D { + .halt_reg =3D 0x17034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nsscc_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nsscfg_clk =3D { + .halt_reg =3D 0x1702c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1702c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nsscfg_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_atb_clk =3D { + .halt_reg =3D 0x17014, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x17014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_atb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qdss_at_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_memnoc_1_clk =3D { + .halt_reg =3D 0x17084, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17084, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_memnoc_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_nssnoc_memnoc_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_memnoc_clk =3D { + .halt_reg =3D 0x17024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_memnoc_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_nssnoc_memnoc_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_nsscc_clk =3D { + .halt_reg =3D 0x17030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_nsscc_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_pcnoc_1_clk =3D { + .halt_reg =3D 0x17080, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17080, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_pcnoc_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_qosgen_ref_clk =3D { + .halt_reg =3D 0x1701c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1701c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_qosgen_ref_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_xo_div4_clk_src.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_snoc_1_clk =3D { + .halt_reg =3D 0x1707c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1707c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_snoc_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_system_noc_bfdcd_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_snoc_clk =3D { + .halt_reg =3D 0x17028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_snoc_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_system_noc_bfdcd_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_timeout_ref_clk =3D { + .halt_reg =3D 0x17020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_timeout_ref_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_xo_div4_clk_src.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_xo_dcd_clk =3D { + .halt_reg =3D 0x17074, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17074, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_nssnoc_xo_dcd_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_ahb_clk =3D { + .halt_reg =3D 0x28030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_aux_clk =3D { + .halt_reg =3D 0x28070, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28070, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_axi_m_clk =3D { + .halt_reg =3D 0x28038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_axi_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie0_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_axi_s_bridge_clk =3D { + .halt_reg =3D 0x28048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_axi_s_bridge_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie0_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_axi_s_clk =3D { + .halt_reg =3D 0x28040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x28040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_axi_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie0_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie0_pipe_clk_src =3D { + .reg =3D 0x28064, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "pcie0_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_PCIE30_PHY0_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_pipe_clk =3D { + .halt_reg =3D 0x28068, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x28068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_pipe_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie0_pipe_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_ahb_clk =3D { + .halt_reg =3D 0x29030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x29030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_aux_clk =3D { + .halt_reg =3D 0x29074, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x29074, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_axi_m_clk =3D { + .halt_reg =3D 0x29038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x29038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_axi_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie1_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_axi_s_bridge_clk =3D { + .halt_reg =3D 0x29048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x29048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_axi_s_bridge_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie1_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_axi_s_clk =3D { + .halt_reg =3D 0x29040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x29040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_axi_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie1_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie1_pipe_clk_src =3D { + .reg =3D 0x29064, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "pcie1_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_PCIE30_PHY1_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_pipe_clk =3D { + .halt_reg =3D 0x29068, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x29068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_pipe_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie1_pipe_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie2_ahb_clk =3D { + .halt_reg =3D 0x2a030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2a030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie2_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie2_aux_clk =3D { + .halt_reg =3D 0x2a078, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2a078, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie2_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie2_axi_m_clk =3D { + .halt_reg =3D 0x2a038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2a038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie2_axi_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie2_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie2_axi_s_bridge_clk =3D { + .halt_reg =3D 0x2a048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2a048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie2_axi_s_bridge_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie2_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie2_axi_s_clk =3D { + .halt_reg =3D 0x2a040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2a040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie2_axi_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie2_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie2_pipe_clk_src =3D { + .reg =3D 0x2a064, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "pcie2_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_PCIE30_PHY2_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie2_pipe_clk =3D { + .halt_reg =3D 0x2a068, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x2a068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie2_pipe_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie2_pipe_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie3_ahb_clk =3D { + .halt_reg =3D 0x2b030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2b030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie3_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie3_aux_clk =3D { + .halt_reg =3D 0x2b07c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2b07c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie3_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie3_axi_m_clk =3D { + .halt_reg =3D 0x2b038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2b038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie3_axi_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie3_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie3_axi_s_bridge_clk =3D { + .halt_reg =3D 0x2b048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2b048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie3_axi_s_bridge_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie3_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie3_axi_s_clk =3D { + .halt_reg =3D 0x2b040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2b040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie3_axi_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie3_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie3_pipe_clk_src =3D { + .reg =3D 0x2b064, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "pcie3_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_PCIE30_PHY3_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie3_pipe_clk =3D { + .halt_reg =3D 0x2b068, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x2b068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie3_pipe_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie3_pipe_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie4_ahb_clk =3D { + .halt_reg =3D 0x2501c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2501c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie4_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie4_aux_clk =3D { + .halt_reg =3D 0x25020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x25020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie4_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie4_axi_m_clk =3D { + .halt_reg =3D 0x25028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x25028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie4_axi_m_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie4_axi_m_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie4_axi_s_bridge_clk =3D { + .halt_reg =3D 0x25038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x25038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie4_axi_s_bridge_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie4_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie4_axi_s_clk =3D { + .halt_reg =3D 0x25030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x25030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie4_axi_s_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie4_axi_s_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie4_pipe_clk_src =3D { + .reg =3D 0x25058, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "pcie4_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_PCIE30_PHY4_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie4_pipe_clk =3D { + .halt_reg =3D 0x2503c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x2503c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie4_pipe_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie4_pipe_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_rchng_clk =3D { + .halt_reg =3D 0x28028, + .clkr =3D { + .enable_reg =3D 0x28028, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_rchng_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie0_rchng_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_rchng_clk =3D { + .halt_reg =3D 0x29028, + .clkr =3D { + .enable_reg =3D 0x29028, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_rchng_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie1_rchng_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie2_rchng_clk =3D { + .halt_reg =3D 0x2a028, + .clkr =3D { + .enable_reg =3D 0x2a028, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie2_rchng_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie2_rchng_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie3_rchng_clk =3D { + .halt_reg =3D 0x2b028, + .clkr =3D { + .enable_reg =3D 0x2b028, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie3_rchng_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie3_rchng_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie4_rchng_clk =3D { + .halt_reg =3D 0x25014, + .clkr =3D { + .enable_reg =3D 0x25014, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie4_rchng_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_pcie4_rchng_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_cmn_hclk =3D { + .halt_reg =3D 0x23030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x23030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_cmn_hclk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_cmn_ldo_clk =3D { + .halt_reg =3D 0x2302c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2302c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_cmn_ldo_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_refgen_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_primess_ahbm_clk =3D { + .halt_reg =3D 0x26038, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x26038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_primess_ahbm_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_primess_ahbm_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_primess_ahbm_partial_clk =3D { + .halt_reg =3D 0x26040, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x26040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_primess_ahbm_partial_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_primess_ahbm_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_primess_ahbs_clk =3D { + .halt_reg =3D 0x26034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x26034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_primess_ahbs_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_primess_atb_clk =3D { + .halt_reg =3D 0x26030, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x26030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_primess_atb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qdss_at_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_primess_axim_clk =3D { + .halt_reg =3D 0x2602c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x2602c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_primess_axim_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_primess_axim_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_primess_axim_partial_clk =3D { + .halt_reg =3D 0x2603c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x2603c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_primess_axim_partial_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_primess_axim_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_primess_clk =3D { + .halt_reg =3D 0x26028, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x26028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_primess_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_primess_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_primess_xo_clk =3D { + .halt_reg =3D 0x26024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x26024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_primess_xo_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qdss_at_clk =3D { + .halt_reg =3D 0x2d034, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x2d034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qdss_at_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qdss_at_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qdss_dap_clk =3D { + .halt_reg =3D 0x2d058, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb004, + .enable_mask =3D BIT(2), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qdss_dap_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qdss_dap_sync_clk_src.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qpic_ahb_clk =3D { + .halt_reg =3D 0x32010, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x32010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qpic_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qpic_clk =3D { + .halt_reg =3D 0x32028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x32028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qpic_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qpic_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qpic_io_macro_clk =3D { + .halt_reg =3D 0x3200c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3200c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qpic_io_macro_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qpic_io_macro_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qpic_sleep_clk =3D { + .halt_reg =3D 0x32018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x32018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qpic_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_ahb_mst_clk =3D { + .halt_reg =3D 0x1014, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb004, + .enable_mask =3D BIT(14), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_ahb_mst_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_ahb_slv_clk =3D { + .halt_reg =3D 0x102c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb004, + .enable_mask =3D BIT(4), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_ahb_slv_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se0_clk =3D { + .halt_reg =3D 0x202c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x202c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se1_clk =3D { + .halt_reg =3D 0x302c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x302c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se2_clk =3D { + .halt_reg =3D 0x3048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se3_clk =3D { + .halt_reg =3D 0x3064, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se4_clk =3D { + .halt_reg =3D 0x3080, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3080, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se4_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se5_clk =3D { + .halt_reg =3D 0x30a4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x30a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se5_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se5_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se6_clk =3D { + .halt_reg =3D 0x4018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x4018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se6_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se6_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_se7_clk =3D { + .halt_reg =3D 0x4034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x4034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_se7_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap_se7_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_refgen_pcie_core_clk =3D { + .halt_reg =3D 0x23020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x23020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_refgen_pcie_core_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_refgen_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_refgen_pcie_hclk =3D { + .halt_reg =3D 0x23024, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x23024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_refgen_pcie_hclk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ahb_clk =3D { + .halt_reg =3D 0x3303c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3303c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_apps_clk =3D { + .halt_reg =3D 0x3302c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3302c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_apps_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_sdcc1_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ice_core_clk =3D { + .halt_reg =3D 0x33034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x33034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_ice_core_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_sdcc1_ice_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_snoc_usb_clk =3D { + .halt_reg =3D 0x2e0c4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2e0c4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_snoc_usb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb0_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy0_ahb_clk =3D { + .halt_reg =3D 0x1704c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1704c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy0_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy0_sys_clk =3D { + .halt_reg =3D 0x17048, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x17048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy0_sys_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_uniphy_sys_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy1_ahb_clk =3D { + .halt_reg =3D 0x1705c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1705c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy1_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy1_sys_clk =3D { + .halt_reg =3D 0x17058, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x17058, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy1_sys_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_uniphy_sys_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy2_ahb_clk =3D { + .halt_reg =3D 0x1706c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1706c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy2_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy2_sys_clk =3D { + .halt_reg =3D 0x17068, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x17068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_uniphy2_sys_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_uniphy_sys_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_aux_clk =3D { + .halt_reg =3D 0x2c04c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x2c04c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb0_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_eud_at_clk =3D { + .halt_reg =3D 0x30004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x30004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_eud_at_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_eud_at_div_clk_src.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_master_clk =3D { + .halt_reg =3D 0x2c044, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x2c044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_master_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb0_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_mock_utmi_clk =3D { + .halt_reg =3D 0x2c050, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x2c050, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_mock_utmi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb0_mock_utmi_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_phy_cfg_ahb_clk =3D { + .halt_reg =3D 0x2c05c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x2c05c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_phy_cfg_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src =3D { + .reg =3D 0x2c074, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_USB3_PHY0_CC_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_pipe_clk =3D { + .halt_reg =3D 0x2c054, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x2c054, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_pipe_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gcc_usb0_pipe_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_sleep_clk =3D { + .halt_reg =3D 0x2c058, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x2c058, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb0_sleep_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_sleep_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb1_master_clk =3D { + .halt_reg =3D 0x3c028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3c028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb1_master_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb1_mock_utmi_clk =3D { + .halt_reg =3D 0x3c024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3c024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb1_mock_utmi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb1_mock_utmi_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb1_phy_cfg_ahb_clk =3D { + .halt_reg =3D 0x3c01c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x3c01c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb1_phy_cfg_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb1_sleep_clk =3D { + .halt_reg =3D 0x3c020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3c020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb1_sleep_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_sleep_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb_cmn_hclk =3D { + .halt_reg =3D 0x2303c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2303c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb_cmn_hclk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb_cmn_ldo_clk =3D { + .halt_reg =3D 0x23038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x23038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb_cmn_ldo_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_refgen_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *gcc_ipq9650_clocks[] =3D { + [GCC_ADSS_PWM_CLK] =3D &gcc_adss_pwm_clk.clkr, + [GCC_ADSS_PWM_CLK_SRC] =3D &gcc_adss_pwm_clk_src.clkr, + [GCC_ANOC_PCIE0_1LANE_M_CLK] =3D &gcc_anoc_pcie0_1lane_m_clk.clkr, + [GCC_ANOC_PCIE0_1LANE_S_CLK] =3D &gcc_anoc_pcie0_1lane_s_clk.clkr, + [GCC_ANOC_PCIE1_2LANE_M_CLK] =3D &gcc_anoc_pcie1_2lane_m_clk.clkr, + [GCC_ANOC_PCIE1_2LANE_S_CLK] =3D &gcc_anoc_pcie1_2lane_s_clk.clkr, + [GCC_ANOC_PCIE2_2LANE_M_CLK] =3D &gcc_anoc_pcie2_2lane_m_clk.clkr, + [GCC_ANOC_PCIE2_2LANE_S_CLK] =3D &gcc_anoc_pcie2_2lane_s_clk.clkr, + [GCC_ANOC_PCIE3_2LANE_M_CLK] =3D &gcc_anoc_pcie3_2lane_m_clk.clkr, + [GCC_ANOC_PCIE3_2LANE_S_CLK] =3D &gcc_anoc_pcie3_2lane_s_clk.clkr, + [GCC_ANOC_PCIE4_1LANE_M_CLK] =3D &gcc_anoc_pcie4_1lane_m_clk.clkr, + [GCC_ANOC_PCIE4_1LANE_S_CLK] =3D &gcc_anoc_pcie4_1lane_s_clk.clkr, + [GCC_CMN_12GPLL_AHB_CLK] =3D &gcc_cmn_12gpll_ahb_clk.clkr, + [GCC_CMN_12GPLL_SYS_CLK] =3D &gcc_cmn_12gpll_sys_clk.clkr, + [GCC_MDIO_AHB_CLK] =3D &gcc_mdio_ahb_clk.clkr, + [GCC_NSS_TS_CLK] =3D &gcc_nss_ts_clk.clkr, + [GCC_NSS_TS_CLK_SRC] =3D &gcc_nss_ts_clk_src.clkr, + [GCC_NSSCC_CLK] =3D &gcc_nsscc_clk.clkr, + [GCC_NSSCFG_CLK] =3D &gcc_nsscfg_clk.clkr, + [GCC_NSSNOC_ATB_CLK] =3D &gcc_nssnoc_atb_clk.clkr, + [GCC_NSSNOC_MEMNOC_1_CLK] =3D &gcc_nssnoc_memnoc_1_clk.clkr, + [GCC_NSSNOC_MEMNOC_BFDCD_CLK_SRC] =3D &gcc_nssnoc_memnoc_bfdcd_clk_src.cl= kr, + [GCC_NSSNOC_MEMNOC_CLK] =3D &gcc_nssnoc_memnoc_clk.clkr, + [GCC_NSSNOC_MEMNOC_DIV_CLK_SRC] =3D &gcc_nssnoc_memnoc_div_clk_src.clkr, + [GCC_NSSNOC_NSSCC_CLK] =3D &gcc_nssnoc_nsscc_clk.clkr, + [GCC_NSSNOC_PCNOC_1_CLK] =3D &gcc_nssnoc_pcnoc_1_clk.clkr, + [GCC_NSSNOC_QOSGEN_REF_CLK] =3D &gcc_nssnoc_qosgen_ref_clk.clkr, + [GCC_NSSNOC_SNOC_1_CLK] =3D &gcc_nssnoc_snoc_1_clk.clkr, + [GCC_NSSNOC_SNOC_CLK] =3D &gcc_nssnoc_snoc_clk.clkr, + [GCC_NSSNOC_TIMEOUT_REF_CLK] =3D &gcc_nssnoc_timeout_ref_clk.clkr, + [GCC_NSSNOC_XO_DCD_CLK] =3D &gcc_nssnoc_xo_dcd_clk.clkr, + [GCC_PCIE0_AHB_CLK] =3D &gcc_pcie0_ahb_clk.clkr, + [GCC_PCIE0_AUX_CLK] =3D &gcc_pcie0_aux_clk.clkr, + [GCC_PCIE0_AXI_M_CLK] =3D &gcc_pcie0_axi_m_clk.clkr, + [GCC_PCIE0_AXI_M_CLK_SRC] =3D &gcc_pcie0_axi_m_clk_src.clkr, + [GCC_PCIE0_AXI_S_BRIDGE_CLK] =3D &gcc_pcie0_axi_s_bridge_clk.clkr, + [GCC_PCIE0_AXI_S_CLK] =3D &gcc_pcie0_axi_s_clk.clkr, + [GCC_PCIE0_AXI_S_CLK_SRC] =3D &gcc_pcie0_axi_s_clk_src.clkr, + [GCC_PCIE0_PIPE_CLK] =3D &gcc_pcie0_pipe_clk.clkr, + [GCC_PCIE0_PIPE_CLK_SRC] =3D &gcc_pcie0_pipe_clk_src.clkr, + [GCC_PCIE0_RCHNG_CLK_SRC] =3D &gcc_pcie0_rchng_clk_src.clkr, + [GCC_PCIE0_RCHNG_CLK] =3D &gcc_pcie0_rchng_clk.clkr, + [GCC_PCIE1_AHB_CLK] =3D &gcc_pcie1_ahb_clk.clkr, + [GCC_PCIE1_AUX_CLK] =3D &gcc_pcie1_aux_clk.clkr, + [GCC_PCIE1_AXI_M_CLK] =3D &gcc_pcie1_axi_m_clk.clkr, + [GCC_PCIE1_AXI_M_CLK_SRC] =3D &gcc_pcie1_axi_m_clk_src.clkr, + [GCC_PCIE1_AXI_S_BRIDGE_CLK] =3D &gcc_pcie1_axi_s_bridge_clk.clkr, + [GCC_PCIE1_AXI_S_CLK] =3D &gcc_pcie1_axi_s_clk.clkr, + [GCC_PCIE1_AXI_S_CLK_SRC] =3D &gcc_pcie1_axi_s_clk_src.clkr, + [GCC_PCIE1_PIPE_CLK] =3D &gcc_pcie1_pipe_clk.clkr, + [GCC_PCIE1_PIPE_CLK_SRC] =3D &gcc_pcie1_pipe_clk_src.clkr, + [GCC_PCIE1_RCHNG_CLK_SRC] =3D &gcc_pcie1_rchng_clk_src.clkr, + [GCC_PCIE1_RCHNG_CLK] =3D &gcc_pcie1_rchng_clk.clkr, + [GCC_PCIE2_AHB_CLK] =3D &gcc_pcie2_ahb_clk.clkr, + [GCC_PCIE2_AUX_CLK] =3D &gcc_pcie2_aux_clk.clkr, + [GCC_PCIE2_AXI_M_CLK] =3D &gcc_pcie2_axi_m_clk.clkr, + [GCC_PCIE2_AXI_M_CLK_SRC] =3D &gcc_pcie2_axi_m_clk_src.clkr, + [GCC_PCIE2_AXI_S_BRIDGE_CLK] =3D &gcc_pcie2_axi_s_bridge_clk.clkr, + [GCC_PCIE2_AXI_S_CLK] =3D &gcc_pcie2_axi_s_clk.clkr, + [GCC_PCIE2_AXI_S_CLK_SRC] =3D &gcc_pcie2_axi_s_clk_src.clkr, + [GCC_PCIE2_PIPE_CLK] =3D &gcc_pcie2_pipe_clk.clkr, + [GCC_PCIE2_PIPE_CLK_SRC] =3D &gcc_pcie2_pipe_clk_src.clkr, + [GCC_PCIE2_RCHNG_CLK_SRC] =3D &gcc_pcie2_rchng_clk_src.clkr, + [GCC_PCIE2_RCHNG_CLK] =3D &gcc_pcie2_rchng_clk.clkr, + [GCC_PCIE3_AHB_CLK] =3D &gcc_pcie3_ahb_clk.clkr, + [GCC_PCIE3_AUX_CLK] =3D &gcc_pcie3_aux_clk.clkr, + [GCC_PCIE3_AXI_M_CLK] =3D &gcc_pcie3_axi_m_clk.clkr, + [GCC_PCIE3_AXI_M_CLK_SRC] =3D &gcc_pcie3_axi_m_clk_src.clkr, + [GCC_PCIE3_AXI_S_BRIDGE_CLK] =3D &gcc_pcie3_axi_s_bridge_clk.clkr, + [GCC_PCIE3_AXI_S_CLK] =3D &gcc_pcie3_axi_s_clk.clkr, + [GCC_PCIE3_AXI_S_CLK_SRC] =3D &gcc_pcie3_axi_s_clk_src.clkr, + [GCC_PCIE3_PIPE_CLK] =3D &gcc_pcie3_pipe_clk.clkr, + [GCC_PCIE3_PIPE_CLK_SRC] =3D &gcc_pcie3_pipe_clk_src.clkr, + [GCC_PCIE3_RCHNG_CLK_SRC] =3D &gcc_pcie3_rchng_clk_src.clkr, + [GCC_PCIE3_RCHNG_CLK] =3D &gcc_pcie3_rchng_clk.clkr, + [GCC_PCIE4_AHB_CLK] =3D &gcc_pcie4_ahb_clk.clkr, + [GCC_PCIE4_AUX_CLK] =3D &gcc_pcie4_aux_clk.clkr, + [GCC_PCIE4_AXI_M_CLK] =3D &gcc_pcie4_axi_m_clk.clkr, + [GCC_PCIE4_AXI_M_CLK_SRC] =3D &gcc_pcie4_axi_m_clk_src.clkr, + [GCC_PCIE4_AXI_S_BRIDGE_CLK] =3D &gcc_pcie4_axi_s_bridge_clk.clkr, + [GCC_PCIE4_AXI_S_CLK] =3D &gcc_pcie4_axi_s_clk.clkr, + [GCC_PCIE4_AXI_S_CLK_SRC] =3D &gcc_pcie4_axi_s_clk_src.clkr, + [GCC_PCIE4_PIPE_CLK] =3D &gcc_pcie4_pipe_clk.clkr, + [GCC_PCIE4_PIPE_CLK_SRC] =3D &gcc_pcie4_pipe_clk_src.clkr, + [GCC_PCIE4_RCHNG_CLK_SRC] =3D &gcc_pcie4_rchng_clk_src.clkr, + [GCC_PCIE4_RCHNG_CLK] =3D &gcc_pcie4_rchng_clk.clkr, + [GCC_PCIE_AUX_CLK_SRC] =3D &gcc_pcie_aux_clk_src.clkr, + [GCC_PCIE_CMN_HCLK] =3D &gcc_pcie_cmn_hclk.clkr, + [GCC_PCIE_CMN_LDO_CLK] =3D &gcc_pcie_cmn_ldo_clk.clkr, + [GCC_PCNOC_BFDCD_CLK_SRC] =3D &gcc_pcnoc_bfdcd_clk_src.clkr, + [GCC_PRIMESS_AHBM_CLK] =3D &gcc_primess_ahbm_clk.clkr, + [GCC_PRIMESS_AHBM_CLK_SRC] =3D &gcc_primess_ahbm_clk_src.clkr, + [GCC_PRIMESS_AHBM_PARTIAL_CLK] =3D &gcc_primess_ahbm_partial_clk.clkr, + [GCC_PRIMESS_AHBS_CLK] =3D &gcc_primess_ahbs_clk.clkr, + [GCC_PRIMESS_ATB_CLK] =3D &gcc_primess_atb_clk.clkr, + [GCC_PRIMESS_AXIM_CLK] =3D &gcc_primess_axim_clk.clkr, + [GCC_PRIMESS_AXIM_CLK_SRC] =3D &gcc_primess_axim_clk_src.clkr, + [GCC_PRIMESS_AXIM_PARTIAL_CLK] =3D &gcc_primess_axim_partial_clk.clkr, + [GCC_PRIMESS_CLK] =3D &gcc_primess_clk.clkr, + [GCC_PRIMESS_CLK_SRC] =3D &gcc_primess_clk_src.clkr, + [GCC_PRIMESS_XO_CLK] =3D &gcc_primess_xo_clk.clkr, + [GCC_QDSS_AT_CLK] =3D &gcc_qdss_at_clk.clkr, + [GCC_QDSS_AT_CLK_SRC] =3D &gcc_qdss_at_clk_src.clkr, + [GCC_QDSS_DAP_CLK] =3D &gcc_qdss_dap_clk.clkr, + [GCC_QDSS_TSCTR_CLK_SRC] =3D &gcc_qdss_tsctr_clk_src.clkr, + [GCC_QPIC_AHB_CLK] =3D &gcc_qpic_ahb_clk.clkr, + [GCC_QPIC_CLK] =3D &gcc_qpic_clk.clkr, + [GCC_QPIC_CLK_SRC] =3D &gcc_qpic_clk_src.clkr, + [GCC_QPIC_IO_MACRO_CLK] =3D &gcc_qpic_io_macro_clk.clkr, + [GCC_QPIC_IO_MACRO_CLK_SRC] =3D &gcc_qpic_io_macro_clk_src.clkr, + [GCC_QPIC_SLEEP_CLK] =3D &gcc_qpic_sleep_clk.clkr, + [GCC_QUPV3_2X_CORE_CLK_SRC] =3D &gcc_qupv3_2x_core_clk_src.clkr, + [GCC_QUPV3_AHB_MST_CLK] =3D &gcc_qupv3_ahb_mst_clk.clkr, + [GCC_QUPV3_AHB_SLV_CLK] =3D &gcc_qupv3_ahb_slv_clk.clkr, + [GCC_QUPV3_WRAP_SE0_CLK] =3D &gcc_qupv3_wrap_se0_clk.clkr, + [GCC_QUPV3_WRAP_SE0_CLK_SRC] =3D &gcc_qupv3_wrap_se0_clk_src.clkr, + [GCC_QUPV3_WRAP_SE1_CLK] =3D &gcc_qupv3_wrap_se1_clk.clkr, + [GCC_QUPV3_WRAP_SE1_CLK_SRC] =3D &gcc_qupv3_wrap_se1_clk_src.clkr, + [GCC_QUPV3_WRAP_SE2_CLK] =3D &gcc_qupv3_wrap_se2_clk.clkr, + [GCC_QUPV3_WRAP_SE2_CLK_SRC] =3D &gcc_qupv3_wrap_se2_clk_src.clkr, + [GCC_QUPV3_WRAP_SE3_CLK] =3D &gcc_qupv3_wrap_se3_clk.clkr, + [GCC_QUPV3_WRAP_SE3_CLK_SRC] =3D &gcc_qupv3_wrap_se3_clk_src.clkr, + [GCC_QUPV3_WRAP_SE4_CLK] =3D &gcc_qupv3_wrap_se4_clk.clkr, + [GCC_QUPV3_WRAP_SE4_CLK_SRC] =3D &gcc_qupv3_wrap_se4_clk_src.clkr, + [GCC_QUPV3_WRAP_SE5_CLK] =3D &gcc_qupv3_wrap_se5_clk.clkr, + [GCC_QUPV3_WRAP_SE5_CLK_SRC] =3D &gcc_qupv3_wrap_se5_clk_src.clkr, + [GCC_QUPV3_WRAP_SE6_CLK] =3D &gcc_qupv3_wrap_se6_clk.clkr, + [GCC_QUPV3_WRAP_SE6_CLK_SRC] =3D &gcc_qupv3_wrap_se6_clk_src.clkr, + [GCC_QUPV3_WRAP_SE7_CLK] =3D &gcc_qupv3_wrap_se7_clk.clkr, + [GCC_QUPV3_WRAP_SE7_CLK_SRC] =3D &gcc_qupv3_wrap_se7_clk_src.clkr, + [GCC_REFGEN_CORE_CLK_SRC] =3D &gcc_refgen_core_clk_src.clkr, + [GCC_REFGEN_PCIE_CORE_CLK] =3D &gcc_refgen_pcie_core_clk.clkr, + [GCC_REFGEN_PCIE_HCLK] =3D &gcc_refgen_pcie_hclk.clkr, + [GCC_SDCC1_AHB_CLK] =3D &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] =3D &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC1_APPS_CLK_SRC] =3D &gcc_sdcc1_apps_clk_src.clkr, + [GCC_SDCC1_ICE_CORE_CLK] =3D &gcc_sdcc1_ice_core_clk.clkr, + [GCC_SDCC1_ICE_CORE_CLK_SRC] =3D &gcc_sdcc1_ice_core_clk_src.clkr, + [GCC_SLEEP_CLK_SRC] =3D &gcc_sleep_clk_src.clkr, + [GCC_SNOC_USB_CLK] =3D &gcc_snoc_usb_clk.clkr, + [GCC_SYSTEM_NOC_BFDCD_CLK_SRC] =3D &gcc_system_noc_bfdcd_clk_src.clkr, + [GCC_UNIPHY0_AHB_CLK] =3D &gcc_uniphy0_ahb_clk.clkr, + [GCC_UNIPHY0_SYS_CLK] =3D &gcc_uniphy0_sys_clk.clkr, + [GCC_UNIPHY1_AHB_CLK] =3D &gcc_uniphy1_ahb_clk.clkr, + [GCC_UNIPHY1_SYS_CLK] =3D &gcc_uniphy1_sys_clk.clkr, + [GCC_UNIPHY2_AHB_CLK] =3D &gcc_uniphy2_ahb_clk.clkr, + [GCC_UNIPHY2_SYS_CLK] =3D &gcc_uniphy2_sys_clk.clkr, + [GCC_UNIPHY_SYS_CLK_SRC] =3D &gcc_uniphy_sys_clk_src.clkr, + [GCC_USB0_AUX_CLK] =3D &gcc_usb0_aux_clk.clkr, + [GCC_USB0_AUX_CLK_SRC] =3D &gcc_usb0_aux_clk_src.clkr, + [GCC_USB0_EUD_AT_CLK] =3D &gcc_usb0_eud_at_clk.clkr, + [GCC_USB0_MASTER_CLK] =3D &gcc_usb0_master_clk.clkr, + [GCC_USB0_MASTER_CLK_SRC] =3D &gcc_usb0_master_clk_src.clkr, + [GCC_USB0_MOCK_UTMI_CLK] =3D &gcc_usb0_mock_utmi_clk.clkr, + [GCC_USB0_MOCK_UTMI_CLK_SRC] =3D &gcc_usb0_mock_utmi_clk_src.clkr, + [GCC_USB0_MOCK_UTMI_DIV_CLK_SRC] =3D &gcc_usb0_mock_utmi_div_clk_src.clkr, + [GCC_USB0_PHY_CFG_AHB_CLK] =3D &gcc_usb0_phy_cfg_ahb_clk.clkr, + [GCC_USB0_PIPE_CLK] =3D &gcc_usb0_pipe_clk.clkr, + [GCC_USB0_PIPE_CLK_SRC] =3D &gcc_usb0_pipe_clk_src.clkr, + [GCC_USB0_SLEEP_CLK] =3D &gcc_usb0_sleep_clk.clkr, + [GCC_USB1_MASTER_CLK] =3D &gcc_usb1_master_clk.clkr, + [GCC_USB1_MOCK_UTMI_CLK] =3D &gcc_usb1_mock_utmi_clk.clkr, + [GCC_USB1_MOCK_UTMI_CLK_SRC] =3D &gcc_usb1_mock_utmi_clk_src.clkr, + [GCC_USB1_MOCK_UTMI_DIV_CLK_SRC] =3D &gcc_usb1_mock_utmi_div_clk_src.clkr, + [GCC_USB1_PHY_CFG_AHB_CLK] =3D &gcc_usb1_phy_cfg_ahb_clk.clkr, + [GCC_USB1_SLEEP_CLK] =3D &gcc_usb1_sleep_clk.clkr, + [GCC_USB_CMN_HCLK] =3D &gcc_usb_cmn_hclk.clkr, + [GCC_USB_CMN_LDO_CLK] =3D &gcc_usb_cmn_ldo_clk.clkr, + [GCC_XO_CLK_SRC] =3D &gcc_xo_clk_src.clkr, + [GPLL0_MAIN] =3D &gpll0_main.clkr, + [GPLL0] =3D &gpll0.clkr, + [GPLL2] =3D &gpll2.clkr, + [GPLL2_OUT_MAIN] =3D &gpll2_out_main.clkr, + [GPLL4] =3D &gpll4.clkr, +}; + +static const struct qcom_reset_map gcc_ipq9650_resets[] =3D { + [GCC_ADSS_BCR] =3D { 0x1c000 }, + [GCC_ADSS_PWM_CLK_ARES] =3D { 0x1c00c, 2 }, + [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] =3D { 0x38000 }, + [GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES] =3D { 0x3800c, 2 }, + [GCC_APSS_AHB_CLK_ARES] =3D { 0x24014, 2 }, + [GCC_APSS_ATB_CLK_ARES] =3D { 0x24034, 2 }, + [GCC_APSS_AXI_CLK_ARES] =3D { 0x24018, 2 }, + [GCC_APSS_TS_CLK_ARES] =3D { 0x24030, 2 }, + [GCC_BOOT_ROM_AHB_CLK_ARES] =3D { 0x1302c, 2 }, + [GCC_BOOT_ROM_BCR] =3D { 0x13028 }, + [GCC_CPUSS_TRIG_CLK_ARES] =3D { 0x2401c, 2 }, + [GCC_GP1_CLK_ARES] =3D { 0x8018, 2 }, + [GCC_GP2_CLK_ARES] =3D { 0x8030, 2 }, + [GCC_GP3_CLK_ARES] =3D { 0x8048, 2 }, + [GCC_MDIO_AHB_CLK_ARES] =3D { 0x17040, 2 }, + [GCC_MDIO_BCR] =3D { 0x1703c }, + [GCC_NSS_BCR] =3D { 0x17000 }, + [GCC_NSS_TS_CLK_ARES] =3D { 0x17018, 2 }, + [GCC_NSSCC_CLK_ARES] =3D { 0x17034, 2 }, + [GCC_NSSCFG_CLK_ARES] =3D { 0x1702c, 2 }, + [GCC_NSSNOC_ATB_CLK_ARES] =3D { 0x17014, 2 }, + [GCC_NSSNOC_MEMNOC_1_CLK_ARES] =3D { 0x17084, 2 }, + [GCC_NSSNOC_MEMNOC_CLK_ARES] =3D { 0x17024, 2 }, + [GCC_NSSNOC_NSSCC_CLK_ARES] =3D { 0x17030, 2 }, + [GCC_NSSNOC_PCNOC_1_CLK_ARES] =3D { 0x17080, 2 }, + [GCC_NSSNOC_QOSGEN_REF_CLK_ARES] =3D { 0x1701c, 2 }, + [GCC_NSSNOC_SNOC_1_CLK_ARES] =3D { 0x1707c, 2 }, + [GCC_NSSNOC_SNOC_CLK_ARES] =3D { 0x17028, 2 }, + [GCC_NSSNOC_TIMEOUT_REF_CLK_ARES] =3D { 0x17020, 2 }, + [GCC_NSSNOC_XO_DCD_CLK_ARES] =3D { 0x17074, 2 }, + [GCC_PCIE0_AHB_CLK_ARES] =3D { 0x28030, 2 }, + [GCC_PCIE0_AUX_CLK_ARES] =3D { 0x28070, 2 }, + [GCC_PCIE0_AXI_M_CLK_ARES] =3D { 0x28038, 2 }, + [GCC_PCIE0_AXI_S_BRIDGE_CLK_ARES] =3D { 0x28048, 2 }, + [GCC_PCIE0_AXI_S_CLK_ARES] =3D { 0x28040, 2 }, + [GCC_PCIE0_BCR] =3D { 0x28000 }, + [GCC_PCIE0_LINK_DOWN_BCR] =3D { 0x28054 }, + [GCC_PCIE0_PHY_BCR] =3D { 0x28060 }, + [GCC_PCIE0_PIPE_CLK_ARES] =3D { 0x28068, 2 }, + [GCC_PCIE0PHY_PHY_BCR] =3D { 0x2805c }, + [GCC_PCIE0_PIPE_RESET] =3D { 0x28058, 0 }, + [GCC_PCIE0_CORE_STICKY_RESET] =3D { 0x28058, 1 }, + [GCC_PCIE0_AXI_S_STICKY_RESET] =3D { 0x28058, 2 }, + [GCC_PCIE0_AXI_S_RESET] =3D { 0x28058, 3 }, + [GCC_PCIE0_AXI_M_STICKY_RESET] =3D { 0x28058, 4 }, + [GCC_PCIE0_AXI_M_RESET] =3D { 0x28058, 5 }, + [GCC_PCIE0_AUX_RESET] =3D { 0x28058, 6 }, + [GCC_PCIE0_AHB_RESET] =3D { 0x28058, 7 }, + [GCC_PCIE1_AHB_CLK_ARES] =3D { 0x29030, 2 }, + [GCC_PCIE1_AUX_CLK_ARES] =3D { 0x29074, 2 }, + [GCC_PCIE1_AXI_M_CLK_ARES] =3D { 0x29038, 2 }, + [GCC_PCIE1_AXI_S_BRIDGE_CLK_ARES] =3D { 0x29048, 2 }, + [GCC_PCIE1_AXI_S_CLK_ARES] =3D { 0x29040, 2 }, + [GCC_PCIE1_BCR] =3D { 0x29000 }, + [GCC_PCIE1_LINK_DOWN_BCR] =3D { 0x29054 }, + [GCC_PCIE1_PHY_BCR] =3D { 0x29060 }, + [GCC_PCIE1_PIPE_CLK_ARES] =3D { 0x29068, 2 }, + [GCC_PCIE1PHY_PHY_BCR] =3D { 0x2905c }, + [GCC_PCIE1_PIPE_RESET] =3D { 0x29058, 0 }, + [GCC_PCIE1_CORE_STICKY_RESET] =3D { 0x29058, 1 }, + [GCC_PCIE1_AXI_S_STICKY_RESET] =3D { 0x29058, 2 }, + [GCC_PCIE1_AXI_S_RESET] =3D { 0x29058, 3 }, + [GCC_PCIE1_AXI_M_STICKY_RESET] =3D { 0x29058, 4 }, + [GCC_PCIE1_AXI_M_RESET] =3D { 0x29058, 5 }, + [GCC_PCIE1_AUX_RESET] =3D { 0x29058, 6 }, + [GCC_PCIE1_AHB_RESET] =3D { 0x29058, 7 }, + [GCC_PCIE2_AHB_CLK_ARES] =3D { 0x2a030, 2 }, + [GCC_PCIE2_AUX_CLK_ARES] =3D { 0x2a078, 2 }, + [GCC_PCIE2_AXI_M_CLK_ARES] =3D { 0x2a038, 2 }, + [GCC_PCIE2_AXI_S_BRIDGE_CLK_ARES] =3D { 0x2a048, 2 }, + [GCC_PCIE2_AXI_S_CLK_ARES] =3D { 0x2a040, 2 }, + [GCC_PCIE2_BCR] =3D { 0x2a000 }, + [GCC_PCIE2_LINK_DOWN_BCR] =3D { 0x2a054 }, + [GCC_PCIE2_PHY_BCR] =3D { 0x2a060 }, + [GCC_PCIE2_PIPE_CLK_ARES] =3D { 0x2a068, 2 }, + [GCC_PCIE2PHY_PHY_BCR] =3D { 0x2a05c }, + [GCC_PCIE2_PIPE_RESET] =3D { 0x2a058, 0 }, + [GCC_PCIE2_CORE_STICKY_RESET] =3D { 0x2a058, 1 }, + [GCC_PCIE2_AXI_S_STICKY_RESET] =3D { 0x2a058, 2 }, + [GCC_PCIE2_AXI_S_RESET] =3D { 0x2a058, 3 }, + [GCC_PCIE2_AXI_M_STICKY_RESET] =3D { 0x2a058, 4 }, + [GCC_PCIE2_AXI_M_RESET] =3D { 0x2a058, 5 }, + [GCC_PCIE2_AUX_RESET] =3D { 0x2a058, 6 }, + [GCC_PCIE2_AHB_RESET] =3D { 0x2a058, 7 }, + [GCC_PCIE3_AHB_CLK_ARES] =3D { 0x2b030, 2 }, + [GCC_PCIE3_AUX_CLK_ARES] =3D { 0x2b07c, 2 }, + [GCC_PCIE3_AXI_M_CLK_ARES] =3D { 0x2b038, 2 }, + [GCC_PCIE3_AXI_S_BRIDGE_CLK_ARES] =3D { 0x2b048, 2 }, + [GCC_PCIE3_AXI_S_CLK_ARES] =3D { 0x2b040, 2 }, + [GCC_PCIE3_BCR] =3D { 0x2b000 }, + [GCC_PCIE3_LINK_DOWN_BCR] =3D { 0x2b054 }, + [GCC_PCIE3_PHY_BCR] =3D { 0x2b060 }, + [GCC_PCIE3_PIPE_CLK_ARES] =3D { 0x2b068, 2 }, + [GCC_PCIE3PHY_PHY_BCR] =3D { 0x2b05c }, + [GCC_PCIE3_PIPE_RESET] =3D { 0x2b058, 0 }, + [GCC_PCIE3_CORE_STICKY_RESET] =3D { 0x2b058, 1 }, + [GCC_PCIE3_AXI_S_STICKY_RESET] =3D { 0x2b058, 2 }, + [GCC_PCIE3_AXI_S_RESET] =3D { 0x2b058, 3 }, + [GCC_PCIE3_AXI_M_STICKY_RESET] =3D { 0x2b058, 4 }, + [GCC_PCIE3_AXI_M_RESET] =3D { 0x2b058, 5 }, + [GCC_PCIE3_AUX_RESET] =3D { 0x2b058, 6 }, + [GCC_PCIE3_AHB_RESET] =3D { 0x2b058, 7 }, + [GCC_PCIE4_AHB_CLK_ARES] =3D { 0x2501c, 2 }, + [GCC_PCIE4_AUX_CLK_ARES] =3D { 0x25020, 2 }, + [GCC_PCIE4_AXI_M_CLK_ARES] =3D { 0x25028, 2 }, + [GCC_PCIE4_AXI_S_BRIDGE_CLK_ARES] =3D { 0x25038, 2 }, + [GCC_PCIE4_AXI_S_CLK_ARES] =3D { 0x25030, 2 }, + [GCC_PCIE4_BCR] =3D { 0x25000 }, + [GCC_PCIE4_LINK_DOWN_BCR] =3D { 0x25044 }, + [GCC_PCIE4_PHY_BCR] =3D { 0x2504c }, + [GCC_PCIE4_PIPE_CLK_ARES] =3D { 0x2503c, 2 }, + [GCC_PCIE4_PIPE_RESET] =3D { 0x25054, 0 }, + [GCC_PCIE4_CORE_STICKY_RESET] =3D { 0x25054, 1 }, + [GCC_PCIE4_AXI_S_STICKY_RESET] =3D { 0x25054, 2 }, + [GCC_PCIE4_AXI_S_RESET] =3D { 0x25054, 3 }, + [GCC_PCIE4_AXI_M_STICKY_RESET] =3D { 0x25054, 4 }, + [GCC_PCIE4_AXI_M_RESET] =3D { 0x25054, 5 }, + [GCC_PCIE4_AUX_RESET] =3D { 0x25054, 6 }, + [GCC_PCIE4_AHB_RESET] =3D { 0x25054, 7 }, + [GCC_PCIE4PHY_PHY_BCR] =3D { 0x25048 }, + [GCC_PCIE_CMN_LDO_BCR] =3D { 0x23028 }, + [GCC_PRIME_SS_BCR] =3D { 0x26004 }, + [GCC_PRIMESS_AHBM_CLK_ARES] =3D { 0x26038, 2 }, + [GCC_PRIMESS_AHBM_PARTIAL_CLK_ARES] =3D { 0x26040, 2 }, + [GCC_PRIMESS_AHBS_CLK_ARES] =3D { 0x26034, 2 }, + [GCC_PRIMESS_ATB_CLK_ARES] =3D { 0x26030, 2 }, + [GCC_PRIMESS_AXIM_CLK_ARES] =3D { 0x2602c, 2 }, + [GCC_PRIMESS_AXIM_PARTIAL_CLK_ARES] =3D { 0x2603c, 2 }, + [GCC_PRIMESS_CLK_ARES] =3D { 0x26028, 2 }, + [GCC_PRIMESS_XO_CLK_ARES] =3D { 0x26024, 2 }, + [GCC_QDSS_APB2JTAG_CLK_ARES] =3D { 0x2d05c, 2 }, + [GCC_QDSS_AT_CLK_ARES] =3D { 0x2d034, 2 }, + [GCC_QDSS_BCR] =3D { 0x2d000 }, + [GCC_QDSS_CFG_AHB_CLK_ARES] =3D { 0x2d068, 2 }, + [GCC_QDSS_DAP_AHB_CLK_ARES] =3D { 0x2d064, 2 }, + [GCC_QDSS_DAP_CLK_ARES] =3D { 0x2d058, 2 }, + [GCC_QDSS_ETR_USB_CLK_ARES] =3D { 0x2d060, 2 }, + [GCC_QDSS_EUD_AT_CLK_ARES] =3D { 0x2d06c, 2 }, + [GCC_QDSS_STM_CLK_ARES] =3D { 0x2d03c, 2 }, + [GCC_QDSS_TRACECLKIN_CLK_ARES] =3D { 0x2d040, 2 }, + [GCC_QDSS_TS_CLK_ARES] =3D { 0x2d078, 2 }, + [GCC_QDSS_TSCTR_DIV16_CLK_ARES] =3D { 0x2d054, 2 }, + [GCC_QDSS_TSCTR_DIV2_CLK_ARES] =3D { 0x2d044, 2 }, + [GCC_QDSS_TSCTR_DIV3_CLK_ARES] =3D { 0x2d048, 2 }, + [GCC_QDSS_TSCTR_DIV4_CLK_ARES] =3D { 0x2d04c, 2 }, + [GCC_QDSS_TSCTR_DIV8_CLK_ARES] =3D { 0x2d050, 2 }, + [GCC_QPIC_AHB_CLK_ARES] =3D { 0x32010, 2 }, + [GCC_QPIC_CLK_ARES] =3D { 0x32028, 2 }, + [GCC_QPIC_BCR] =3D { 0x32000 }, + [GCC_QPIC_IO_MACRO_CLK_ARES] =3D { 0x3200c, 2 }, + [GCC_QPIC_SLEEP_CLK_ARES] =3D { 0x32018, 2 }, + [GCC_QUPV3_2X_CORE_CLK_ARES] =3D { 0x1020, 2 }, + [GCC_QUPV3_AHB_MST_CLK_ARES] =3D { 0x1014, 2 }, + [GCC_QUPV3_AHB_SLV_CLK_ARES] =3D { 0x102c, 2 }, + [GCC_QUPV3_BCR] =3D { 0x1000 }, + [GCC_QUPV3_CORE_CLK_ARES] =3D { 0x1018, 2 }, + [GCC_QUPV3_WRAP_SE0_CLK_ARES] =3D { 0x202c, 2 }, + [GCC_QUPV3_WRAP_SE0_BCR] =3D { 0x2000 }, + [GCC_QUPV3_WRAP_SE1_CLK_ARES] =3D { 0x302c, 2 }, + [GCC_QUPV3_WRAP_SE1_BCR] =3D { 0x3000 }, + [GCC_QUPV3_WRAP_SE2_CLK_ARES] =3D { 0x3048, 2 }, + [GCC_QUPV3_WRAP_SE2_BCR] =3D { 0x3030 }, + [GCC_QUPV3_WRAP_SE3_CLK_ARES] =3D { 0x3064, 2 }, + [GCC_QUPV3_WRAP_SE3_BCR] =3D { 0x304c }, + [GCC_QUPV3_WRAP_SE4_CLK_ARES] =3D { 0x3080, 2 }, + [GCC_QUPV3_WRAP_SE4_BCR] =3D { 0x3068 }, + [GCC_QUPV3_WRAP_SE5_CLK_ARES] =3D { 0x30a4, 2 }, + [GCC_QUPV3_WRAP_SE5_BCR] =3D { 0x308c }, + [GCC_QUPV3_WRAP_SE6_CLK_ARES] =3D { 0x4018, 2 }, + [GCC_QUPV3_WRAP_SE6_BCR] =3D { 0x4000 }, + [GCC_QUPV3_WRAP_SE7_CLK_ARES] =3D { 0x4034, 2 }, + [GCC_QUPV3_WRAP_SE7_BCR] =3D { 0x401c }, + [GCC_QUSB2_0_PHY_BCR] =3D { 0x2c068 }, + [GCC_QUSB2_1_PHY_BCR] =3D { 0x3c030 }, + [GCC_REFGEN_PCIE_BCR] =3D { 0x2301c }, + [GCC_REFGEN_PCIE_CORE_CLK_ARES] =3D { 0x23020, 2 }, + [GCC_SDCC1_APPS_CLK_ARES] =3D { 0x3302c, 2 }, + [GCC_SDCC1_ICE_CORE_CLK_ARES] =3D { 0x33034, 2 }, + [GCC_SDCC_BCR] =3D { 0x33000 }, + [GCC_TLMM_AHB_CLK_ARES] =3D { 0x3e004, 2 }, + [GCC_TLMM_CLK_ARES] =3D { 0x3e008, 2 }, + [GCC_TLMM_BCR] =3D { 0x3e000 }, + [GCC_UNIPHY0_AHB_CLK_ARES] =3D { 0x1704c, 2 }, + [GCC_UNIPHY0_BCR] =3D { 0x17044 }, + [GCC_UNIPHY0_PMA_BCR] =3D { 0x17098 }, + [GCC_UNIPHY0_SYS_CLK_ARES] =3D { 0x17048, 2 }, + [GCC_UNIPHY1_AHB_CLK_ARES] =3D { 0x1705c, 2 }, + [GCC_UNIPHY1_BCR] =3D { 0x17054 }, + [GCC_UNIPHY1_PMA_BCR] =3D { 0x1709c }, + [GCC_UNIPHY1_SYS_CLK_ARES] =3D { 0x17058, 2 }, + [GCC_UNIPHY2_AHB_CLK_ARES] =3D { 0x1706c, 2 }, + [GCC_UNIPHY2_BCR] =3D { 0x17064 }, + [GCC_UNIPHY2_PMA_BCR] =3D { 0x170a0 }, + [GCC_UNIPHY2_SYS_CLK_ARES] =3D { 0x17068, 2 }, + [GCC_UNIPHY0_XPCS_ARES] =3D { 0x17050, 2 }, + [GCC_UNIPHY1_XLGPCS_ARES] =3D { 0x17060, 1 }, + [GCC_UNIPHY1_XPCS_ARES] =3D { 0x17060, 2 }, + [GCC_UNIPHY2_XLGPCS_ARES] =3D { 0x17070, 1 }, + [GCC_UNIPHY2_XPCS_ARES] =3D { 0x17070, 2 }, + [GCC_USB0_AUX_CLK_ARES] =3D { 0x2c04c, 2 }, + [GCC_USB0_MASTER_CLK_ARES] =3D { 0x2c044, 2 }, + [GCC_USB0_MOCK_UTMI_CLK_ARES] =3D { 0x2c050, 2 }, + [GCC_USB0_PHY_BCR] =3D { 0x2c06c }, + [GCC_USB0_PHY_CFG_AHB_CLK_ARES] =3D { 0x2c05c, 2 }, + [GCC_USB0_PIPE_CLK_ARES] =3D { 0x2c054, 2 }, + [GCC_USB0_SLEEP_CLK_ARES] =3D { 0x2c058, 2 }, + [GCC_USB1_BCR] =3D { 0x3c000 }, + [GCC_USB1_MASTER_CLK_ARES] =3D { 0x3c028, 2 }, + [GCC_USB1_MOCK_UTMI_CLK_ARES] =3D { 0x3c024, 2 }, + [GCC_USB1_PHY_CFG_AHB_CLK_ARES] =3D { 0x3c01c, 2 }, + [GCC_USB1_SLEEP_CLK_ARES] =3D { 0x3c020, 2 }, + [GCC_USB3PHY_0_PHY_BCR] =3D { 0x2c070 }, + [GCC_USB_BCR] =3D { 0x2c000 }, + [GCC_USB_CMN_LDO_BCR] =3D { 0x23034 }, +}; + +static const struct of_device_id gcc_ipq9650_match_table[] =3D { + { .compatible =3D "qcom,ipq9650-gcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_ipq9650_match_table); + +static const struct regmap_config gcc_ipq9650_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x3f024, + .fast_io =3D true, +}; + +static struct clk_hw *gcc_ipq9650_hws[] =3D { + &gpll0_div2.hw, + &gcc_xo_div4_clk_src.hw, + &gcc_qdss_dap_sync_clk_src.hw, + &gcc_eud_at_div_clk_src.hw, +}; + +static const struct qcom_cc_desc gcc_ipq9650_desc =3D { + .config =3D &gcc_ipq9650_regmap_config, + .clks =3D gcc_ipq9650_clocks, + .num_clks =3D ARRAY_SIZE(gcc_ipq9650_clocks), + .resets =3D gcc_ipq9650_resets, + .num_resets =3D ARRAY_SIZE(gcc_ipq9650_resets), + .clk_hws =3D gcc_ipq9650_hws, + .num_clk_hws =3D ARRAY_SIZE(gcc_ipq9650_hws), +}; + +static int gcc_ipq9650_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gcc_ipq9650_desc); +} + +static struct platform_driver gcc_ipq9650_driver =3D { + .probe =3D gcc_ipq9650_probe, + .driver =3D { + .name =3D "qcom,gcc-ipq9650", + .of_match_table =3D gcc_ipq9650_match_table, + }, +}; + +static int __init gcc_ipq9650_init(void) +{ + return platform_driver_register(&gcc_ipq9650_driver); +} +core_initcall(gcc_ipq9650_init); + +static void __exit gcc_ipq9650_exit(void) +{ + platform_driver_unregister(&gcc_ipq9650_driver); +} +module_exit(gcc_ipq9650_exit); + +MODULE_DESCRIPTION("QTI GCC IPQ9650 Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Tue Jun 16 19:36:52 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B63D1378D74 for ; Wed, 29 Apr 2026 15:24:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777476297; cv=none; b=cDZeeewEyJfnErNF+XQYxJX+tqKC6Xh+5F8oekxXSEUWqLvra/cCfTqWrwsLwhsXcD6w1BJBWnshwjg10AC7iNBaK1867EpIfZW/NMhpDc+t+5D+O+0rgMrqRvCv7jGS/413pyvCyhy+k3StoDv9IdKlpAqESYgX4orozYpq5KU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777476297; c=relaxed/simple; bh=AjymDrwSTwOmf+14wlE4sp4uE3esnCFm6QfMo2Rljqo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IBFZru9krcsYOXAfJ4TQRhI/RHx/zhcnW3TimEnUpse9BTeclJ9rCLL7q6/U7Pe+NSiIcrg/b1OT3SHn7gWyq3muVJFOpNckiOinxG8Ua7GMU6LV41I9RZocbN2tmAN3bVHrKLBfEIX0+SJYpPlDp1xw3PDnK+mtvD0ltcAHBf0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=N8oqG2jD; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=jPQ6/FwD; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="N8oqG2jD"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="jPQ6/FwD" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 63TEQhUL1797251 for ; Wed, 29 Apr 2026 15:24:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= vq3mUikISBUWPMEsDJ3y9/npean2U4ruSFjDqwFpI4I=; b=N8oqG2jDWombJYvq tZsB63F2YmRClEKLURoKXuOpMS/B6byGpue31iVLZROIriU/aLbommp1WCdYe6aG bz4gG5U0cVSLqPYKL9GdwnTknbSGu8E8ZAJVpDWLMCZSQvvEfmAdUGdf1XtBuTfJ oczLT90+JMv7uR8vCE1Ts9Mg8TKcS5LBIouSD3RVp9Gwt40VVyzH624Z/8ZNWZaN cBjzwH9ys8Gax5ULFSEz6Fr3gY62cm/3IiecRfhS0wpePgTeZxIh4/3na6obVRcD 0PUGbyd0iKZ7Qcs/DnwQY/kjusRmZ3x77OTncVtmDB7SO98WIivai2H9Jm8R4704 Nr3TDQ== Received: from mail-pj1-f71.google.com (mail-pj1-f71.google.com [209.85.216.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dukrp075c-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 29 Apr 2026 15:24:56 +0000 (GMT) Received: by mail-pj1-f71.google.com with SMTP id 98e67ed59e1d1-3649e59f0ddso1254631a91.2 for ; Wed, 29 Apr 2026 08:24:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1777476295; x=1778081095; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=vq3mUikISBUWPMEsDJ3y9/npean2U4ruSFjDqwFpI4I=; b=jPQ6/FwDtJanM0DyDNhpAQO7U1HzRvaZW9XSIQwJha20Z1Y10lrrar1cILecs8q/jM iUNl8q7hMImBzfRK/CDq9y6U8VFi0Cyi+I8cHMaQ6rImToN+4U44w3VWvj+aX0EV/wRD DeA6T5zZUv9ajNk4UbRig+0ij+uvCo0fJ5ozfhn8IZ7fRWIWrWzlkKvFCUm61PKMjRpd vhDKo1TAe/Ho6MJqASmFRCRjljhCbZkANV/eYoiINn0IVkqTLRnZEYDanuPfG9qHiFqq NLW8dWqt/bkCjBD+y1a5CTCjU9zHaw7iT/s78v7A3rLFByxB4i3rgBpaoAY2ZqmyI+iH epVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777476295; x=1778081095; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=vq3mUikISBUWPMEsDJ3y9/npean2U4ruSFjDqwFpI4I=; b=ZHaJigh548uCZbyMMH3Br0NBaeMg5SKh70NNlC0m2ViYlYcK/fWOIOy1d+ciqibnER o87/fVo7RJFL4O6+V884pbgOIKcHa+4PRywJ8YLQRQSsxUhdRnnokbRZOiV2PflSoQMC EAt+/7qnJxiyrkWDMHPkLHnR8NptMCq/R5Nd5lVwgJdihaNbYMPC22FudN5ZtcHAtTFk ltMhgLka2zsO4KQLyYvfPXvjoZYrcAQs/8NW0FWnZUGbzP4/ovoI0o1fN+0qamOf7Olo BAG9/fnZZhvAcTE1RJ1odKWxbHmxgP3CQfJvmzaeFCtD5GtNoziu4DhtJfKLB9BfqSCn kmOA== X-Forwarded-Encrypted: i=1; AFNElJ+ZdRdHmcMR0Gv+CmTso2H1sYNJAbQsrAKxyqzcxb0B73TDgnkTyteSkS8yoBDeAnENLBGBbGviQD3YcFk=@vger.kernel.org X-Gm-Message-State: AOJu0YwOZeOnptpSWTvacUOIIOxmslWakYJsWR9JS2kmQM2+bETaKZMh 9abd1+ixNb+l4KckfEGl+Sb55uWxhg+dg/gwRnJyphTO2eWk9m4Dpi6UbGEPU0kXDE+ebJT2GIZ k4SbLYgKvnDWRAeUh9j0PFaJeG8Mr6wYrnrdHHWEz1+yt+9o03Uic41Rk2LK/iaTSUPY= X-Gm-Gg: AeBDievxq7JK5L/QWRpLufUJSccLQz3xQ52Qz9GFm3RJpbXJfM3ElEAPrGfBO0yVXyc LXlIhybbz25VaZDruj/PaNFrPzMbQiYp3OUf30GbRLwe/IvQRU7yB0MQx3FznjPgpbtea+3DTZI zlSxZicSPGQ2dUReudsEZJedwVNbs06jXj4IwYatoh+TKkf1lUzqLwhQFeE9ocDR382BjVFZyaJ jfOb4EIP41bVLfaiWJjgFHdevAYTlvTTDJMbGDOuHUNhLkZZTn2xewhcmYpM1agbA4x/V5KTJ2u priLbwBu7UUtC15Oe082rzig8olqq3ExlxVHYY0Jhw1VqS7UKt+MmL8YmTqncXtEeFv3wEPf2k8 lO/deTOSHDAaRG1vzMfe46ybAR0EtQf6AcU3FXUtbeEhN99njxHNtqr9kaaqi9GJI828EPkDTpT /cZKrVX2TJ1qfamesLg5bkI56TWBsZw53dtnj4JIeJYnfNTpLPtVQ/1XQ5Ilqc26pKgO0= X-Received: by 2002:a17:90b:5444:b0:35d:9f7c:142c with SMTP id 98e67ed59e1d1-36492055f11mr8811665a91.26.1777476295004; Wed, 29 Apr 2026 08:24:55 -0700 (PDT) X-Received: by 2002:a17:90b:5444:b0:35d:9f7c:142c with SMTP id 98e67ed59e1d1-36492055f11mr8811612a91.26.1777476294352; Wed, 29 Apr 2026 08:24:54 -0700 (PDT) Received: from hu-kathirav-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-364bd588ad5sm66732a91.3.2026.04.29.08.24.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Apr 2026 08:24:52 -0700 (PDT) From: Kathiravan Thirumoorthy Date: Wed, 29 Apr 2026 20:54:24 +0530 Subject: [PATCH v2 3/4] dt-bindings: qcom: add IPQ9650 boards Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260429-ipq9650_boot_to_shell-v2-3-9b0dc3d1f3a8@oss.qualcomm.com> References: <20260429-ipq9650_boot_to_shell-v2-0-9b0dc3d1f3a8@oss.qualcomm.com> In-Reply-To: <20260429-ipq9650_boot_to_shell-v2-0-9b0dc3d1f3a8@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kathiravan Thirumoorthy , Krzysztof Kozlowski X-Mailer: b4 0.15.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1777476269; l=894; i=kathiravan.thirumoorthy@oss.qualcomm.com; s=20230906; h=from:subject:message-id; bh=AjymDrwSTwOmf+14wlE4sp4uE3esnCFm6QfMo2Rljqo=; b=ZiGr36yeLWDWz/rwMpos3EpHE6sMlPJGhdwRjn53GQe03ljyPYrbSrZitAR0iHT9+PWL07Hzs eLR2oWrl5mlDp3lpObDcbE0nYeU6EOzow5MCaRcZ17MxBcAHiHVDcBr X-Developer-Key: i=kathiravan.thirumoorthy@oss.qualcomm.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Proofpoint-ORIG-GUID: umSOWneegf5s5kf63e2SlHC5aQx3Lvoc X-Proofpoint-GUID: umSOWneegf5s5kf63e2SlHC5aQx3Lvoc X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI5MDE1NSBTYWx0ZWRfX1GIoJXPiCYOW A0x15Inse+asX4ThSAIsLWJEjvclDWUjv9Eev6TpJVw0Wp3rWvjA/DSu5sr1iOri2s5KLoPrTqi c/kybxJLgm5g9OkoY+DrO65Qq0bUxRRUW/EcOxryf38m94CXbioTXIW+xCFNoKTmgq0bvIPQZ41 aw/8Vc5PD2BAplOaZPxXfWtNf/MTTHNFv6qvp8bp9BWRivvFhUjpgdALHT+EcIP6nyuReShVuTg lt/qBVRKon1lO1RtLyQament1kSwu8I2+5RBIsJO4xQhm1xPsuFhSE8kWGv4i3ivqDCdUm1L6iG 4BGKUXAcGUqiEzdc75X9M/j/KpdM4yT1GexAJq9Z1izmE+RxcoDBSigrdfEslLm6sRNTfwRoNh1 28eGDHww/BiEKXiMXNNmqtUidkz49gDvKdv0rN0kKq7TUx62YzDmiAAWNUU3DorNf+UmsczIPaX fu2rAhT9bwiIQ5WWpvQ== X-Authority-Analysis: v=2.4 cv=WoQb99fv c=1 sm=1 tr=0 ts=69f222c8 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=w0Gmm53Jqs2pEdcyGHcA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-29_01,2026-04-28_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 adultscore=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 suspectscore=0 bulkscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604290155 Document the new IPQ9650 SoC/board device tree bindings. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kathiravan Thirumoorthy --- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index b4943123d2e4..5d0855765fdb 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -365,6 +365,11 @@ properties: - qcom,ipq9574-ap-al02-c9 - const: qcom,ipq9574 =20 + - items: + - enum: + - qcom,ipq9650-rdp488 + - const: qcom,ipq9650 + - items: - enum: - qcom,kaanapali-mtp --=20 2.34.1 From nobody Tue Jun 16 19:36:52 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EEC2837B400 for ; Wed, 29 Apr 2026 15:25:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777476304; cv=none; b=u8zsrHSYp9uOCk5AtxAXQAwCstzJGm4QQ8l4xwwS7SqNpPI4nE0WXNUs+KRsgql+Bv30TLjEfU63e5o/atXu+G+AxgZKqS9xCU1Pq9RPuuTFzG/SGvHTpvCxTFWr8Wt4xJhzMLhQ+Ltok5NZiiJ4raPxmt7UygW6BLYBXfY2/XM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777476304; c=relaxed/simple; bh=J5yfDWjRPOg45bYa1539C2lhtkSrcvJpcd7225W2npA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CjCnx5nyT4mZH3xk7SZwdZdKRq8wljgBRvgl9EzRCG+ixqgz2UaOHHSiHBzrHmaLgbz+8Ym4BGtELopiELzWZqOJHazuZHY0zD4FFTpOyNaEz9QqIm5DTPicaJfplFXySpCdGu6eyZ+t6bx8C1L3YGChucrT1Q7HfS2OMiVyAa4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Col6oXuT; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=kEuAlbz6; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Col6oXuT"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="kEuAlbz6" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 63T8pth32094157 for ; Wed, 29 Apr 2026 15:25:02 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= pBxrTnylXxKJx5MyZsEuxtXxFkSCDa7WzRS0TCgvkKI=; b=Col6oXuT70RWTMIr ukTIGP8Sz9i464t9hnzoYU88uubFi8tUAM5YUIo6L6TN7Tx8SM2gtyom8tpl+stb wmAQkIxaxGazkUsYkj4WPTbPUFMiZGk7NJYWH8HrYmkbcHdyk2PpNXxmuxfS3SkZ 0EazD2NpaFbOSExczcGISOPeuSQDbCbUpFoHPL3ZVUdFaIPcOhSurpqJ/rigFD6A NnFAflNOD3jNFtRKetFGVFri7iGPwk2OLdYHPJlqwbgl5QZ6/xSFBJLSFyla/S0n J9Hw5KZlY2H88IJncJwfkp1ch1CqSVinY0IVQ+/yYDIgsJuBHlbf53Wp2J1aGorz Gpr8GQ== Received: from mail-pj1-f69.google.com (mail-pj1-f69.google.com [209.85.216.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dudh3sxh9-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 29 Apr 2026 15:25:02 +0000 (GMT) Received: by mail-pj1-f69.google.com with SMTP id 98e67ed59e1d1-3649e59f0ddso1254730a91.2 for ; Wed, 29 Apr 2026 08:25:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1777476301; x=1778081101; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=pBxrTnylXxKJx5MyZsEuxtXxFkSCDa7WzRS0TCgvkKI=; b=kEuAlbz6o1y0PDPyLcXnL59z/M/HSlB5xZ1gkU9uO/UrceNo1m7wzncNlEORVGf2oM fBoQaj2kt4QoODU5rei/FGfGEVu3zcyI4aSHhmfjCWTbg/4Q9WsQmeK9K/2bnF+VsT/C +m05Hm6LJt2P3OCoY2awrD4Wsgw9XI73G5CbLGm7fAjKIiiEnywpmpEOf+9FGSpD4UgK 2gcFPpJZMniuLe8oqJMN5GYozaQBLr2bZbdOrlXxMIm+qnXpFOTlieoPd/2STe/uOPMv iss/b6lrsA2tCeF1b2M0LEv86H/Az71ku+1FjonkWPNTCyDqgxsqZIKV7qO3qYqv38GV LUrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777476301; x=1778081101; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=pBxrTnylXxKJx5MyZsEuxtXxFkSCDa7WzRS0TCgvkKI=; b=Sjgf0rPRvorRdxs9hwFBW5EZIvHo+73W65MY/VsoSxT9Rt66ZcfAXCYaBhmVdSXVaE SS/Vsr7sXnzgvEw++PVEkaOW6a4tr3yVMvDcEPruCg5SjVdGPtdzxJR9CLjG+bgVy7Rd c+70LyGyZzhEWcGMnWCNDfM39XO7q26ujHVGMAHrXCO9DV4FNRQynm/toIIHNLPR/C7K tQkLxImsocBB2gImg3zQ5Y+7gupTWr2JUXlk82IKij9Gbl5VdspKQ932r/x0YHOI3kKN RkUjVWTxiH+DLu1KVgbM5WOrtoSladkJcF3jZ2Zfc6G0JjYe+iIe4JZ916Xevt4v/QrQ YlEg== X-Forwarded-Encrypted: i=1; AFNElJ8nvzzbQkFNfe9Iov7fmjJXT9IzzVtM5jdV2lpcOzBOxqjJMZiVM1Gc3s7/vtpMGXPr0OOKDzqQpgQkfUw=@vger.kernel.org X-Gm-Message-State: AOJu0YyNs4m7KTtJnIRTrPcasyJuHqL9wnczNZikUQsSvsU5GfZLemHP RmehbIfz8yztW5MxVv9Z9X+ORNGX1vGyaEGf/3O/SD9d7XAbLXbZYn2THt+legkIyGYuPvJfVA0 +IC7AK8FceniczH2i1FeJAHS3UJIRgfyFlE1NsdbtguLQ/qe4SdKmOgyrgV3T01in259NIPYcl1 o= X-Gm-Gg: AeBDiesF6ZS5U7OE2M8FzVSFXXj+hZApTHE2Br3lW0UwksrBgmgdAX7lq1ED1qnBaBe J7K7U1R8yuyEQsc7mAdvl3mD7mEdaccdYOaJf1s+vrFrDmMrnJ5m8fsZNijvOJXjxqMPnE22TNN r25fydcZrFPM6A/OAxrthI/Nq59JSiq5OYipPny+vnBqKUzLqCrp2Qwc9idlurvMtvaWeVrDsLk z3um5kzJCXQrXk2QoKR/EXf5fm1VCw6UwphnUYtJlwPM9JZIT95a+7HvNizMP859OJEAn572G3d PYrkWRD6Ywctn9DOBdRxxKLACbyoySMqY1zxTj8KdjmmVG9MeDrXlavf/YKNlSOKTvceOSSxLl2 ZhTzj9OrnsVTc7r4Q/1D2TDtepmTnEEfdzhreB0iJUVexN2+sT3Thr7jVlYDIgi3q6xiAcH+mJt +UDrou4QrQHv67uOAE6pCSx8QSKE4fMtzYVfqS4vf1+K+ZJsYGUiqvQecO7BeoykUYQ0Q= X-Received: by 2002:a17:90b:2f8f:b0:35f:bb33:d727 with SMTP id 98e67ed59e1d1-3649202dabcmr7725706a91.20.1777476300770; Wed, 29 Apr 2026 08:25:00 -0700 (PDT) X-Received: by 2002:a17:90b:2f8f:b0:35f:bb33:d727 with SMTP id 98e67ed59e1d1-3649202dabcmr7725659a91.20.1777476300090; Wed, 29 Apr 2026 08:25:00 -0700 (PDT) Received: from hu-kathirav-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-364bd588ad5sm66732a91.3.2026.04.29.08.24.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Apr 2026 08:24:58 -0700 (PDT) From: Kathiravan Thirumoorthy Date: Wed, 29 Apr 2026 20:54:25 +0530 Subject: [PATCH v2 4/4] arm64: dts: qcom: add IPQ9650 SoC and rdp488 board support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260429-ipq9650_boot_to_shell-v2-4-9b0dc3d1f3a8@oss.qualcomm.com> References: <20260429-ipq9650_boot_to_shell-v2-0-9b0dc3d1f3a8@oss.qualcomm.com> In-Reply-To: <20260429-ipq9650_boot_to_shell-v2-0-9b0dc3d1f3a8@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kathiravan Thirumoorthy X-Mailer: b4 0.15.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1777476269; l=11163; i=kathiravan.thirumoorthy@oss.qualcomm.com; s=20230906; h=from:subject:message-id; bh=J5yfDWjRPOg45bYa1539C2lhtkSrcvJpcd7225W2npA=; b=TuXyG5L6vZeoKTurozGdwlw5JuDEtvlWL0AV2sMrX482L87dixn2TAUTsiR5Xktz4bW3pkdht FaOobSe/EThDzv+9k3f0emVQM/qKpWCjJft0ZPbUG7lp2u9ZnZKtSio X-Developer-Key: i=kathiravan.thirumoorthy@oss.qualcomm.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Proofpoint-GUID: BTsMTg4YZNYQB8JXjDJTSn-YBaw7OzN_ X-Authority-Analysis: v=2.4 cv=A4dc+aWG c=1 sm=1 tr=0 ts=69f222ce cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=fBkTXTPqfNaV2XDYC8MA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-ORIG-GUID: BTsMTg4YZNYQB8JXjDJTSn-YBaw7OzN_ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI5MDE1NSBTYWx0ZWRfX7m9eEPmY5WgZ 5zMlnIIz9qOl3EAVlI4sy8Uel+AFiNE0QfKP/zRdEPVqKeaWh/snEJwdkC0UZFzYg6nM4KpQCFl mNlcGOL+tXIW8AxyYXLwurill/Ji6b9BQyFZ378u2v4NqlQgulLzMmiK0turIg3fXJLc6CVpkos YtAcTYRxEyNNrTVsJ5Zb/Xieikc5fsHXHloT6djxZAbsMHwgNNsFh+tT4llWOswp0RK4OwTKv86 i69TNSuzk+SFlEIOw60Lun/kr6mJjbk1Q2MRGaFhjDSxGNR2FKKMHOzOMvC5UPXDsz7mVqp+Te+ nrmInlMdCPsLMuwmTG7brOC4hii45wnKsh7y9SSRelgCv1E2DFkc5gLhJ2WiK4vUnSVG+3dN7fn ojMsnXMD7c9asK+ZvbUensMFWLoXq8SVdFv0Pf2c3kM+Y7a+z5GWUnT9TzLs2p8R0srJjZ8/FMo 65z6+/DvpDunZHKmpEQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-29_01,2026-04-28_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 bulkscore=0 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604290155 Add initial device tree support for the Qualcomm IPQ9650 SoC and rdp488 board. Signed-off-by: Kathiravan Thirumoorthy --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq9650-rdp488.dts | 79 ++++++ arch/arm64/boot/dts/qcom/ipq9650.dtsi | 376 ++++++++++++++++++++++++= ++++ 3 files changed, 456 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 4ba8e7306419..dba16311ca2b 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -39,6 +39,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp433.dtb ipq9574-r= dp433-emmc.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp449.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp453.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp454.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9650-rdp488.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D kaanapali-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D kaanapali-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq9650-rdp488.dts b/arch/arm64/boot/= dts/qcom/ipq9650-rdp488.dts new file mode 100644 index 000000000000..6871f3dc4eaf --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9650-rdp488.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "ipq9650.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. IPQ9650 RDP488"; + compatible =3D "qcom,ipq9650-rdp488", "qcom,ipq9650"; + + aliases { + serial0 =3D &uart1; + }; + + chosen { + stdout-path =3D "serial0"; + }; +}; + +&sdhc { + max-frequency =3D <192000000>; + bus-width =3D <4>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + pinctrl-0 =3D <&sdhc_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32000>; +}; + +&tlmm { + qup_uart1_default_state: qup-uart1-default-state { + pins =3D "gpio43", "gpio44"; + function =3D "qup_se6"; + drive-strength =3D <8>; + bias-pull-down; + }; + + sdhc_default_state: sdhc-default-state { + clk-pins { + pins =3D "gpio5"; + function =3D "sdc_clk"; + drive-strength =3D <8>; + bias-disable; + }; + + cmd-pins { + pins =3D "gpio4"; + function =3D "sdc_cmd"; + drive-strength =3D <8>; + bias-pull-up; + }; + + data-pins { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "sdc_data"; + drive-strength =3D <8>; + bias-pull-up; + }; + }; +}; + +&uart1 { + pinctrl-0 =3D <&qup_uart1_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&xo_board { + clock-frequency =3D <24000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq9650.dtsi b/arch/arm64/boot/dts/qc= om/ipq9650.dtsi new file mode 100644 index 000000000000..4a383b53c3b5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9650.dtsi @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&intc>; + + clocks { + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + xo_board: xo-board-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + + l3_0: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-unified; + }; + }; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x100>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_100>; + + l2_100: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x200>; + enable-method =3D "psci"; + + l2_200: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x300>; + enable-method =3D "psci"; + + l2_300: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x400>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_400>; + + l2_400: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + + core4 { + cpu =3D <&cpu4>; + }; + }; + }; + }; + + firmware { + optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + + scm { + compatible =3D "qcom,scm-ipq9650", "qcom,scm"; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0x0 0x80000000 0x0 0x0>; + }; + + pmu-a55 { + compatible =3D "arm,cortex-a55-pmu"; + interrupts =3D ; + }; + + pmu-a78 { + compatible =3D "arm,cortex-a78-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + bootloader@8a100000 { + reg =3D <0x0 0x8a100000 0x0 0x400000>; + no-map; + }; + + smem@8a500000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x8a500000 0x0 0x40000>; + no-map; + + hwlocks =3D <&tcsr_mutex 3>; + }; + + tfa@8a600000 { + reg =3D <0x0 0x8a600000 0x0 0x80000>; + no-map; + }; + + optee@8a680000 { + reg =3D <0x0 0x8a680000 0x0 0x280000>; + no-map; + }; + }; + + soc@0 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-ranges =3D <0 0 0 0 0x10 0>; + ranges =3D <0 0 0 0 0x10 0>; + + tlmm: pinctrl@1000000 { + compatible =3D "qcom,ipq9650-tlmm"; + reg =3D <0x0 0x01000000 0x0 0x300000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 54>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gcc: clock-controller@1800000 { + compatible =3D "qcom,ipq9650-gcc"; + reg =3D <0x0 0x01800000 0x0 0x40000>; + clocks =3D <&xo_board>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + tcsr_mutex: hwlock@1917000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x01917000 0x0 0x57000>; + #hwlock-cells =3D <1>; + }; + + qupv3: geniqup@1ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x01ac0000 0x0 0x2000>; + clocks =3D <&gcc GCC_QUPV3_AHB_MST_CLK>, + <&gcc GCC_QUPV3_AHB_SLV_CLK>; + clock-names =3D "m-ahb", "s-ahb"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + uart1: serial@1a98000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0x0 0x01a98000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP_SE6_CLK>; + clock-names =3D "se"; + interrupts =3D ; + status =3D "disabled"; + }; + }; + + sdhc: mmc@7804000 { + compatible =3D "qcom,ipq9650-sdhci", "qcom,sdhci-msm-v5"; + reg =3D <0x0 0x07804000 0x0 0x1000>, + <0x0 0x07805000 0x0 0x1000>; + reg-names =3D "hc", + "cqhci"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", + "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; + clock-names =3D "iface", + "core", + "xo"; + non-removable; + + status =3D "disabled"; + }; + + intc: interrupt-controller@f200000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x0f200000 0x0 0x10000>, + <0x0 0x0f240000 0x0 0xa0000>; + #interrupt-cells =3D <0x4>; + interrupt-controller; + #redistributor-regions =3D <1>; + redistributor-stride =3D <0x0 0x20000>; + interrupts =3D ; + mbi-ranges =3D <800 160>; + msi-controller; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity =3D <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity =3D <&cpu4>; + }; + }; + }; + + timer@f420000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0x0f420000 0x0 0x1000>; + ranges =3D <0 0 0 0x10000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + frame@f421000 { + reg =3D <0x0f421000 0x1000>, + <0x0f422000 0x1000>; + interrupts =3D , + ; + frame-number =3D <0>; + }; + + frame@f423000 { + reg =3D <0x0f423000 0x1000>; + interrupts =3D ; + frame-number =3D <1>; + + status =3D "disabled"; + }; + + frame@f425000 { + reg =3D <0x0f425000 0x1000>, + <0x0f426000 0x1000>; + interrupts =3D ; + frame-number =3D <2>; + + status =3D "disabled"; + }; + + frame@f427000 { + reg =3D <0x0f427000 0x1000>; + interrupts =3D ; + frame-number =3D <3>; + + status =3D "disabled"; + }; + + frame@f429000 { + reg =3D <0x0f429000 0x1000>; + interrupts =3D ; + frame-number =3D <4>; + + status =3D "disabled"; + }; + + frame@f42b000 { + reg =3D <0x0f42b000 0x1000>; + interrupts =3D ; + frame-number =3D <5>; + + status =3D "disabled"; + }; + + frame@f42d000 { + reg =3D <0x0f42d000 0x1000>; + interrupts =3D ; + frame-number =3D <6>; + + status =3D "disabled"; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + , + ; + }; +}; --=20 2.34.1