From nobody Wed Jun 17 01:51:18 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B1F13C3C01 for ; Tue, 28 Apr 2026 15:49:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777391370; cv=none; b=rRR1HTIcwZrWS7PuRoMDSIy5KI4OTSuDRLYl4qZaSEY98giILgLgzeC0nfG9m6XfJ32oSZcDse0BFzkU1AxcGDZmfbl1KXMVC2k86GuKTnhTdy09jIQUoW95mrxJZBJYjyJNY0jSz3vhcNQagWLx25w4V3xds3IimnlTV8XnxEk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777391370; c=relaxed/simple; bh=yAz71WBSfKVkJdRbKsp2DdeDzueQdWiLO7GR2fC4KCY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=W9rG2aIcp48sTh26MuehVI60twAUNZJr33CGNCIgwIDgDf/JW/Qcs7rQfkpu2W8X2Rgzg4itvj4zwtOLfY0uYIdXShNGstrxb3fyV2ljTTNLFH04vrU41UqV8nqqnKeGgFO3BizbOcqetAV7/VNgUHe4d14yG3xbyCvWXakwg88= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=PSV4k2/j; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="PSV4k2/j" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1777391367; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=no94Uiu927bsgrxHuWd7npipmK1+PZ4oAjvPn/KPnlM=; b=PSV4k2/jG8mET3GA/zfNKCQQHlMuq20ZWH3nKgat3zKn9HTncBTH8TUgGheehzA2MLdk8i tuJq3TZ/QKW6NTqgYP92RLUlpg67ZB4XR6eL4laQUT5aacF8rC27t1zoK1jAfNV0R4wRIW p8LKqjkW9wMKcqWL7ZpDkIzBjfUrJCc= Received: from mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-154-nQfN3ARVPzuc0fnyikzJ6Q-1; Tue, 28 Apr 2026 11:49:23 -0400 X-MC-Unique: nQfN3ARVPzuc0fnyikzJ6Q-1 X-Mimecast-MFC-AGG-ID: nQfN3ARVPzuc0fnyikzJ6Q_1777391361 Received: from mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.4]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 0A6461800451; Tue, 28 Apr 2026 15:49:21 +0000 (UTC) Received: from p16v.redhat.com (unknown [10.44.49.234]) by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 5B2CE300757C; Tue, 28 Apr 2026 15:49:15 +0000 (UTC) From: Ivan Vecera To: netdev@vger.kernel.org Cc: Arkadiusz Kubalewski , "David S. Miller" , Donald Hunter , Eric Dumazet , Jakub Kicinski , Jiri Pirko , Jonathan Corbet , Michal Schmidt , Paolo Abeni , Pasi Vaananen , Petr Oros , Prathosh Satish , Shuah Khan , Simon Horman , Vadim Fedorenko , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 1/2] dpll: add pin operational state Date: Tue, 28 Apr 2026 17:49:06 +0200 Message-ID: <20260428154907.2820654-2-ivecera@redhat.com> In-Reply-To: <20260428154907.2820654-1-ivecera@redhat.com> References: <20260428154907.2820654-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Content-Type: text/plain; charset="utf-8" Add pin-operstate enum and operstate_on_dpll_get callback to report the actual hardware status of a pin with respect to its parent DPLL device. Unlike pin-state (which reflects administrative intent set by the user), operstate reflects what the hardware is actually doing. Defined operational states: - active: pin is qualified and actively used by the DPLL - standby: pin is qualified but not actively used by the DPLL - no-signal: pin does not have a valid signal - qual-failed: pin signal failed qualification The operstate is reported inside the pin-parent-device nested attribute alongside the existing state and phase-offset attributes. Signed-off-by: Ivan Vecera Reviewed-by: Jiri Pirko Reviewed-by: Petr Oros Reviewed-by: Vadim Fedorenko --- Documentation/driver-api/dpll.rst | 38 ++++++++++++++++----------- Documentation/netlink/specs/dpll.yaml | 31 ++++++++++++++++++++++ drivers/dpll/dpll_netlink.c | 27 +++++++++++++++++++ drivers/dpll/dpll_nl.c | 3 ++- drivers/dpll/dpll_nl.h | 2 +- include/linux/dpll.h | 6 +++++ include/uapi/linux/dpll.h | 23 ++++++++++++++++ 7 files changed, 113 insertions(+), 17 deletions(-) diff --git a/Documentation/driver-api/dpll.rst b/Documentation/driver-api/d= pll.rst index 93c191b2d0898..37eaef785e304 100644 --- a/Documentation/driver-api/dpll.rst +++ b/Documentation/driver-api/dpll.rst @@ -65,35 +65,43 @@ request, where user provides attributes that result in = single pin match. Pin selection =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -In general, selected pin (the one which signal is driving the dpll -device) can be obtained from ``DPLL_A_PIN_STATE`` attribute, and only -one pin shall be in ``DPLL_PIN_STATE_CONNECTED`` state for any dpll -device. +Pin state (``DPLL_A_PIN_STATE``) reflects the administrative intent set +by the user. Pin operational state (``DPLL_A_PIN_OPERSTATE``) reflects +what the hardware is actually doing with the pin. =20 Pin selection can be done either manually or automatically, depending on hardware capabilities and active dpll device work mode (``DPLL_A_MODE`` attribute). The consequence is that there are -differences for each mode in terms of available pin states, as well as -for the states the user can request for a dpll device. +differences for each mode in terms of available pin states the user can +request for a dpll device. =20 -In manual mode (``DPLL_MODE_MANUAL``) the user can request or receive -one of following pin states: +In manual mode (``DPLL_MODE_MANUAL``) the user can request one of +following pin states: =20 -- ``DPLL_PIN_STATE_CONNECTED`` - the pin is used to drive dpll device -- ``DPLL_PIN_STATE_DISCONNECTED`` - the pin is not used to drive dpll +- ``DPLL_PIN_STATE_CONNECTED`` - the pin is selected to drive dpll device +- ``DPLL_PIN_STATE_DISCONNECTED`` - the pin is not selected to drive + dpll device =20 -In automatic mode (``DPLL_MODE_AUTOMATIC``) the user can request or -receive one of following pin states: +In automatic mode (``DPLL_MODE_AUTOMATIC``) the user can request one of +following pin states: =20 - ``DPLL_PIN_STATE_SELECTABLE`` - the pin shall be considered as valid input for automatic selection algorithm - ``DPLL_PIN_STATE_DISCONNECTED`` - the pin shall be not considered as a valid input for automatic selection algorithm =20 -In automatic mode (``DPLL_MODE_AUTOMATIC``) the user can only receive -pin state ``DPLL_PIN_STATE_CONNECTED`` once automatic selection -algorithm locks a dpll device with one of the inputs. +The actual hardware status of a pin is reported via the operational +state (``DPLL_A_PIN_OPERSTATE``) attribute nested under the parent +device: + +- ``DPLL_PIN_OPERSTATE_ACTIVE`` - pin is qualified and actively used + by the DPLL +- ``DPLL_PIN_OPERSTATE_STANDBY`` - pin is qualified but not actively + used by the DPLL +- ``DPLL_PIN_OPERSTATE_NO_SIGNAL`` - pin does not have a valid signal +- ``DPLL_PIN_OPERSTATE_QUAL_FAILED`` - pin signal failed qualification + checks =20 Shared pins =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D diff --git a/Documentation/netlink/specs/dpll.yaml b/Documentation/netlink/= specs/dpll.yaml index 40465a3d7fc20..c45de70a47ce6 100644 --- a/Documentation/netlink/specs/dpll.yaml +++ b/Documentation/netlink/specs/dpll.yaml @@ -212,6 +212,27 @@ definitions: name: selectable doc: pin enabled for automatic input selection render-max: true + - + type: enum + name: pin-operstate + doc: | + defines possible operational states of a pin with respect to its + parent DPLL device, valid values for DPLL_A_PIN_OPERSTATE attribute + entries: + - + name: active + doc: pin is qualified and actively used by the DPLL + value: 1 + - + name: standby + doc: pin is qualified but not actively used by the DPLL + - + name: no-signal + doc: pin does not have a valid signal + - + name: qual-failed + doc: pin signal failed qualification (e.g. frequency or phase moni= tor) + render-max: true - type: flags name: pin-capabilities @@ -488,6 +509,14 @@ attribute-sets: Value of (DPLL_A_PIN_MEASURED_FREQUENCY % DPLL_PIN_MEASURED_FREQUENCY_DIVIDER) is a fractional part of a measured frequency value. + - + name: operstate + type: u32 + enum: pin-operstate + doc: | + Operational state of the pin with respect to its parent DPLL + device. Unlike state (which reflects the administrative intent), + operstate reflects the actual hardware status. =20 - name: pin-parent-device @@ -501,6 +530,8 @@ attribute-sets: name: prio - name: state + - + name: operstate - name: phase-offset - diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c index af7ce62ec55ca..05cf946b4be5e 100644 --- a/drivers/dpll/dpll_netlink.c +++ b/drivers/dpll/dpll_netlink.c @@ -324,6 +324,30 @@ dpll_msg_add_pin_on_dpll_state(struct sk_buff *msg, st= ruct dpll_pin *pin, return 0; } =20 +static int +dpll_msg_add_pin_operstate(struct sk_buff *msg, struct dpll_pin *pin, + struct dpll_pin_ref *ref, + struct netlink_ext_ack *extack) +{ + const struct dpll_pin_ops *ops =3D dpll_pin_ops(ref); + struct dpll_device *dpll =3D ref->dpll; + enum dpll_pin_operstate operstate; + int ret; + + if (!ops->operstate_on_dpll_get) + return 0; + ret =3D ops->operstate_on_dpll_get(pin, + dpll_pin_on_dpll_priv(dpll, pin), + dpll, dpll_priv(dpll), + &operstate, extack); + if (ret) + return ret; + if (nla_put_u32(msg, DPLL_A_PIN_OPERSTATE, operstate)) + return -EMSGSIZE; + + return 0; +} + static int dpll_msg_add_pin_direction(struct sk_buff *msg, struct dpll_pin *pin, struct dpll_pin_ref *ref, @@ -650,6 +674,9 @@ dpll_msg_add_pin_dplls(struct sk_buff *msg, struct dpll= _pin *pin, if (ret) goto nest_cancel; ret =3D dpll_msg_add_pin_on_dpll_state(msg, pin, ref, extack); + if (ret) + goto nest_cancel; + ret =3D dpll_msg_add_pin_operstate(msg, pin, ref, extack); if (ret) goto nest_cancel; ret =3D dpll_msg_add_pin_prio(msg, pin, ref, extack); diff --git a/drivers/dpll/dpll_nl.c b/drivers/dpll/dpll_nl.c index 1e652340a5d73..58235845fa3d5 100644 --- a/drivers/dpll/dpll_nl.c +++ b/drivers/dpll/dpll_nl.c @@ -12,11 +12,12 @@ #include =20 /* Common nested types */ -const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_PHASE_= OFFSET + 1] =3D { +const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_OPERST= ATE + 1] =3D { [DPLL_A_PIN_PARENT_ID] =3D { .type =3D NLA_U32, }, [DPLL_A_PIN_DIRECTION] =3D NLA_POLICY_RANGE(NLA_U32, 1, 2), [DPLL_A_PIN_PRIO] =3D { .type =3D NLA_U32, }, [DPLL_A_PIN_STATE] =3D NLA_POLICY_RANGE(NLA_U32, 1, 3), + [DPLL_A_PIN_OPERSTATE] =3D NLA_POLICY_RANGE(NLA_U32, 1, 4), [DPLL_A_PIN_PHASE_OFFSET] =3D { .type =3D NLA_S64, }, }; =20 diff --git a/drivers/dpll/dpll_nl.h b/drivers/dpll/dpll_nl.h index 7419679b69779..fa8280e3dd14c 100644 --- a/drivers/dpll/dpll_nl.h +++ b/drivers/dpll/dpll_nl.h @@ -13,7 +13,7 @@ #include =20 /* Common nested types */ -extern const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN= _PHASE_OFFSET + 1]; +extern const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN= _OPERSTATE + 1]; extern const struct nla_policy dpll_pin_parent_pin_nl_policy[DPLL_A_PIN_ST= ATE + 1]; extern const struct nla_policy dpll_reference_sync_nl_policy[DPLL_A_PIN_ST= ATE + 1]; =20 diff --git a/include/linux/dpll.h b/include/linux/dpll.h index b7277a8b484d2..b6f16c884b99e 100644 --- a/include/linux/dpll.h +++ b/include/linux/dpll.h @@ -85,6 +85,12 @@ struct dpll_pin_ops { const struct dpll_device *dpll, void *dpll_priv, enum dpll_pin_state *state, struct netlink_ext_ack *extack); + int (*operstate_on_dpll_get)(const struct dpll_pin *pin, + void *pin_priv, + const struct dpll_device *dpll, + void *dpll_priv, + enum dpll_pin_operstate *operstate, + struct netlink_ext_ack *extack); int (*state_on_pin_set)(const struct dpll_pin *pin, void *pin_priv, const struct dpll_pin *parent_pin, void *parent_pin_priv, diff --git a/include/uapi/linux/dpll.h b/include/uapi/linux/dpll.h index 871685f7c353b..cb363cccf2e2a 100644 --- a/include/uapi/linux/dpll.h +++ b/include/uapi/linux/dpll.h @@ -178,6 +178,28 @@ enum dpll_pin_state { DPLL_PIN_STATE_MAX =3D (__DPLL_PIN_STATE_MAX - 1) }; =20 +/** + * enum dpll_pin_operstate - defines possible operational states of a pin = with + * respect to its parent DPLL device, valid values for DPLL_A_PIN_OPERST= ATE + * attribute + * @DPLL_PIN_OPERSTATE_ACTIVE: pin is qualified and actively used by the D= PLL + * @DPLL_PIN_OPERSTATE_STANDBY: pin is qualified but not actively used by = the + * DPLL + * @DPLL_PIN_OPERSTATE_NO_SIGNAL: pin does not have a valid signal + * @DPLL_PIN_OPERSTATE_QUAL_FAILED: pin signal failed qualification (e.g. + * frequency or phase monitor) + */ +enum dpll_pin_operstate { + DPLL_PIN_OPERSTATE_ACTIVE =3D 1, + DPLL_PIN_OPERSTATE_STANDBY, + DPLL_PIN_OPERSTATE_NO_SIGNAL, + DPLL_PIN_OPERSTATE_QUAL_FAILED, + + /* private: */ + __DPLL_PIN_OPERSTATE_MAX, + DPLL_PIN_OPERSTATE_MAX =3D (__DPLL_PIN_OPERSTATE_MAX - 1) +}; + /** * enum dpll_pin_capabilities - defines possible capabilities of a pin, va= lid * flags on DPLL_A_PIN_CAPABILITIES attribute @@ -257,6 +279,7 @@ enum dpll_a_pin { DPLL_A_PIN_PHASE_ADJUST_GRAN, DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT, DPLL_A_PIN_MEASURED_FREQUENCY, + DPLL_A_PIN_OPERSTATE, =20 __DPLL_A_PIN_MAX, DPLL_A_PIN_MAX =3D (__DPLL_A_PIN_MAX - 1) --=20 2.53.0 From nobody Wed Jun 17 01:51:18 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 995463E0C66 for ; Tue, 28 Apr 2026 15:49:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777391376; cv=none; b=PYirc82IbleDxkwBxUOqYQp1K00PQDhT7MneyxQrf3HRAV4IXYky+PI7tfpdGQpY1sJ+L9FkyxQ2EsQPXNnQ08G8Rtd4w8Y59SmisVaBt5CukV/kh5bhJFxpEA5Gm2/boPVut8SWzBXdTM8bJA5D27RgXcWhwlqnyA0apbT3rAY= ARC-Message-Signature: i=1; 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Tue, 28 Apr 2026 15:49:26 +0000 (UTC) Received: from p16v.redhat.com (unknown [10.44.49.234]) by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 66A09300756E; Tue, 28 Apr 2026 15:49:21 +0000 (UTC) From: Ivan Vecera To: netdev@vger.kernel.org Cc: Arkadiusz Kubalewski , "David S. Miller" , Donald Hunter , Eric Dumazet , Jakub Kicinski , Jiri Pirko , Jonathan Corbet , Michal Schmidt , Paolo Abeni , Pasi Vaananen , Petr Oros , Prathosh Satish , Shuah Khan , Simon Horman , Vadim Fedorenko , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 2/2] dpll: zl3073x: implement pin operational state reporting Date: Tue, 28 Apr 2026 17:49:07 +0200 Message-ID: <20260428154907.2820654-3-ivecera@redhat.com> In-Reply-To: <20260428154907.2820654-1-ivecera@redhat.com> References: <20260428154907.2820654-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Content-Type: text/plain; charset="utf-8" Implement operstate_on_dpll_get callback for input pins to report the actual hardware status: - active: pin is the currently locked reference - standby: signal is valid but pin is not actively used - no-signal: reference monitor reports Loss of Signal (LOS) - qual-failed: reference monitor reports a qualification failure (SCM, CFM, GST, PFM, eSync or Split-XO) Separate administrative state (state_on_dpll_get) from operational state: admin state now reports purely the user-requested intent (connected in reflock mode, selectable in auto mode). Switch periodic monitoring to track operstate changes instead of the mixed admin/oper state that was previously reported. Add ref_mon_status bit definitions to regs.h. Signed-off-by: Ivan Vecera Reviewed-by: Petr Oros --- drivers/dpll/zl3073x/dpll.c | 108 ++++++++++++++++++++++++------------ drivers/dpll/zl3073x/regs.h | 9 ++- 2 files changed, 79 insertions(+), 38 deletions(-) diff --git a/drivers/dpll/zl3073x/dpll.c b/drivers/dpll/zl3073x/dpll.c index c95e93ef3ab04..6fd718696de0d 100644 --- a/drivers/dpll/zl3073x/dpll.c +++ b/drivers/dpll/zl3073x/dpll.c @@ -38,7 +38,7 @@ * @prio: pin priority <0, 14> * @esync_control: embedded sync is controllable * @phase_gran: phase adjustment granularity - * @pin_state: last saved pin state + * @operstate: last saved operational state * @phase_offset: last saved pin phase offset * @freq_offset: last saved fractional frequency offset * @measured_freq: last saved measured frequency @@ -55,7 +55,7 @@ struct zl3073x_dpll_pin { u8 prio; bool esync_control; s32 phase_gran; - enum dpll_pin_state pin_state; + enum dpll_pin_operstate operstate; s64 phase_offset; s64 freq_offset; u32 measured_freq; @@ -500,46 +500,41 @@ zl3073x_dpll_input_pin_phase_adjust_set(const struct = dpll_pin *dpll_pin, } =20 /** - * zl3073x_dpll_ref_state_get - get status for given input pin + * zl3073x_dpll_ref_operstate_get - get operational state for input pin * @pin: pointer to pin - * @state: place to store status + * @operstate: place to store operational state * - * Checks current status for the given input pin and stores the value - * to @state. + * Returns the actual hardware state of the pin: whether it is actively + * used by the DPLL, has no signal, failed qualification, or is simply + * not in use. * * Return: 0 on success, <0 on error */ static int -zl3073x_dpll_ref_state_get(struct zl3073x_dpll_pin *pin, - enum dpll_pin_state *state) +zl3073x_dpll_ref_operstate_get(struct zl3073x_dpll_pin *pin, + enum dpll_pin_operstate *operstate) { struct zl3073x_dpll *zldpll =3D pin->dpll; struct zl3073x_dev *zldev =3D zldpll->dev; - const struct zl3073x_chan *chan; - u8 ref; - - chan =3D zl3073x_chan_state_get(zldev, zldpll->id); - ref =3D zl3073x_input_pin_ref_get(pin->id); + const struct zl3073x_ref *ref; + u8 ref_id; =20 - /* Check if the pin reference is connected */ - if (ref =3D=3D zl3073x_dpll_connected_ref_get(zldpll)) { - *state =3D DPLL_PIN_STATE_CONNECTED; - return 0; - } + ref_id =3D zl3073x_input_pin_ref_get(pin->id); =20 - /* If the DPLL is running in automatic mode and the reference is - * selectable and its monitor does not report any error then report - * pin as selectable. - */ - if (zl3073x_chan_mode_get(chan) =3D=3D ZL_DPLL_MODE_REFSEL_MODE_AUTO && - zl3073x_dev_ref_is_status_ok(zldev, ref) && - zl3073x_chan_ref_is_selectable(chan, ref)) { - *state =3D DPLL_PIN_STATE_SELECTABLE; + /* Check if this pin is the currently locked reference */ + if (ref_id =3D=3D zl3073x_dpll_connected_ref_get(zldpll)) { + *operstate =3D DPLL_PIN_OPERSTATE_ACTIVE; return 0; } =20 - /* Otherwise report the pin as disconnected */ - *state =3D DPLL_PIN_STATE_DISCONNECTED; + /* Check reference monitor status */ + ref =3D zl3073x_ref_state_get(zldev, ref_id); + if (ref->mon_status & ZL_REF_MON_STATUS_LOS) + *operstate =3D DPLL_PIN_OPERSTATE_NO_SIGNAL; + else if (!zl3073x_ref_is_status_ok(ref)) + *operstate =3D DPLL_PIN_OPERSTATE_QUAL_FAILED; + else + *operstate =3D DPLL_PIN_OPERSTATE_STANDBY; =20 return 0; } @@ -551,10 +546,48 @@ zl3073x_dpll_input_pin_state_on_dpll_get(const struct= dpll_pin *dpll_pin, void *dpll_priv, enum dpll_pin_state *state, struct netlink_ext_ack *extack) +{ + struct zl3073x_dpll *zldpll =3D dpll_priv; + struct zl3073x_dpll_pin *pin =3D pin_priv; + const struct zl3073x_chan *chan; + u8 mode, ref; + + chan =3D zl3073x_chan_state_get(zldpll->dev, zldpll->id); + ref =3D zl3073x_input_pin_ref_get(pin->id); + mode =3D zl3073x_chan_mode_get(chan); + + switch (mode) { + case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: + if (ref =3D=3D zl3073x_chan_ref_get(chan)) + *state =3D DPLL_PIN_STATE_CONNECTED; + else + *state =3D DPLL_PIN_STATE_DISCONNECTED; + break; + case ZL_DPLL_MODE_REFSEL_MODE_AUTO: + if (zl3073x_chan_ref_is_selectable(chan, ref)) + *state =3D DPLL_PIN_STATE_SELECTABLE; + else + *state =3D DPLL_PIN_STATE_DISCONNECTED; + break; + default: + *state =3D DPLL_PIN_STATE_DISCONNECTED; + break; + } + + return 0; +} + +static int +zl3073x_dpll_input_pin_operstate_on_dpll_get(const struct dpll_pin *dpll_p= in, + void *pin_priv, + const struct dpll_device *dpll, + void *dpll_priv, + enum dpll_pin_operstate *operstate, + struct netlink_ext_ack *extack) { struct zl3073x_dpll_pin *pin =3D pin_priv; =20 - return zl3073x_dpll_ref_state_get(pin, state); + return zl3073x_dpll_ref_operstate_get(pin, operstate); } =20 static int @@ -1248,6 +1281,7 @@ static const struct dpll_pin_ops zl3073x_dpll_input_p= in_ops =3D { .frequency_get =3D zl3073x_dpll_input_pin_frequency_get, .frequency_set =3D zl3073x_dpll_input_pin_frequency_set, .measured_freq_get =3D zl3073x_dpll_input_pin_measured_freq_get, + .operstate_on_dpll_get =3D zl3073x_dpll_input_pin_operstate_on_dpll_get, .phase_offset_get =3D zl3073x_dpll_input_pin_phase_offset_get, .phase_adjust_get =3D zl3073x_dpll_input_pin_phase_adjust_get, .phase_adjust_set =3D zl3073x_dpll_input_pin_phase_adjust_set, @@ -1663,7 +1697,7 @@ zl3073x_dpll_pin_phase_offset_check(struct zl3073x_dp= ll_pin *pin) * 2) For other pins use appropriate ref_phase register if the phase * monitor feature is enabled. */ - if (pin->pin_state =3D=3D DPLL_PIN_STATE_CONNECTED) + if (pin->operstate =3D=3D DPLL_PIN_OPERSTATE_ACTIVE) reg =3D ZL_REG_DPLL_PHASE_ERR_DATA(zldpll->id); else if (zldpll->phase_monitor) reg =3D ZL_REG_REF_PHASE(ref_id); @@ -1828,7 +1862,7 @@ zl3073x_dpll_changes_check(struct zl3073x_dpll *zldpl= l) } =20 list_for_each_entry(pin, &zldpll->pins, list) { - enum dpll_pin_state state; + enum dpll_pin_operstate operstate; bool pin_changed =3D false; =20 /* Output pins change checks are not necessary because output @@ -1837,18 +1871,18 @@ zl3073x_dpll_changes_check(struct zl3073x_dpll *zld= pll) if (!zl3073x_dpll_is_input_pin(pin)) continue; =20 - rc =3D zl3073x_dpll_ref_state_get(pin, &state); + rc =3D zl3073x_dpll_ref_operstate_get(pin, &operstate); if (rc) { dev_err(dev, - "Failed to get %s on DPLL%u state: %pe\n", + "Failed to get %s on DPLL%u oper state: %pe\n", pin->label, zldpll->id, ERR_PTR(rc)); return; } =20 - if (state !=3D pin->pin_state) { - dev_dbg(dev, "%s state changed: %u->%u\n", pin->label, - pin->pin_state, state); - pin->pin_state =3D state; + if (operstate !=3D pin->operstate) { + dev_dbg(dev, "%s oper state changed: %u->%u\n", + pin->label, pin->operstate, operstate); + pin->operstate =3D operstate; pin_changed =3D true; } =20 diff --git a/drivers/dpll/zl3073x/regs.h b/drivers/dpll/zl3073x/regs.h index d425dc67250fe..8015808bdf548 100644 --- a/drivers/dpll/zl3073x/regs.h +++ b/drivers/dpll/zl3073x/regs.h @@ -98,7 +98,14 @@ =20 #define ZL_REG_REF_MON_STATUS(_idx) \ ZL_REG_IDX(_idx, 2, 0x02, 1, ZL3073X_NUM_REFS, 1) -#define ZL_REF_MON_STATUS_OK 0 /* all bits zeroed */ +#define ZL_REF_MON_STATUS_OK 0 +#define ZL_REF_MON_STATUS_LOS BIT(0) +#define ZL_REF_MON_STATUS_SCM BIT(1) +#define ZL_REF_MON_STATUS_CFM BIT(2) +#define ZL_REF_MON_STATUS_GST BIT(3) +#define ZL_REF_MON_STATUS_PFM BIT(4) +#define ZL_REF_MON_STATUS_ESYNC BIT(6) +#define ZL_REF_MON_STATUS_SPLIT_XO BIT(7) =20 #define ZL_REG_DPLL_MON_STATUS(_idx) \ ZL_REG_IDX(_idx, 2, 0x10, 1, ZL3073X_MAX_CHANNELS, 1) --=20 2.53.0