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Tue, 28 Apr 2026 02:31:53 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:8851:8e5e:9c47:30d1]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4464004ed80sm5389589f8f.34.2026.04.28.02.31.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Apr 2026 02:31:53 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Michael Turquette , Stephen Boyd , Brian Masney , Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v5 1/2] clk: divider: Add KUnit tests for clk_divider_bestdiv() ULONG_MAX handling Date: Tue, 28 Apr 2026 10:31:45 +0100 Message-ID: <20260428093146.3171672-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260428093146.3171672-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260428093146.3171672-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add KUnit tests to verify the behaviour of clk_divider_bestdiv() when clk_round_rate() is called with ULONG_MAX, which is the canonical way to probe the maximum rate a clock can produce. Two test cases are introduced: - clk_divider_bestdiv_ulong_max_returns_max_rate: registers a 1 GHz fixed-rate parent driving a table-based divider whose smallest entry is div=3D2 (entries: 2, 4, 8). Calls clk_hw_round_rate(div_hw, ULONG_MAX) and checks the result. - clk_divider_bestdiv_mux_ulong_max_returns_max_rate: places a two-input mux (4 GHz and 2 GHz fixed-rate parents, CLK_SET_RATE_PARENT) ahead of the same table-based divider to verify correct parent selection under ULONG_MAX. Both tests use an explicit clk_div_table with a minimum divider of 2 so that the pre-loop maxdiv clamping in clk_divider_bestdiv(): maxdiv =3D min(ULONG_MAX / rate, maxdiv); clamps maxdiv to 1, causing _next_div() to return 2 on the first iteration and skip the loop body entirely. This makes bestdiv fall back to the maximum divider, returning the minimum rate rather than the maximum. The expected values intentionally reflect the buggy output: - test 1: PARENT_RATE_1GHZ / 8 (minimum rate, not maximum) - test 2: 0 (invalid, loop never populated bestdiv) These will be corrected to PARENT_RATE_1GHZ / 2 and PARENT_RATE_4GHZ / 2 respectively once the fix to clk_divider_bestdiv() is applied. Signed-off-by: Lad Prabhakar Reviewed-by: Brian Masney --- v4->v5: - Made use of KUNIT_DEFINE_ACTION_WRAPPER(). - Added RB tag v3->v4: - Dropped unregister_fixed_rate/unregister_divider/unregister_mux wrapper - Added entry in .kunitconfig file - Fixed reverse christmas tree order in clk_divider_bestdiv_ulong_max_returns_max_rate - Updated MODULE_DESCRIPTION() to be more specific v2->v3: - Added false positive expected values - Updated the commit message - Added dependency on !S390 in Kconfig --- drivers/clk/.kunitconfig | 1 + drivers/clk/Kconfig | 8 ++ drivers/clk/Makefile | 1 + drivers/clk/clk-divider_test.c | 153 +++++++++++++++++++++++++++++++++ 4 files changed, 163 insertions(+) create mode 100644 drivers/clk/clk-divider_test.c diff --git a/drivers/clk/.kunitconfig b/drivers/clk/.kunitconfig index 8a0ea41934a2..ea05b9a28c80 100644 --- a/drivers/clk/.kunitconfig +++ b/drivers/clk/.kunitconfig @@ -4,6 +4,7 @@ CONFIG_OF=3Dy CONFIG_OF_OVERLAY=3Dy CONFIG_COMMON_CLK=3Dy CONFIG_CLK_KUNIT_TEST=3Dy +CONFIG_CLK_DIVIDER_KUNIT_TEST=3Dy CONFIG_CLK_FIXED_RATE_KUNIT_TEST=3Dy CONFIG_CLK_GATE_KUNIT_TEST=3Dy CONFIG_CLK_FD_KUNIT_TEST=3Dy diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index b2efbe9f6acb..fdeb87ff8fd9 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -573,4 +573,12 @@ config CLK_FD_KUNIT_TEST help Kunit test for the clk-fractional-divider type. =20 +config CLK_DIVIDER_KUNIT_TEST + tristate "KUnit tests for clk divider bestdiv" if !KUNIT_ALL_TESTS + depends on KUNIT + depends on !S390 + default KUNIT_ALL_TESTS + help + Kunit test for the clk-divider type. + endif diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index a3e2862ebd7e..dc653b458f56 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -21,6 +21,7 @@ clk-test-y :=3D clk_test.o \ kunit_clk_hw_get_dev_of_node.dtbo.o \ kunit_clk_parent_data_test.dtbo.o obj-$(CONFIG_COMMON_CLK) +=3D clk-divider.o +obj-$(CONFIG_CLK_DIVIDER_KUNIT_TEST) +=3D clk-divider_test.o obj-$(CONFIG_COMMON_CLK) +=3D clk-fixed-factor.o obj-$(CONFIG_COMMON_CLK) +=3D clk-fixed-rate.o obj-$(CONFIG_CLK_FIXED_RATE_KUNIT_TEST) +=3D clk-fixed-rate-test.o diff --git a/drivers/clk/clk-divider_test.c b/drivers/clk/clk-divider_test.c new file mode 100644 index 000000000000..cb56931456b8 --- /dev/null +++ b/drivers/clk/clk-divider_test.c @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * KUnit tests for clk_divider_bestdiv() + */ +#include +#include +#include +#include +#include + +#define PARENT_RATE_1GHZ GIGA +#define PARENT_RATE_2GHZ (2 * GIGA) +#define PARENT_RATE_4GHZ (4 * GIGA) + +KUNIT_DEFINE_ACTION_WRAPPER(clk_hw_unregister_fixed_rate_wrapper, + clk_hw_unregister_fixed_rate, struct clk_hw *); +KUNIT_DEFINE_ACTION_WRAPPER(clk_hw_unregister_divider_wrapper, + clk_hw_unregister_divider, struct clk_hw *); +KUNIT_DEFINE_ACTION_WRAPPER(clk_hw_unregister_mux_wrapper, + clk_hw_unregister_mux, struct clk_hw *); + +static const struct clk_div_table bestdiv_table[] =3D { + { .val =3D 0, .div =3D 2 }, + { .val =3D 1, .div =3D 4 }, + { .val =3D 2, .div =3D 8 }, + { /* sentinel */ } +}; + +/* + * Test that clk_round_rate(clk, ULONG_MAX) returns the maximum achievable + * rate for a divider clock. + */ +static void clk_divider_bestdiv_ulong_max_returns_max_rate(struct kunit *t= est) +{ + struct clk_hw *parent_hw, *div_hw; + unsigned long rate; + u32 *fake_reg; + + fake_reg =3D kunit_kzalloc(test, sizeof(*fake_reg), GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, fake_reg); + + parent_hw =3D clk_hw_register_fixed_rate(NULL, "bestdiv-parent", + NULL, 0, PARENT_RATE_1GHZ); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent_hw); + KUNIT_ASSERT_EQ(test, 0, + kunit_add_action_or_reset(test, clk_hw_unregister_fixed_rate_wrapper, + parent_hw)); + + div_hw =3D clk_hw_register_divider_table(NULL, "bestdiv-div", + "bestdiv-parent", + CLK_SET_RATE_PARENT, + (void __iomem __force *)fake_reg, + 0, 2, 0, bestdiv_table, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, div_hw); + KUNIT_ASSERT_EQ(test, 0, + kunit_add_action_or_reset(test, clk_hw_unregister_divider_wrapper, + div_hw)); + + /* + * ULONG_MAX is the canonical way to probe the maximum rate a clock + * can produce. + */ + rate =3D clk_hw_round_rate(div_hw, ULONG_MAX); + KUNIT_EXPECT_EQ(test, rate, PARENT_RATE_1GHZ / 8); +} + +/* + * Test that clk_round_rate(clk, ULONG_MAX) returns the correct maximum ra= te + * when a mux clock sits between a divider and its parent candidates. + * + * Topology: + * + * [fixed 4 GHz] --\ + * +--> [mux CLK_SET_RATE_PARENT] --> [div {2,4,8} CLK_= SET_RATE_PARENT] + * [fixed 2 GHz] --/ + * + */ +static void clk_divider_bestdiv_mux_ulong_max_returns_max_rate(struct kuni= t *test) +{ + static const char * const mux_parents[] =3D { + "bestdiv-mux-parent-a", + "bestdiv-mux-parent-b", + }; + struct clk_hw *parent_a_hw, *parent_b_hw, *mux_hw, *div_hw; + u32 *fake_reg_mux, *fake_reg_div; + unsigned long rate; + + fake_reg_mux =3D kunit_kzalloc(test, sizeof(*fake_reg_mux), GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, fake_reg_mux); + + fake_reg_div =3D kunit_kzalloc(test, sizeof(*fake_reg_div), GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, fake_reg_div); + + /* Higher-rate parent: the mux should select this for ULONG_MAX. */ + parent_a_hw =3D clk_hw_register_fixed_rate(NULL, "bestdiv-mux-parent-a", + NULL, 0, PARENT_RATE_4GHZ); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent_a_hw); + KUNIT_ASSERT_EQ(test, 0, + kunit_add_action_or_reset(test, clk_hw_unregister_fixed_rate_wrapper, + parent_a_hw)); + + /* Lower-rate parent: should not be selected. */ + parent_b_hw =3D clk_hw_register_fixed_rate(NULL, "bestdiv-mux-parent-b", + NULL, 0, PARENT_RATE_2GHZ); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent_b_hw); + KUNIT_ASSERT_EQ(test, 0, + kunit_add_action_or_reset(test, clk_hw_unregister_fixed_rate_wrapper, + parent_b_hw)); + + /* + * 1-bit mux register selects between the two parents. + * CLK_SET_RATE_PARENT allows the divider's rate request to + * propagate into clk_mux_determine_rate(). + */ + mux_hw =3D clk_hw_register_mux(NULL, "bestdiv-mux", + mux_parents, ARRAY_SIZE(mux_parents), + CLK_SET_RATE_PARENT, + (void __iomem __force *)fake_reg_mux, + 0, 1, 0, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, mux_hw); + KUNIT_ASSERT_EQ(test, 0, + kunit_add_action_or_reset(test, clk_hw_unregister_mux_wrapper, + mux_hw)); + + div_hw =3D clk_hw_register_divider_table(NULL, "bestdiv-mux-div", + "bestdiv-mux", + CLK_SET_RATE_PARENT, + (void __iomem __force *)fake_reg_div, + 0, 2, 0, bestdiv_table, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, div_hw); + KUNIT_ASSERT_EQ(test, 0, + kunit_add_action_or_reset(test, clk_hw_unregister_divider_wrapper, + div_hw)); + + rate =3D clk_hw_round_rate(div_hw, ULONG_MAX); + KUNIT_EXPECT_EQ(test, rate, 0); +} + +static struct kunit_case clk_divider_bestdiv_test_cases[] =3D { + KUNIT_CASE(clk_divider_bestdiv_ulong_max_returns_max_rate), + KUNIT_CASE(clk_divider_bestdiv_mux_ulong_max_returns_max_rate), + {} +}; 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Tue, 28 Apr 2026 02:31:54 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:8851:8e5e:9c47:30d1]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4464004ed80sm5389589f8f.34.2026.04.28.02.31.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Apr 2026 02:31:53 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Michael Turquette , Stephen Boyd , Brian Masney , Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v5 2/2] clk: divider: Fix clk_divider_bestdiv() returning min rate for large rate requests Date: Tue, 28 Apr 2026 10:31:46 +0100 Message-ID: <20260428093146.3171672-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260428093146.3171672-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260428093146.3171672-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar clk_divider_bestdiv() clamps maxdiv using: maxdiv =3D min(ULONG_MAX / rate, maxdiv); to avoid overflow in rate * i. However, requests like clk_round_rate(clk, ULONG_MAX), which are used to determine the maximum supported rate of a clock, result in maxdiv being clamped to 1. If no valid divider of 1 exists in the table the loop is never entered and bestdiv falls back to the maximum divider with the minimum parent rate, causing clk_round_rate(clk, ULONG_MAX) to incorrectly return the minimum supported rate instead of the maximum. Fix this by removing the pre-loop maxdiv clamping and replacing the unprotected rate * i multiplication with check_mul_overflow(). Guard the exact-match short-circuit with !overflow to prevent a clamped target_parent_rate of ULONG_MAX from falsely matching parent_rate_saved and causing premature loop exit. Break out of the loop after evaluating the first overflowing divider since clk_hw_round_rate(parent, ULONG_MAX) returns a constant for all subsequent iterations, meaning no better candidate can be found, and continuing would cause exponential recursive calls in chained divider clocks. Update the KUnit test expected values to reflect the corrected behaviour: - clk_divider_bestdiv_ulong_max_returns_max_rate: PARENT_RATE_1GHZ / 8 (minimum rate, pre-fix) -> PARENT_RATE_1GHZ / 2 (maximum rate) - clk_divider_bestdiv_mux_ulong_max_returns_max_rate: 0 (invalid, pre-fix) -> PARENT_RATE_4GHZ / 2 (maximum rate with mux selecting the 4 GHz parent and applying the smallest table divider of 2) Signed-off-by: Lad Prabhakar Reviewed-by: Brian Masney --- v4->v5: - No change v3->v4: - No change v2->v3: - Added Rb tag - Added the expected value for the tests - updated the commit message --- drivers/clk/clk-divider.c | 25 +++++++++++++++++-------- drivers/clk/clk-divider_test.c | 4 ++-- 2 files changed, 19 insertions(+), 10 deletions(-) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index c3804bbc06f9..36bfaf7200e2 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -15,6 +15,7 @@ #include #include #include +#include =20 /* * DOC: basic adjustable divider clock that cannot gate @@ -301,6 +302,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, struc= t clk_hw *parent, int i, bestdiv =3D 0; unsigned long parent_rate, best =3D 0, now, maxdiv; unsigned long parent_rate_saved =3D *best_parent_rate; + unsigned long target_parent_rate; =20 if (!rate) rate =3D 1; @@ -315,15 +317,11 @@ static int clk_divider_bestdiv(struct clk_hw *hw, str= uct clk_hw *parent, return bestdiv; } =20 - /* - * The maximum divider we can use without overflowing - * unsigned long in rate * i below - */ - maxdiv =3D min(ULONG_MAX / rate, maxdiv); - for (i =3D _next_div(table, 0, flags); i <=3D maxdiv; i =3D _next_div(table, i, flags)) { - if (rate * i =3D=3D parent_rate_saved) { + bool overflow =3D check_mul_overflow(rate, (unsigned long)i, &target_par= ent_rate); + + if (!overflow && target_parent_rate =3D=3D parent_rate_saved) { /* * It's the most ideal case if the requested rate can be * divided from parent clock without needing to change @@ -332,13 +330,24 @@ static int clk_divider_bestdiv(struct clk_hw *hw, str= uct clk_hw *parent, *best_parent_rate =3D parent_rate_saved; return i; } - parent_rate =3D clk_hw_round_rate(parent, rate * i); + /* + * Clamp target_parent_rate to ULONG_MAX on overflow. The true + * required parent rate exceeds what can be represented, so ask + * the parent for the highest rate it can produce. There is no + * point continuing the loop past this since larger dividers + * only move further from the requested rate. + */ + if (overflow) + target_parent_rate =3D ULONG_MAX; + parent_rate =3D clk_hw_round_rate(parent, target_parent_rate); now =3D DIV_ROUND_UP_ULL((u64)parent_rate, i); if (_is_best_div(rate, now, best, flags)) { bestdiv =3D i; best =3D now; *best_parent_rate =3D parent_rate; } + if (overflow) + break; } =20 if (!bestdiv) { diff --git a/drivers/clk/clk-divider_test.c b/drivers/clk/clk-divider_test.c index cb56931456b8..8ee1614128d0 100644 --- a/drivers/clk/clk-divider_test.c +++ b/drivers/clk/clk-divider_test.c @@ -61,7 +61,7 @@ static void clk_divider_bestdiv_ulong_max_returns_max_rat= e(struct kunit *test) * can produce. */ rate =3D clk_hw_round_rate(div_hw, ULONG_MAX); - KUNIT_EXPECT_EQ(test, rate, PARENT_RATE_1GHZ / 8); + KUNIT_EXPECT_EQ(test, rate, PARENT_RATE_1GHZ / 2); } =20 /* @@ -133,7 +133,7 @@ static void clk_divider_bestdiv_mux_ulong_max_returns_m= ax_rate(struct kunit *tes div_hw)); =20 rate =3D clk_hw_round_rate(div_hw, ULONG_MAX); - KUNIT_EXPECT_EQ(test, rate, 0); + KUNIT_EXPECT_EQ(test, rate, PARENT_RATE_4GHZ / 2); } =20 static struct kunit_case clk_divider_bestdiv_test_cases[] =3D { --=20 2.54.0