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Mon, 27 Apr 2026 22:39:38 -0700 From: Tariq Toukan To: Leon Romanovsky , Jason Gunthorpe , "Saeed Mahameed" , Tariq Toukan CC: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" , Mark Bloch , "Moshe Shemesh" , Parav Pandit , Shay Drori , Kees Cook , Daniel Jurgens , Or Har-Toov , Simon Horman , Jiri Pirko , Adithya Jayachandran , , , , Gal Pressman , Dragos Tatulea Subject: [PATCH mlx5-next 1/4] mlx5: Rename the vport number enums for host PF and VF Date: Tue, 28 Apr 2026 08:38:48 +0300 Message-ID: <20260428053851.220089-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260428053851.220089-1-tariqt@nvidia.com> References: <20260428053851.220089-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000C6189:EE_|SA3PR12MB9089:EE_ X-MS-Office365-Filtering-Correlation-Id: c0c25694-4656-46b0-72a9-08dea4e89726 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|7416014|376014|1800799024|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: 3RMIofOv9HARQ2Lmtaux4voEMsyJvbBirLb1UxVa1w8zMMfW0y/xyuo5PMpdQ2AJv35UDpZh6oC1ecv8h/SBZriLq3otdk7Ko9atOdvRZK6d8WS1ExQ8gY8XrTUCimNlPTX9OkZi/fqfUqoW/RAo+ZZfp2fn0oBdmAFyIrANciHb0k7KPyLavd+HqVmyQH9JTPHvTxRKazgtXuWHwQchxA0CT+jWle5zrJDH0q+IAeAeIM5FNZ/mP2alw/PxI/vwvzrrdsCgNiNFMLY06aA40qtaQFonsv/lwQ2c+1JkDKeEzKGpyTP4HrqeCBs6er1HXfp2TXtvIhvajAzHF8R+YDcPQmiXywfAYDNe1u4QUx09hfYklEkt0Yss7Vnk/xOVOAThkQ6M1CKU4alHM49MtdYKc6XM1k5teGxjLin5kA+PVyBtQaToX4tZyFG8Vnqgo1kkxVO0dB+9iOjAQYKFsFt53BI9rc0XkEc4CCHEHgBdfLxeAexgbEg1PJdPSa2RJE5/vqYzptTQORprYMMwA9jwmJQCunoRCi5go9VolNK5QzMAxH0Y7gyPzUG9vXVv+yKt/cZdX5gSQZhJXtJtNks8a9FQ/0tbEOt8+taHLxu62+mBaLRuxhGrmOVrxiIKedHxgCNvDbrrmd86tzN2do+riQycagZb3F2skxaWZ751n2/+nFiKKdcAcJPa6amxpiVgAgqQQdx/ToMhFaPtNm0vFeDpyoNAbxLTbe/1BsvS12gx/IYM/8+3AxoV29WltZerd936A1UfZPzEfe7GLQ== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(7416014)(376014)(1800799024)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 5IGade0Jg7NGDSi5vrjbYQ1knWeDWdEYhnKRsig0qj3gvaF3CFIDxeBYUAhMqkPw5RyrdZrYuQv6fj4d2d3FYi3Lb6RvTxxYNJd88egvfp0ODcorI2RaFa4EspW2HlYaP7J+Bk8shI8IepZaXgI6hJwbJ5CZrTyBkwNeuzMSLagICyXwCmaD7OCQwcDdjfLPfiLgehtcQkXsKIl/7bQ8NR/nvFepYmpLKMCLTvfAX0qUjk28M2yMpfgkEWHdyRRZRZS+ABDB+i6A1ZAa75sA2Im7ZTl7vt7jvOYAf2kJXPmlk03N+gslYCjGx5sYck7W2eLjzV7L9eUqqjWltMH0/i1QC19xHDL/e/MRqY1RmKmpSqdAubOfivq83UTu0A94ErDOpDM+2SWRld72fFgMxFYsTEMkn44JOceqR1nVI2qejHK16o1Abf0hW6V2o1v5 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2026 05:40:00.7336 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c0c25694-4656-46b0-72a9-08dea4e89726 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000C6189.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB9089 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh Rename the vport number enums MLX5_VPORT_PF to MLX5_VPORT_HOST_PF and MLX5_VPORT_FIRST_VF to MLX5_VPORT_FIRST_HOST_VF to indicate that these vport indices represent the host PF and its VFs. This prepares the code for upcoming support of an additional PF type. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- drivers/infiniband/hw/mlx5/counters.c | 4 ++-- .../mellanox/mlx5/core/esw/devlink_port.c | 7 +++--- .../ethernet/mellanox/mlx5/core/esw/ipsec.c | 2 +- .../net/ethernet/mellanox/mlx5/core/eswitch.c | 22 +++++++++---------- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 2 +- .../mellanox/mlx5/core/eswitch_offloads.c | 17 ++++++++------ .../mellanox/mlx5/core/steering/hws/vport.c | 2 +- include/linux/mlx5/eswitch.h | 2 +- include/linux/mlx5/vport.h | 4 ++-- 9 files changed, 33 insertions(+), 29 deletions(-) diff --git a/drivers/infiniband/hw/mlx5/counters.c b/drivers/infiniband/hw/= mlx5/counters.c index 5b4482dd6274..5a79e834ddea 100644 --- a/drivers/infiniband/hw/mlx5/counters.c +++ b/drivers/infiniband/hw/mlx5/counters.c @@ -697,7 +697,7 @@ static void mlx5_ib_fill_counters(struct mlx5_ib_dev *d= ev, u32 port_num) { bool is_vport =3D is_mdev_switchdev_mode(dev->mdev) && - port_num !=3D MLX5_VPORT_PF; + port_num !=3D MLX5_VPORT_HOST_PF; const struct mlx5_ib_counter *names; int j =3D 0, i, size; =20 @@ -802,7 +802,7 @@ static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev = *dev, struct mlx5_ib_counters *cnts, u32 port_num) { bool is_vport =3D is_mdev_switchdev_mode(dev->mdev) && - port_num !=3D MLX5_VPORT_PF; + port_num !=3D MLX5_VPORT_HOST_PF; u32 num_counters, num_op_counters =3D 0, size; =20 size =3D is_vport ? ARRAY_SIZE(vport_basic_q_cnts) : diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c b/d= rivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c index e1d11326af1b..8a79764345e7 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c @@ -13,7 +13,8 @@ mlx5_esw_get_port_parent_id(struct mlx5_core_dev *dev, st= ruct netdev_phys_item_i =20 static bool mlx5_esw_devlink_port_supported(struct mlx5_eswitch *esw, u16 = vport_num) { - return (mlx5_core_is_ecpf(esw->dev) && vport_num =3D=3D MLX5_VPORT_PF) || + return (mlx5_core_is_ecpf(esw->dev) && + vport_num =3D=3D MLX5_VPORT_HOST_PF) || mlx5_eswitch_is_vf_vport(esw, vport_num) || mlx5_core_is_ec_vf_vport(esw->dev, vport_num); } @@ -35,7 +36,7 @@ static void mlx5_esw_offloads_pf_vf_devlink_port_attrs_se= t(struct mlx5_eswitch * if (external) controller_num =3D dev->priv.eswitch->offloads.host_number + 1; =20 - if (vport_num =3D=3D MLX5_VPORT_PF) { + if (vport_num =3D=3D MLX5_VPORT_HOST_PF) { memcpy(dl_port->attrs.switch_id.id, ppid.id, ppid.id_len); dl_port->attrs.switch_id.id_len =3D ppid.id_len; devlink_port_attrs_pci_pf_set(dl_port, controller_num, pfnum, external); @@ -216,7 +217,7 @@ int mlx5_esw_offloads_devlink_port_register(struct mlx5= _eswitch *esw, struct mlx if (err) goto rate_err; =20 - if (vport_num =3D=3D MLX5_VPORT_PF) { + if (vport_num =3D=3D MLX5_VPORT_HOST_PF) { err =3D mlx5_esw_devlink_port_res_register(esw, &dl_port->dl_port); if (err) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec.c b/drivers/= net/ethernet/mellanox/mlx5/core/esw/ipsec.c index da10e04777cf..8b12c3ae0cf7 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec.c @@ -209,7 +209,7 @@ static int esw_ipsec_vf_offload_set_bytype(struct mlx5_= eswitch *esw, struct mlx5 struct mlx5_core_dev *dev =3D esw->dev; int err; =20 - if (vport->vport =3D=3D MLX5_VPORT_PF) + if (vport->vport =3D=3D MLX5_VPORT_HOST_PF) return -EOPNOTSUPP; =20 if (type =3D=3D MLX5_ESW_VPORT_IPSEC_CRYPTO_OFFLOAD) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.c index 123c96716a54..80ba360347e7 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -926,7 +926,7 @@ int mlx5_esw_vport_enable(struct mlx5_eswitch *esw, str= uct mlx5_vport *vport, /* Sync with current vport context */ vport->enabled_events =3D enabled_events; vport->enabled =3D true; - if (vport->vport !=3D MLX5_VPORT_PF && + if (vport->vport !=3D MLX5_VPORT_HOST_PF && (vport->info.ipsec_crypto_enabled || vport->info.ipsec_packet_enabled= )) esw->enabled_ipsec_vf_count++; =20 @@ -979,7 +979,7 @@ void mlx5_esw_vport_disable(struct mlx5_eswitch *esw, s= truct mlx5_vport *vport) MLX5_CAP_GEN(esw->dev, vhca_resource_manager)) mlx5_esw_vport_vhca_id_unmap(esw, vport); =20 - if (vport->vport !=3D MLX5_VPORT_PF && + if (vport->vport !=3D MLX5_VPORT_HOST_PF && (vport->info.ipsec_crypto_enabled || vport->info.ipsec_packet_enabled= )) esw->enabled_ipsec_vf_count--; =20 @@ -1314,7 +1314,7 @@ int mlx5_esw_host_pf_enable_hca(struct mlx5_core_dev = *dev) if (!mlx5_core_is_ecpf(dev) || !mlx5_esw_allowed(esw)) return 0; =20 - vport =3D mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF); + vport =3D mlx5_eswitch_get_vport(esw, MLX5_VPORT_HOST_PF); if (IS_ERR(vport)) return PTR_ERR(vport); =20 @@ -1340,7 +1340,7 @@ int mlx5_esw_host_pf_disable_hca(struct mlx5_core_dev= *dev) if (!mlx5_core_is_ecpf(dev) || !mlx5_esw_allowed(esw)) return 0; =20 - vport =3D mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF); + vport =3D mlx5_eswitch_get_vport(esw, MLX5_VPORT_HOST_PF); if (IS_ERR(vport)) return PTR_ERR(vport); =20 @@ -1368,7 +1368,7 @@ mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitch = *esw, =20 /* Enable PF vport */ if (pf_needed && mlx5_esw_host_functions_enabled(esw->dev)) { - ret =3D mlx5_eswitch_load_pf_vf_vport(esw, MLX5_VPORT_PF, + ret =3D mlx5_eswitch_load_pf_vf_vport(esw, MLX5_VPORT_HOST_PF, enabled_events); if (ret) return ret; @@ -1423,7 +1423,7 @@ mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitch = *esw, mlx5_esw_host_pf_disable_hca(esw->dev); pf_hca_err: if (pf_needed && mlx5_esw_host_functions_enabled(esw->dev)) - mlx5_eswitch_unload_pf_vf_vport(esw, MLX5_VPORT_PF); + mlx5_eswitch_unload_pf_vf_vport(esw, MLX5_VPORT_HOST_PF); return ret; } =20 @@ -1450,7 +1450,7 @@ void mlx5_eswitch_disable_pf_vf_vports(struct mlx5_es= witch *esw) if ((mlx5_core_is_ecpf_esw_manager(esw->dev) || esw->mode =3D=3D MLX5_ESWITCH_LEGACY) && mlx5_esw_host_functions_enabled(esw->dev)) - mlx5_eswitch_unload_pf_vf_vport(esw, MLX5_VPORT_PF); + mlx5_eswitch_unload_pf_vf_vport(esw, MLX5_VPORT_HOST_PF); } =20 static void mlx5_eswitch_get_devlink_param(struct mlx5_eswitch *esw) @@ -1822,7 +1822,7 @@ static int mlx5_query_hca_cap_host_pf(struct mlx5_cor= e_dev *dev, void *out) =20 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); MLX5_SET(query_hca_cap_in, in, op_mod, opmod); - MLX5_SET(query_hca_cap_in, in, function_id, MLX5_VPORT_PF); + MLX5_SET(query_hca_cap_in, in, function_id, MLX5_VPORT_HOST_PF); MLX5_SET(query_hca_cap_in, in, other_function, true); return mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); } @@ -1914,10 +1914,10 @@ static int mlx5_esw_vports_init(struct mlx5_eswitch= *esw) xa_init(&esw->vports); =20 if (mlx5_esw_host_functions_enabled(dev)) { - err =3D mlx5_esw_vport_alloc(esw, idx, MLX5_VPORT_PF); + err =3D mlx5_esw_vport_alloc(esw, idx, MLX5_VPORT_HOST_PF); if (err) goto err; - if (esw->first_host_vport =3D=3D MLX5_VPORT_PF) + if (esw->first_host_vport =3D=3D MLX5_VPORT_HOST_PF) xa_set_mark(&esw->vports, idx, MLX5_ESW_VPT_HOST_FN); idx++; for (i =3D 0; i < mlx5_core_max_vfs(dev); i++) { @@ -2195,7 +2195,7 @@ bool mlx5_eswitch_is_vf_vport(struct mlx5_eswitch *es= w, u16 vport_num) =20 bool mlx5_eswitch_is_pf_vf_vport(struct mlx5_eswitch *esw, u16 vport_num) { - return vport_num =3D=3D MLX5_VPORT_PF || + return vport_num =3D=3D MLX5_VPORT_HOST_PF || mlx5_eswitch_is_vf_vport(esw, vport_num); } =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.h index 5128f5020dae..f6a23930f308 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -684,7 +684,7 @@ static inline bool mlx5_esw_is_owner(struct mlx5_eswitc= h *esw, u16 vport_num, static inline u16 mlx5_eswitch_first_host_vport_num(struct mlx5_core_dev *= dev) { return mlx5_core_is_ecpf_esw_manager(dev) ? - MLX5_VPORT_PF : MLX5_VPORT_FIRST_VF; + MLX5_VPORT_HOST_PF : MLX5_VPORT_FIRST_HOST_VF; } =20 static inline bool mlx5_eswitch_is_funcs_handler(const struct mlx5_core_de= v *dev) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index a078d06f4567..c32335df6b64 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -1216,9 +1216,10 @@ static int esw_add_fdb_peer_miss_rules(struct mlx5_e= switch *esw, =20 if (mlx5_core_is_ecpf_esw_manager(peer_dev) && mlx5_esw_host_functions_enabled(peer_dev)) { - peer_vport =3D mlx5_eswitch_get_vport(peer_esw, MLX5_VPORT_PF); + peer_vport =3D mlx5_eswitch_get_vport(peer_esw, + MLX5_VPORT_HOST_PF); esw_set_peer_miss_rule_source_port(esw, peer_esw, spec, - MLX5_VPORT_PF); + MLX5_VPORT_HOST_PF); =20 flow =3D mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw), spec, &flow_act, &dest, 1); @@ -1300,7 +1301,8 @@ static int esw_add_fdb_peer_miss_rules(struct mlx5_es= witch *esw, =20 if (mlx5_core_is_ecpf_esw_manager(peer_dev) && mlx5_esw_host_functions_enabled(peer_dev)) { - peer_vport =3D mlx5_eswitch_get_vport(peer_esw, MLX5_VPORT_PF); + peer_vport =3D mlx5_eswitch_get_vport(peer_esw, + MLX5_VPORT_HOST_PF); mlx5_del_flow_rules(flows[peer_vport->index]); } add_pf_flow_err: @@ -1342,7 +1344,8 @@ static void esw_del_fdb_peer_miss_rules(struct mlx5_e= switch *esw, =20 if (mlx5_core_is_ecpf_esw_manager(peer_dev) && mlx5_esw_host_functions_enabled(peer_dev)) { - peer_vport =3D mlx5_eswitch_get_vport(peer_esw, MLX5_VPORT_PF); + peer_vport =3D mlx5_eswitch_get_vport(peer_esw, + MLX5_VPORT_HOST_PF); mlx5_del_flow_rules(flows[peer_vport->index]); } =20 @@ -4435,7 +4438,7 @@ static bool mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch *esw, u16 vport_num) { /* Currently, only ECPF based device has representor for host PF. */ - if (vport_num =3D=3D MLX5_VPORT_PF && + if (vport_num =3D=3D MLX5_VPORT_HOST_PF && (!mlx5_core_is_ecpf_esw_manager(esw->dev) || !mlx5_esw_host_functions_enabled(esw->dev))) return false; @@ -4791,7 +4794,7 @@ int mlx5_devlink_pf_port_fn_state_get(struct devlink_= port *port, const u32 *query_out; bool pf_disabled; =20 - if (vport->vport !=3D MLX5_VPORT_PF) { + if (vport->vport !=3D MLX5_VPORT_HOST_PF) { NL_SET_ERR_MSG_MOD(extack, "State get is not supported for VF"); return -EOPNOTSUPP; } @@ -4820,7 +4823,7 @@ int mlx5_devlink_pf_port_fn_state_set(struct devlink_= port *port, struct mlx5_vport *vport =3D mlx5_devlink_port_vport_get(port); struct mlx5_core_dev *dev; =20 - if (vport->vport !=3D MLX5_VPORT_PF) { + if (vport->vport !=3D MLX5_VPORT_HOST_PF) { NL_SET_ERR_MSG_MOD(extack, "State set is not supported for VF"); return -EOPNOTSUPP; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/vport.c b= /drivers/net/ethernet/mellanox/mlx5/core/steering/hws/vport.c index d8e382b9fa61..6dc3b11b7926 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/vport.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/vport.c @@ -50,7 +50,7 @@ static int hws_vport_add_gvmi(struct mlx5hws_context *ctx= , u16 vport) static bool hws_vport_is_esw_mgr_vport(struct mlx5hws_context *ctx, u16 vp= ort) { return ctx->caps->is_ecpf ? vport =3D=3D MLX5_VPORT_ECPF : - vport =3D=3D MLX5_VPORT_PF; + vport =3D=3D MLX5_VPORT_HOST_PF; } =20 int mlx5hws_vport_get_gvmi(struct mlx5hws_context *ctx, u16 vport, u16 *vp= ort_gvmi) diff --git a/include/linux/mlx5/eswitch.h b/include/linux/mlx5/eswitch.h index 67256e776566..3b29a3c6794d 100644 --- a/include/linux/mlx5/eswitch.h +++ b/include/linux/mlx5/eswitch.h @@ -217,7 +217,7 @@ static inline bool is_mdev_switchdev_mode(struct mlx5_c= ore_dev *dev) static inline u16 mlx5_eswitch_manager_vport(struct mlx5_core_dev *dev) { return mlx5_core_is_ecpf_esw_manager(dev) ? - MLX5_VPORT_ECPF : MLX5_VPORT_PF; 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The new field support by firmware is indicated by the function_id_type_vhca_id capability bit, which is already exposed in hca caps. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- include/linux/mlx5/mlx5_ifc.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 49f3ad4b1a7c..06ec1f5d2c6c 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -8452,7 +8452,9 @@ struct mlx5_ifc_enable_hca_in_bits { u8 op_mod[0x10]; =20 u8 embedded_cpu_function[0x1]; - u8 reserved_at_41[0xf]; + u8 reserved_at_41[0x2]; + u8 function_id_type[0x1]; + u8 reserved_at_44[0xc]; u8 function_id[0x10]; =20 u8 reserved_at_60[0x20]; @@ -8497,7 +8499,9 @@ struct mlx5_ifc_disable_hca_in_bits { u8 op_mod[0x10]; =20 u8 embedded_cpu_function[0x1]; - u8 reserved_at_41[0xf]; + u8 reserved_at_41[0x2]; + u8 function_id_type[0x1]; + u8 reserved_at_44[0xc]; u8 function_id[0x10]; =20 u8 reserved_at_60[0x20]; --=20 2.44.0 From nobody Wed Jun 17 05:12:34 2026 Received: from CO1PR03CU002.outbound.protection.outlook.com (mail-westus2azon11010026.outbound.protection.outlook.com [52.101.46.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 425DD33CEA9; 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This field has been deprecated in firmware and is not referenced by the mlx5 driver, so it can be safely removed. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- include/linux/mlx5/mlx5_ifc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 06ec1f5d2c6c..02b57b2286da 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -12725,7 +12725,6 @@ struct mlx5_ifc_query_esw_functions_out_bits { struct mlx5_ifc_host_params_context_bits host_params_context; =20 u8 reserved_at_280[0x180]; - u8 host_sf_enable[][0x40]; }; =20 struct mlx5_ifc_sf_partition_bits { --=20 2.44.0 From nobody Wed Jun 17 05:12:34 2026 Received: from SN4PR0501CU005.outbound.protection.outlook.com (mail-southcentralusazon11011038.outbound.protection.outlook.com [40.93.194.38]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FD3131F996; Tue, 28 Apr 2026 05:40:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 27 Apr 2026 22:40:06 -0700 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Mon, 27 Apr 2026 22:40:05 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Mon, 27 Apr 2026 22:39:59 -0700 From: Tariq Toukan To: Leon Romanovsky , Jason Gunthorpe , "Saeed Mahameed" , Tariq Toukan CC: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" , Mark Bloch , "Moshe Shemesh" , Parav Pandit , Shay Drori , Kees Cook , Daniel Jurgens , Or Har-Toov , Simon Horman , Jiri Pirko , Adithya Jayachandran , , , , Gal Pressman , Dragos Tatulea Subject: [PATCH mlx5-next 4/4] net/mlx5: Extend query_esw_functions output for multi-function support Date: Tue, 28 Apr 2026 08:38:51 +0300 Message-ID: <20260428053851.220089-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260428053851.220089-1-tariqt@nvidia.com> References: <20260428053851.220089-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000B:EE_|PH8PR12MB7422:EE_ X-MS-Office365-Filtering-Correlation-Id: 9297ca3c-eab3-4d54-66e8-08dea4e8a595 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700016|7416014|56012099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: bbUP7i2oc4N9LnLcFcODlffrNOQFTnG7S9XcWhPFCyx+Evr9jlUEjSe5HQYKXd9uiTqhWVs1DeDzG95iwWMk/frzeXb+DYWvXXmBXINzMBSXYb2eLRoZNBUGeK/CY+eY7HT+T7/XIP2Zm4/FPPPTn3IMX1pty3Rb6dfZf2OLfFyBzmIVJpt9lfYJ7B5/OIkXO+PBI3+4Cf6LnrC0UMV8iBcW89cSYslOOEGTOSflJXBggAv1z8fKmXIu3n+GPAggB/DitI7XyxB3+srQjHIFIAc6zm1+TB2O/0hjc+qwxXJWh1s858gyyxEoCoPn2S5n6MV97tR4WHVD57F1YPO5APfo5kYxvdnNp7hcE/EHRAdWuAQev9T9j0P7TtnRIDdItvdX84xwYSdMRbh1KafFvYNCgRmXp8aHGIQkWWRkX7XzJXzE8KRLBNnTNZiunClvP7Zb7+2p4/NNXyaGMn/Vyet9uUBLrWEus7nWGDYII+G0FHApsvq/s/wdENGZ5k/urMiLPMzXqJW5ixZpXJAogqUZHk1FH+Xjv2bEUAQs70uOhzyar03YfazhTdhl8ehpuvZpRL2y6DnmD32M0prT2px+aF5r/Ltn2+nr5FRG2LgmRXBC+pHK5iguWXwwOhB7O98qjxK8/k7zs35cAPQ9DnOu49oDAkW4KW0eRu7Ql4aKdjy/p3GXgWAPTWH/ZFXpdWN0aV2IPNcbt1UqYiPlwxWJAo3oBK6g7+r3S5foSRLvxU3XY0XN7VS35IieHAmdBhuI+KtcH+hz16nR+dNx7Q== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700016)(7416014)(56012099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Ey9GAaBCxbUUidyVPhROJXxSJWKp7sV8MrqMobVo1tYqR/9j9u+UPSpd4I5A9eUGw3PCHV+dTQRos1xBzA7UTFbq/i2h0pCdsb6w39ulP30fjLKGqcsUPp+83FllauzIaGX3ZHzxkEtlkT+UoFruFIvu7wd87ku5iH6CscjmcQb47eUK4QTpTA4KsDV/8IcBMf2z4t8Fm2e9cWu6OsSFbKeSBsWBHldjloiOye+wN89rkCEUGmuzgWQqHi3E1njgeC3gNlPkib8u/gKaOw1xdgkIVi8nOljv2bakxL86pMNXE6IMAiXsPJPxvrN1M06WBN61OxRMdJvkMrREcV49rP/0bdF4dZsXtg43gfp8eGzW2oygTBuONPfak4IB+dBxGv+wtJMgG2oSO3RDFB1C+AXIbYUPs5cJU/0W0bLat9zFQbkDQEOe8ekVNtZqmG8O X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2026 05:40:24.8865 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9297ca3c-eab3-4d54-66e8-08dea4e8a595 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7422 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh Update the query_esw_functions command to support a new response layout that can report data for multiple network functions. Setting bit 14 of the op_mod field selects the v1 layout with network_function_params entries instead of the legacy host_params_context. The query_host_net_function_v1 read-only capability indicates firmware support for layout version 1, and query_host_net_function_num_max advertises the maximum number of network function entries. Define a new network_function_params layout and a net_function_params union that groups host_params_context and network_function_params. Rework the query_esw_functions output to use a flexible array of this union, and adjust existing driver callers to use it. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/eswitch.c | 14 ++-- .../mellanox/mlx5/core/eswitch_offloads.c | 25 +++++--- .../mlx5/core/sf/mlx5_ifc_vhca_event.h | 8 --- .../net/ethernet/mellanox/mlx5/core/sriov.c | 7 +- include/linux/mlx5/mlx5_ifc.h | 64 +++++++++++++++++-- 5 files changed, 91 insertions(+), 27 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.c index 80ba360347e7..408f729d8914 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -1045,6 +1045,7 @@ const u32 *mlx5_esw_query_functions(struct mlx5_core_= dev *dev) static int mlx5_esw_host_functions_enabled_query(struct mlx5_eswitch *esw) { const u32 *query_host_out; + void *host_params; =20 if (!mlx5_core_is_ecpf_esw_manager(esw->dev)) return 0; @@ -1053,9 +1054,11 @@ static int mlx5_esw_host_functions_enabled_query(str= uct mlx5_eswitch *esw) if (IS_ERR(query_host_out)) return PTR_ERR(query_host_out); =20 + host_params =3D MLX5_ADDR_OF(query_esw_functions_out, + query_host_out, net_function_params); esw->esw_funcs.host_funcs_disabled =3D - MLX5_GET(query_esw_functions_out, query_host_out, - host_params_context.host_pf_not_exist); + MLX5_GET(host_params_context, host_params, + host_pf_not_exist); =20 kvfree(query_host_out); return 0; @@ -1475,6 +1478,7 @@ static void mlx5_eswitch_get_devlink_param(struct mlx= 5_eswitch *esw) static void mlx5_eswitch_update_num_of_vfs(struct mlx5_eswitch *esw, int num_vfs) { + void *host_params; const u32 *out; =20 if (num_vfs < 0) @@ -1489,8 +1493,10 @@ mlx5_eswitch_update_num_of_vfs(struct mlx5_eswitch *= esw, int num_vfs) if (IS_ERR(out)) return; =20 - esw->esw_funcs.num_vfs =3D MLX5_GET(query_esw_functions_out, out, - host_params_context.host_num_of_vfs); + host_params =3D MLX5_ADDR_OF(query_esw_functions_out, out, + net_function_params); + esw->esw_funcs.num_vfs =3D MLX5_GET(host_params_context, host_params, + host_num_of_vfs); if (mlx5_core_ec_sriov_enabled(esw->dev)) esw->esw_funcs.num_ec_vfs =3D num_vfs; =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index c32335df6b64..b859aa5062ca 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -3664,6 +3664,7 @@ esw_vfs_changed_event_handler(struct mlx5_eswitch *es= w, int work_gen, { struct devlink *devlink; bool host_pf_disabled; + void *host_params; u16 new_num_vfs; =20 devlink =3D priv_to_devlink(esw->dev); @@ -3673,10 +3674,12 @@ esw_vfs_changed_event_handler(struct mlx5_eswitch *= esw, int work_gen, if (work_gen !=3D atomic_read(&esw->esw_funcs.generation)) goto unlock; =20 - new_num_vfs =3D MLX5_GET(query_esw_functions_out, out, - host_params_context.host_num_of_vfs); - host_pf_disabled =3D MLX5_GET(query_esw_functions_out, out, - host_params_context.host_pf_disabled); + host_params =3D MLX5_ADDR_OF(query_esw_functions_out, out, + net_function_params); + new_num_vfs =3D MLX5_GET(host_params_context, host_params, + host_num_of_vfs); + host_pf_disabled =3D MLX5_GET(host_params_context, host_params, + host_pf_disabled); =20 if (new_num_vfs =3D=3D esw->esw_funcs.num_vfs || host_pf_disabled) goto unlock; @@ -3743,6 +3746,7 @@ int mlx5_esw_funcs_changed_handler(struct notifier_bl= ock *nb, unsigned long type static int mlx5_esw_host_number_init(struct mlx5_eswitch *esw) { const u32 *query_host_out; + void *host_params; =20 if (!mlx5_core_is_ecpf_esw_manager(esw->dev)) return 0; @@ -3752,8 +3756,10 @@ static int mlx5_esw_host_number_init(struct mlx5_esw= itch *esw) return PTR_ERR(query_host_out); =20 /* Mark non local controller with non zero controller number. */ - esw->offloads.host_number =3D MLX5_GET(query_esw_functions_out, query_hos= t_out, - host_params_context.host_number); + host_params =3D MLX5_ADDR_OF(query_esw_functions_out, + query_host_out, net_function_params); + esw->offloads.host_number =3D MLX5_GET(host_params_context, + host_params, host_number); kvfree(query_host_out); return 0; } @@ -4792,6 +4798,7 @@ int mlx5_devlink_pf_port_fn_state_get(struct devlink_= port *port, { struct mlx5_vport *vport =3D mlx5_devlink_port_vport_get(port); const u32 *query_out; + void *host_params; bool pf_disabled; =20 if (vport->vport !=3D MLX5_VPORT_HOST_PF) { @@ -4806,8 +4813,10 @@ int mlx5_devlink_pf_port_fn_state_get(struct devlink= _port *port, if (IS_ERR(query_out)) return PTR_ERR(query_out); =20 - pf_disabled =3D MLX5_GET(query_esw_functions_out, query_out, - host_params_context.host_pf_disabled); + host_params =3D MLX5_ADDR_OF(query_esw_functions_out, query_out, + net_function_params); + pf_disabled =3D MLX5_GET(host_params_context, host_params, + host_pf_disabled); =20 *opstate =3D pf_disabled ? DEVLINK_PORT_FN_OPSTATE_DETACHED : DEVLINK_PORT_FN_OPSTATE_ATTACHED; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sf/mlx5_ifc_vhca_event= .h b/drivers/net/ethernet/mellanox/mlx5/core/sf/mlx5_ifc_vhca_event.h index 4fc870140d71..487c94b56203 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/sf/mlx5_ifc_vhca_event.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/sf/mlx5_ifc_vhca_event.h @@ -4,14 +4,6 @@ #ifndef __MLX5_IFC_VHCA_EVENT_H__ #define __MLX5_IFC_VHCA_EVENT_H__ =20 -enum mlx5_ifc_vhca_state { - MLX5_VHCA_STATE_INVALID =3D 0x0, - MLX5_VHCA_STATE_ALLOCATED =3D 0x1, - MLX5_VHCA_STATE_ACTIVE =3D 0x2, - MLX5_VHCA_STATE_IN_USE =3D 0x3, - MLX5_VHCA_STATE_TEARDOWN_REQUEST =3D 0x4, -}; - struct mlx5_ifc_vhca_state_context_bits { u8 arm_change_event[0x1]; u8 reserved_at_1[0xb]; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sriov.c b/drivers/net/= ethernet/mellanox/mlx5/core/sriov.c index bf6f631cf2ce..6eb6026eadd6 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/sriov.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/sriov.c @@ -274,6 +274,7 @@ void mlx5_sriov_detach(struct mlx5_core_dev *dev) static u16 mlx5_get_max_vfs(struct mlx5_core_dev *dev) { u16 host_total_vfs; + void *host_params; const u32 *out; =20 if (mlx5_core_is_ecpf_esw_manager(dev)) { @@ -284,8 +285,10 @@ static u16 mlx5_get_max_vfs(struct mlx5_core_dev *dev) */ if (IS_ERR(out)) goto done; - host_total_vfs =3D MLX5_GET(query_esw_functions_out, out, - host_params_context.host_total_vfs); + host_params =3D MLX5_ADDR_OF(query_esw_functions_out, out, + net_function_params); + host_total_vfs =3D MLX5_GET(host_params_context, host_params, + host_total_vfs); kvfree(out); return host_total_vfs; } diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 02b57b2286da..6a675f918c40 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1935,7 +1935,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 max_flow_counter_31_16[0x10]; u8 max_wqe_sz_sq_dc[0x10]; =20 - u8 reserved_at_2e0[0x7]; + u8 query_host_net_function_num_max[0x5]; + u8 reserved_at_2e5[0x2]; u8 max_qp_mcg[0x19]; =20 u8 reserved_at_300[0x10]; @@ -2027,7 +2028,7 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 log_max_current_mc_list[0x5]; u8 reserved_at_3f8[0x1]; u8 silent_mode_query[0x1]; - u8 reserved_at_3fa[0x1]; + u8 query_host_net_function_v1[0x1]; u8 log_max_current_uc_list[0x5]; =20 u8 general_obj_types[0x40]; @@ -12704,6 +12705,54 @@ struct mlx5_ifc_host_params_context_bits { u8 reserved_at_80[0x180]; }; =20 +enum mlx5_ifc_vhca_state { + MLX5_VHCA_STATE_INVALID =3D 0x0, + MLX5_VHCA_STATE_ALLOCATED =3D 0x1, + MLX5_VHCA_STATE_ACTIVE =3D 0x2, + MLX5_VHCA_STATE_IN_USE =3D 0x3, + MLX5_VHCA_STATE_TEARDOWN_REQUEST =3D 0x4, +}; + +enum { + MLX5_PCI_PF_TYPE_EXTERNAL_HOST_PF =3D 0x0, + MLX5_PCI_PF_TYPE_SATELLITE_PF =3D 0x1, +}; + +struct mlx5_ifc_network_function_params_bits { + u8 host_number[0x8]; + u8 pci_pf_type[0x4]; + u8 reserved_at_c[0x4]; + u8 pci_num_vfs[0x10]; + + u8 pci_total_vfs[0x10]; + u8 pci_bus[0x8]; + u8 pci_device_function[0x8]; + + u8 vhca_id[0x10]; + u8 vhca_state[0x4]; + u8 reserved_at_54[0xc]; + + u8 reserved_at_60[0xa]; + u8 esw_vport_manual[0x1]; + u8 pci_bus_assigned[0x1]; + u8 pci_vf_info_valid[0x1]; + u8 reserved_at_6d[0x13]; + + u8 pci_vf_stride[0x10]; + u8 pci_first_vf_offset[0x10]; + + u8 reserved_at_a0[0x160]; +}; + +union mlx5_ifc_net_function_params_bits { + struct mlx5_ifc_host_params_context_bits host_params_context; + struct mlx5_ifc_network_function_params_bits network_function_params; +}; + +enum { + MLX5_QUERY_ESW_FUNC_OP_MOD_LAYOUT_V1 =3D BIT(14), +}; + struct mlx5_ifc_query_esw_functions_in_bits { u8 opcode[0x10]; u8 reserved_at_10[0x10]; @@ -12720,11 +12769,16 @@ struct mlx5_ifc_query_esw_functions_out_bits { =20 u8 syndrome[0x20]; =20 - u8 reserved_at_40[0x40]; + u8 reserved_at_40[0x20]; =20 - struct mlx5_ifc_host_params_context_bits host_params_context; + u8 net_function_num[0x8]; + u8 reserved_at_68[0x18]; =20 - u8 reserved_at_280[0x180]; + union { + u8 reserved_at_80[0x380]; + DECLARE_FLEX_ARRAY(union mlx5_ifc_net_function_params_bits, + net_function_params); + }; }; =20 struct mlx5_ifc_sf_partition_bits { --=20 2.44.0